1.

Course Code : CpE 314

2. Course Title : Introduction to HDL
3. Prerequisite :
4. Credits : 3 units

5. Course Description

A laboratory course that introduces hardware description language as a tool for designing and testing combinational and sequential circuit. It covers fundamental of
concepts of HDL and the basic building blocks of HDL programming.
6. Course Learning Outcomes and Relationships to Program Educational Objectives

Course Learning Outcomes Program Objectives

At the end of Semester, the students can: a b c d
a. Use a Hardware Description Language (HDL) to emulate hardware logic gate operation, establish data
flows, and model desired logic behavior.
b. Simulate hardware designs using HDL and verify the results.
c. Synthesize and test designs on Programmable Logic Device (PLD) hardware.

7. Course Content
Outcomes-Based
Evidence of Outcomes Course Program Values
Course Objectives, Topics, Desired Student Learning Assessment (OBA)
Objectives Outcomes Integration
Time Allotment Outcomes Activities
Topic: SKSU VMGO, Classroom Policies, Course Overview, Course Requirements, Grading System (3 hours)
1.1 Student can be aware of
1. Discuss the VMGO of the Individual participation in Group and individual Respect
and appreciate of the
university, classroom class discussion and discussions
university’s VMGO,
policies, scope of the group presentation Obedience
classroom policies,
course, course Rubrics for participation
course overview,
requirements and grading Patriotism
requirements and grading
system
system.

Topic:  Introduction to Verilog HDL (10 hours)

2.1 Verilog HDL 2.1 Students will know the Video Presentation Student and class a, b, e a, b, c, d Gratefulness
function of Verilog as HDL, participation
Levels of Design Description, accomplished by Appreciation
Concurrency, Simulation and professor.
Synthesis, Function
Verification, Systems tasks, Students participation in Rubrics score card
programming language question and answer
interface, Module, Simulation activity facilitated by
and Synthesis tools. Language teacher
Constructs and Conventions:
Introduction, Keywords,
Identifiers, White Space
Characters, Comments,
Numbers, Strings, Logic values,
Strengths, Data types, Scalars
and Vectors, Parameters,
Operators.
Topic: Gate Level Modeling (9 hours)

3.1 Gate Level Modeling 3.1 Students will know the topics Students participation in Presentation of outputs a, b, c, d a, b, c, d Unity and
included in gate level modelling question and answer teamwork
like Introduction, AND Gate activity facilitated by Rubrics for outputs
Primitive, Module, Structure, teacher Self-Discipline
Other Gate Primitives, Rubrics for group
Illustrative Examples, Tristate Group dynamics dynamics/discussion
Gates, Array of Instances of
Primitives, Design of Flip –
Flops with Gate Primitives,
Delays, Strengths and
Construction Resolution, Net
Types, Design of Basic Circuit.
Modeling at Dataflow Level:
Introduction, Continuous
Assignment Structure, Delays
and Continuous Assignments
Assignment to Vectors,
Operators.
Topic: Behavioral Modeling (9 hours)
4.1 Behavioral Modeling 4.1 Students will know the Students participation in Presentation of outputs a, b, c, d a, b, c, d Unity and
topics included in behavioral question and answer teamwork
modelling like Operations and activity facilitated by Rubrics for outputs
Assignments, Functional teacher Work Discipline
Bifurcation, Initial Construct, Rubrics for group
Always Construct, Assignments Group dynamics dynamics/discussion
with Delays, Wait Construct,
Multiple Always Block, Designs
at Behavioral Level, Blocking
and Non-Blocking
Assignments, The Case
Statement, Simulation Flow if
an if-Else Constructs, Assign-
De-Assign Construct, Repeat
Construct, for Loop, the Disable
Construct, While Loop, For
Ever Loop, Parallel Blocks,
Force Release, Construct,
Event.
Topic:  Switch Level Modeling (12 hours)

5.1 Switch Level Modeling 5.1 Student will know the topics Students participation in Presentation of outputs a, b, c, d, e a, b, c, d Unity and
under switch level modelling question and answer teamwork
like Basic Transistor Switches, activity facilitated by Rubrics for outputs
CMOS Switches, Bidirectional teacher
Gates, Time Delays with Switch
Primitives, Instantiation with Group dynamics
Strengths and Delays, Strength
Contention with Triger Nets.
System Tasks, Functions and
Compiler Directives:
Parameters, Path Delays,
Module Parameters, System
Tasks and Functions, File
Based Tasks and Functions,
Computer Directives,
Hierarchical Access, User
Defined Primitives.
Topic: Sequential Circuit Description (9 hours)

6.1 Sequential Circuit 6.1 Student will know the topics Students participation in Presentation of outputs b, c, d, e a, b, c,d Unity and
Description under sequential circuit question and answer teamwork
description like Sequential activity facilitated by Rubrics for outputs
Models – Feedback teacher
Model, Capacitive Model, Rubrics for group Hard work
Implicit Model, Basic Group dynamics dynamics/discussion
Memory Components,
Functional Register, Static
Machine Coding,
Sequential Synthesis.
Component Test and
Verification: Test Bench-
Combinational Circuit
Testing, Sequential Circuit
Testing, Test Bench
Techniques, Design
Verification, Assertion
Verification

8. Course Evaluation

Course Requirements:
Grading System
MIDTERM FINAL TERM
Exam 50% Exam 50%
Attendance/ Participation 20% Attendance/ Participation 10%
Quizzes/Assignment 30% Quizzes/Assignment 20%
Total 100% Total 100%

(Midterm Grade + Final Term Grade) / 2 = Final Grade

Schedule of Examination

Midterm -
 Final Term -
Classes End -

9. References

TEXTBOOKS:

 T R Padmanabhan, B.Bala Tripura Sundari, Design Through Verilog HDL,2009, Wiley.

 Zainalabdien Navabi, Verilog Digital System Design, TMH,2nd Edition,
 Stephen Brown, Zvonkoc Vranesic, “Fundamentals of Digital Logic with Verilog Design”, 2nd Edition, 2010, TMH
 Sunggu Lee, “ Digital Logic Design using Verilog, State Machine & Synthesis for FPGA,” Cengage Learning 2009
 Verilog HDL – Samir Palnitkar, 2nd Edition, Pearson Education, 2009.
 Advanced Digital Design with verilog HDL – Michel D.Ciletti, PHI,2009