M S Engineering College: Digital Electronics Lab Manual

M S Engineering College
Navarathna Agrahara, Sadahalli Post

Off. Kempe Gowda International Airport Road,
Bengaluru - 562110, Karnataka, India,
Digital Electronics Lab Manual

(18ECL38)
Prepared By
Dr. Venkateshappa
Professor& Head
Department of Electronics and Communication Engineering
M. S. Engineering College, Bengaluru – 562110
M S Engineering College
Vision
M.S.Engineering College shall blossom into a technical institution of national
importance with global network.
Mission
• To be the leading institution in imparting Quality Engineering Education with value
systems amongst students to face global challenges.
• To inculcate best engineering practices amongst students through quality education,

creativity, innovation and entrepreneurial skills.
• To make the institute to be recognized as among the leading institutions imparting

Quality Engineering Education; To produce world class professionals who possess
knowledge, skills and necessary values that help them take challenges at a global level
Quality Policy
Striving for Excellence in Quality Engineering Education.
 Our commitment to comply with mandatory requirements.
 Continually improve the effectiveness and quality management system.
 Our commitment to achieve total customer satisfaction by assuring successful

completion of the degree with skill sets to solve the Engineering problems
 By providing training at all the levels with placement assistance.
 Use of modern technology and its conditional up gradation.
 Participation of all the stakeholders to meet the expectations.

Department of Electronics and Communication Engineering
Vision
To equip students with strong technical knowledge by logical and innovative
thinking in Electronics and Communication Engineering domain to meet expectations
of the industry as well as society.
Mission
 To educate a new generation of Electronics and Communication Engineers by
providing them with a strong theoretical foundation, good design experience and
exposure to research and development to meet ever changing and ever demanding
needs of the Electronic Industry in particular, along with IT & other inter disciplinary
fields in general.
 Provide ethical and value based education by promoting activities addressing the
societal needs.
 To build up knowledge and skills of students to face the challenges across the globe
with confidence and ease.
Quality Policy
Our quality policy is to develop an effective source of technical man power with
the ability to adapt to an intellectually and technologically changing environment to
contribute to the growth of nation with the participative efforts of the management, staff,
students and industry while keeping up ethical and moral standards required
Program Outcomes:
1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering
fundamentals, and an engineering specialization to the solution of complex engineering
problems.
2. Problem analysis: Identify, formulate, review research literature, and analyze

complex engineering problems reaching substantiated conclusions using first principles
of mathematics, natural sciences, and engineering sciences.
3. Design/development of solutions: Design solutions for complex engineering

problems and design system components or processes that meet the specified needs with
appropriate consideration for the public health and safety, and the cultural, societal, and
environmental considerations.
4. Conduct investigations of complex problems: Use research-based knowledge and
research methods including design of experiments, analysis and interpretation of data,
and synthesis of the information to provide valid conclusions.
5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and
modern engineering and IT tools including prediction and modeling to complex
engineering activities with an understanding of the limitations.
6. The engineer and society: Apply reasoning informed by the contextual knowledge to
assess societal, health, safety, legal and cultural issues and the consequent
responsibilities relevant to the professional engineering practice.
7. Environment and sustainability: Understand the impact of the professional

engineering Solutions in societal and environmental contexts, and demonstrate the
knowledge of, and need for sustainable development.
8. Ethics: Apply ethical principles and commit to professional ethics and

responsibilities and norms of the engineering practice.
9. Individual and team work: Function effectively as an individual, and as a member

or leader in diverse teams, and in multidisciplinary settings.
10. Communication: Communicate effectively on complex engineering activities

with the engineering community and with society at large, such as, being able to
comprehend and write effective reports and design documentation, make effective
presentations, and give and receive clear instructions.
11. Project management and finance: Demonstrate knowledge and understanding of

the engineering and management principles and apply these to one’s own work, as a
member and leader in a team, to manage projects and in multidisciplinary
environments.
12. Life-long learning: Recognize the need for, and have the preparation and ability to
engage in independent and life-long learning in the broadest context of technological change.
PSO-Program Specific Objectives
1. An ability to understand the concepts of basic Electronics & Communication

Engineering and to apply them to various areas like Signal processing, VLSI,
Embedded systems, Communication Systems, Digital & Analog Devices, etc.
2. An ability to solve complex Electronics and Communication Engineering problems,

using latest hardware and software tools, along with analytical skills to arrive cost
effective and appropriate solutions.
3. Wisdom of social and environmental awareness along with ethical responsibility to

have a successful career and to sustain passion and zeal for real-world applications
using optimal resources as an Entrepreneur.
Program Educational Objectives

PEO I: To develop the ability among students to understand the concept of core electronics
subjects that will facilitate understanding of new technology.
PEO II: To embed a strong foundation in the engineering fundamentals to solve, analyze and
design real time engineering products.
PEO III: To give exposures to emerging edge technologies, adequate training and
opportunities to work as team on multidisciplinary projects with effective communication
skills and leadership qualities.
Digital Electronics Lab -18ECL38 2019-
20
DIGITAL ELECTRONICS LAB

SEMESTER – III (EC/TC)
[As per Choice Based Credit System (CBCS) Scheme]
Laboratory Code 18ECL38 CIE Marks 40
Number of Lecture 01Hr Tutorial (Instructions) + SEE Marks 60
Hours/Week 02 Hours Laboratory
RBT Level L1, L2, L3 Exam Hours 03
CREDITS – 02
Course objectives: This laboratory course enables students to get practical experience in
design, realisation and verification of Demorgan‘s Theorem, SOP, POS forms
Full/Parallel Adders, Subtractors and Magnitude Comparator Demultiplexers and
Decoders applications Flip-Flops, Shift registers and Counters
NOTE:
1. Use discrete components to test and verify the logic gates. The IC umbers given are
suggestive. Any equivalent IC can be used.
2. For experiment No. 11 and 12 any open source or licensed simulation tool may be used.
Laboratory Experiments: Page Marks
No
1. Verify (a) Demorgan‘s Theorem for 2 variables. (b) The sum-of 04-07
product and product-of-sum expressions using universal gates.
2. Design and implement (a) Full Adder using (i) basic logic gates and 08-12
(ii) NAND gates. (b) Full subtractor using (i) basic logic gates and (ii)
NANAD gates.
3. Design and implement 4-bit Parallel Adder/ Subtractor using IC 13-15
7483.
4. Design and Implementation of 5-bit Magnitude Comparator using IC 16-17
7485.
5. Realize (a) Adder & Subtractor using IC 74153. 18-22
(b) 3-variable function using IC 74151(8:1MUX).
6. Realize a Boolean expression using decoder IC74139. 23-24
7. Realize Master-Slave JK, D & T Flip-Flops using NAND Gates. 25-27
8. Realize the following shift registers using IC7474/IC 7495 28-32
(a) SISO (b) SIPO (c) PISO (d) PIPO (e) Ring and (f) Johnson counter.
Dept. of ECE M.S. Engineering College Page 1

20
9. Realize (i) Mod-N Asynchronous Counter using IC7490 and 33-

35
ii) Mod-N Synchronous counter using IC74192
10. Design Pseudo Random Sequence generator using 7495. 36-
37
11. Simulate Full- Adder using simulation tool.
12. Simulate Mod-8 Synchronous UP/DOWN Counter using simulation
tool.
Average = Total Marks scored / Total Number of Exp
Course Outcomes:
On the completion of this laboratory course, the students will be able to: Demonstrate the truth
table of various expressions and combinational circuits using logic gates. Design and test
various combinational circuits such as adders, subtractors, comparators, multiplexers. Realize
Boolean expression using decoders. Construct and test flips-flops, counters and shift registers.
Simulate full adder and up/down counters.
Conduct of Practical Examination:
All laboratory experiments are to be included for practical examination. Students are allowed
to pick one experiment from the lot. Strictly follow the instructions as printed on the cover
page of answer script for breakup of marks. Change of experiment is allowed only once and
Marks allotted to the procedure part to be made zero.
IA Evaluation
Record Conduction of Lab Internals Total
maintenance
Write up Execution of the Viva
(weekly submission) required Result
10M 10M 15M 5M 40M

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Experiment No: 1(A) Date:

Demorgan’s Theorem for 2 variables
Aim: To verify Demorgan’s theorem for 2 variables
Components required: IC7404, 7432, 7408, Digital IC Trainer Kit, Patch cords
Theory:-
Theorem 1: The compliment of the product of two variables is equal to the sum of the
compliment of each variable. Thus according to De-Morgan’s laws or DeMorgan's theorem if
A and B are the two variables or Boolean numbers. Then accordingly,
Theorem 2: The compliment of the sum of two variables is equal to the product of the
compliment of each variable. Thus according to De Morgan’s theorem if A and B are the two
variables then,
De-Morgan's laws can also be implemented in Boolean algebra in the following steps:-
1. While doing Boolean algebra at first replace the given operator. That is (+) is replaced
with (.) and (.) is replaced with (+).
2. Compliment of each of the term is to be found.
Procedure:
1. Realize the Demorgans theorem using logic gates.
2. Connect VCC and ground as shown in the pin diagram.
3. Make connections as per the logic gate diagram.
4. Apply the different combinations of input according to the truth tables.
Verify that the results are correct.

20

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Experiment No: 1(B) Date:

Sum of Product and Product of Sum
Aim: To design sum-of product and product-of-sum expressions using Basic gates and
Universal gates.
Components Required: IC 7408 (AND), IC 7404 (NOT), IC 7432 (OR), IC 7400(NAND),
IC 7402 (NOR), IC 7486 (EX-OR), IC Trainer Kit, Patch cords
Theory:
Canonical Forms (Normal Forms): Any Boolean function can be written in disjunctive
normal form (sum of min-terms) or conjunctive normal form (product of max-terms).A
Boolean function can be represented by a Karnaugh map in which each cell corresponds to
two minterm.
Sum of minterms : Sum Of Product (SOP)
Product of maxterms : Product Of Sum (POS)
Procedure:
1. Verify that the gates are working.
2. Construct a truth table for the given problem.
3. Draw a Karnaugh Map corresponding to the given truth table.
4. Simplify the given Boolean expression manually using the Karnaugh Map. A.
Implementation Using Logic Gates:
5. Realize the simplified expression using logic gates.
6. Connect VCC and ground as shown in the pin diagram.
7. Make connections as per the logic gate diagram.
8. Apply the different combinations of input according to the truth tables.
Verify that the results are correct.
B. Implementation Using Universal Gates:
1. Convert the AND-OR logic into NAND-NAND and NOR-NOR logic.
2. Realize the simplified Boolean expressions using only NAND gates, and then using only
NOR gates.
3. Connect the circuits according to the circuit diagrams, apply inputs according to the truth
table and verify the results.

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Result:

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Experiment No: 2 Date:

ADDERS AND SUBTRACTORS
Aim: (i) To realize half/full adder using Logic gates & NAND gates
(ii) To realize half/full Subtractor using Logic gates & NAND gates
Components Required:
IC 7408, IC 7432, IC 7486, IC 7404, IC 7400, Patch cords
Theory:
Half-Adder: A combinational logic circuit that performs the addition of two data bits, A and
B, is called a half-adder. Addition will result in two output bits; one of which is the sum bit S,
and the other is the carry bit, C. The Boolean functions describing the half-adder are:
Truth Table
A B S =A⊕B C = A.B
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
S =A⊕B C = A.B

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Full-Adder: The half-adder does not take the carry bit from its previous stage into account.
This carry bit from its previous stage is called carry-in bit. A combinational logic circuit that
adds two data bits, A and B, and a carry-in bit, Cin , is called a full-adder. The Boolean
functions describing the full-adder are:
Truth Table
A B C S C=
=A⊕B⊕C A.B+C(A+B)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Realization using basic gates
Realization using NAND gates
S = A ⊕B ⊕ Cin C = A.B+ Cin (A + B)

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Half Subtractor: Subtracting a single-bit binary value B from another A (i.e. A-B) produces
a difference bit D and a borrow out bit Br. This operation is called half subtraction and the
circuit to realize it is called a half subtractor. The Boolean functions describing the half-
Subtractor are:
Truth Table
A B D =A⊕B Br = A.B
0 0 0 0
0 1 1 1
1 0 1 1
1 1 0 0
D =A ⊕ B Br= A’.B
(ii) Using NAND gates

Full Subtractor: Subtracting two single-bit binary values, B, Cin from a single-bit value A
produces a difference bit D and a borrow out Br bit. This is called full subtraction. The
Boolean functions describing the full subtractor are:
D = A⊕ B ⊕ Cin
Br= A’.B + A’ .Cin + B . Cin

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Truth Table
A B C S C=
=A⊕B⊕C A’.B+A’.C+B.C
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Procedure:
1. Verify for working of the gates.
2. Make the connections as per the circuit diagram for the half adder circuit, on the trainer
kit.

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3. Switch on the VCC power supply and apply the various combinations of the inputs
according to the respective truth tables.
4. Verify that the outputs are according to the expected results.
5. Repeat the procedure for the full adder circuit, the half subtractor and full subtractor
circuits.
6. Verify that the sum/difference and carry/borrow bits are according to the expected values.
Result:

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PARALLEL ADDER AND SUBTRACTOR USING 7483
Aim: To design and set up the following circuit using IC 7483.
i) A 4-bit binary parallel adder.
ii) A 4-bit binary parallel subtractor.
Components Required: IC 7483, IC 7486, Patch Cords etc.
Theory:
The Full adder can add single-digit binary numbers and carries. The largest sum that can be
obtained using a full adder is (11)2. Parallel adders can add multiple-digit numbers. If full
adders are placed in parallel, we can add two- or four-digit numbers or any other size desired.
1. 4-BIT BINARY ADDER
Example: 7+2=09 which is equal to (1001)2
• 7 is realized at A3 A2 A1 A0 = 0111
• 2 is realized at B3 B2 B1 B0 = 0010 Sum = (1001)2
Procedure for Adding two 4-Bit data:

1. Check all the components for their working.
2. Insert the appropriate IC into the IC base.

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3. Make connections as shown in the circuit diagram.

4. Apply augend and addend bits on A and B and cin=0.
5. Verify the results and observe the output of ADDER CIRCUIT
2. 4-Bit Binary Subtractor.
(i) 4 bit subtraction operation using 7483 for A>B and Cin=1
Example: 8 – 3 = 5 which is equal to (0101)2
• 3 is realized at B3 B2 B1 B0 through X-OR gates = 0011
• Output of X-OR gate is 1’s complement = 1100
• 2’s Complement can be obtained by adding Cin =1
Therefore Cin =1
A3 A2 A1 A0 = 1 0 0 0
B3 B2 B1 B0 = 1 1 0 0
S3 S2 S1 S0 = 0 1 0 1 Cout = 1 (Ignored)
(ii) 4 bit subtraction operation using 7483 for A<B and Cin=1
Example: 14 – 15 = -1 (1111)2
• 15 is realized at B3 B2 B1 B0 through X-OR gates = 1111
• Output of X-OR gate is 1’s complement of 15 = 0000
• 2’s Complement can be obtained by adding Cin = 1
Therefore Cin = 1
A3 A2 A1 A0 = 1 1 1 0
B3 B2 B1 B0 = 0 0 0 0
S3 S2 S1 S0 = 1 1 1 1
Since the most significant bit of the result is 1, this is a negative number, so form the two's
complement of (1111)=-(0001)2

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Procedure for subtracting two 4-Bit data:

4. Apply Minuend and subtrahend bits on A and B and cin=1.
5. Verify the results and observe the outputs.
Result:

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COMPARATOR
Aim: To realize 5 Bit magnitude comparator using IC 7485.
Components required: IC 7485, Patch Cords & IC Trainer Kit.
Theory:
Magnitude Comparator is a logical circuit, which compares two signals A and B and
generates three logical outputs, whether A > B, A = B, or A < B. IC 7485 is a high speed
4-bit Magnitude comparator, which compares two 4-bit words. The A = B Input must
be held high for proper compare operation.
OR

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Procedure:
3. Make connections as shown in the circuit diagram. 4. Apply 0 for the bits A5, A6, A7,
B5, B6, B7 OR ground them. 5. Apply given data to the rest of the bits.
6. Verify the results and observe the outputs.
Result:

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Experiment No: 5(a) Date:

REALIZATION OF ADDER AND SUBTRACTOR USING IC 74153
Aim: To design adder and subtractor using IC 74153
Components Required: IC 74153, Patch Cords & IC Trainer Kit.
Theory:
Multiplexers are very useful components in digital systems. They transfer a large number of
information units over a smaller number of channels, (usually one channel) under the control
of selection signals.
Multiplexer means many to one. A multiplexer is a circuit with many inputs but only one
output. By using control signals (select lines) we can select any input to the output.
Multiplexer is also called as data selector because the output bit depends on the input data bit
that is selected. The general multiplexer circuit has 2n input signals, n control/select signals
and 1 output signal.
Pin Daigram:

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Procedure:
1. The connection is made as shown in the diagram.
2. Here, S1 and S0 are the channel selection lines,I0, I1, I2, I3 are the respective data lines of
the channels and Y is the output.
3. Based on the selection lines one of the inputs will be selected at the output, and thus the
truth table is verified.
Result:

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Experiment No: 5(b) Date:
REALIZATION OF 3 VARIABLE FUNCTION USING IC 74151 (8:1 MUX)

Aim: To design and set up the following circuit
3 variables function using IC 74151 (8:1 MUX)
Components Required: IC74151, Patch Cords & IC Trainer Kit.
B. 3 Variable function using IC 74151

Pin Diagram
Procedure:
1. For the given expression, a truth table is to be written.
2. An expression in SOP format is to be written.
3. The connection is made according to the obtained expression.
4. The truth table is verified for that particular expression.

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Result:

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REALIZE A BOOLEAN EXPRESSION USING DECODER IC 74139
Aim: To realize a Boolean expression using decoder IC 74139
Components Required: IC74139, Patch Cords & IC Trainer Kit.
Theory: A decoder is a combinational circuit that connects the binary information from “n”
input lines to a maximum of 2n unique output lines. Decoder is also called a min-term
generator/maxterm generator. A min-term generator is constructed using AND and NOT
gates. The appropriate output is indicated by logic 1 (positive logic). Max-term generator is
constructed using NAND gates. The appropriate output is indicated by logic 0 (Negative
logic). The IC 74139 accepts two binary inputs and when enable provides 4 individual active
low outputs. The device has 2 enable inputs (Two active low).
Pin Diagram:

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Procedure:
1. For the given Boolean expression, a truth table is to be written.
2. An expression in SOP format is to be written.
3. The connection is made according to the obtained expression.
4. The truth table is verified for that particular expression.
Result:

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Aim: To realize the following Flip-flops using NAND gate: Master slave JK , D and T
Flip-flops.
Components required: IC 7410, IC7400, Patch Cords
Theory:
A flip-flop is a circuit that has two stable states and can be used to store state information. A
flip-flop is a bistable multivibrator. The circuit can be made to change state by signals applied
to one or more control inputs and will have one or two outputs. It is the basic storage element
in sequential logic. Flip-flops and latches are a fundamental building block of digital
electronics systems used in computers, communications, and many other types of systems.
A flip–flop is a “bit bucket”; it holds a single binary bit .Flip flops are actually an application
of logic gates. With the help of Boolean logic we can create memory with them. Flip flops
can also be considered as the most basic idea of a Random Access Memory [RAM].
The most commonly used application of flip flops is in the implementation of a feedback
circuit. As a memory relies on the feedback concept, flip flops can be used to design it.
Procedure:
1. Make the connections as shown in the circuit diagrams.
2. Apply inputs as shown in the truth tables,
3. Check the outputs of the circuits; verify that they match with truth table.

20

20

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SHIFT REGISTERS
Aim: Realize the following shift registers using IC7495
(a)SISO (b) SIPO (c)PISO (d) PIPO (e) Ring and (f) Johnson Counter.
Components required: IC 7495, patch cords etc.
Theory:
• A shift register is a group of flip-flops (typically 4 or 8) that are arranged so that the values
stored in the flip-flops are shifted from one flip-flop to the next for every clock.
• Shift registers are used extensively in logic circuits to control digital displays.
• A classic example is numbers being typed into a calculator. As the numbers are entered, the
digits shift to the left one position. This shifting is controlled by a shift register.
(a).SERIAL INPUT SERIAL OUTPUT (SISO):

Procedure:
1. Connections are made as shown in the SISO circuit diagram.
2. Make sure the 7495 is operating in SISO mode by ensuring Pin 6 (Mode) is set to
LOW, and connect clock input to Clk 1(Pin 9).
3. The shift register is loaded with 4 bits of data one by one serially.
4. At the end of the 4thclock pulse, the first data ‘d0’ appears at QD.
5. Apply another clock pulse, to get the second data bit, ‘d1’ at QD. Applying yet
another clock pulse gets the third data bit, ‘d2’ at QD, and so on.

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(b). SERIAL INPUT PARALLEL OUTPUT (SIPO/Right Shift):

Procedure:
1. Connections are made as shown in the SISO circuit diagram.
2. Make sure the 7495 is operating in SIPO mode by ensuring Pin 6 (Mode) is set to
LOW, and connect clock input to Clk 1(Pin 9).
3. Apply the first data at pin 1 (SD1) and apply one clock pulse. We observe that this
data appears at pin 13 (QA).
4. Now, apply the second data at SD1. Apply a clock pulse. We now observe that the
earlier data is shifted from QA to QB, and the new data appears at QA.
5. Repeat the earlier step to enter data, until all bits are entered one by one.
6. At the end of the 4th clock pulse, we notice that all 4 bits are available at the
parallel output pins QA through QD.

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© PARALLEL INPUT SERIAL OUTPUT (PISO):

Procedure:
1. Connections are made as shown in the PISO circuit diagram.
2. Now apply the 4-bit data at the parallel I/P pins A, B, C, D (pins 2 through 5).
3. Keeping the mode control M on HIGH, apply one clock pulse. The data applied at
the parallel input pins A, B, C, D will appear at the parallel output pins QA, QB, QC,
QD respectively.
4. Now set the Mode Control M to LOW, and apply clock pulses one by one. Observe
the data coming out in a serial mode at QD.
5. We observe now that the IC operates in PISO mode with parallel inputs being
transferred to the output side serially.
(e). PARALLEL INPUT PARALLEL OUTPUT (PIPO):

Procedure:
1. Connections are made as shown in the PIPO mode circuit diagram.
2. Set Mode Control M to HIGH to enable Parallel transfer.
3. Apply the 4 data bits as input to pins A, B, C, D.
4. Apply one clock pulse at Clk 2 (Pin 8).
5. Note that the 4 bit data at parallel inputs A, B, C, D appears at the
Parallel output pins QA, QB, QC, QD respectively.

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(e). Ring Counter and (f) Johnson Counter

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Theory:
A ring counter is a circular shift register which is initiated such that only one of its
flip-flops is the state one while others are in their zero states.
A ring counter is a Shift Register with the output of the last one connected to the input
of the first, that is, in a ring. Typically, a pattern consisting of a single bit is circulated
so the state repeats every n clock cycles if n flip-flops are used. It can be used as a
cycle counter of n states.
A Johnson counter (or switch tail ring counter, twisted-ring counter, walking-ring
counter, or Moebius counter) is a modified ring counter, where the output from the
last stage is inverted and fed back as input to the first stage. The register cycles
through a sequence of bit-patterns, whose length is equal to twice the length of the
shift register, continuing indefinitely. These counters find specialist applications,
including those similar to the decade counter, digital-to-analog conversion, etc. They
can be implemented easily using D- or JK-type flip-flops.
Procedure:
1. Make the connections as shown in the respective circuit diagram.
2. Initial condition is set by setting up the circuit as shown in the figure.
3. Apply clock and observe the output after each clock pulse, record the observations
and verify that they match the expected outputs from the truth table.
4. Repeat the same procedure as above for the Johnson Counter circuit and verify its
operation.
Result:

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REALIZE I) MOD N ASYNCHRONOUS COUNTER USING IC7490
II) MOD N SYNCHRONOUS COUNTER USING IC74192
Aim: To rig up Mod N asynchronous counter using IC 7490 and synchronous counter
using IC 74192.
Components required: IC7490, Patch cords, trainer kit, etc.
Procedure:
3. Clock pulses are applied one by one at the clock input and output is observed at
QA, QB, QC and QD
4. Verify the Truth Table and observe the outputs.
Note: Internal block diagram of IC 7490

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Circuit diagram: Count up from 3 to 8

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Circuit diagram: Count down from 12 to 5
Note: IC 74192 is BCD Counter and IC 74193 is Binary Counter.
Result:

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DESIGN PSEUDO RANDOM SEQUENCE GENERATOR USING IC 7495
Aim: To design and study the operation of a pseudo random Sequence generator
using 7495.
Components required: IC 7495, IC 7486, Patch Cords & IC Trainer kit.
Procedure:
1. Truth table is constructed for the given sequence, and Karnaugh maps are drawn in
order to obtain a simplified Boolean expression for the circuit.
2. Connections are made as shown in the circuit diagram.
3. Mode M is set to LOW (0), and clock pulses are fed through Clk 1 (pin 9).
4. Clock pulses are applied at CLK 1 and the output values are noted, and checked
against the expected values from the truth table.
5. The functioning of the circuit as a sequence generator is verified.

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Result:

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M S Engineering College

Navarathna Agrahara, Sadahalli Post

Digital Electronics Lab Manual

• To inculcate best engineering practices amongst students through quality education,

• To make the institute to be recognized as among the leading institutions imparting

 Continually improve the effectiveness and quality management system.

 Our commitment to achieve total customer satisfaction by assuring successful

 By providing training at all the levels with placement assistance.

 Use of modern technology and its conditional up gradation.

 Participation of all the stakeholders to meet the expectations.

2. Problem analysis: Identify, formulate, review research literature, and analyze

3. Design/development of solutions: Design solutions for complex engineering

7. Environment and sustainability: Understand the impact of the professional

8. Ethics: Apply ethical principles and commit to professional ethics and

9. Individual and team work: Function effectively as an individual, and as a member

10. Communication: Communicate effectively on complex engineering activities

11. Project management and finance: Demonstrate knowledge and understanding of

1. An ability to understand the concepts of basic Electronics & Communication

2. An ability to solve complex Electronics and Communication Engineering problems,

3. Wisdom of social and environmental awareness along with ethical responsibility to

Program Educational Objectives

DIGITAL ELECTRONICS LAB

Dept. of ECE M.S. Engineering College Page 1

9. Realize (i) Mod-N Asynchronous Counter using IC7490 and 33-

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Experiment No: 1(A) Date:

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Experiment No: 1(B) Date:

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Experiment No: 2 Date:

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Realization using NAND gates

S = A ⊕B ⊕ Cin C = A.B+ Cin (A + B)

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(ii) Using NAND gates

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Experiment No: 3 Date:

Procedure for Adding two 4-Bit data:

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3. Make connections as shown in the circuit diagram.

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Procedure for subtracting two 4-Bit data:

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Experiment No: 4 Date:

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Experiment No: 5(a) Date:

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Experiment No: 5(b) Date:

REALIZATION OF 3 VARIABLE FUNCTION USING IC 74151 (8:1 MUX)

B. 3 Variable function using IC 74151

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