2.

1 8085 PROGRAMMING
2.1.1 Addressing Modes (Ref2: Section 0.9.2)
Operand indicates the data on which specified operation is to be performed by the
processor. It could be provided in three ways: data may be in a register, memory location
or included in the instruction itself. Addressing mode implies the way in which an operand
is presented for execution. There are five addressing modes in 8085 processor: register
addressing, direct addressing, immediate addressing, indirect addressing and implied
addressing.
Register addressing: all the operands are registers. eg: MOV A, B; ADD C.
Direct addressing: operand is a memory location and its address is mentioned in the
instruction. eg: STA address; LDA address.
Immediate addressing: source operand is a data of 8 /16-bits and is included in the
instruction itself. eg: MVI B, data; ORI data
Indirect addressing: One of the operands is a memory location and indirectly specified.
i.e. instead of providing the address directly, it is loaded into a 16-bit register pair and its
name is mentioned in the instruction. eg. MOV C, M; STAX B.
Implied addressing: Operands are obvious from the opcode itself and will not be
mentioned specifically. eg. CMA; STC
2.2.2 Instruction Set Classification (Ref1: Section 2.2)
An instruction is a binary pattern implemented inside a microprocessor to perform a
specific function. The list of all instructions, called instruction set, shows what functions a
processor can perform. The 8085 instruction set consists of 74 basic instructions and
considering all variations, total number of instructions in the set is 246. The instructions
are classified into five functional categories: data transfer, arithmetic, logical, branching
and machine control.
Data transfer (copy): This group of instructions copies data from one location (source) to
another (destination) without changing the source contents. Flags bits are not affected
during the process. The data transfer can be of following types:
a) between two registers (eg: MOV A, B)
b) between memory location & register (eg: LDA address, MOV C, M)
c) specific data byte to a register / memory location (eg: MVI D, data)
d) between an I/O device & accumulator (eg: IN port address, OUT port address)
Arithmetic: This group of instructions performs arithmetic operations such as addition,
subtraction, increment and decrement. One of the operands will be the accumulator for
addition / subtraction operations. (ADD H, INR E, SUI Data)
Logical: These instructions perform logical operations such as AND, OR, XOR, Rotate,
Compare and Complement. For all logical instructions, one operand will be the
accumulator. (ANA D, ORI Data, CMP L)
Branching: This group of instructions alters the sequence of program execution either
conditionally or unconditionally. They include functions like Jump, Call, Return and Restart.
(JZ address, JNC address, CALL address)
Machine Control: These instructions control machine functions. They are Halt, Interrupt
and No Operation. (HLT, EI, DI, NOP)
Note: The size of an instruction may vary between 1-3 bytes. Instructions that mention
an 8-bit data are two byte long while those consisting of 16-bit data/address are 3-byte
type. All other instructions belong to 1-byte type.
2.2.3 Simple Program example (NOT FOR EXAM)
Program to find out the sum of two 8-bit numbers stored in memory locations 4500H and
4501H.
4100 LDA 4500H
4103 MOV B,A
4104 LDA 4501H
4107 ADD B
4108 STA 4600H
410B HLT

2.2.4 Integrated Development Environment (IDE) (Ref1: Section 11.2-11.4)

(NOT FOR EXAM)
Assembly language program for an 8085 system can be developed in a Windows PC using
the outlined steps:
1. Editing: Writing the assembly language program.
2. Assembling: Converting the mnemonics into object code.
3. Linking: Creating an executable binary code out of the program.
4. Simulation: Verifying the program execution.
5. Debugging: Troubleshooting the program.

The IDE is a collection of software tools that enables the user to develop programs for the
desired processor.
EDITOR: It allows the user to enter, modify and store a group of text under a file name.
The process is known as editing. Editors are of two types: line editors (such as Notepad)
work with one line at a time and full screen editors (word processors such as MS-Word)
manage a full screen of information at a time. While saving the program for 8085, it must
be given file extension .asm so that it can be recognized by the subsequent tools. The file
thus generated is called source code.
ASSEBLER: It is the tool that translates source code into binary code form and generates
object file. This function is similar to hand assembly, in which user looks up the code for
each mnemonic in the list. Assembler also perform related functions such as error checking
and memory address allocation. Together with object file, assembler also generates a list
file and a HEX file. The former is for documentation purpose and latter will be downloaded
to the target system at the end of the development cycle.
While using assembler, it is to be noted that the target system and program development
PC must have same processor. However, cross-assembler is an assembler that can
generate the object code for desired processor while working on a system with different
processor. i.e. if a Pentium based PC to being used to develop the program for an 8085
system, then cross-assembler is required for the process.
LINKER: It accepts the object file and generates an executable file in binary code.
SIMULATOR: It enables the user to execute the generated program in PC without having
the target system so that the program can be verified. There may also be facilities to
observe intermediate results.
DEBUGGER: It allows the user to test and debug the program file. Following functions are
usually possible in debugging:
• Make changes in program file
• Examine and modify memory contents
• Set breakpoints and display register contents
• Trace the program execution one instruction at a time
• Disassemble the program
Note: After the development process, the binary code (HEX file) of the program is
transferred to the target system. Once downloaded, the program can be executed in the
target system independently.

2.3 8085 MACHINE CYCLES AND BUS TIMINGS

• Instruction size in 8085 varies between 1-3 bytes.
• To execute an instruction, processor may perform multiple machine cycles.
• Basic machine cycles are:
1. Opcode fetch
2. Memory read
3. Memory write
4. I/O read
5. I/O write
6. Interrupt Acknowledgement
2.3.1 Opcode fetch
• Getting the opcode (first byte of the instruction) from memory into microprocessor.
• First operation in any instruction cycle.
• At T1: Place the status signals, higher address byte, lower address byte, assert ALE
• At T2: Asserts RD signal, gets opcode 3EH from memory into data bus → PC
incremented to 2001H.
• At T3: Place opcode in IR, RD is disabled.
• At T4: Opcode is decoded, next course of action is decided.
2.3.2 Memory read
 • Getting the value stored in the location 2001H to Accumulator.
• At T1: Place status signals, higher address byte, lower address byte, assert ALE.
• At T2: Asserts RD signal, gets value from memory into data bus → PC incremented
to 2002H.
• At T3: Value placed in Acc → RD is disabled.
2.3.3 Timing diagram for the instruction MVI A, 32H
• This instruction needs two machine cycles to complete the operation → one opcode
fetch and one memory read.
• Figure below shows the combined timing diagram for the instruction.

Calculation of time requirement of an instruction

Let clock f = 2 MHz
T-state = 1/f = 0.5µS
Execution time for opcode fetch (4T)=2µS
Execution time for memory read(3T)=1.5µS
Execution time for instruction (7T) =3.5µS
2.3.4. Memory write
• Storing the value in Acc into the location 2001H.
• At T1: Place status signals, higher address byte, lower address byte, assert ALE.
 • At T2: Asserts WR signal, value 32H from Acc is placed in data bus → PC incremented
to 2002H.
• At T3: Value stored in location 2001H → WR is disabled.

2.4 PERIPHERAL INTERFACING ICs

• I/O devices are of different functions and specifications.
• Microprocessor cannot manage them appropriately → needs extra hardware to
handle them.
• Various interfacing ICs designed → programmable.
1. Programmable Peripheral Interface
2. Programmable Interval Timer
3. Programmable Serial Communication Interface
4. Programmable Keyboard / Display Interface
2.5 PROGRAMMABLE PERIPHERAL INTERFACEN (PPI-8255)
• Widely used, flexible, economical.
• Can be used with any Intel microprocessor.
• 24 bidirectional I/O lines → 3 ports: PORT A, PORT B, PORT C.

• Port A & Port B are 8-bit ports.

• Port C → used either as two 4-bit ports (PCU , PCL) or 8 one-bit ports.
 • Port A and PCU → Group A

• Port B and PCL → Group B

2.5.1 Block diagram

• IC8255 Consists of two 8-bit ports (PA & PB), two 4-bit ports (PCU & PCL), data bus
buffer and control logic.

1. PORT A, B, C:
• Contains three ports (PA, PB and PC).
• Port A & Port B are 8-bit ports.

• Port C → used either as two 4-bit ports (PCU , PCL) or eight 1-bit ports.

2. Group A & Group B control:

• Functionally, the ports are grouped under two sets → Group A & Group B.
• Port A and PCU → Group A.
• Port B and PCL → Group B.
• Group control blocks receives control information and issues commands to the
associated ports.
3. Data Bus Buffer:
• 8-bit tri-state buffer to interface the chip to the system data bus.
• Data, control word and status information are transferred through the data bus.
4. Read/Write Control:
• To control the internal operation.
• To control the transfer of data, control word or status words.
• Accepts inputs from address bus and control bus of µP → issues command to other
blocks.
a) CS (Chip Select):
➢ Low on this input selects the PPI for communication with µP.
➢ Derived from the address bus using a logic circuit.
b) A1, A0 (Port Select):
➢ Select desired port or control register for writing / reading.
➢ Control register can only be written into → no reading.
➢ Note : Signals CS, A1 & A0 together decides the port addresses.

c) RD (Read):
➢ Low on this input enables the read operation. i.e. data on the selected port
is read into CPU through data bus.
d) WR (Write):
➢ Low on this input enables the write operation. i.e. data is written into the
selected port or control register.
2.5.2 Functional Modes
• Basically two functional modes :
1. BSR mode → Bit Set Reset → for Port C only → can handle each bit in PC
individually.
2. I/O mode → for all ports → further options : mode 0,1,2.
 I/O mode operation
a) Mode 0:
• All ports are simple input / output ports.
• Each port can be programmed to function as I/P or O/P.
• No handshake facility
b) Mode 1:
• Handshake mode.
• Port A & Port B are used as 8bit i/p or o/p port.
• 3 bits of PCU & PCL are used as handshake signals for PA & PB respectively.
• Remaining 1 bit each of PCU & PCL - simple I/O functions.
• Handshake signals (with PA / PB as input):
1) STB (strobe input) : Signal from I/O device to indicate that data is sent.
2) IBF (input buffer full) : Acknowledgement by PPI on obtaining STB to
indicate that the data is received.
3) INTR (interrupt request) : Interrupt signal sent by PPI to µP on obtaining
STB → µP immediately reads the data from the port of PPI.
• Handshake signals (with PA / PB as output) are:
1) OBF (output buffer full) : Signal sent by PPI to peripheral device when a
data byte is received from µP → Data also transferred.
2) ACK (Acknowledgement) : Sent by peripheral device on obtaining data byte.
3) INTR (interrupt request) : Interrupt signal sent by PPI to µP to request for
next data byte.
c) Mode 2:
• Bidirectional communication with handshake.
• Applicable only to Port A.
• Mainly used for data transfer between two computers.
• Five bits of Port C are used for control signals.
• Port B may be programmed independently in mode 0 or 1.
• Remaining 3 bits of Port C may be used for simple I/O or handshake of PB.
Control word
• Function of the ports (i/p or o/p, mode etc.) is decided by writing a control word
into the control register of PPI.

• Control word is an 8 bit pattern → D7 – D0

• If D7 is 1 → I/O mode; if D7 is 0 → BSR mode.
 BSR Control word

I/O Control word

2.6 PROGRAMMABLE INTERVAL TIMER (PIT-8253)

• Generates accurate time delay.
• Applications include one shot generator, event counter, time measurement between
two events, RTC etc.
• IC8253 → 24 pin IC → maximum clock 2.6 MHz.
• Three 16-bit counters → six possible modes of operation.
• IC8254 is an upgraded version → pin compatible → can operate with higher clock
frequency.
2.6.1 Block Diagram
• Includes 3 counters, Read / write control logic, data bus buffer and control register.

•
1. Data Bus Buffer : 8-bit tri-state bidirectional buffer to interface the chip to the
µP data bus.
2. Control Word Register : Command word to specify counter to be used, mode,
etc.
3. Control logic :
RD & WR are used for specifying read or write operation → Address lines A1 &
A0 → select counter / control register.
CS → to select the chip via decoding circuitry.
4. Count registers
16-bit count value is loaded to the register of selected counter → Decremented
at each clock until reaches 0.
Gate → used to enable / disable the counter.
OUT → used to indicate the end of counting.
2.6.2 Modes of operation
• IC8253 can operate in one of six possible modes.
1. Mode 0: Interrupt on terminal count
➢ OUT pin is low initially → count value loaded into the register → counter
decremented in each clock → OUT goes high when count register reaches
zero → this can be used as an interrupt.
 2. Mode 1: Hardware-Retriggerable one-shot
➢ OUT is initially high → OUT goes low when GATE is triggered → goes high
again at the end of the count → thus creates a one-shot pulse.
3. Mode 2: Rate generator
➢ To generate a pulse equal to the clock period.
➢ OUT stays high during counting until reaches 1 → goes low for one clock
period → count value reloaded automatically → pulses equal to one clock
period are generated continuously.
4. Mode 3: Square wave generator
➢ OUT is high → count loaded → decremented by 2 for each clock → when
reaches zero, OUT goes low → count reloaded → decremented by 2 for each
clock → OUT is high → this process repeated.
➢ Thus, a continuous square wave with period equal to count is generated.
5. Mode 4: Software-Triggered Strobe
➢ OUT is initially high → goes low for one clock at the end of the count.
6. Mode 5: Hardware-Triggered Strobe
➢ Similar to mode4 except that it is triggered by the rising pulse of the gate.
➢ OUT is low initially → count begins when gate is triggered → at the end of the
count, OUT goes low for one clock period.
2.6.3 Control word
2.7 PROGRAMMABLE KEYBOARD / DISPLAY INTERFACE (8279)
• Interfacing matrix keyboard & multiplexed display.
• 40 pin IC → two segments → Keyboard, display.
• Keyboard entries are stored in internal FIFO memory → interrupt generated.
• Display segment has RAM → character code is stored.
2.7.1 Block diagram
• Four major sections : Keyboard, scan, display, µP interface.

Keyboard section:
• The eight lines RL0 – RL7 connected to eight columns of keyboard.
• 8 X 8 FIFO RAM → 8 registers of 8 bit size.
• Keypress is stored in FIFO RAM → interrupt request is generated.
• Status of Shift, CNTL/STB are also stored.
• Keys automatically debounced.
• Two modes → 2 Key lockout, N Key roll over.
• 2 key lockout → if two keys are pressed simultaneously, only first key is
recognized.
• N key roll over → simultaneous keys are recognized
Scan section:
• Scan counter & 4 scan lines SL0 – SL3 → row selection.
• Used for both keyboard section and display section.
a) Decoded mode
➢ scan lines give 4 values repeatedly → 1110, 1101, 1011, 0111.
➢ Selects one of 4 rows in keyboard (4 X 8 keyboard).
➢ Connects four 7 segment displays.
b) Encoded mode
➢ Scan lines give 4 bit binary count → external 4 to 16 decoder attached.
➢ Selects one of the 8 rows of keyboard (8X8 keyboard).
➢ Connects sixteen 7-segment LEDs
Display section:
• Codes for characters to be displayed are stored in 16 X 8 display RAM.
• Display registers A , B → 4 bits → holds bit pattern of character to be displayed.
• Eight output lines in two groups → A0 – A3 & B0 – B3
• Can also be used as one group of 8 lines.
• Output lines are connected to 7 segment LEDs.
µP interface section:
• Eight bidirectional data lines (DB0-DB7) connecting to Data bus.
• A0 → Buffer address → 0 for data & 1 for control word / status.
• IRQ → interrupt request → set when data exists in FIFO RAM.
• CLK → works with 100KHz.
• RESET → resetting the device.
• RD → to specify read operation.
• WR → to specify write operation.
• CS → to select the chip via decoding circuitry.
2.7.2 Keyboard interface working
• Scan lines helps to scan keyboard rows one by one → selected row has logic 0 at
its input.
• If any key in that row is pressed, corresponding RL line becomes logic low.
• Using row & column numbers, depressed key is identified → ASCII code is stored
in FIFO RAM.
• IRQ is generated → processor read the key code.
2.7.3 Display interface working
• Code for character to be displayed is stored in display RAM.
 • Using scan lines, desired display is chosen
• Code is transferred to display the character.
2.8 SERIAL I/O CONCEPTS
• 8085 transfers 8-bit data over data bus → parallel mode.
• In serial mode, one bit data is transferred at a time over a single line → parallel to
serial conversion needed.
• Also, start bit and stop bit are required in asynchronous serial communication.
• Implemented through software or programmable chips.
• In 8085, software controlled serial transmission is via the pins SID & SOD →
hardware approach is USART.
• IC8251 is a USART → programmable, widely used.
2.9 PROGRAMMABLE COMMUNICATION INTERFACE (8251)
• Designed for synchronous and asynchronous serial data communication.
• Control logic determines the functions of the chip as per control word.
• Modem control → to set up data communication over telephone lines.
• Data bus buffer interfaces the chip with µP data bus.
2.9.1 Block diagram
Read / Write Control Logic:
• Consists of three buffer registers → control register for holding control word,
status register to indicate the ready status of the peripheral, bi-directional data
register for holding the data.
• There are six input signals to the control logic.
a) CS (Chip Select): to select 8251 → connected to address bus through a
decoding circuitry.
b) C/D (control / data) when high, control or status register is addressed → when
low, data bus buffer is accessed.
c) WR (write): µP is going to write into the chip.
d) RD (read): µP is going to read from the chip.
e) RESET : To reset the chip.
f) CLK: the clock input → usually connected to system clock.
Transmitter section:
• Converts parallel data from µP into serial stream and transmit via TxD line with
appropriate framing bits.
Receiver section:
• Receives serial stream from peripheral device via RxD line, removes framing bits,
converts into parallel data and transfers to µP.

Reference:
1. Ramesh S. Goankar. 8085 Microprocessors Architecture Application and
Programming. Penram International, 5/e.
2. Lyla B.Das : Microprocessors and Microcontrollers, Pearson Education,2011.