HEF4521B

24-stage frequency divider and oscillator

Rev. 05 — 5 November 2009 Product data sheet

1. General description
The HEF4521B consists of a chain of 24 toggle flip-flops with an overriding asynchronous
master reset input (MR), and an input circuit that allows three modes of operation. The
single inverting stage (A2 to Y2) will function as: a crystal oscillator, an input buffer for an
external oscillator or in combination with A1 as an RC oscillator. The crystal oscillator
operates in Low-power mode when pins VSS1 and VDD1 are supplied via external resistors.

Each flip-flop divides the frequency of the previous flip-flop by two, consequently the
HEF4521B will count up to 224 = 16777216. The counting advances on the HIGH-to-LOW
transition of the clock (A2). The outputs from each of the last seven stages (218 to 224) are
available for additional flexibility.

It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS

(usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is
also suitable for use over the full industrial (−40 °C to +85 °C) temperature range.

2. Features
n Low power crystal oscillator operation
n Fully static operation
n 5 V, 10 V, and 15 V parametric ratings
n Standardized symmetrical output characteristics
n Operates across the full industrial temperature range −40 °C to +85 °C
n Complies with JEDEC standard JESD 13-B

3. Applications
n Industrial

4. Ordering information
Table 1. Ordering information
All types operate from −40 °C to +85 °C.
Type number Package
Name Description Version
HEF4521BP DIP16 plastic dual in-line package; 16-leads (300 mil) SOT38-4
HEF4521BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
NXP Semiconductors HEF4521B
24-stage frequency divider and oscillator

5. Functional diagram

5 4 2 9

VDD1 Y2 MR A1

A2
6 CP
STAGES 1 to 8
VSS1 CD Q8
3

CP
STAGES 9 to 16
CD Q16

CP
STAGES 17 to 24
CD

Q24 Q18 Q19 Q20 Q21 Q22 Q23 Y1

1 10 11 12 13 14 15 7
001aae708

Fig 1. Functional diagram

VDD1
VDD

A2 to FFs to logic

VSS
VSS1

Y2 001aae711

Fig 2. Schematic diagram of clock input circuitry

HEF4521B_5 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 05 — 5 November 2009 2 of 17

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Product data sheet
HEF4521B_5

NXP Semiconductors
MR A1
Y2
Q Q Q Q Q Q Q Q
FF 1 FF 2 FF 3 FF 4 FF 5 FF 6 FF 7 FF 8
A2 T T T T T T T T

VSS1
CD CD CD CD CD CD CD CD

VDD1

Q Q Q Q Q Q Q Q
FF 9 FF 10 FF 11 FF 12 FF 13 FF 14 FF 15 FF 16
T T T T T T T T

CD CD CD CD CD CD CD CD
Rev. 05 — 5 November 2009

Q Q Q Q Q Q Q Q
FF 17 FF 18 FF 19 FF 20 FF 21 FF 22 FF 23 FF 24
T T T T T T T T

CD CD CD CD CD CD CD CD

24-stage frequency divider and oscillator

Q24 Q18 Q19 Q20 Q21 Q22 Q23 Y1
001aae710

Fig 3. Logic diagram

HEF4521B
© NXP B.V. 2009. All rights reserved.
3 of 17
NXP Semiconductors HEF4521B
24-stage frequency divider and oscillator

6. Pinning information

6.1 Pinning

HEF4521B

Q24 1 16 VDD

MR 2 15 Q23

VSS1 3 14 Q22

Y2 4 13 Q21

VDD1 5 12 Q20

A2 6 11 Q19

Y1 7 10 Q18

VSS 8 9 A1

001aae709

Fig 4. Pin configuration

6.2 Pin description

Table 2. Pin description
Symbol Pin Description
MR 2 master reset input
VSS1 3 ground supply voltage 1
VDD1 5 supply voltage 1
Y1, Y2 7, 4 external oscillator connection
VSS 8 ground supply voltage
A1, A2 9, 6 external oscillator connection
Q18 to Q24 10, 11, 12, 13, 14, 15, 1 output
VDD 16 supply voltage

7. Count capacity
Table 3. Count capacity
Output Count capacity
Q18 218 = 262144
Q19 219 = 524288
Q20 220 = 1048576
Q21 221 = 2097152
Q22 222 = 4194304
Q23 223 = 8388608
Q24 224 = 16777216

HEF4521B_5 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 05 — 5 November 2009 4 of 17

NXP Semiconductors HEF4521B
24-stage frequency divider and oscillator

8. Functional Test
A test function has been included to reduce the test time required to test all 24 counter
stages. This test function divides the counter into three 8-stage sections by connecting
VSS1 to VDD and VDD1 to VSS. 255 counts are loaded into each of the 8-stage sections in
parallel via A2 (connected to Y2). All flip-flops are now at a HIGH level. The counter is now
returned to the normal 24-stage in series configuration by connecting VSS1 to VSS and
VDD1 to VDD. Entering one more pulse into input A2 will cause the counter to ripple from
an all HIGH state to an all LOW state.

Table 4. Functional test sequence

Inputs Control terminals Outputs Remarks
MR A2 Y2 VSS1 VDD1 Q18 to Q24
H L L VDD VSS L counter is in three 8-stage sections in parallel mode; A2 and Y2
are interconnected (Y2 is now input); counter is reset by MR.
L see see VDD VSS H 255 pulses are clocked into A2, Y2. The counter advances on
Remarks Remarks the LOW to HIGH transition.
column column
L L L VSS VSS H VSS1 is connected to VSS.
L H L VSS VSS H the input A2 is made HIGH.
L H L VSS VDD H VDD1 is connected to VDD; Y2 is now made floating and
becomes an output; the device is now in the 224 mode.
L ↓ VSS VDD L counter ripples from an all HIGH state to an all LOW state.

[1] H = HIGH voltage level; L = LOW voltage level; ↓ = HIGH to LOW transition.

9. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDD supply voltage −0.5 +18 V
IIK input clamping current VI < −0.5 V or VI > VDD + 0.5 V - ±10 mA
VI input voltage −0.5 VDD + 0.5 V
IOK output clamping current VO < −0.5 V or VO > VDD + 0.5 V - ±10 mA
II/O input/output current - ±10 mA
IDD supply current to any supply terminal - ±100 mA
Tstg storage temperature −65 +150 °C
Tamb ambient temperature −40 +85 °C
Ptot total power dissipation DIP16 package [1] - 750 mW
SO16 package [2] - 500 mW
P power dissipation per output - 100 mW

[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C.

HEF4521B_5 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 05 — 5 November 2009 5 of 17

NXP Semiconductors HEF4521B
24-stage frequency divider and oscillator

10. Recommended operating conditions

Table 6. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
VDD supply voltage 3 - 15 V
VI input voltage 0 - VDD V
Tamb ambient temperature in free air −40 - +85 °C
∆t/∆V input transition rise and fall rate VDD = 5 V - - 3.75 µs/V
VDD = 10 V - - 0.5 µs/V
VDD = 15 V - - 0.08 µs/V

11. Static characteristics

Table 7. Static characteristics
VSS = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter Conditions VDD Tamb = −40 °C Tamb = 25 °C Tamb = 85 °C Unit
Min Max Min Max Min Max
VIH HIGH-level input voltage |IO| < 1 µA 5V 3.5 - 3.5 - 3.5 - V
10 V 7.0 - 7.0 - 7.0 - V
15 V 11.0 - 11.0 - 11.0 - V
VIL LOW-level input voltage |IO| < 1 µA 5V - 1.5 - 1.5 - 1.5 V
10 V - 3.0 - 3.0 - 3.0 V
15 V - 4.0 - 4.0 - 4.0 V
VOH HIGH-level output voltage |IO| < 1 µA 5V 4.95 - 4.95 - 4.95 - V
10 V 9.95 - 9.95 - 9.95 - V
15 V 14.95 - 14.95 - 14.95 - V
VOL LOW-level output voltage |IO| < 1 µA 5V - 0.05 - 0.05 - 0.05 V
10 V - 0.05 - 0.05 - 0.05 V
15 V - 0.05 - 0.05 - 0.05 V
IOH HIGH-level output current VO = 2.5 V 5V −1.7 - −1.4 - −1.1 - mA
VO = 4.6 V 5V −0.52 - −0.44 - −0.36 - mA
VO = 9.5 V 10 V −1.3 - −1.1 - −0.9 - mA
VO = 13.5 V 15 V −3.6 - −3.0 - −2.4 - mA
IOL LOW-level output current VO = 0.4 V 5V 0.52 - 0.44 - 0.36 - mA
VO = 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA
VO = 1.5 V 15 V 3.6 - 3.0 - 2.4 - mA
II input leakage current 15 V - ±0.3 - ±0.3 - ±1.0 µA
IDD supply current IO = 0 A 5V - 20 - 20 - 150 µA
10 V - 40 - 40 - 300 µA
15 V - 80 - 80 - 600 µA
CI input capacitance - - - - 7.5 - - pF

HEF4521B_5 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 05 — 5 November 2009 6 of 17

NXP Semiconductors HEF4521B
24-stage frequency divider and oscillator

12. Dynamic characteristics

Table 8. Dynamic characteristics
VSS = 0 V; Tamb = 25 °C; for test circuits see Figure 6; unless otherwise specified.
Symbol Parameter Conditions VDD Extrapolation formula Min Typ Max Unit
tPHL HIGH to LOW A2 to Q18; 5V [1] 923 ns + (0.55 ns/pF) CL - 950 1900 ns
propagation delay see Figure 5 10 V 339 ns + (0.23 ns/pF) CL - 350 700 ns
15 V 212 ns + (0.16 ns/pF) CL - 220 440 ns
Qn to Qn + 1; 5V 13 ns + (0.55 ns/pF) CL - 40 80 ns
see Figure 5 10 V 4 ns + (0.23 ns/pF) CL - 15 30 ns
15 V 2 ns + (0.16 ns/pF) CL - 10 20 ns
MR to Qn 5V 93 ns + (0.55 ns/pF) CL - 120 240 ns
10 V 44 ns + (0.23 ns/pF) CL - 55 110 ns
15 V 32 ns + (0.16 ns/pF) CL - 40 80 ns
A1 to Y1; 5V 63 ns + (0.55 ns/pF) CL - 90 180 ns
see Figure 5 10 V 24 ns + (0.23 ns/pF) CL - 35 70 ns
15 V 17 ns + (0.16 ns/pF) CL - 25 50 ns
tPLH LOW to HIGH A2 to Q18; 5V [1] 923 ns + (0.55 ns/pF) CL - 950 1900 ns
propagation delay see Figure 5 10 V 339 ns + (0.23 ns/pF) CL - 350 700 ns
15 V 212 ns + (0.16 ns/pF) CL - 220 440 ns
Qn to Qn + 1; 5V 13 ns + (0.55 ns/pF) CL - 40 80 ns
see Figure 5 10 V 4 ns + (0.23 ns/pF) CL - 15 30 ns
15 V 2 ns + (0.16 ns/pF) CL - 10 20 ns
A1 to Y1; 5V 33 ns + (0.55 ns/pF) CL - 60 120 ns
see Figure 5 10 V 19 ns + (0.23 ns/pF) CL - 30 60 ns
15 V 12 ns + (0.16 ns/pF) CL - 20 40 ns
tt transition time Qn; see Figure 5 5V [1] 10 ns + (1.00 ns/pF) CL - 60 120 ns
10 V 9 ns + (0.42 ns/pF) CL - 30 60 ns
15 V 6 ns + (0.28 ns/pF) CL - 20 40 ns
tW pulse width A2 HIGH; 5V 80 40 - ns
minimum width; 10 V 40 20 - ns
see Figure 5
15 V 30 15 - ns
MR HIGH; 5V 70 35 - ns
minimum width; 10 V 40 20 - ns
see Figure 5
15 V 30 15 - ns
trec recovery time MR; see Figure 5 5V +20 −10 - ns
10 V +15 −5 - ns
15 V 15 0 - ns
fmax maximum frequency A1; see Figure 5 5V 6 12 - MHz
10 V 12 25 - MHz
15 V 17 35 - MHz

[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).

HEF4521B_5 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 05 — 5 November 2009 7 of 17

NXP Semiconductors HEF4521B
24-stage frequency divider and oscillator

Table 9. Dynamic power dissipation PD

PD can be calculated from the formulas shown. VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C.
Symbol Parameter VDD Typical formula for PD (µW) where:
PD dynamic power 5V PD = 1200 × fi + Σ(fo × CL) × VDD2 fi = input frequency in MHz,
dissipation 10 V PD = 5100 × fi + Σ(fo × CL) × VDD2 fo = output frequency in MHz,
15 V PD = 13050 × fi + Σ(fo × CL) × VDD 2 CL = output load capacitance in pF,
VDD = supply voltage in V,
Σ(CL × fo) = sum of the outputs.

13. Waveforms

VI

MR input VM

0V
tW
1/fmax
VI

A2 input VM

0V
trec tW
tPHL tPLH
VOH
90 %
Qn output
10 %
VOL
tt tt
001aae712

a. Pulse widths, maximum frequency, recovery and transition times and A2 to Qn propagation delays

VI VOH

A1 input VM Qn output VM

0V VOL
tPLH tPHL tPLH tPHL

VOH VOH

Y1 output VM Qn + 1 output VM

VOL VOL
Y1 propagation delays Qn to Qn + 1 propagation delays
001aak015

b. A1 to Y1, MR to Qn and Qn to Qn + 1 propagation delays

Measurement points are given in Table 10.
The logic levels VOH and VOL are typical output voltage levels that occur with the output load.
Fig 5. Waveforms showing measurement of dynamic characteristics

HEF4521B_5 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 05 — 5 November 2009 8 of 17

NXP Semiconductors HEF4521B
24-stage frequency divider and oscillator

tW
VI
90 %
negative
pulse VM VM
10 %
0V
tf tr

tr tf
VI
90 %
positive
pulse VM VM
10 %
0V
tW
001aaj781

a. Input waveforms

VDD

VI VO
G DUT

RT CL

001aag182

b. Test circuit
Test data is given in Table 10.
Definitions for test circuit:
Device Under Test (DUT);
CL = Load capacitance including jig and probe capacitance;
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
Fig 6. Test circuit for switching times

Table 10. Measurement points and test data

Supply voltage Input Load
VI VM tr, tf CL
5 V to 15 V VDD 0.5VI ≤ 20 ns 50 pF

HEF4521B_5 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 05 — 5 November 2009 9 of 17

NXP Semiconductors HEF4521B
24-stage frequency divider and oscillator

14. Application information

VDD

Ro 1.8 MΩ R(1)

VDD VDD1

A1 Y1
Y2
Q18
A2
HEF4521B

CS CT

MR Q24

VSS VSS1

R(1)

001aae713

(1) Optional for low power operation.

Fig 7. Crystal oscillator circuit

Table 11. Typical characteristics for crystal oscillator

See Figure 7.
Parameter 500 kHz circuit 50 kHz circuit Unit
Crystal characteristics
Resonance frequency 500 50 kHz
Crystal cut S N -
Equivalent resistance; RS 1 6.2 kΩ
External resistor/capacitor values
Ro 47 750 kΩ
CT 82 82 pF
CS 20 20 pF

HEF4521B_5 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 05 — 5 November 2009 10 of 17

NXP Semiconductors HEF4521B
24-stage frequency divider and oscillator

001aae715
RTC VDD 102
C
fosc (1)
(kHz)
RS VDD VDD1

A1 Y1 10
Y2 (2)

Q18
A2
HEF4521B

MR Q24

VSS VSS1

10−1
1 10 102 RTC (kΩ) 103
001aae714 10−1 1 10 C (nF) 102

1 VDD = 10 V; The test circuit is shown in Figure 8.

f ≈ ---------------------------------- ; R S ≥ 2R TC , where:
2.3 × R TC × C (1) RTC; C = 1 nF; RS ≈ 2 RTC.
(2) C; RTC = 56 kΩ; RS = 120 kΩ.
f is in Hz, R is in Ω, and C is in F.

V IL ( max )
R S + R TC < --------------------- , where:
I LI

VIL(max) = maximum input voltage LOW; and

ILI = input leakage current.

Fig 8. RC oscillator circuit Fig 9. Oscillator frequency as a function of

RTC and C

HEF4521B_5 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 05 — 5 November 2009 11 of 17

NXP Semiconductors HEF4521B
24-stage frequency divider and oscillator

001aae658
12.5
gfs
(mA/V)
10
(1)

7.5
(2)
Rbias

560 kΩ 5 (3)
VDD

0.47 µF 100 µF 2.5

A2 Y2

Vi input output io
A
(f = 1 kHz)
0
VSS 0 5 10 15
001aae820 VDD (V)

gfs = dio/dvi with vo constant (see Figure 11). (1) Average + 2 s.

(2) Average.
(3) Average − 2 s, where ‘s’ is the observed standard
deviation.
Fig 10. Test setup for measuring forward Fig 11. Typical forward transconductance gfs as a
transconductance function of the supply voltage at Tamb = 25 °C

001aae716 001aae717
75 20

IDD
gain (mA)
(VO/VI)
15
50
typ
typ
10

25
5

0 0
0 5 10 15 0 5 10 15
VDD (V) VDD (V)

Fig 12. Voltage gain VO/VI as a function of supply Fig 13. Supply current as a function of supply voltage
voltage

330 kΩ

A2 Y2
001aae718

Fig 14. Test setup for measuring the Figure 12 and Figure 13 graphs

HEF4521B_5 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 05 — 5 November 2009 12 of 17

NXP Semiconductors HEF4521B
24-stage frequency divider and oscillator

15. Package outline

DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4

D ME
seating plane

A2 A

L A1

c
Z e w M
b1
(e 1)
b b2
16 9 MH

pin 1 index
E

1 8

0 5 10 mm
scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

UNIT
A A1 A2
b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1)
max. min. max. max.
1.73 0.53 1.25 0.36 19.50 6.48 3.60 8.25 10.0
mm 4.2 0.51 3.2 2.54 7.62 0.254 0.76
1.30 0.38 0.85 0.23 18.55 6.20 3.05 7.80 8.3

inches 0.068 0.021 0.049 0.014 0.77 0.26 0.14 0.32 0.39
0.17 0.02 0.13 0.1 0.3 0.01 0.03
0.051 0.015 0.033 0.009 0.73 0.24 0.12 0.31 0.33

Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

95-01-14
SOT38-4
03-02-13

Fig 15. Package outline SOT38-4 (DIP16)

HEF4521B_5 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 05 — 5 November 2009 13 of 17

NXP Semiconductors HEF4521B
24-stage frequency divider and oscillator

SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

D E A
X

y HE v M A

16 9

Q
A2
(A 3) A
A1
pin 1 index
θ
Lp

1 8 L

e w M detail X
bp

0 2.5 5 mm
scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ
max.
0.25 1.45 0.49 0.25 10.0 4.0 6.2 1.0 0.7 0.7
mm 1.75 0.25 1.27 1.05 0.25 0.25 0.1 o
0.10 1.25 0.36 0.19 9.8 3.8 5.8 0.4 0.6 0.3 8
o
0.010 0.057 0.019 0.0100 0.39 0.16 0.244 0.039 0.028 0.028 0
inches 0.069 0.01 0.05 0.041 0.01 0.01 0.004
0.004 0.049 0.014 0.0075 0.38 0.15 0.228 0.016 0.020 0.012

Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

99-12-27
SOT109-1 076E07 MS-012
03-02-19

Fig 16. Package outline SOT109-1 (SO16)

HEF4521B_5 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 05 — 5 November 2009 14 of 17

NXP Semiconductors HEF4521B
24-stage frequency divider and oscillator

16. Revision history

Table 12. Revision history
Document ID Release date Data sheet status Change notice Supersedes
HEF4521B_5 20091105 Product data sheet - HEF4521B_4
Modifications: • Section 2 “Features” ESD values removed.
• Section 10 “Recommended operating conditions” ∆t/∆V values updated.
• Abbreviations section removed.
HEF4521B_4 20090421 Product data sheet - HEF4521B_CNV_3
HEF4521B_CNV_3 19950101 Product specification - HEF4521B_CNV_2
HEF4521B_CNV_2 19950101 Product specification - -

HEF4521B_5 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 05 — 5 November 2009 15 of 17

NXP Semiconductors HEF4521B
24-stage frequency divider and oscillator

17. Legal information

17.1 Data sheet status

Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.

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NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in Applications — Applications that are described herein for any of these
modifications or additions. NXP Semiconductors does not give any products are for illustrative purposes only. NXP Semiconductors makes no
representations or warranties as to the accuracy or completeness of representation or warranty that such applications will be suitable for the
information included herein and shall have no liability for the consequences of specified use without further testing or modification.
use of such information. Limiting values — Stress above one or more limiting values (as defined in
Short data sheet — A short data sheet is an extract from a full data sheet the Absolute Maximum Ratings System of IEC 60134) may cause permanent
with the same product type number(s) and title. A short data sheet is intended damage to the device. Limiting values are stress ratings only and operation of
for quick reference only and should not be relied upon to contain detailed and the device at these or any other conditions above those given in the
full information. For detailed and full information see the relevant full data Characteristics sections of this document is not implied. Exposure to limiting
sheet, which is available on request via the local NXP Semiconductors sales values for extended periods may affect device reliability.
office. In case of any inconsistency or conflict with the short data sheet, the Terms and conditions of sale — NXP Semiconductors products are sold
full data sheet shall prevail. subject to the general terms and conditions of commercial sale, as published
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notice. This document supersedes and replaces all information supplied prior
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18. Contact information

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]

HEF4521B_5 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 05 — 5 November 2009 16 of 17

NXP Semiconductors HEF4521B
24-stage frequency divider and oscillator

19. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Ordering information . . . . . . . . . . . . . . . . . . . . . 1
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7 Count capacity . . . . . . . . . . . . . . . . . . . . . . . . . . 4
8 Functional Test. . . . . . . . . . . . . . . . . . . . . . . . . . 5
9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
10 Recommended operating conditions. . . . . . . . 6
11 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
12 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
13 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
14 Application information. . . . . . . . . . . . . . . . . . 10
15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13
16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15
17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
17.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
17.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
17.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
17.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
18 Contact information. . . . . . . . . . . . . . . . . . . . . 16
19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.

© NXP B.V. 2009. All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 5 November 2009
Document identifier: HEF4521B_5