Lecture 27: Metallization and

polishing

Contents
1 Metallization basics 1

2 Metallization materials 5
2.1 Aluminum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Al-Si alloys . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Al-Cu alloys . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4 Pure Cu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Metallization techniques 8
3.1 Physical vapor deposition (PVD) . . . . . . . . . . . . . . . . 8
3.2 CVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.3 Electroplating . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4 Planarization 12

5 Copper dual-damascene process 14

1 Metallization basics
Integrated circuit fabrication is traditionally divided into two segments, that
follow one after the other in the fab.

1. FEOL (Front end of the line) - these refer to the fabrication of the
active and passive elements of the circuit. These are the resistors (or
conductors), capacitors, diodes, and transistors that make up the var-
ious elements of the IC.

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2. BEOL (Back end of the line) - these are the metallic layers that are
used to make the interconnections between the various components
fabricated in FEOL and also to the connections for the external devices.
With increase in device complexity, the separation of the IC processing into
two segments is also important in terms of device fabrication. Current metal-
lization in the IC industry is based on copper, which is a deep defect forming
impurity in Si. Thus, Cu contamination in Si can destroy device functional-
ity. By separating the fabrication into two segments, it is possible to isolate
the Si processing from the metals (primarily Cu) and prevent contamina-
tion. There are strict process and physical separation between the FEOL
and BEOL.
Metallization refers to the “wiring” of the various components together to
get a functioning circuit. In the first IC fabricated (by Jack Kilby) metal con-
nections were made by external wiring (aluminum). Future devices, starting
from the modifications made by Robert Noyce, had metal lines that were
fabricated along with the IC. Typical steps in patterning a metal layer are
shown in figure 1. There are a variety of techniques for depositing metal
layers in a IC.
1. Sputtering is a physical vapor deposition process mainly used for Al
and its alloys e.g. Al-Cu alloys
2. Chemical vapor deposition (CVD) is mainly used for poly Si (for
gate in MOSFET) and tungsten (metal plugs for trench filling). It is
also used for depositing barrier layers (silicides and nitrides) between
Si and Cu.
3. Electroplating is used for Cu deposition (dual-damascene process)
With increase in level of integration, the metallization materials have changed.
At the same time, the number of metal layers required have also increased
(due to decrease in available area between the components). In MSI (medium
scale integration), a single layer of metallization was sufficient, as shown in
figure 1. But with increase in integration level, the number of metal layers
have also increased.
A two level metallization scheme is shown in figure 2. The first level of metals
provides the connection to the semiconductor i.e. the source, drain, and gates
of a transistor. This is done by creating contact holes, using a photomask,
a process called contact masking. Then, metal lines are vapor deposited and
the excess metal is removed during lift-off. Usually, there is also a post an-
nealing step for alloying. The metal lines are then further connected to each
other, to form circuits, and then to the external devices by using a second

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Figure 1: Sequence of steps in metallization. Here, the metal line connects a

doped region to the rest of the wafer. For this, (a) the wafer is (b) patterned
using a soft lithography mask. (c) The metal layer is deposited uniformly
and (d) the mask, with the rest of the metal is removed. Adapted from
Microchip fabrication - Peter van Zant.

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Figure 2: A two level metallization scheme. The first layer of metal makes
contact with the junctions in the device, while the second layer of metal
makes contact with the first layer and also with the external circuit. The
connections are made by defining trenches, called vias, which are separated
by dielectrics. Adapted from Microchip fabrication - Peter van Zant.

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Figure 3: A four level metallization scheme. With increase in integration

the number of metal layers also increases. This is because the individual
contacts are spaced closer and hence there is not enough area to make all
the electrical connections in one level. Adapted from Microchip fabrication -
Peter van Zant.

level of metallization. The two levels are separated by interlayer dielectrics

to prevent shorting. This is called intermetallic dielectric layer (IML). The
levels can be extended to more than two, depending on the integration level.
A four layer scheme is shown in figure 3. Current IC technology (28 nm
technology) has eleven layers of metallization. A cross sectional image of
the metal layers is shown in figure 4.

2 Metallization materials
2.1 Aluminum
The original metal used for wiring was pure Al. In the first circuit design
proposed by Robert Noyce, pure Al was used for fabricating the wires. The
main advantage of using Al is that it can be easily vapor deposited (simple
thermal evaporation will work since Al has a low melting point). It also has
good adhesion to SiO2 , low contact resistance, and it is easy to pattern since

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Figure 4: Eleven layers of metallization. The Si transistor is right at the

bottom and in terms of scale much smaller than the top metal layers. The
top layer makes contact with the leads for connections to external devices.
Source http://electroiq.com/chipworks real chips blog/2012/12/11/intel-
details-22nm-trigate-soc-process-at-iedm/

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Figure 5: Contact issues in Al-Si contacts. (a) Excess alloying leads to

melting of the Al(b) Silicide formation in the metal layer, by using a Al-Si
alloy (c) Barrier metal is usually deposited to prevent reaction between Al
and Si. Adapted from Microchip fabrication - Peter van Zant.

thermal evaporation can be integrated with resist lithography technology.

2.2 Al-Si alloys

The problem with pure Al is that it has a low melting point of 660 ◦ C. When
Al in contact with pure Si is heated, it forms an alloy with an eutectic point
of 577 ◦C. This leads to dissolution of metal, especially in the formation of
shallow junctions, and can lead to shortening of the contacts, as shown in
figure 5.
There are two solutions to this. One is to use a barrier metal that does
not alloy with Al or Si and separates the two. The barrier metal should
not significantly reduce the conduction through the channel. Typically, high
temperature metals like Ti and W or compounds like TiN are used. These
are sputter deposited on the wafer. Another option is to use Al with 1-2%
Si as the contact material. This minimizes Al alloying with the Si wafer but
does not eliminate it completely. Thermal evaporation of Al-Si might now
work due to the large difference in the melting points of the two elements
and other techniques like sputtering or e-beam evaporation are needed to
maintain compositions of the contact.

2.3 Al-Cu alloys

With increase in device integration (from MSI to LSI and VLSI), the thick-
ness of the metal layers decreases. This leads to the problem of electro-
migration, especially in thin Al layers. This is because thin films with an
electrical field gradient, due to the applied voltage, also develop a thermal
gradient due to resistive heating. The thermal gradient is acute for thinner

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layers since their resistance is higher. This causes local heating and migration
of material from thinner areas of the wire, which can cause an open circuit.
To reduce electromigration, 0.5-4% Cu is usually added to Al. Cu alloys
with Al, to form CuAl2 precipitates (GP zones). These precipitates pin the
grain boundaries and reduce electromigration. Sometimes Si is also added
to prevent Si dissolution from the wafer. The typical alloy composition for a
metal layer is Al-1.5%Si-4%Cu.

2.4 Pure Cu
With smaller metal layers, Al-Cu has a high resistance (high resistivity of
Al alloy) and hence to increase wire conductance pure Cu replaced Al as the
metallization layer. Pure Cu contacts were introduced by IBM in 1990s and
the standard was quickly adopted across the industry. Cu can be easily met-
allized. It can be deposited by thermal evaporation, but more importantly, it
can be electroplated on the wafer, which decreases the cost, since expensive
vacuum chamber equipment is not needed. The biggest problem is that Cu
diffuses into Si and SiO2 . These form deep level defects in Si which can ‘kill’
the device. Hence, a barrier metal, usually TiW or TiN or TaN or metal sili-
cides, is needed. These can be deposited by sputtering or for deep trenches,
can be deposited by chemical vapor deposition. As mentioned earlier, the
use of Cu separates the wafer manufacturing into FEOL and BEOL, with
strict physical separation between the two to prevent contamination. Usu-
ally, equipment involved in FEOL and BEOL are placed in different locations
in the fab and special clothing is used for people working with BEOL tools.

3 Metallization techniques
3.1 Physical vapor deposition (PVD)
There are a variety of physical vapor deposition techniques. As the name
implies, atoms/molecules (vapor) of the desired material are directly de-
posited on to the substrate from the vapor phase. There are different PVD
techniques, which differ on the how the ‘vapor’ is obtained. PVD is a line-
of-sight deposition technique, so that the substrate must be in front of the
source. The deposition rate depends on the distance between the two. The
simplest PVD technique is thermal evaporation. A schematic of the process
is shown in figure 6. The material to be evaporated is heated (by resistive
heating) and the atoms are then deposited on the substrate.
E-beam evaporation, is a deposition technique, where instead of using resis-

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Figure 6: Thermal evaporator unit. The metal is vaporized by resistive heat-

ing and then deposited on the wafers. The evaporation source is a tungsten
filament that can be heated by passing current. Multiple sources are possible
in a single chamber. Adapted from Microchip fabrication - Peter van Zant.

tive heating to form the vapor, an electron beam is used to melt the material
and form the vapor. The e-beam evaporation source is shown in 7. E-beam
evaporator is useful for depositing materials with high melting points like Si,
Ti, W, which cannot be easily deposited by thermal evaporation.
Both, thermal evaporation and e-beam evaporation have deposition rates of
a few Å per second. For depositing thick films (few hundred nm to µm),
sputtering is used. The schematic of the sputter deposition process is shown
in figure 8. In sputter deposition, the material to be deposited is made the
target electrode. This can be a pure metal, alloy or even compounds. Sput-
tering process can maintain the stoichiometry of the target electrode, unlike
thermal or e-beam evaporation. An inert gas, like argon, is introduced in the
vacuum chamber. They are ionized by using an electron beam and the accel-
erated ions strike the target electrode and remove material, a process called
sputtering. Thus, the ‘vapor’ is created by the positively charged ions. The
vapor atoms are then deposited on the substrate. The advantage of sputter-
ing is that deposition rates of a few nm per second can be easily obtained.
There are three main sputtering techniques: DC, RF and magnetron sput-
tering. Their difference lies in how the Ar ions are accelerated and made
to strike the target. In magnetron sputtering, magnetic fields are used to

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Figure 7: An e-beam evaporator unit. An electron beam is focused on the

crucible and used to melt the metal. The vapor formed is then deposited
on the substrate. The advantage of e-beam evaporator is that high melting
point metals can be deposited and contamination minimized, since there is
only local melting of the source. Adapted from Microchip fabrication - Peter
van Zant.

Figure 8: Schematic of the sputter deposition process. Energetic ions impinge

on a target and remove atoms, which are then deposited on the substrate.
High deposition rates and composition control can be achieved in sputtering.
Adapted from Microchip fabrication - Peter van Zant.

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Figure 9: Schematic of the magnetron sputtering process. Magnetic field are

used to direct the electron beam to ionize the gas in front of the target. This
increased deposition rate and greater contamination control. Adapted from
Microchip fabrication - Peter van Zant.

confine the electrons in front of the target to increase the ionization of the
Ar gas and thus increase deposition rate. This also results in lower chamber
pressure requirement, making this a cleaner process. The schematic of the
magnetron sputtering process is shown in figure 9.

3.2 CVD
The CVD process was seen earlier in the context of deposited films. In
metallization, CVD process is used for the deposition of the barrier layer that
separates the metal from Si. This is good for large aspect ratio structures,
as shown in figure 10. A typical reaction for depositing tungsten is by the
reduction of tungsten hexaflouride.

2W F6 + 3Si → 2W + 3SiF4
(1)
2W F6 + 3H2 → 2W + 6HF

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Figure 10: CVD process for growing conformal layers on deep trenches. De-
position on large aspect ratio structures cannot be done by PVD techniques,
since the method will cover the hole before depositing deep inside the trench.
Source http://abelson.matse.illinois.edu/

3.3 Electroplating
The electroplating process is commonly used for the deposition of copper.
The advantage is the low cost and temperature requirements, compared to
other vacuum deposition techniques. High deposition rates can be obtained,
compared to PVD processes. Electroplating requires a uniform seed layer.
This is obtained by sputtering and the seed layer is 30-200 nm thick. The
electroplating bath is shown in figure 11. The wafer, containing the seed
layer, is made the cathode. The copper to be deposited is the electrolyte (in
the form of CuSO4 ). This is reduced in the bath (equation shown in figure
11) and the Cu is then plated on the wafer surface. The process leads to
a copper overfill, creating a rough surface and the excess material is then
removed by polishing.

4 Planarization
Planarization is a process of achieving a flat profile on the wafer surface.
This is important for lithography, since a flat wafer is needed to avoid reg-
istration errors when the mask is aligned with the wafer and to get proper

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Figure 11: Schematic of the electroplating process. Electroplating is usually

used for copper deposition. A seed layer is first deposited by PVD process,
usually sputtering. Then the material is dipped in the bath containing copper
ions. During electrochemical reaction, copper is deposited on the seed layer.
Adapted from Microchip fabrication - Peter van Zant.

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Figure 12: Non planarized vs. planarized IC. The difference lies in the rough-
ness of the various interfaces, which can lead to change in electrical properties.
Source http://linx-consulting.com/Specialty-abrasives-CMP.html

focusing. Most deposition process produce a surface with a finite rough-

ness which usually increases with increased deposition rate and thickness.
Chemical mechanical polishing (CMP) is a technique to achieve global
planarization, i.e. over the entire wafer. The difference between a planarized
and non-planarized wafer is shown in figure 12.
In planarization, the wafer is mounted on a rotating platen. It is then pol-
ished using a polishing pad and a slurry containing abrasive particles. The
abrasive particles attack the wafer surface and remove small particles. The
polishing pad and platen rotate in opposite directions and the slurry carries
away the small particles. This removal is the mechanical polishing part. The
slurry material is chosen such that it can also dissolve or etch the surface
material away. This constitutes the chemical removal part and hence, the
technique is called CMP. The schematic of the CMP process is shown in fig-
ure 13. Typically, the polishing pad is made of polyurethane foam, while the
slurry depends on the material to be removed. For metals, usually alumina
is used, while etchants like KOH and NH4 OH are used for silicon oxide pol-
ishing. After CMP, there is a post cleaning step that involves cleaning the
wafers with de-ionized water and then N2 blow drying. This removes any
excess slurry particles from the wafer surface.

5 Copper dual-damascene process

Current IC fabrication uses the Cu metallization process that has replaced
the use of Al-Cu alloys. Cu has a lower resistivity and lower electromigration

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Figure 13: Schematic of a planarization setup. The wafer is help upside

down on a rotating platen. A slurry is aupplied to the surface, that helps
in material removal. The platen can be heated/cooled, while both the wafer
and platen are rotated. It is also possible to move the wafer across the platen
surface. Source https://www.crystec.com/alpovere.htm

effect as compared to Al. But copper has its own set of problems, in that,
it is hard to remove by etching and can diffuse easily through the SiO2 layer
and form deep defects in Si. Cu also has poor adhesion on SiO2 so this can
cause structural issues, especially when used in multilayers. The damascene
process is a unique series of steps that was developed for copper metalliza-
tion, for large scale production. It features a lithography process, followed
by a low-k dielectric or barrier layer deposition, separating the metal layers,
copper electroplating, and chemical mechanical polishing of the metal. The
process resembles the damascene process that was developed in the Middle
ages around Damascus in Syria, which was used for metal inlay work on ar-
tifacts.
In a multilayer metallization scheme, there are inter layer dielectrics (ILD)
separating the various metal layers, see figures 2, 3, and 4. SiO2 can be used
as the dielectric layer but this has a problem for high performance circuits
due to the RC constant of the circuit system, where R stands for the resis-
tance and C for the capacitance. The main contributor to the capacitance
component is the dielectric constant of the of the ILD. SiO2 has a dielectric
constant of 3.9 and a lower value is preferable for faster circuit operation. A
variety of low k dielectrics (1.5-2.0 range) have been developed. These are
based on metal oxides or organic based. Some of the low k dielectrics are
listed in table 1.

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Table 1: List of low k dielectric materials for inter layer dielectrics. Adapted
from Microchip fabrication - Peter van Zant.
Metal system Low-k material
Aluminum parylene
hydrogen silsesquioxane (HSQ)
Methyl silsesquioxane
F-doped oxide
F-doped amorphous C
Parylene-F (AF4 )
Xerogel
Gold polyimide
Benzocyclobutene (BCB)
Xerogel

The schematic of the damascene process is shown in figure 14. The various
steps involved in this process are
1. The dielectric layer is first deposited. In the case of organic low k
dielectrics, it is spun on and patterned. For oxide layers, CVD is used
for deposition though it is harder to integrate this with conventional
lithography.
2. The metal layer is then deposited, by electroplating. A barrier layer
(tungsten or metal silicide) is first deposited followed by the seed layer.
Then electroplating is used to deposit the rest of the metal.
3. CMP process is used to remove the excess metal and achieve planar
surface.
4. The process is then repeated for multiple layers.
For multilayer metal connections, the metal from one layer needs to be con-
nected to the metal layer from the preceeding layer and to any subsequent
layers. This is done using vias. For making electrical connections between
metals in the same layers, trenches are fabricated. In the damascene pro-
cess, both the trenches and vias and filled together in one step, this is the
reason it is called a dual damascene process. The patterning can be either
trench first or via first. A via first process is shown in figure15. Here, the vias
are first patterned and opened in the low k dielectric. Then, the trenches are
patterned. After that, both vias and trenches are filled with metal and then
excess removed by CMP. In trench first, the trenches are first patterned and
a second patterning opens the vias in them.

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Figure 14: The dual damascene process overview. (a) The interlayer dielec-
tric is deposited and then patterned for the metal deposition. (b) Metal is
deposited, usually by electroplating. (c) Excess metal is removed by pla-
narization. Adapted from Microchip fabrication - Peter van Zant.

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Figure 15: A via first dual damascene process (a) - (e). The lower level
interconnects are already defined. After the ILD layer is deposited, vias
are etched first and then trenches. Both are then filled with metal, and
then polished. The reverse process is also possible. Adapted from Microchip
fabrication - Peter van Zant.

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