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CS/EE-520 - Computer Architecture Quiz-4 (Sec 2), November 07, 2017 (Fall 2017)

The document describes the execution of instructions in a loop across multiple iterations on a triple-issue out-of-order processor. It details the issue, execution, memory, writeback and commit stages of each instruction over two iterations of the loop. Key execution units and latencies are specified. RAW hazards between dependent instructions across and within iterations are noted.

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37 views1 page

CS/EE-520 - Computer Architecture Quiz-4 (Sec 2), November 07, 2017 (Fall 2017)

The document describes the execution of instructions in a loop across multiple iterations on a triple-issue out-of-order processor. It details the issue, execution, memory, writeback and commit stages of each instruction over two iterations of the loop. Key execution units and latencies are specified. RAW hazards between dependent instructions across and within iterations are noted.

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CS/EE-520 - Computer Architecture

Quiz-4 (Sec 2), November 07, 2017 (Fall 2017)


Solutions

Consider execution of the following loop on a triple-issue/commit speculative processor. Assume that there is
only one memory unit (with effective address calculation) for LD/SD instructions. In addition, there are
separate units for integer ALU operations and branch condition evaluation.

You have: infinite ROB entries, and infinite Reservation Stations (RS) for FP MUL/DIV, 3 CDB. NOTE: Consider inter-
iteration dependence where applicable.

Execution stage lengths are: DIV.D: 20 cc, MUL.D: 10 cc, ADD.D/SUB.D: 3 cc, Int ALU op/Br/LD: 1 cc, SD: 2cc

MEM WR to
ITER # INSTRUCTION ISSUE EXEC COMMIT COMMENTS
READ CDB
1 L.D F1, 0(R3) 1 2 3 4 5

1 DIV.D F2, F1, F3 1, 2-4 5-24 - 25 26 RAW(F1)

1 MUL.D F5, F2, F4 1, 2-25 26-35 - 36 37 RAW(F2)

1 DADDIU R3, R3, -8 2 3 - 4, 5-36 37

1 L.D F12, 48(R2) 2 3 4 5, 6-36 37

1 ADD.D F7, F12, F4 2, 3-5 6-8 - 9, 10-37 38 RAW(F12)

1 S.D F7, 0(R2) 3 4,5-9,10-37 - - 38 RAW(F7)

1 DADDIU R2, R2, -8 3 4 - 5, 6-37 38

1 BNEZ R2, Loop 3, 4-5 6, 7-38 - - 39 RAW(R2)

2 L.D F1, 0(R3) 4 5 6 7, 8-38 39

2 DIV.D F2, F1, F3 4, 5-7 8-27 - 28, 29-38 39 RAW(F1)

2 MUL.D F5, F2, F4 4, 5-28 29-38 - 39 40 RAW(F2)


2 DADDIU R3, R3, -8 5 6 - 7, 8-39 40

2 L.D F12, 48(R2) 5 6 7 8, 9-39 40

2 ADD.D F7, F12, F4 5, 6-8 9-11 - 12, 13-40 41 RAW(F12)

2 S.D F7, 0(R2) 6 7,8-12,13- - - 41 RAW(F7)


40
2 DADDIU R2, R2, -8 6 7 - 8, 9-40 41

2 BNEZ R2, Loop 6, 7-8 9, 10-41 - - 42 RAW(R2)

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