Systronix 20x4 LCD

Brief Technical Data

July 31, 2000

Here is brief data for the Systronix 20x4 character LCD. It is a DataVision part and uses the
Samsung KS0066 LCD controller. It's a clone of the Hitachi HD44780. We're not aware of any
incompatabilities between the two - at least we have never seen any in all the code and custom
applications we have done.

This 20x4 LCD is electrically and mechanically interchangeable with 20x4 LCDs from several
other vendors. The only differences we've seen among different 20x4 LCDs are:

1) LED backlight brightness, voltage and current vary widely, as does the quality of the display

2) There is a resistor “Rf” which sets the speed of the LCD interface by controlling the internal
oscillator frequency. Several displays we have evaluated have a low resistor value. This makes
the display too slow. Looking at the Hitachi data sheet page 56, it appears that perhaps the
“incorrect” resistor is really intended for 3V use of the displays.

At 5V the resistor Rf should be 91 Kohms. At 3V it should be 75 Kohms. Using a 3V display at

5V is acceptable from a voltage standpoint (the display can operate on 3-5V) but the oscillator
will then be running too slowly. One fix is to always check the busy flag and not use a fixed time
delay in your code, then it will work regardless of the LCD speed. The other option is to always
allow enough delay for the slower display.

All Systronix 20x4 LCDs have the 91 Kohm resistor and are intended for 5V operation.

Thank you for purchasing Systronix embedded control products and accessories. If you have any
other questions please email to [email protected] or phone +1-801-534-1017, fax +1-801-
534-1019.
 ABSOLUTE MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS (REFLECTIVE TYPE)
Standard Value Test Standard Value
Item Symbol Item Min. Typ. Condition
Symbol Max.
Min. Typ. Max. Unit Unit
Supply Voltage for Logic VDD- Input “High” Voltage 0 V 7.0
2.2 VEE VV
IH
Supply Voltage for LCD Driver VDD-VEEInput “Low” Voltage VIL 13.5 0.6 VV
Input Voltage Output
VI “High” Voltage
VSS VOH IOH=0.2mA V2.2
DD VV
Operature Temp. Topr Output “Low” Voltage0 VOL IOL=1.2mA 50 °C
0.4 V
Storage Temp. Tstg Supply Current -20 IDD VDD=5.0A 70 2.5 °C
4.0 mA

PIN FUNCTIONS BLOCK DIAGRAM

No Symbol Function No Symbol Function
1 VSS GND, 0V 10 DB3 Data Bus
2 VDD +5V 11 DB4
3 VEE for LCD Drive 12 DB5
4 RS Function Select 13 DB6
5 R/W Read/Write 14 DB7
6 E Enable Signal 15 LEDA
LED Power Supply
7-9 DB0-DB2 Data Bus Line 16 LEDA
HD44780U
Table 4 Correspondence between Character Codes and Character Patterns (ROM Code: A00)

Upper 4
Lower
4 Bits
Bits 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
CG
RAM
xxxx0000 (1)

xxxx0001 (2)

xxxx0010 (3)

xxxx0011 (4)

xxxx0100 (5)

xxxx0101 (6)

xxxx0110 (7)

xxxx0111 (8)

xxxx1000 (1)

xxxx1001 (2)

xxxx1010 (3)

xxxx1011 (4)

xxxx1100 (5)

xxxx1101 (6)

xxxx1110 (7)

xxxx1111 (8)

Note: The user can specify any pattern for character-generator RAM.

184
Initializing by Instruction
If the power supply conditions for correctly operating the internal reset circuit are not met, initialization
by instructions becomes necessary.

Refer to Figures 25 and 26 for the procedures on 8-bit and 4-bit initializations, respectively.

Power on

Wait for more than 15 Wait for more than 40

ms after VCC rises to
ms after VCC rises to
4.5 V
2.7 V

RS R/WDB7 DB6 DB5 DB4 DB3DB2 DB1

DB0 BF cannot be checked before this instruction.
0 0 0 0 1 1 * * * * Function set (Interface is 8 bits long.)

Wait for more than 4.1 ms

RS R/WDB7 DB6 DB5 DB4 DB3 DB2 DB1

DB0 BF cannot be checked before this instruction.
0 0 0 0 1 1 * * * * Function set (Interface is 8 bits long.)

Wait for more than 100 s

RS R/WDB7 DB6 DB5 DB4 DB3 DB2

DB1DB0 BF cannot be checked before this instruction.
0 0 0 0 1 1 * * * * Function set (Interface is 8 bits long.)

BF can be checked after the following

instructions. When BF is not checked, the
waiting time between instructions is longer than
the execution instuction time. (See Table 6.)
Function set (Interface is 8 bits long. Specify
RS R/WDB7 DB6 DB5 DB4 DB3 DB2 DB1
DB0 the number of display lines and character
font.)
0 0 0 0 1 1 N F * * The number of display lines and character font
cannot be changed after this point.
0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 0 0 0 1 Display off
0 0 0 0 0 0 0 1 I/D S Display clear
Entry mode
set

Initialization ends

Figure 25 8-Bit Interface

212
Reset Function

Initializing by Internal Reset Circuit

An internal reset circuit automatically initializes the HD44780U when the power is turned on. The
following instructions are executed during the initialization. The busy flag (BF) is kept in the busy state
until the initialization ends (BF = 1). The busy state lasts for 10 ms after VCC rises to 4.5 V.

1. Display clear
2. Function set:
DL = 1; 8-bit interface data
N = 0; 1-line display
F = 0; 5 8 dot character font
3. Display on/off control:
D = 0; Display off
C = 0; Cursor off
B = 0; Blinking off
4. Entry mode set:
I/D = 1; Increment by 1
S = 0; No shift

Note: If the electrical characteristics conditions listed under the table Power Supply Conditions Using
Internal Reset Circuit are not met, the internal reset circuit will not operate normally and will fail
to initialize the HD44780U. For such a case, initial-ization must be performed by the MPU as
explained in the section, Initializing by Instruction.

Instructions

Outline

Only the instruction register (IR) and the data register (DR) of the HD44780U can be controlled by the
MPU. Before starting the internal operation of the HD44780U, control information is temporarily stored
into these registers to allow interfacing with various MPUs, which operate at different speeds, or various
peripheral control devices. The internal operation of the HD44780U is determined by signals sent from
the MPU. These signals, which include register selection signal (RS), read/

write signal (R/:), and the data bus (DB0 to DB7), make up the HD44780U instructions (Table 6). There
are four categories of instructions that:

Designate HD44780U functions, such as display format, data length, etc.

Set internal RAM addresses
Perform data transfer with internal RAM
Perform miscellaneous functions

190
 HD44780U
Normally, instructions that perform data transfer with internal RAM are used the most. However, auto-
incrementation by 1 (or auto-decrementation by 1) of internal HD44780U RAM addresses after each data
write can lighten the program load of the MPU. Since the display shift instruction (Table 11) can perform
concurrently with display data write, the user can minimize system development time with maximum
programming efficiency.

When an instruction is being executed for internal operation, no instruction other than the busy
flag/address read instruction can be executed.

Because the busy flag is set to 1 while an instruction is being executed, check it to make sure it is 0
before sending another instruction from the MPU.

Note: Be sure the HD44780U is not in the busy state (BF = 0) before sending an instruction from the
MPU to the HD44780U. If an instruction is sent without checking the busy flag, the time between
the first instruction and next instruction will take much longer than the instruction time itself.
Refer to Table 6 for the list of each instruc-tion execution time.

Table 6 Instructions

Execution Time
Code (max) (when fcp or
Instruction RS R/: DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description f is 270 kHz)
OSC

Clear 0 0 0 0 0 0 0 0 0 1 Clears entire display and sets

display DDRAM address 0 in
address counter.
Return 0 0 0 0 0 0 0 0 1 — Sets DDRAM address 0 in 1.52 ms
home address counter. Also
returns display from being
shifted to original position.
DDRAM contents remain
unchanged.
Entry 0 0 0 0 0 0 0 1 I/D S Sets cursor move direction 37 µs
mode set and specifies display shift.
These operations are
performed during data
write and read.

Display 0 0 0 0 0 0 1 D C B Sets entire display (D) on/off, 37 µs

on/off cursor on/off (C), and blinking
control of cursor position character
(B).
Cursor or 0 0 0 0 0 1 S/C R/L — — Moves cursor and shifts 37 µs
display display without changing
shift DDRAM contents.
Function 0 0 0 0 1 DL N F — — Sets interface data length 37 µs
set (DL), number of display lines
ACG ACG ACG ACG ACG ACG Sets CGRAM address. (N), and character font (F).
37 µs
Set 0 0 0 1
CGRAM CGRAM data is sent and
address received after this setting.
Set 0 0 1 ADD ADD ADD ADD ADD ADD ADD Sets DDRAM address. 37 µs
DDRAM DDRAM data is sent and
address received after this setting.
Read busy 0 1 BF AC AC AC AC AC AC AC Reads busy flag (BF) 0 µs
flag & indicating internal operation is
address being performed and reads
address counter contents.

191
HD44780U
Table 6 Instructions (cont)

Execution Time
Code (max) (when fcp or
Instruction RS R/: DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description f is 270 kHz)
OSC

Write data
1 0 Write data Writes data into DDRAM or 37 µs
to CG or
CGRAM. tADD = 4 µs*
DDRAM
Read data
1 1 Read data Reads data from DDRAM 37 µs
from CG or
or tADD = 4 µs*
DDRAM
CGRAM.
I/D = 1: Increment
DDRAM: Display data RAM Execution time
I/D = 0: Decrement
CGRAM: Character generator changes when
S = 1: Accompanies display shift
RAM frequency changes
S/C = 1: Display shift
ACG: CGRAM address Example:
S/C = 0: Cursor move ADD: DDRAM address
When fcp or fOSC is
R/L = 1: Shift to the right (corresponds to cursor
R/L = 0: Shift to the left 250 kHz,
address) 270 = 40s
DL = 1: 8 bits, DL = 0: 4 bits 37 s
AC: Address counter used 250
N = 1: 2 lines, N = 0: 1 line for both DD and CGRAM
F = 1: 5 10 dots, F = 0: 5 8 dots addresses
BF = 1: Internally operating
BF = 0: Instructions acceptable
Note: — indicates no effect.
* After execution of the CGRAM/DDRAM data write or read instruction, the RAM address counter
is incremented or decremented by 1. The RAM address counter is updated after the busy flag
turns off. In Figure 10, tADD is the time elapsed after the busy flag turns off until the address
counter is updated.

Busy signal Busy state

(DB7 pin)

Address counter
(DB0 to DB6 pins) A A+1

t ADD
Note: t ADD depends on the operation frequency
t ADD = 1.5/(f cp or f OSC ) seconds

Figure 10 Address Counter Update

192