Implementation of a Multi-channel

UART Controller Based on FIFO

Abstract: To meet modern complex control for short distance transmission. Serial
systems communication demands, the paper communication is another way of communication
presents a multi-channel UART controller based impossible
used extensively because of its simple structure
on FIFO(First In First Out) technique and and long transmission to distance. But sometimes a
FPGA(Field Programmable Gate Array). The common serial port could implement
not meet requirements of
paper presents design method of asynchronous complex systems with this
different Baud Rates
FIFO and structure of the controller. This multi-Baud
equipments even some special Baud Rate
controller is designed with FIFO circuit block and
equipments. As showing in figure 1, inRate a system, the
UART (Universal Asynchronous Receiver communication system
Transmitter) circuit block within FPGA to PC’s Baud Rate is 115200bps and the Ep1 i.e.
implement communication in modern complex equipment 1’s Baud without
Rate is 57600bps, equipment
control systems quickly and effectively. Form the 2’s Baud Rate is 19200bps, anda other equipments
are set at 9600bps or special
other Baud Rates. It is
communication sequence diagrams, it is easily to
Baud
know that this controller can be used to
Rate
implement communication when master
equipment andFPGA,
slaver equipment are set at converter.
Keywords: FIFO, UART
different Baud Rate. It also can be used to
reduce synchronization error between sub-
I INTRODUCTION
systems in a system with several sub-systems.
Today, owing istoreconfigurable
The controller availability of
andstate-of-the-art
scalable.
microcontrollers and digital signal processors
(DSPs), complex control algorithms can be easily
implemented to attain the desired system
performance. But in actual control systems, it is
difficult to attain the expected result for various
factors affect the control systems such as control
algorithms itself, capability of controllers, capability
of implement equipment and states of control
circumstance [1]. Except those factors,
communication parameters of control systems
including Baud Rate, BER (Bit Error Rate) and
synchronization between sub-systems also engender
great effect.control
In several In order to improve
systems, UART precision
a kind ofof control
serial
system and make good use of modern
communication circuit is used widely. A universal control
algorithms,
asynchronous we should pay much more
receive/transmit attention
(UART) is an on
communication
integrated circuit in control systems.
which plays the most important
role in serial communication. It handles the
conversion between serial and parallel data. Serial
communication reduces the distortion of a signal,
therefore makes data transfer between two
In some complex systems, communications
systems separated in great distance possible [2].
between the master controller and slaver
controllers are implemented by serial or parallel
port. Parallel communication needs a lot of multi-
bit address bus and data bus and it is only
convenient
To solve these problems described as above, we always not zero. This paper introduces a way of
design a multi-channel UART controller based on designing FIFO based on FPGAs with high
FIFO techniques and FPGAs. It can receive data write/read speed and high reliability.
with a UART block at a certain Baud Rate and Generally, a FIFO consists of a RAM Array block, a
transmit data to sub-equipment with a UART block Status block, a writer pointer (WR_ptr) and a read
at the same Baud Rate or at other kind of Baud point (RD_ptr) and its structure is showing in figure
Rate which is different from the receiving Baud 2.
A RAM array with separate read and write ports is
Rate. And it also can be used to reduce time delay used to stored data. The writer pointer points to
between
FPGA sub-controllers.
(Field Programmable Gate Array) is using the locationffd8ffe000104a464946000
that will be written next, and the read
extensively and playing more and more important pointer points to the location that will be read
roles in the designing of digital circuit. Its currently.1020100c800c80000ffe20c
A write operation increments the writer
programmable characteristics make circuit design pointer and 584943435f50524f46494c4
a read operation increments the read
much more flexible and shorten the time to market. pointer. On 500010100000c484c696e6
reset, both pointers are reset to zero,
Using FPGAs can also improve the system’s the FIFO is empty. The writer pointer happens to be
integration, reliability and reduce power the next FIFOf021000006d6e747252474
location to be written and the reader
consumptions. FPGAs are always used to implement pointer 22058595a2007ce0002000
is pointing to invalid data. The
simple interface circuit or complex state machines to 9000600310000616373704
responsibility of the status block is to generate the
satisfy different system requirements. In this paper, “Empty” and “Full” signals to the FIFO. If the “Full”
using a FPGAEP1C6Q produced by ALTERA and FIFO d534654000000004945432
is active then the FIFO can not accommodate more
techniques design a Baud Rate converter to data and 0735247420000000000000
if the “Empty” is active then the FIFO can
implement communications within equipments at not provide 000000000000000f6d6000
more data to readout. When writing
different Baud Rates. FIFOs are usually used for data into the FIFO “wclk” will be used as the clock
clock domains crossing to safely pass data from one
100000000d32d485020200
domain and when reading data out of the FIFO
clock domain to another asynchronous clock domain. 0000000000000000000000
“rclk” willffd8ffe000104a4649460001020100c800c800
be used as the clock domain. These both
Using a FIFO to pass data from one clock domain to 00ffe20c584943435f50524f46494c450001010
clock domains0000000000000000000000
are asynchronous.
another clock domain requires multi-asynchronous 0000c484c696e6f021000006d6e74725247422
clock design techniques. There are different ways to
0000000000000000000000
058595a2007ce000200090006003100006163
design a FIFO right. This paper details one method 0000000000000000000000
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thatseveral
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data a safe
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FIFO between
system, high two
speeddifferent
controlclock domains
system basedusing
on Gray
PCI
code.
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and multi-DSP signal processing system, FIFO is 0000000000000000000000000000000000000
used to complete communication between high 1840000006c77747074000
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speed device and low speed device or to complete 001f000000014626b70740
001840000006c77747074000001f0000000146
communication between the same sub-controller. 0000204000000147258595
26b707400000204000000147258595a000002
FIFO is the most important part of these systems 18000000146758595a0000022c00000014625
and it works as a bridge between different devices a000002180000001467585
8595a0000024000000014646d6e6400000254
[3, 4]. As the same, in our controller, asynchronous 95a0000022c00000014625
00000070646d6464000002c40000008876756
FIFO based on FPGA is also the most important part. 5640000034c0000008676696577000003d400
8595a00000240000000146
Fig.1. Multi-equipments communication diagram
0000246c756d69000003f8000000146d656173
So the features and capabilities of the
asynchronous FIFO determine the features of our 46d6e64000002540000007
0000040c00000024746563680000043000000
controller. FIFO can be used to complete In adesigning
6-DOF robot, there are 6 sub-controllers
00c725452430000043c0000080c6754524300
of asynchronous
0646d6464000002c400000 which
FIFOs, two difficult
are all the
problems same notstructure to beOne designed.
00043c0000080c625452430000043c0000080c
can be ignored. is how The PC is
to judge
communicationII inDESIGN
parallel
OF or serial port. FIFOS
ASYNCHRONOUS 088767565640000034c000
used to
FIFOs 7465787400000000436f70797269676874202
implement
status according the tocontrol algorithm
the writer pointer of and
the
A. Introduction to FIFO read 0008676696577000003d40
863292031393938204865776c6574742d5061
robot pointer.
and send
The othercontrol
is how parameters to sub-
to design circuit to
An asynchronous FIFO refers to a FIFO design where 636b61726420436f6d70616e79000064657363
controllers and sub-controllers are used to collect
data values are written to a FIFO buffer from one
synchronize
feedback
00000246c756d69000003f
asynchronous clock
0000000000000012735247422049454336313
domains
signals and send them to the PC. The PC
to avoid
Metastability.
clock domain and the data value are read from the B. Status 8000000146d65617300000
of Empty and
and sub-controllers Full of FIFO with each other
936362d322e31000000000000000000000012
communicate
735247422049454336313936362d322e31000
same FIFO buffer from another clock domain, where Creating
on a RS485 40c0000002474656368000
emptyBUS and
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important part ofnumber
address designing and a theFIFO.PCNo matter
uses this
other. FIFOs are always used for data cache, storing under
numberwhat
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circumstance,
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the
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PC wantscan 000043c0000080c6754524
not point
to send data toto the
node same6, itaddress
has to of the
access
signals. And asynchronous FIFOs are often used to
quickly and safely pass data from one clock domain
FIFO.
front 5So, 30000043c0000080c62545
nodes,the this
empty and full
engenders time signals playmakes
delay and very
important
performance rolesofwithin the FIFO that they
robot’s eachblockDOFaccessnot
to another asynchronous clock domain. In
to
2430000043c0000080c746
further read or So writeit respectively. The critical
asynchronous clock circuit, periods and phases of synchronization. reduces the control
importance
algorithm’s 5787400000000436f70797
of this blocking
precision lies in the
and brings fact that
difficulties in
each clock domain are completely independent so
the probability of data loss is pointer
researching 2696768742028632920313
positions
of the are the
control only control
algorithm. that is over
the FIFO, and write or read operation
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2007 Second IEEE Conference2633 22e3100000000000000000
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changes the pointers. Generally, in an ordinary This is what causes the real difficulty. If you were to
0006d6e74725
FIFO, 484c696e6f0210
when the read pointer 00000c484c696
equals
247422058595 to the writer sample the read pointer with the write pointer (or
pointer the FIFO is empty. a2007ce00020But in a circular FIFO it vice versa), you will potentially run into a problem
00006d6e74725 both
is either empty or full when
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of the pointers called metastability. Metastability is the name for
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are equal. and 6e7472524742
Because the full000616373704 empty signals can the physical phenomenon that happens when an
not only2007ce0002000
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pointers’ value but also event tries to sample another event. In a physical
9000600310000 ce0002000900 circuit
be influenced by the 000494543207
operation that caused the the metastability causes the output
pointers to become equal. 352474200000If a reset or read makes uncertainty either be a logical 1 or a logical 0 or
616373704d534
the pointers other,060031000061
equal to each 000000000000 the FIFO is really something between. In physical systems, sampling
empty.
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the pointersthe FIFO equal,
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or an event by another event yields unpredictable
6d6000100000
FIFO is4543207352474
empty, we [5].
full can set a direction 540000000049 results. Unpredictability also implies another
flag
000d32d48502
keeps track of
what causes the pointers to become equal to each phenomenon and this is the real danger that
other. 2000000000000 454320735247
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The flag tells the status circuit the direction
000000000000
0000000000000
in which the FIFO is currently 420000000000
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C. Solutions by metastability is a difficulty in
of Metastability
000f6d60001000
implementation of ffd8ffe000104a4
the direction 000000000000
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64946000102010 Metastability can cause unpredictable problems in
complex because you have000000000000
to set the threshold of
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000000000000
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design technique used to 000000000000 100000000d32
distinguish between full best to reduce the metastability. If asynchronous
0100000c484c69 element is in a system, metastability is
0000000000000
and empty is to add an extra d48502020000 unavoidable. There is absolutely no way to
bit
000000000000
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The to loglength
pointers
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2
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depth 0000000000000
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000616373704d5
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000018400000
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FIFO 64 byte (8 bits one 06c777470740
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byte), 0000000000000
the writer and read pointers’ length 2is log 64 =6.
000000000000
00001f000000
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n +1 bits pointer
Using 0000000000000 00000000000000 n
000000000000
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when is the number of complex, empirical and experimental data to arrive
0f6d60001000000
address bits required to 000020400000
access the entire FIFO at. In a D flip-flop, when the input signal changes
0000000116370 00d32d48502020 000000000000
0147258595a0
memory buffer. when both
00000000000000 pointers including the In instantaneously
the FIFO, it needsfrom 0 to 1the
to sample value tof=0
at time , the with
a counter
7274000001500
MSBs are equal the FIFO is empty. 000000000000
000021800000
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clockof Q is
that is synchronous
uncertain. This is counter
to the metastability.
clock. Thus it
0146758595a0
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0000033646573
full when both pointers , except the
00000000000000 000000011637
000022c00000
MSBs are equal. will meet a situation where the counter is changing from
6300000184000
As figure the array
3 showing, when 0146258595a0
00000000000000 _ size of the FFFF to 0000, and every single bit goes metastable. This
072740000015
00000000000000
FIFO is 8 bytes,tothe
bits required number
access the ofentire
address
000024000000 FIFO memory means that the counter would potentially read any value
0006c77747074 00000000001163000000033646
between FFFF to 0000 and the FIFO does not work. The
buffer is 4. With an 014646d6e640
additional
70727400000150 address bit the full
000001f0000000
and empty signals 00000033646573
can be easily 573630000018
000025400000
created [5, 6]. most important things that must to be done are to make
63000001840000
14626b7074000 40000006c777
070646d64640
006c7774707400
sure that not all bits of the counter will change
00002c400000
0020400000014 0001f0000000146 47074000001f0simultaneously.
088767565640
26b70740000020
In order to minimize the probability of
occurrence of such errors, we should make sure that
7258595a00000 00000014626b precisely one bit changes every time the counter
000034c00000
40000001472585
95a00000218000
086766965770
2180000001467 000146758595a0
RD_ptr[3:0] 707400000204 increments. So we need a counter that counts in the Gray
00003d400000
58595a0000022 000022c0000001
000000147258 codes.
0246c756d690
46258595a00000
Gray codes are named after the person who
originally patented the code back in 1953, Frank Gray.
c000000146258 595a00000218 Gray code is different form binary code that is every next
00003f800000
24000000014646
0146d6561730
d6e64000002540
595a000002400 0000070646d646
WR_ptr RD_ptr
000000146758 value differs from the previous in only one bit position.
000040c00000
WR_ptr RD_ptr
4000002c400000
0000014646d6e 08876756564000595a0000022c codes is as following:
024746563680 The conversion between the Binary codes and the Gray
000043000000 gn
6400000254000 0034c000000867 000000146258
00c725452430 (1)
6696577000003d
ffd8ffe000104a4649460001020100c800c80000 =b
g =⊕ ∀bb i ≠n
00070646d6464 595a00000240
000043c00000
4000000246c756
ffe20c584943435f50524f46494c4500010100000 ii n
i+1

00000014646d and
On reset d69000003f80000
000002c400000
WR_ptr<=
c484c696e6f021000006d6e7472524742205859
80c675452430
00146d65617300
0 0887675656400
5a2007ce00020009000600310000616373704d5
000043c00000 bn
00040c00000024
6e6400000254
346540000000049454320735247420000000000
80c625452430 (2)
RD_ptr<= 74656368000004
000000000000000000f6d6000100000000d32d4 =g
bi ii+1
=⊕∀gbi ≠n
0 00034c0000008 00000070646d n
000043c00000
300000000c7254
850202000000000000000000000000000000000
52430000043c00
6766965770000 full 80c746578740
000000000000000000000000000000000000000 There are multiple ways to design a Gray code
00080c675452436464000002c4
Fig.3.FIFO and empty conditions
000000000000000000000001163707274000001
0000000436f7 counter and this paper details a simple and
0000043c000008
The 03d4000000246 fundamentally
0c625452430000 000000887675
status 500000003364657363000001840000006c77747
block 079726967687
074000001f000000014626b7074000002040000
performs straight forward method to do the design. The
c756d69000003f
operations on the 420286329203
two pointers,
043c0000080c74 65640000034c
and these run off
00147258595a00000218000000146758595a000 technique describe in this paper uses only one set
two different clock domains. 139393820486
65787400000000
0022c000000146258595a000002400000001464
8000000146d65 436f70797269676 000000867669 of flip-flops for the Gray code counter as showing
5776c6574742
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000000000127
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02863292031393938204865776c6574742d5061
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2007 543363139363
IEEE Conference on Industrial Electronics and
000000000000012735247422049454336313936
80c6754524300 2e310000000000
Applications 000002474656
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 ffd8ffe0001 ffd8ffe0 ffd8ff ffd8ffffd8ff
04a4649460 00104a4 e00010 e00010e00010
001020100c 6494600 4a4649 4a46494a4649
800c80000ff 0102010 460001 460001460001
e20c584943 0c800c80 020100 020100020100
in figure 4. In a FIFO, 435f50524f4
converts the Gray code 000ffe20
to The controller c800c8 also has a block of Baud c800c8c800c8
Rate
Binary code, increments 6494c45000
it and convert it back c5849434
to Generator0000ffeto engender different Baud0000ffe 0000ffe
Rates to
the Gray code and store it. The Gray code counter content requirements for different kind of systems.
10100000c4 35f50524 20c584
assumes that the outputs of registers bits are the This block is constituted by timers (32/16 bits
20c58420c584
Gray code value. The Gray code outputs are then timers), frequency dividers and a Baud 943435
84c696e6f02 f46494c4 943435 943435Rate
passed to the Gray 1000006d6e
to binary converter which 5000101 f50524f
is setting register. f50524f
f50524f
passed to a binary adder to generate the00000c48
7472524742 next 46494c 46494c46494c
binary value which is passed to the binary to Gray ffd8ffe000104a4649460001020100c800c80000ffe
The first fact
converter that to 2058595a20
remember
generates theabout
next Graya Gray code 4c696e6f
code
valueis 450001 450001
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that
stored the in code 07ce000200
distance
register. between any two adjacent 0210000 696e6f021000006d6e74725247422058595a2007ce
010000 010000010000
words is just 1(only one bit can change from one 00020009000600310000616373704d53465400000
0900060031
Gray count to the next). The second fact to
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0c484c 0c484c0c484c
0000616373
remember about a Gray code counter is that most 7252474 696e6f 696e6f
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00000000000000000000000000000000000000000
useful Gray code counters 704d534654 must have 2205859 00000000000000000000000000000000000000000
power-of-2 021000 021000021000
counts in the sequence.
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clk 0524f46494c4500010100000c484 c80000ffe20c584943
ary ffd8ffe000104a4649460001020100c800c8
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technique and the COM 2007ce
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FIFO block2007ce
as
00010100000c484c6
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10100000c484c696e6f021000006d6e74725 mentioned before, we design a multi-channel
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00310000616373704d534654000
4d53465 00146d6561730000040c000000247465636800000
000200 000200000200
74725247422058595 controller. It can be used to implement
4300000000c725452430000043c0000080c6754524
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Fig.4.Gray counter
000004945432073524742000000architecture
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4000000 090006
communications 090006
between MCUs in a complex
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2d48502020
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04d53465400000000 0049454 system. 003100
And it can also be used to003100
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complete
0100000000d32d4850202000000
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III IMPLEMENTATION OF A MULTI-CHANNEL UART 031393938204865776c6574742d5061636b617264
0000000000
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CONTROLLER
49454320735247420
00000000000000000000000000000000000 3207352 communication006163 between high speed 006163
device 006163
and
00000000000000000
00000000000000000001163707274000001 20436f6d70616e7900006465736300000000000000
low speed device. Structure of the controller is
A. Hardware 0000000000
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structure
0000000000f6d6000
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showing figure 6. The controller is built 73704d
within a
000000000000000000000000000 100000000d32d4850
0000000000
7747074000001f000000014626b70740000
000000001163707274000001500
In the multi-channel controller, 20200000000000000
there
0204000000147258595a000002180000001 are
0000000
different FPGA 534654 is based 534654
00000000000000000127352474220494543363139
– EP1C6Q240 which on 534654
SRAM
36362d322e3100000000000000000000000000000
0000000000
000003364657363000001840000
blocks including UART
00000000000000000
block, 00000000000000000 0000000
Status Detectors,
46758595a0000022c000000146258595a00 technique 000000
0000000000000000000000000 000000
produced by ALTERA. It is possible 000000
to
00024000000014646d6e640000025400000
006c77747074000001f000000014 design small scale memorizer like FIFOs. When
asynchronous FIFOs 0000000000 and Baud 0000000
block 00000000000000000
070646d6464000002c40000008876756564
Rate 004945 004945004945
Generator 626b70740000020400000014725
block. Each block has different function designing
00000000000000000 FIFOs within FPGAs, you should consider
in the
The first
0000000000
0000034c0000008676696577000003d4000
8595a0000021800000014675859
controller.
part is UART circuit block
00000000000001163 0000f6d6
and its structure
000246c756d69000003f8000000146d6561
432073 432073
ffd8ffe000104a4649460001020100c800c80000ffe20c58
the capacity of FIFO in practice and also 432073
consider
70727400000150000 4943435f50524f46494c4500010100000c484c696e6f021
0000000000
5a0000022c000000146258595a0
730000040c0000002474656368000004300
is shown in figure 5. It consists 0001000
of three parts
00033646573630000
the FPGAs’524742
capacities. 524742
000006d6e74725247422058595a2007ce0002000900060 524742
000024000000014646d6e640000
000000c725452430000043c0000080c6754
Receive Circuit, 0000000000
Transmit Circuit and
52430000043c0000080c625452430000043
025400000070646d6464000002c 00000d3
Control/Status
01840000006c77747
074000001f0000000
000000 000000
0310000616373704d5346540000000049454320735247 000000
Registers. c0000080c7465787400000000436f7079726
The Transmit Circuit consists of a 420000000000000000000000000000f6d6000100000000
0000000000
400000088767565640000034c00
Transmit00008676696577000003d400000
14626b70740000020
9676874202863292031393938204865776c
Buffer and a Shift 4000000147258595a
Register. Transmit
2d48502 000000 000000
d32d48502020000000000000000000000000000000000
000000
Buffer loads 0000116370
6574742d5061636b61726420436f6d70616
data being transmitted
0246c756d69000003f8000000146 from local
00000218000000146
e7900006465736300000000000000127352
0200000
CPU. 000000 000000
000000000000000000000000000000000000000000000 000000
Register 7274000001
accepts data758595a0000022c00
And Shiftd6561730000040c000000247465 0000000
from the Transmit
47422049454336313936362d322e3100000 000000000000000011637072740000015000000033646
000000 000000000000
0000146258595a000
00000000000000000127352474220494543 57363000001840000006c77747074000001f0000000146
Buffer and send it to the TXD pin one by one bit.
The Receive
5000000033
6368000004300000000c7254524
Circuit consists of
0024000000014646d
36313936362d322e3100000000000000000 0000000
a Receive Shift
0000f6 0000f6
26b707400000204000000147258595a00000218000000 0000f6
30000043c0000080c6754524300 6e640000025400000
6465736300
00000000000000000000000000000000000
Register 00043c0000080c6254524300000 070646d6464000002
and a Receive Buffer. The Receive Shift 0000000 d60001 d60001
146758595a0000022c000000146258595a000002400000 d60001
00 > c4000000887675656 0014646d6e640000025400000070646d6464000002c400
Register receives data 0001840000
43c0000080c7465787400000000
from RXD one by one
40000034c00000086 0000000
bit. 000000 000000
000088767565640000034c0000008676696577000003d4 000000
The Receive 436f707972696768742028632920
Buffer loads data 76696577000003d40
from long-distance
006c777470
MCU and31393938204865776c6574742d5
gets it ready for the local
0000000
PC to read. The
00000246c756d6900
00d32d 00d32d
000000246c756d69000003f8000000146d656173000004 00d32d
0c0000002474656368000004300000000c725452430000
Control Register a 74000001f0
061636b61726420436f6d70616e7 0003f8000000146d6
special function register is 0000000
used 485020 485020
043c0000080c675452430000043c0000080c6254524300
485020
900006465736300000000000000 561730000040c0000
to control the UART 0000001462
and indicate status
00247465636800000 0000000
of it. 200000 200000
00043c0000080c7465787400000000436f707972696768 200000
According 127352474220494543363139363
to each bit’s value the UART will choose
6b70740000 4300000000c725452
0000000 000000 000000
74202863292031393938204865776c6574742d5061636b 000000
different62d322e31000000000000000000
kind of communication 430000043c0000080
method and the 61726420436f6d70616e79000064657363000000000000
0204000000
000012735247422049454336313
UART knows what to do to receive
c675452430000043c 0000000
or transmit data. 000000 000000
0012735247422049454336313936362d322e310000000 000000
936362d322e3100000000000000 0000080c625452430
FIFOs are used to store 147258595a
data received
000000000000000000000000000 0000000
from the
000043c0000080c74 PC 000000 000000
00000000000000012735247422049454336313936362d 000000
and get ready for sub MCUs. When writing data
65787400000000436 into 322e31000000000000000000000000000000000000000
0000000000000 0000021800
Gray 0000000 000000
B. Software structure 000000000000
FIFOs and reading data out of f7079726967687420
FIFOs we could set 000000000000000
different clock domains 0000146758 28632920313939382
according to the PC’s
04865776c6574742d
0000000
and 000000 000000000000
MCUs’ Baud Rate. 595a000002 So it can be 5061636b617264204
used to implement 0000001 000000 000000000000
communications between MCUs 36f6d70616e790000
at different Baud
2c00000014 64657363000000000 1637072 000000 000000000000
Rate .
6258595a00 00000127352474220
49454336313936362
7400000 000000 000000000000
0002400000 d322e310000000000 1500000 000000 000000000000
00000000000012735
0014646d6e 24742204945433631 0033646 000000 000000000000
3936362d322e31000
6400000254 00000000000000000 5736300 000000 000000000000
0000007064
2007 Second
00000000000000000 0001840 000000
IEEE Conference on Industrial Electronics and
00000000000000000
000000000000
6d64640000
Applications Gray 000006c7 000000 000000000000
02c4000000 7747074 000000 000000000000
8876756564 000001f0 000000 000000000000
0000034c00 0000001 116370 116370116370
0000867669 4626b70 727400 727400727400
 ffd8ffe
000104
a46494
600010
201006
You can use software codes in Verilog 700750
HDL to stop writing to the FIFO. When FIFO is empty you
design FPGAs hardware architecture, it 000ffe2
is easy to can not read from it any more. Then the Status
write
create and adjustffd8ffe000104a4
to satisfy requirements of Detector will set Empty high or to indicate the status
applications. There 64946000102010 0c5849
are one UART used to of FIFO and read
stop operation
reading from it. stop
When FIFO is not
it will until next
communicate with PC or other main MCU43435f5
06700750000ffe2 and there full or empty it will be written or read data
access
are also four other0c584943435f50 0524f46
UARTs used to communication according the control order. After finishing all is
with sub MCUs. Each 524f46494c4500
channel has two FIFOs, one coming.
for receiving data010100000c484c
494c45
and the other for transmitting
696e6f02100000
data. Each FIFO’s depth is 64 Bytes. The000101 software
6d6e7472524742
flow chart is shown in figure 7.
2058595a2007ce 00000c
00020009000600 484c69
31000061637370
ffd8ffe000104a46494600010
4d534654000000 6e6f021
201006700750000ffe20c5849
00494543207352 000006 IV
43435f50524f46494c4500010
47420000000000
d6e747 SIMULATION AND VERIFICATION
00000000000000
100000c484c696e6f02100000
0000f6d6000100 252474
6d6e74725247422058595a20
000000d32d4850 220585
20200000000000
07ce00020009000600310000
00000000000000 95a200
616373704d53465400000000
00000000000000 7ce000
494543207352474200000000
00000000000000
200090
00000000000000
00000000000000000000f6d60
00000000000000 006003
00100000000d32d485020200
00000000000000 100006
11637072740000
000000000000000000000000
01500000003364 163737
000000000000000000000000
65736300000184 04d534
000000000000000000000000
0000006c777470
654000
74000001f00000
000000000000000000000116
0014626b707400 000004
370727400000150000000336
00020400000014 945432
7258595a000002
4657363000001840000006c7
18000000146758 073524
7747074000001f00000001462
595a0000022c00 742000
As showing in figure 7, when FIFO is full you can
0000146258595a
6b7074000002040000001472
byte into the FIFO. At000000
not write any more00000240000000 this time,
58595a000002180000001467
the Status Detector 000000
will set CS high to indicate
14646d6e640000 that
58595a0000022c0000001462
the FIFO is full and02540000007064 000000
6d6464000002c4
58595a000002400000001464
Reset 00000088767565 000000
6d6e64000002540000007064
Rxd 640000034c0000 0f6d600
Empty1 00867669657700
6d6464000002c40000008876
cs1 0003d400000024 010000
7565640000034c0000008676
FIFO1 6c756d69000003 0000d3
696577000003d4000000246c
Empty2
f8000000146d65
2d4850
61730000040c00
756d69000003f8000000146d6
cs2
00002474656368 202000
FIFO2
561730000040c00000024746
Empty3
00000430000000 000000
0c725452430000
56368000004300000000c725
cs3
043c0000080c67 000000
452430000043c0000080c675
FIFO3 5452430000043c 000000
Empty4 0000080c625452
452430000043c0000080c625 000000
cs4 430000043c0000
452430000043c0000080c746
FIFO4 080c7465787400 000000
5787400000000436f70797269
000000436f7079
000000
72696768742028
676874202863292031393938
63292031393938 000000
204865776c6574742d506163
204865776c6574 000000
742d5061636b61
6b61726420436f6d70616e790
726420436f6d70 000000
000646573630000000000000
616e7900006465 000000
012735247422049454336313
73630000000000
000000
00001273524742
936362d322e3100000000000
20494543363139 000000
000000000001273524742204
36362d322e3100 000000
00000000000000
9454336313936362d322e310
00000012735247 000000
000000000000000000000000
42204945433631 000000
000000000000000000000000
3936362d322e31
001163
00000000000000
00000 00000000000000 707274
00000000000000 000001
000000000000
 ffd8ffe000104a46494600010201008a008a0000ffe20c584943435f50524f4649
4c4500010100000c484c696e6f021000006d6e74725247422058595a2007ce00
020009000600310000616373704d53465400000000494543207352474200000
00000000000000000000000f6d6000100000000d32d485020200000000000000
000000000000000000000000000000000000000000000000000000000000000
000000000000000000116370727400000150000000336465736300000184000
0006c77747074000001f000000014626b707400000204000000147258595a000
00218000000146758595a0000022c000000146258595a000002400000001464
6d6e640000025400000070646d6464000002c400000088767565640000034c00
To verify design of the controller a test bench is
00008676696577000003d4000000246c756d69000003f8000000146d65617300
written to make verification in Modelsim. Data
00040c0000002474656368000004300000000c725452430000043c0000080c67
received from the PC or other main MCU will be stored
in FIFOs within FPGA till the controller received the
5452430000043c0000080c625452430000043c0000080c746578740000000043
commands to order the controller to send data to sub-
6f70797269676874202863292031393938204865776c6574742d5061636b6172
Fig.9. Transmitting sequence produced
controllers. Then bythedifferent Baudwill set a kind of Baud
controller
6420436f6d70616e790000646573630000000000000012735247422049454336
Rates
Rate according to commands desired. As showing in
313936362d322e3100000000000000000000001273524742204945433631393
figure 8, the controller is receiving data and store the
ffd8ffe000104a46494600010201008100810000ffe20c584943435f50524f46494c4500010100000c484c696e6f0210
6362d322e310000000000000000000000000000000000000000000000000000
data received to different
are FIFO waiting
to for
00006d6e74725247422058595a2007ce00020009000600310000616373704d534654000000004945432073524742
When sub-controllers required read.data at
receive
00
0000000000000000000000000000f6d6000100000000d32d48502020000000000000000000000000000000000000
different Baud Rates, the controller can set each
00000000000000000000000000000000000000000000000000000000001163707274000001500000003364657363
channel at its required Baud Rate to transmit data.
000001840000006c77747074000001f000000014626b707400000204000000147258595a000002180000001467585
The transmitting sequence is showing as following in
95a0000022c000000146258595a0000024000000014646d6e640000025400000070646d6464000002c4000000887
67565640000034c0000008676696577000003d4000000246c756d69000003f8000000146d6561730000040c000000
figure 9. The controller sends data at the same time
2474656368000004300000000c725452430000043c0000080c675452430000043c0000080c625452430000043c000
but at different
When Baud Rate
sub-controllers are required to receive data
0080c7465787400000000436f70797269676874202863292031393938204865776c6574742d5061636b6172642043
at the same Baud Rate, the controller can also set
6f6d70616e790000646573630000000000000012735247422049454336313936362d322e31000000000000000000
000012735247422049454336313936362d322e310000000000000000000000000000000000000000000000000000
all channels at the same Baud Rate to transmit
00
data as showing in figure 9. All sub-MCU can
receive
We data
design at channels
four the same in time.
Verilog HDL as totally the
same structure use always block to implement
communication. So on theory, there are no time
differences between sub-controller when the
controller
Fig.10. Transmitting sequence transmits
produced dataBaud
by the same to sub-controllers at the
same
Ratetime. But in fact, there are hardware delays in
FPGAs and these delays may causes sub-controllers
can not receiver data from the controller at the
same time precisely. Comparing with the delays in
RS485 net these delays can be ignored. So using
this controller can greatly improve synchronization
REFERENCES
of sub-controllers [8, 9].
nous FIFO technique implements a multi-channel UART controller within FPGA based on SRAM with high speed and high reliability. The controlle
ffd8ffe000104a46494600010201006600660000ffe20c584943435f50524f46494c4500010100000c484c696e6f
021000006d6e74725247422058595a2007ce00020009000600310000616373704d53465400000000494543207
Wang, “UART-based Reliable Communication and 35247420000000000000000000000000000f6d6000100000000d32d4850202000000000000000000000000000
performance Analysis” , Computer Engineering, Vol 32 No. 10, May 2006, pp15-21 F.S. Pan, F. ZHAO, J. Xi and Y. Luo, “Implem
0000000000000000000000000000000000000000000000000000000000000000000011637072740000015000
00003364657363000001840000006c77747074000001f000000014626b707400000204000000147258595a000
00218000000146758595a0000022c000000146258595a0000024000000014646d6e640000025400000070646d
6464000002c400000088767565640000034c0000008676696577000003d4000000246c756d69000003f800000
of each sub-controller. The controller is reconfigurable and scalable. The fault of FPGA based on SRAM is reconfigurable, so the controller’s fault
0146d6561730000040c0000002474656368000004300000000c725452430000043c0000080c67545243000004
3c0000080c625452430000043c0000080c7465787400000000436f70797269676874202863292031393938204
of Petro?chemical Technology Vol 14 No.12, June 2006, pp26-29 C. E. Cummings, “Simulation and Synthesis Techniques for Asynchronous FIFO Design”, SNUG San Jose 2002
865776c6574742d5061636b61726420436f6d70616e7900006465736300000000000000127352474220494543
36313936362d322e31000000000000000000000012735247422049454336313936362d322e31000000000000
000000000000000000000000000000000000000000

nd Control Networks”, Beijing: TUP, 2003.6

Fig.8. Receiving sequence

2007 Second IEEE Conference on Industrial Electronics and