Scribd
Upload
26 views7 pages

ECN-252 Lab 6 - Lakshya Taragi (19111022 - O6) : Part 1: Implement The Bough-Wooley Multiplier Circuit

Uploaded by

Tanishq Varshney

This document summarizes Lakshya Taragi's work on ECN-252 Lab 6. It discusses implementing (1) a Bough-Wooley multiplier circuit in LTspice using custom subcircuits for full-adders and half-adders, and verifying it produces the expected output of -7 for the multiplication of -1 and 7. It also discusses (2) designing a 4-bit comparator circuit in LTspice, simulating it for sample inputs of 8 and 4, and verifying it correctly outputs that 8 is greater than 4. However, it notes this comparator design does not work for signed integers in 2's complement form, as it does not consider the most significant bits as sign bits.

Copyright:

© All Rights Reserved
Download as DOCX, PDF, TXT or read online from Scribd
Download as docx, pdf, or txt

ECN-252 Lab 6 - Lakshya Taragi (19111022 - O6) : Part 1: Implement The Bough-Wooley Multiplier Circuit

Uploaded by

Tanishq Varshney
26 views7 pages
This document summarizes Lakshya Taragi's work on ECN-252 Lab 6. It discusses implementing (1) a Bough-Wooley multiplier circuit in LTspice using custom subcircuits for full-adders and half-adders, and verifying it produces the expected output of -7 for the multiplication of -1 and 7. It also discusses (2) designing a 4-bit comparator circuit in LTspice, simulating it for sample inputs of 8 and 4, and verifying it correctly outputs that 8 is greater than 4. However, it notes this comparator design does not work for signed integers in 2's complement form, as it does not consider the most significant bits as sign bits.

Original Title

Report

Copyright

© © All Rights Reserved

Available Formats

DOCX, PDF, TXT or read online from Scribd

Did you find this document useful?

Is this content inappropriate?

This document summarizes Lakshya Taragi's work on ECN-252 Lab 6. It discusses implementing (1) a Bough-Wooley multiplier circuit in LTspice using custom subcircuits for full-adders and half-adders, and verifying it produces the expected output of -7 for the multiplication of -1 and 7. It also discusses (2) designing a 4-bit comparator circuit in LTspice, simulating it for sample inputs of 8 and 4, and verifying it correctly outputs that 8 is greater than 4. However, it notes this comparator design does not work for signed integers in 2's complement form, as it does not consider the most significant bits as sign bits.

Copyright:

© All Rights Reserved
Download as DOCX, PDF, TXT or read online from Scribd
Download as docx, pdf, or txt
26 views7 pages

ECN-252 Lab 6 - Lakshya Taragi (19111022 - O6) : Part 1: Implement The Bough-Wooley Multiplier Circuit

Uploaded by

Tanishq Varshney
This document summarizes Lakshya Taragi's work on ECN-252 Lab 6. It discusses implementing (1) a Bough-Wooley multiplier circuit in LTspice using custom subcircuits for full-adders and half-adders, and verifying it produces the expected output of -7 for the multiplication of -1 and 7. It also discusses (2) designing a 4-bit comparator circuit in LTspice, simulating it for sample inputs of 8 and 4, and verifying it correctly outputs that 8 is greater than 4. However, it notes this comparator design does not work for signed integers in 2's complement form, as it does not consider the most significant bits as sign bits.

Copyright:

© All Rights Reserved
Download as DOCX, PDF, TXT or read online from Scribd
Download as docx, pdf, or txt
You are on page 1/ 7

ECN-252 Lab 6

- Lakshya Taragi (19111022 – O6)

Part 1: Implement the Bough-Wooley multiplier


circuit

Circuit:
Modified multiplier circuit from lab-5 (includes custom subcircuit components
for full-adder and half-adder).

LTspice Symbols:

Labels added in higher file:

*Custom subcircuits don’t render in respective schematic (higher) files because of changed paths

Set no. = mod(19111022, 4) + 1 = 3


A=-1; B=7
Signed 4-bit representation: A = 1110, B = 0111
A*B = -7 = 11111001  Expected result
(2’s complement form, 8-bit representation)

Output Simulation:
Verification:
Output = Z7Z6Z5Z4Z3Z2Z1Z0 = 11111001= -7  Verified

Part 2: 4-bit comparator


Circuit:

Sample numbers:
A=8, B=4
In binary system:
A=(1000)2, B=(0100)2
A > B  Expected result

Output Simulation:
Verification:
Output = a_more_than_b = 1, other two = 0 Verified

NO, this scheme does not work for signed integers (2’s complement
form): it is a magnitude comparator circuit and does not consider
MSB (A3 and B3) as sign bits.

From above table, we know if A3 and B3 are equal, current circuit


gives correct result. In case if only one of them is high (1), we need to
flip the results of the current circuit. We can use XOR to deal with
that situation.

You might also like