Scribd
Upload
77 views9 pages

Military College of Signals Digital Logic Design: Lab Engr Hammad

This document discusses a lab experiment on multiplexers and demultiplexers. The objectives are to design and implement both a 4x1 multiplexer and a 1x4 demultiplexer. The multiplexer is built using smaller 2x1 and 4x1 multiplexer blocks. Components used include logic gates. Review questions are provided to test understanding of multiplexers, demultiplexers, their applications and differences.

Uploaded by

ahmad khan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
77 views9 pages

Military College of Signals Digital Logic Design: Lab Engr Hammad

This document discusses a lab experiment on multiplexers and demultiplexers. The objectives are to design and implement both a 4x1 multiplexer and a 1x4 demultiplexer. The multiplexer is built using smaller 2x1 and 4x1 multiplexer blocks. Components used include logic gates. Review questions are provided to test understanding of multiplexers, demultiplexers, their applications and differences.

Uploaded by

ahmad khan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 9

MILITARY COLLEGE OF SIGNALS

DIGITAL LOGIC DESIGN


BEE 56 A

LAB REPORT NO: 07


SUBMITTED BY:
 Usama Khan
 Babar Rasool
 Ishaq Khan
 Imran Ali
SUBMITTED TO: LAB ENGR HAMMAD
Lab 07
Multiplexer / Demultiplexer
OBJECTIVES

• Design and of both Multiplexor and De-Multiplexer


• Designing Large block using smaller block of Multiplexer
COMPONENTS REQUIRED

• Heath Kit Digital Trainer


• 7411, 3 I/P AND gate
• 7432 , OR gate
• 7404 hex inverter
INTRODUCTION Multiplexer:

Multiplexer (MUX), sometimes called data selector is a combinational logic circuit that
selects on of 2n inputs and route it to the output. Multiplexer means transmitting large number of
information units over smaller number of channels or lines. In a digital Multiplexer, the selection of
a particular line from 2n inputs is controlled by n select lines of multiplexer. Fig shows the block
diagram and truth table for a 4x1 MUX.
Large Multiplexers can be implemented using smaller blocks of multiplexors. For example, consider
an 8x1 MUX, this can be implemented using 2 4x1 MUXES and 1 2x1 MUX as shown in figure.
Demultiplexer:

The Demultiplexer is combinational logic circuit that performs the reverse operation of
Multiplexer. It has only one input line and select lines. For n select lines, it has 2n output lines.
Select lines rout the input to the particular output line. By applying logic 1 to the input, circuits act
like typical decoder. Block diagram of 1x4 Demultiplexer and its truth table is shown in figure.
REVIEW QUESTIONS

1- Design and implement 4x1 multiplexer


Circuit diagram:
Explanation:
Components used
 4082 4-INPUT AND GATE
 7432 2-INPUT OR GATE
 7404 STD HEX INVERTER
 LOGICPROBE
 LOGIC STATE SOURCE
a. Here we used 4_input AND gates.
b. One input is connected to either 10,11,I2,I3 and other two inputs of AND gate
are connected with select lines.
c. 4TH INPUT connected with E
d. In order to get input from 11 we will give S0 “0” input and because of NOT gate
it will become “1” and will give S1 “1” and there is no NOT gate connected to it
so, output will remain 1.
e. So, both inputs are “1” as a result the output will be dependent only on input we
give to I1. If I1 “1” is “1” the output will be “1” because all the inputs are “1”
then AND operation will give output “1” and if I1 is “0” the output will be “0” at
U2.
f. All the other gates will turn off because of AND operation e.g In U1, we gave
input S0 “0” and S1 “1” and both the gate will NOT their inputs and because of
AND gate it will remain OFF.
g. U1 is “0” and if U2 is “1” after the OR operation the output at U7 will be 1.
h. U3,U4 are “0” after that OR operation will be performed and output of U8 will
give “0”
i. At last at the output of U9 we will get “1” because of OR operation.
2. Design a 4x1 multiplexor using the smaller blocks of
multiplexers.

I0
2x1 MUX
I1

2x1 MUX
S0 0
S0

I2
2x1 MUX
I3 S1
S0

S0

TRUTH TABLE
S0 S1 OUTPUT
0 0 I0
0 1 I1
1 0 I2
1 1 I3
Sr. Key Decoder De-Multiplexer
No.

1 Purpose A Decoder decodes an A De-Multiplexer routes an


encrypted input signal to input signal to multiple
multiple output signals from output signals.
one format to another format.

2 Input/Output A Decoder has 'n' input lines A De-Multiplexer has single


and maximum of 2n output input, 'n' selection lines and
lines. maximum of 2n outputs.

3 Inverse Decoder's inverse is Encoder. De-Multiplexer's inverse is


Multiplexer.

4 Usage Decoder is used to detect bits, De-Multiplexer is used in


encoding of data. switching, data distribution.

5 Select Lines Decoder has no select lines. De-Multiplexer contains


select lines.

6 Application Decoder is heavily used in De-Multiplexer is employed


networking applications. in communication systems.

You might also like