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Lab 09

This document discusses sequential logic circuits including the R/S latch, flip-flop, and D flip-flop. It begins by explaining the difference between combinational and sequential circuits, with sequential circuits being able to store previous states. It then provides details on designing R/S latches using both NAND and NOR gates. Next, it describes the R/S flip-flop which works similarly but is synchronized to a clock. Finally, it introduces the D flip-flop which transfers the input data on the rising clock edge. The objectives are to design these circuits using NAND, NOR, AND gates on a Heath Kit trainer board with a 1Hz clock.

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38 views

Lab 09

This document discusses sequential logic circuits including the R/S latch, flip-flop, and D flip-flop. It begins by explaining the difference between combinational and sequential circuits, with sequential circuits being able to store previous states. It then provides details on designing R/S latches using both NAND and NOR gates. Next, it describes the R/S flip-flop which works similarly but is synchronized to a clock. Finally, it introduces the D flip-flop which transfers the input data on the rising clock edge. The objectives are to design these circuits using NAND, NOR, AND gates on a Heath Kit trainer board with a 1Hz clock.

Uploaded by

ALvi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Digital Logic Design By Muhammad Hammad

Lab 09
R/S Latch, Flip Flop and D type Flip Flop

OBJECTIVES

• Design the RS Latch using the NAND gates and NOR gates
• Designing the RS Flip Flop and D Flip Flop

COMPONENTS REQUIRED

• Heath Kit Digital Trainer


• 7402, quad 2 i/p Nor gate
• 7400, quad 2 i/p Nand gate
• 7404 hex inverter

INTRODUCTION

In combinational logic circuit, outputs are fully determined by the current inputs. As soon as any
change occurs in the any input, it changes the output. Combinational circuits do not have any
mechanism to hold the previous output or they do not have any memory element. In order to
introduce the memory element in digital design, feedback mechanism is used with the
combinational logic. Such circuits are called sequential circuits which can hold the previous
value (previous state) of output till power is provided to it regardless of input. Sequential
elements are used to design the memory to store the information.

Fig: Block diagram of a sequential circuit

In sequential circuits, output follow a sequence i.e. output depends onto the previous state
(output). Every output of the circuit represents a particular state of the circuit. When inputs are
applied and output is generated say Q state (present). When inputs are changed, a new output
says Q+1 sate is generated. In that case Q is the previous state. Sequential circuits can be
synchronous or Asynchronous.

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Digital Logic Design By Muhammad Hammad

The most basic memory unit is latch which can store 1 bit of information. It uses the feedback to
hold the data and can be designed using either universal gate (NAND or NOR). Figure shows
the design of an RS (Reset, Set) Latch using both NOR and NAND gates. In deriving the truth
table, the fact has been used that if any input of NOR gate is 1; its output is 0 regardless of the
other input. Whenever latch is powered up, it is in Reset state.

Fig: Basic RS Latch using NOR Gates

Q is the output state and Q’ is the complimented output. Initially when powered up, latch is in
Reset state thus Q=0. When S is applied, it is set and Q=1. After that sequence, when both the
inputs are 0, latch will store the previous output which was 1.Then a Reset is applied and Q
becomes 0. After that sequence when both the inputs are 0, latch will store its previous output i.e.
Q=0. When both the inputs become 1, output of latch is undetermined(x) because it violates the
rule of Q and Q’. Thus 1, 1 input id forbidden but for experiment this input can be applied. Given
latch can also be implemented using NAND gates but in that case the table is completely
opposite so complemented version if inputs (R,S) are applied to get the same behavior as above.

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Digital Logic Design By Muhammad Hammad

The latch discussed was an Asynchronous circuit. There is no timing information. As soon as the
input is changed, it follows the output (internal gate delays are ignored). In order to synchronize
the digital circuits, a clock pulse is applied to them. All the events are synchronized on clock
pulse and the output is only forwarded once the positive clock pulse appeared. An RS flip-flop is
the same circuit with the introduction of clock.

(a) Logic Diagram (b) Characteristic table

(c) Characteristic Equation (d) Graphic Symbol

In the characteristic table, in the first four entries, previous output is considered as 0 while in the
next four entries, previous output is considered as 1. It behaves like the latch but just work on
clock pulses. When S and R=0, it retains the previous output. This latch can also be implemented
using the NOR and AND gates.

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Digital Logic Design By Muhammad Hammad

Fig: RS flip-flop using AND, NOR gates

The D Flip Flop:


D stands for data transfer. In the D flip-flop, it transfers whatever flip-flop gets on the D input. D
flip flop is same as RS flip flop with an additional D input and an inverter.

(a) Logic Diagram

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Digital Logic Design By Muhammad Hammad

Review Questions:

1. Design and Implement an RS Latch and Flip Flop


2. Design and Implement D Flip flop

Use 1 Hz clock frequency available on heath kit

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