BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE, PILANI, K.K.

BIRLA GOA CAMPUS

SECOND SEMESTER (2018-19), Comprehensive Examination
Time : 3 hours Maximum Marks: 120 Date : 04-5-2019 Closed Book
ANALOG ELECTRONICS (EEE / INSTR F 341)
Time: 1 hour PART- A Maximum Marks: 40
ID: Name:
Instructions: (i) Answer All questions.
Total Marks
(ii) Write the answers in the question paper itself.
(iii) For IC 741 op-amp the saturation voltage is 13V with supply voltage of 15V.
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1. Consider the circuit shown in Fig.1. Assume the operational amplifier is ideal.Find the value of I0 and VOP if
Vi=2V, =99 and VBE=0.7V. Vin (V) 4 Marks

0 t (ms)
1 2 3 4
-1

V0

0 t (ms)

Fig.1 Fig.2

Expression relating I0 and Vi I0 in mA VOP in volts

2. Draw the waveform of steady state output voltage for an integrator using 741 with R= 8 k and C= 50nF
to an input voltage as shown in Fig.2 above. Mark the output voltage levels. - 4 Marks

3. A 5-bit D/A converter produces VOUT = 0.2 V for a digital input of 00001. Find the value of Vout for an
input of 11111. - 4 Marks

4. If the differential voltage gain and the common mode voltage gain of a differential amplifier are 48 dB
and 2 dB respectively, then its common mode rejection ratio = - 1 Mark

5. Draw the voltage waveforms expected at points A and B. Mark the amplitude and time period of the
waveform for two cycles. AssumeV2(t)= 5 sin (2103t)and V2(0)=0V. - 4 Marks
VA

VB

t
6. A certain 8-bit DAC has a full-scale output of 2mA and a full-scale error of ± 0.5% of full scale output
current. What is the range of possible outputs for an input of 10000000? - 3 Marks

Ideal output current Maximum output current Minimum output current (with
(without any error) (with error) error)

7. For the 4 bit DAC shown in the Fig.3, the output voltage V0 is - 3 Marks

Fig.3 Fig.4

8. For the Op-Amp circuit shown in the Fig.4,V0 is - 2 Marks

9. How many op-amps are required to implement this equation and draw the circuit diagram? - 3 Marks

12. What should be the minimum amplitude of the sinusoidal input so that the circuit shown in Fig.5 works as
a Schmitt trigger if R1&R2 = 1 k and the bias voltage of the opamp is ±15 V? - 3 Marks

Fig.6

Fig.5
13. Find the stability factor and the output impedance of the voltage regulator circuit shown in Fig.6, if the
Zener resistance = 1 k. - 3 Marks

14. A PLL locks on to an input signal of frequency range 10 kHz to 35 kHz as frequency increases and from 25
kHz to 5 kHz when frequency decreases. Find its lock range & capture range.
- 3 Marks
15. What is the frequency of oscillation of the circuit in Fig.7? - 3 Marks

Fig.7

******All the Best*****

 BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE , PILANI, K.K. BIRLA GOA CAMPUS
SECOND SEMESTER (2018-19), Comprehensive Examination
Time : 3 hours Maximum Marks: 120 Date : 04-5-2019 Closed Book
ANALOG ELECTRONICS (EEE / INSTR F341)
Time: 2 hours PART- B Maximum Marks : 80
--------------------------------------------------------------------------------------------------------------------------------
Instructions: (i) Answer All questions. Start your question on a new page.
(ii) For IC 741 op-amp the saturation voltage is 13V with supply voltage of 15V.
(iii) Wherever necessary draw neat diagrams.
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1 Calculate the output voltage V01, V02, and V0 for the circuit shown in Fig.1 when V1 = 2.5 V and V2 = 2.25 V.
- 10 Marks

2. An 8 bit SAR (successive approximation register) type ADC has a Vref = 16 V. It is faulty and its 4th bit (b4)
from MSB is always stuck at 1. What will be the binary code after it has converted an analog input voltage
= 8 V? What is the error between the actual input and the DAC output of this ADC? Write binary code and
DAC output in tabular form as given below in your main answer sheet. - 10 Marks

Step size b7(MSB) b6 b5 b4 b3 b2 b1 b0(LSB) DAC output

1
.
.
8

3. Design an inverting amplifier filter with the following transfer function shown in Fig.2. Assume input
resistor = 1 k. Draw the circuit diagram as well. - 10 Marks

Fig.2
4. (a) Design a regulator circuit shown in the Fig.3 using an opamp and 8V zener diode to maintain a regulated
output voltage of 19V. Assume that the unregulated input varies between 25 V and 40 V and that the
current through the zener diode must be at least 20 mA to keep it in its breakdown region. Assume VBE=
0.7 V. - 5 Marks

(b) Draw the modified circuit diagram using current limiting technique to limit the maximum current to 0.5
A. What will be output voltage when RL= 100  and RL=10? - 5 Marks

Fig.4
Fig.3

5. Find the range of frequencies that can be generated by the circuit shown in Fig. 4. - 8 Marks

6. The PSPICE code of a circuit is as given below. Draw the circuit diagram and draw the waveforms at nodes
10, 3, 4 and 13. Identify the function. - 12 Marks
* sample pspice code
xa1 3 27 8 4 UA741
VCC 7 0 DC 15
VEE 08 DC 15
RF 2 4 12K
R11 210 12K
R21 10 3 12K
xa2 0 3 7 8 13 ua741
d1 13 3 d1n4002 Fig.5
V1 120 sin(0 10 100)
.lib nom.lib
.OP
.PROBE
.TRAN 1M 10M
.END
7. Design the triangular wave generator shown in Fig.5 such that the peak to peak value of its output = 6 V,
frequency = 1 kHz and the maximum current conducted by all resistors should not exceed 12 mA, when
both the opamps are powered from ±12 V rails. Also find the current sourced by both opamps, assuming
that both are identical and the output Vo is being fed to a buffer amplifier to prevent loading. - 10 Marks

8. (a) Design and draw R-2R ladder type DAC circuit using an inverting summing amplifier with four switches
such that the output voltage V0 equals R F  a3 a 2 a1 a 0 
V0     5 V
10  2 4 8 16 
(b) Find the value of RF such V0=2.5 V when the digital input signal is a3a2a1a0=1000.
(c) Using the results of part (b) find V0 for a3a2a1a0=0011 and a3a2a1a0=1011. - 10 Marks
******All the Best*****