International Training Workshop On FPGA Design For Scientific Instrumentation and Computing 11 - 22 November 2013
International Training Workshop On FPGA Design For Scientific Instrumentation and Computing 11 - 22 November 2013
International Training Workshop On FPGA Design For Scientific Instrumentation and Computing 11 - 22 November 2013
11 - 22 November 2013
Pirouz Bazargan-Sabet
Department ASIM, LIP6, University Pierre & Marie Curie (VI), place
Jussieu, 75252 Paris Cedex 0
France
Outline
N-MOS transistor
G
D D S
G
S W
N+ N+
Si L P-
P-MOS transistor
G
S D S
G
D
P+ P+
Si N- P-
N-MOS P-MOS
D D S S
G G G G
S S D D
D = S when G = 1 D = S when G = 0
W
Conductance ∝
L
For the same size, a P-MOS is twice
more resistive than an N-MOS
Not
S
G 2W/L
Dual CMOS gate
D
D
G W/L
S
Series Parallel
Parallel Series
P network
To set the output to 0 a path has to
be created through the N network
A series of N-transistor must be
conducting
N network
Π
Example :
2W/L
W/L
2W/L
W/L
W/L
W/L
Some gates :
Nand : 4 W/L
Nor :
W/L W/L
Some gates :
Multiplexer :
Some gates :
Multiplexer :
If If
is not defined
Tri-state driver
Some gates :
If If
is not defined
If then
If
then
Pass-transistor
Some gates :
If If
is not defined
If then
If then
Pass-transistor
Some gates :
If If
is not defined
CMOS Switch
Some gates :
Multiplexer :
Some gates :
Multiplexer :
Some gates :
Nxor :
I need and
Some gates :