Name Muhammad Ahsan Abbas Roll No. Sp-2018/BSCS/030 Assignment Digital Logic Design

Name Muhammad Ahsan Abbas
Roll no. Sp-2018/BSCS/030
Assignment Digital Logic Design
Submitted To : Sir Hassan Sultan

Introduction
An FGPA is a device that contains a matrix of reconfigurable gate array logic
circuitry.
When a FGPA is configured, the internal circuitry is connected in a way that

creates a hardware implementation of the software application. Unlike
processors, FGPA use dedicated hardware for processing logic and do not have an
operating system. FGpA are truly parallel in nature so different processing
operations do not have to compete for the same resources. As a result, the
performance of one part of the application is not affected when additional
processing is added. Also, mulpitle control loops can run on a single FGPA device
at different rates. FGPA based conrol systems can enforce critical interlock logic
and can be designed to prevent I/O forcing by an operator. However, unlike hard-
wired printed circuit board designs which have fixed hardware resources. FGPA
based systems can literally rewrite their internal circuitry to allow reconfiguration
after the control system is developed to the field, FGPA devices deliver the
performance and reliability of dedicated hardware circuitry.
A single FPGA can replace thousands of discrete components by incorporating

millions of logic gates in a single integrated circuit (IC) chip. The internal resources
of an FPGA chip consist of a matrix of configurable logic blocks (CLBs) surrounded
by a periphery of I/O blocks shown in Fig. 20.1. Signals are routed within the FPGA
matrix by programmable interconnect switches and wire routes.
In an FPGA logic blocks are implemented using multiple level low fan-in gates,
which gives it a more compact design compared to an implementation with two-
level AND-OR logic. FPGA provides its user a way to configure:
1. The intersection between the logic blocks

2. The function of each logic block.
Logic block of an FPGA can be configured in such a way that it can provide
functionality as simple as that of transistor or as complex as that of a
microprocessor. It can used to implement different combinations of
combinational and sequential logic functions. Logic blocks of an FPGA can be
implemented by any of the following:
1. Transistor pairs
2. Combinational gates like basic NAND gates or XOR gates
3. n-input Lookup tables
4. Multiplexers
5. Wide fan-in And-OR structure.
Routing in FPGAs consists of wire segments of varying lengths which can be

interconnected via electrically programmable switches. Density of logic block
used in an FPGA depends on length and number of wire segments used for
routing. Number of segments used for interconnection typically is a tradeoff
between density of logic blocks used and amount of area used up for routing.
Evaluation of FPGA
In the world of digital electronic systems, there are three basic kinds of devices:
memory, microprocessors, and logic. Memory devices store random information
such as the contents of spreadsheets or database. Microprocessors execute
software instructions to perform a wide variety of tasks such as running a word
processing program or video game. Logic devices provide specific functions,
including device-to-device interfacing, data communication, signal processing,
data display, timing and control operations, and almost every other function a
system must perform.
When PLAs were introduced in the early 1970s, by Philips, their main drawbacks
were that they were expensive to manufacture and offered somewhat poor
speed-performance. Both disadvantages were due to the two levels of
configurable logic, because programmable logic planes were difficult to
manufacture and introduced significant propagation delays. To overcome these
weaknesses, Programmable Array Logic (PAL) devices were developed. PALs
provide only a single level of programmability, consisting of a programmable
“wired” AND plane that feeds fixed OR-gates. PALs usually contain flip-flops
connected to the OR-gate outputs so that sequential circuits can be realized.
These are often referred to as Simple Programmable Logic Devices (SPLDs). Fig.
20.3 shows a simplified structure of PLA and PAL.
FPGA Structural Classification Basic structure of an FPGA includes logic elements,

programmable interconnects and memory. Arrangement of these blocks is
specific to particular manufacturer. On the basis of internal arrangement of blocks
FPGAs can be divided into three classes:
Symmetrical arrays
This architecture consists of logic elements (called CLBs) arranged in rows and
columns of a matrix and interconnect laid out between them shown in Fig 20.2.
This symmetrical matrix is surrounded by I/O blocks which connect it to outside
world. Each CLB consists of n-input Lookup table and a pair of programmable flip
flops. I/O blocks also control functions such as tristate control, output transition
speed. Interconnects provide routing path. Direct interconnects between adjacent
logic elements have smaller delay compared to general purpose interconnect.
Row based architecture

Row based architecture shown in Fig 20.5 consists of alternating rows of logic
modules and programmable interconnect tracks. Input output blocks is located in
the periphery of the rows. One row may be connected to adjacent rows via
vertical interconnect. Logic modules can be implemented in various combinations.
Combinatorial modules contain only combinational elements which Sequential
modules contain both combinational elements along with flip flops. This
sequential module can implement complex combinatorial-sequential functions.
Routing tracks are divided into smaller segments connected by anti-fuse elements
between them.
Hierarchical PLDs
This architecture is designed in hierarchical manner with top level containing only
logic blocks and interconnects. Each logic block contains number of logic modules.
And each logic module has combinatorial as well as sequential functional
elements. Each of these functional elements is controlled by the programmed
memory. Communication between logic blocks is achieved by programmable
interconnects arrays. Input output blocks surround this scheme of logic blocks
and interconnects.

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Name Muhammad Ahsan Abbas Roll No. Sp-2018/BSCS/030 Assignment Digital Logic Design

Uploaded by

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Name Muhammad Ahsan Abbas

Roll no. Sp-2018/BSCS/030

Assignment Digital Logic Design

Submitted To : Sir Hassan Sultan

When a FGPA is configured, the internal circuitry is connected in a way that

A single FPGA can replace thousands of discrete components by incorporating

1. The intersection between the logic blocks

2. Combinational gates like basic NAND gates or XOR gates

3. n-input Lookup tables

5. Wide fan-in And-OR structure.

Routing in FPGAs consists of wire segments of varying lengths which can be

FPGA Structural Classification Basic structure of an FPGA includes logic elements,

Row based architecture

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