Cadence

wrong colours in ams libraries with the new cadence version

How to set another text editor for functional views?
In the extracted view of a layout and in the schematic one can highlight nets using the probe
command. ( Verify -> Probe ) Usually the nets are selected with a mouse click. How can I
enter the name in the CIW ?
How to get full size hardcopies of your schematic ? (And not schematics that occupy just the
left corner of the paper sheet!)
Starting cdsspice with the -s option When running large parametrical analyses the memory
manager runs out of memory and recommends starting cdsspice with the -s option. In the old
cadence version this was possible through an options button. Has anyone found out how to do
in the new cadence version?
How do I obtain a circuit from a Verilog functional description?
Which variable sets the path for the temporary files during extraction ? (similiar to
DRCTEMPDIR for DRC)
If you use parametric powernets with the AMS Library and you get an error PowerNet:
unspecified syntax error
Is it possible to run DRC/Extract in batch mode?
Is it possible to generate multiple contacts for a bus in the Virtuoso Layout Editor by placing
the first one and defining the pitch by placing the second one? In the Composer this is
possible! If you have to generate bus-contacts with names in<1:32>, it is somehow enoying to
place 32 contacts one after the other!
AnalogArtist: Do the colors in the waveform window match the colors of the markers/probes
in the schematic window?
How do I find the marker of one single specified DRC-Error among several others in a very
large layout?
How can I prevent that Cadence is blocked for any use during extraction or during DRC?
How do I prevent Cadence Composer (the Schematic editor) from crashing?
Some of the menue-applications in CADENCE are not longer where they used to be.
How can one create a new cellview in a way, that it is automatically put into the desired
category
How can I change the value for the -s option starting cdsSpice from analog artist in a mixed
signal simulation.
How can I change the thickness of the graphs in the waveform window of analog artist?
Using analog arist, how can you use arithmetic expressions of several design variables
without getting error messages like ’*Error* The net ’nil’ is neither a global net nor is it
defined on the current cellView for: ..." having absolutely nothing to do with the properties of
your design you changed using the expressions of design variables mentiones above ???
Using analog arist, how can you use arithmetic expressions of several design variables
without getting error messages like ’*Error* The net ’nil’ is neither a global net nor is it
defined on the current cellView for: ..." having absolutely nothing to do with the properties of
your design you changed using the expressions of design variables mentiones above ???
Using analog arist, how can you use arithmetic expressions of several design variables
without getting error messages like ’*Error* The net ’nil’ is neither a global net nor is it
defined on the current cellView for: ..." having absolutely nothing to do with the properties of
your design you changed using the expressions of design variables mentiones above ???
Using analog arist, how can you use arithmetic expressions of several design variables
 without getting error messages like ’*Error* The net ’nil’ is neither a global net nor is it
defined on the current cellView for: ..." having absolutely nothing to do with the properties of
your design you changed using the expressions of design variables mentiones above ???
Where and how do I set the viewlist and the stoplist for the LVS netlister?
Where and how do I set the viewlist and the stoplist for the LVS netlister?
How can I start an LVS from the unix-shell without having a running icfb?

Question ID: 5

Question: (Submitted by an unknown user on Wed Feb 25 14:11:52 MET 1998)

wrong colours in ams libraries with the new cadence version

Answer: (Submitted by an unknown user on Wed Feb 25 14:11:52 MET 1998)

In the tech file directory there is a display.drf_ams_std file. Copy it into your lib as
display.drf to obtain the original colours.

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Question ID: 29

Question: (Submitted by Martin Feuerstack-Raible on Wed Mar 11 09:57:50 MET 1998)

How to set another text editor for functional views?

Answer: (Submitted by Martin Feuerstack-Raible on Wed Mar 11 09:57:50 MET 1998)

In ~/cdsinit_personal edit the following line

editor = your_editor

e. g. editor = nedit

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Question ID: 31

Question: (Submitted by Michael Keller on Fri Mar 13 18:18:17 MET 1998)

In the extracted view of a layout and in the schematic one can highlight nets using the probe
command. ( Verify -> Probe ) Usually the nets are selected with a mouse click. How can I
enter the name in the CIW ?

Answer: (Submitted by Michael Keller on Fri Mar 13 18:18:17 MET 1998)

To enter the name in the CIW it has to be surrounded quote:

 "123" matches net /123

"+654" matches device /+654

"Bias" matches Bias

Only matched nets might be cross probed.

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Question ID: 39

Question: (Submitted by Joerg Langeheine on Mon Apr 20 17:19:51 METDST 1998)

How to get full size hardcopies of your schematic ? (And not schematics that occupy just the
left corner of the paper sheet!)

Answer: (Submitted by Joerg Langeheine on Mon Apr 20 17:19:51 METDST 1998)

For plotting your schematic you use the path Design/Plot/Submit. You’ll get a new window
containing a knob "plot options". Click there, adjust the printer, and click on the knob "Fit to
page". The scale factor (Next to that knob) probably will change !) Now you should (after
customizing the rest of the settings to your convenience) get a nice hardcopy. By the way, this
works for hierarchical plots too !

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Question ID: 40

Question: (Submitted by an unknown user on Mon May 25 15:42:13 METDST 1998)

Starting cdsspice with the -s option When running large parametrical analyses the memory
manager runs out of memory and recommends starting cdsspice with the -s option. In the old
cadence version this was possible through an options button. Has anyone found out how to do
in the new cadence version?

Answer: (Submitted by Chitu Cristian on Fri Nov 6 09:42:40 MET 1998)

Place the the following lines in your .cdsenv file in your home login directory, before you
start the Cadence session.
spectreS.init languageSize int 200
spectreS.init spiceSize int 300

cdsSpice.init languageSize int 200

cdsSpice.init spiceSize int 300

hspiceS.init languageSize int 200

hspiceS.init spiceSize int 300

In this way you increase the memory for the analog simulators: spectreS, cdsSpice and
 hspiceS.

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Question ID: 41

Question: (Submitted by Martin Feuerstack-Raible on Mon Jul 13 13:05:35 METDST 1998)

How do I obtain a circuit from a Verilog functional description?

Answer: (Submitted by Martin Feuerstack-Raible on Mon Jul 13 13:05:35 METDST 1998)

You may use Synergy from within the Cadence design framework to automatically generate
the circuit. A step by step introduction of using Synergy can be found at the following URL:

http://wwwasic.ihep.uni-heidelberg.de/~feuersta/asiclab/VerilogCookbook/index.html

Your design must obey certain style guidelines to be synthesizeable.

Please refer to the Openbook documentation:
Openbook Main Menu
HDL tools
Logic Synthesis: Verilog
Synergy HDL Synthesizer and Optimizer Modelling Style Guide

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Question ID: 43

Question: (Submitted by Edgar Sexauer on Mon Jul 20 19:24:20 METDST 1998)

Which variable sets the path for the temporary files during extraction ? (similiar to
DRCTEMPDIR for DRC)

Answer: (Submitted by Dirk Droste on Tue Jul 21 08:35:23 METDST 1998)

As far as I know there is no special path variable for storing temporary files during
extraxction - cadence uses normally the /usr/tmp path or the /tmp path to save its temporary
files...

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Question ID: 44

Question: (Submitted by Michael Keller on Thu Jul 30 17:42:21 METDST 1998)

If you use parametric powernets with the AMS Library and you get an error PowerNet:
unspecified syntax error
Answer: (Submitted by Michael Keller on Thu Jul 30 17:42:21 METDST 1998)

To inherit the parametric power nets to the sub instances you add CDF-Parameters called
PowerNet_vdd, PowerNet_vddd or PowerNet_whatsoever.
The sub instance can reference to this CDF Parameter using the skill function
pPar("Name") lets say pPar("PowerNet_gnd").
To add the CDF parameter use the Tools button in the CIW
Tools->CDF->Edit
In the popup add the LibName and the CellName you want to edit and select CDF-Type Base.
Otherwise the data you add is only valid during the current session.
Select Component Parameter->Add. In the popup change the cyclic fields

paramType to string

parseAsNumber to no

parseAsCEL to yes

storeDefault to no

add the name for your PowerNet in the name field

and you might add a default value as well -->> defValue field
If you use parseAsNumber = yes you will get the error mentioned in the Question.

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Question ID: 46

Question: (Submitted by Michael Keller on Fri Jul 31 10:14:49 METDST 1998)

Is it possible to run DRC/Extract in batch mode?

Answer: (Submitted by Michael Keller on Fri Jul 31 10:14:49 METDST 1998)

To run a DRC at a cpecified time use the UNIX command at

Example:
at 0:00
ivVerify drc CellName layout -lib LibName -full [-echo]
Cntrl D
the system will prompt with:
warning: commands will be executed using /usr/bin/sh
job 901867440.a at Fri Jul 31 08:44:00 1998

If you switch drc with extract an extraction is performed. The program has to be started in the
directory where the library is located and there has to be your cds.lib file as well.
You might start drc and extract one after the other during one nigth. at 0:00
ivVerify drc CellName layout -lib LibName -full [-echo]
ivVerify extract CellName layout -lib LibName -full [-echo]
Cntrl D
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Question ID: 52

Question: (Submitted by Dirk Droste on Mon Nov 9 10:57:58 MET 1998)

Is it possible to generate multiple contacts for a bus in the Virtuoso Layout Editor by placing
the first one and defining the pitch by placing the second one? In the Composer this is
possible! If you have to generate bus-contacts with names in<1:32>, it is somehow enoying to
place 32 contacts one after the other!

Answer: (Submitted by Martin Feuerstack-Raible on Tue Apr 20 13:07:44 METDST 1999)

In the layout editor use the Menu ASIC-Tools: Create Bus Pins.

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Question ID: 53

Question: (Submitted by Ulrich Trunk on Mon Nov 23 15:09:55 MET 1998)

AnalogArtist: Do the colors in the waveform window match the colors of the markers/probes
in the schematic window?

Answer: (Submitted by Ulrich Trunk on Mon Nov 23 15:09:55 MET 1998)

No, the colors don’t match! So don’t get confused and belive that one of Kirchhoff’s Rules
might be violated.....

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Question ID: 54

Question: (Submitted by Dirk Droste on Sun Nov 29 22:46:12 MET 1998)

How do I find the marker of one single specified DRC-Error among several others in a very
large layout?

Answer: (Submitted by Dirk Droste on Sun Nov 29 22:46:12 MET 1998)

Usually, if you are using Pad-Cells from AMS, the final DRC of your chip will give a number
of mysterious DRC errors in the Pad-Rin. But there might by single errors caused by your
design, somewhere in the large area at some place, for example:
\o 5 no MET3 on PAD, #6.1
\o 12 6.1.3/W2PA Minimum Bond pad size = 85.0
\o 5338 4.1.9/S1DFIN Minimum NPLUS spacing to DIFF = 0.8
\o 117 4.5.3/BAD1M1 MET1 > 20 um x 300 um without slots
\o 816 6.1.11/E9M1CT Minimum MET1 enclosure of PADCON = 2.0
 \o 129 4.7.6/BAD1M2 MET2 > 20 um x 300 um without slots
\o 2 4.5.1/S2M1M1 Minimum MET1 spacing to WIDE_MET1 = 1.3
\o 5 no VIA2 on PAD, #6.1
\o 112 4.9.4/BAD1M3 MET3 > 20 um x 300 um without slots
\o 10574 4.1.4/S1DFIP Minimum PPLUS spacing to DIFF = 0.8
\o 2 3.1.2/S1WNWN Minimum NTUB spacing = 4.8
\o 1 3.10.3/S1M1M1 Minimum MET1 notch = 0.8 // my mistake
\o 9 no MET1 on MET1 Pin
\o 1694 NDIFF intersects NTUB # 4.1.7/E1WNDN
\o 28 4.9.8/E1M3M3 Minimum MET3 enclosure of M3HOLE = 9.0
\o 724 4.1.5/S1DNWN Minimum NDIFF spacing to NTUB = 1.8
\o 20 6.1.9/E1CTVI Minimum PADCON enclosure of PADVIA1 = 1.0
\o 19588 Total errors found
\o 10 Other warnings

Now, you wish to find that marker causing the error:

\o 1 3.10.3/S1M1M1 Minimum MET1 notch = 0.8

You just need to search for a shape with a property ’drcWhy’ and the value "3.10.3/S1M1M1
Minimum MET1 notch = 0.8"...

So, execute the following steps:

activate the layer ("marker" "er") with the LSW

choose ’edit’->’set valid layers’ in the LSW

check the layer ("marker" "er")

OK

search for a shape with a property-entry "3.10.3/S1M1M1 Minimum MET1 notch =

0.8"

choose ’edit’->’search’ in virtuoso

check ’zoom to figure’

cycle to search for "shape" in "current cellview"

press ’add criteria’

choose "property" name "drcWhy" "==" "3.10.3/S1M1M1 Minimum MET1 notch

0.8"

press ’apply’

The window will focus on your error...

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Question ID: 71
Question: (Submitted by Edgar Sexauer on Mon Feb 8 10:52:51 MET 1999)

How can I prevent that Cadence is blocked for any use during extraction or during DRC?

Answer: (Submitted by Edgar Sexauer on Mon Feb 8 10:52:51 MET 1999)

You have to use the switch "remote" instead of "local" in the DRC or extract query window.
You then have to supply a machine name (which can also be the name of the machine you are
already working on). Cadence then starts the DRC or extract as an ordinary shell-command,
and you can use your Cadence in parallel.

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Question ID: 74

Question: (Submitted by Martin Feuerstack-Raible on Tue Apr 20 12:57:04 METDST 1999)

How do I prevent Cadence Composer (the Schematic editor) from crashing?

Answer: (Submitted by Martin Feuerstack-Raible on Tue Apr 20 12:57:04 METDST 1999)

A workaround is to modify your .Xdefaults file. Add one of the following lines to the
.Xdefaults file in your login directory:

*enableEtchedInMenu: False
or
Opus*enableEtchedInMenu: False

Note: The "*enableEtchedInMenu" is more global and will alter the resource for any
applications which may use it. It may be more practical to set the
"Opus*enableEtchedInMenu" and let it affects to only Cadence Opus.

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Question ID: 77

Question: (Submitted by Dan Husmann on Mon Jul 12 14:41:27 METDST 1999)

Some of the menue-applications in CADENCE are not longer where they used to be.

Answer: (Submitted by Dan Husmann on Mon Jul 12 14:41:27 METDST 1999)

The reason of this may be the language you are using. If you changed the LANG expression
into german language (e.g. de_DE.iso88591) this problem will occure. To check which
language is set type "echo $LANG". If you want to change it type "export
LANG=new_language" (e.g. C) and then start cadence from the same shell.

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 Question ID: 83

Question: (Submitted by Joerg Langeheine on Tue Jul 20 16:38:09 METDST 1999)

How can one create a new cellview in a way, that it is automatically put into the desired
category

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Question ID: 115

Question: (Submitted by Joerg Langeheine on Fri Sep 17 10:09:59 METDST 1999)

How can I change the value for the -s option starting cdsSpice from analog artist in a mixed
signal simulation.

Answer: (Submitted by Joerg Langeheine on Fri Sep 17 10:09:59 METDST 1999)

The question was asked and answered already for the case of pure analog simulations. The
default value however for mixed signal simulations is even smaller and amounts to 10
meaning 10 000 double floating point words, or in present implementations probably 80
kByte.

To change the two memory size related values used to start cdsSpice with the -s and -S
options which here are referred to as ssize and Ssize you have to add the following lines to the
’.cdsenv’ file in your home directory.
spectreSVerilog.init languageSize int ssize
spectreSVerilog.init spiceSize int Ssize

The exact meaning of these two variables is explained in the open book cdsSpice user
manual. The actual page can be found by searching for "Run out of memory" in the open
book.

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Question ID: 118

Question: (Submitted by Edgar Sexauer on Fri Jan 14 17:31:01 MET 2000)

How can I change the thickness of the graphs in the waveform window of analog artist?

Answer: (Submitted by Ulrich Trunk on Fri Jan 14 20:43:15 MET 2000)

In the WaveForm window go to curves->edit...->Pen There are solid lines of different

thicknesses, but unfortunately they can’t be distinguished in the selection window, so you
have to try them....
Add new answer

Question ID: 121

Question: (Submitted by Joerg Langeheine on Mon Jan 31 11:32:02 MET 2000)

Using analog arist, how can you use arithmetic expressions of several design variables
without getting error messages like ’*Error* The net ’nil’ is neither a global net nor is it
defined on the current cellView for: ..." having absolutely nothing to do with the properties of
your design you changed using the expressions of design variables mentiones above ???

Add new answer

Question ID: 122

Question: (Submitted by Joerg Langeheine on Mon Jan 31 11:32:02 MET 2000)

Using analog arist, how can you use arithmetic expressions of several design variables
without getting error messages like ’*Error* The net ’nil’ is neither a global net nor is it
defined on the current cellView for: ..." having absolutely nothing to do with the properties of
your design you changed using the expressions of design variables mentiones above ???

Add new answer

Question ID: 123

Question: (Submitted by Joerg Langeheine on Mon Jan 31 11:32:02 MET 2000)

Using analog arist, how can you use arithmetic expressions of several design variables
without getting error messages like ’*Error* The net ’nil’ is neither a global net nor is it
defined on the current cellView for: ..." having absolutely nothing to do with the properties of
your design you changed using the expressions of design variables mentiones above ???

Add new answer

Question ID: 124

Question: (Submitted by Joerg Langeheine on Mon Jan 31 11:50:20 MET 2000)

Using analog arist, how can you use arithmetic expressions of several design variables
without getting error messages like ’*Error* The net ’nil’ is neither a global net nor is it
defined on the current cellView for: ..." having absolutely nothing to do with the properties of
your design you changed using the expressions of design variables mentiones above ???

Add new answer

 Question ID: 125

Question: (Submitted by Edgar Sexauer on Thu Feb 24 13:31:29 MET 2000)

Where and how do I set the viewlist and the stoplist for the LVS netlister?

Answer: (Submitted by Edgar Sexauer on Thu Feb 24 13:31:29 MET 2000)

You have to add definitions to your .simrc -file, which is located in the rundirectory of
Cadence. Add for example the following lines: lvsSchematicStopList = ’( "auLvs" )
lvsSchematicViewList = ’( "auLvs" "schematic" "cmos.sch" "symbol" )

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Question ID: 126

Question: (Submitted by Edgar Sexauer on Thu Feb 24 13:31:29 MET 2000)

Where and how do I set the viewlist and the stoplist for the LVS netlister?

Answer: (Submitted by Edgar Sexauer on Thu Feb 24 13:31:29 MET 2000)

You have to add definitions to your .simrc -file, which is located in the rundirectory of
Cadence. Add for example the following lines: lvsSchematicStopList = ’( "auLvs" )
lvsSchematicViewList = ’( "auLvs" "schematic" "cmos.sch" "symbol" )

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Question ID: 127

Question: (Submitted by Edgar Sexauer on Sat Apr 22 20:07:36 METDST 2000)

How can I start an LVS from the unix-shell without having a running icfb?

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