AEC Unit 5
AEC Unit 5
Date
Page
ftltex -
PtLeting is achieNedb palSiVe_CDmpouw
Ond HALAe Cpmpouents whe
utdUih
OPAP foras an a VC filtee
the gain ConstO
F i e maintain beLow
Or above Dr inbetwen the Cut off
Quencit and boued on tAS the
Oze catsieid as
OLow palsfiltet_
(2 Band pausfut
10
fc
Non inYLing tow NonInYLEng luiqh.
paLs S u t pas sfitte
N ve
Vo Vi V
V
R
ve
Ra R
RI
R
R2 Ra
AAA-
+ve
RL
Vo
M
ve
4
A- 1+ R2
A- 1+ R2 Ri
Ri
fc
fc 2T RCC
2 T RC
R_ubnq A
Vouage fouo we Vottaae ouDw
|+ve |V
6 Vo
www.
ve R -ve
OFc fc L
2T RC 2TT RC
A-
-A
R
6
Vo
-ve
fCE 12 KHz E 12x10 120oo
lA-IS
FCE A R2
2TT RC RI
Assume Ro25
-1S 2
RI
RF
S
RiE O-133 2
FC
2TT Po C
C
2T Ra x fC 23.14) x2x 12 x IDx ib
6-63 x LD x 10
Fc 12kH2
AAA
L2 te
A- 1+R2 Ec
2TT RC s9
R
R2 2K C ber1en_oi1 UE t o O-001Uf
ASsume
Calcuate RL uing A
A- I+ R2
RI
15 1+2
Ri
R 2
1S
RI 1-33 k-
fc
2TT RC YCx(ur
RE
2T FcxC 2x3-14 x 1216xo1xIb-6
R 132. 69 k .
fc12KHZ
R A--15
fe60oHZ
C
Vo
A-C -O
C2
Fc -
2TT RC
ASSumne C2
O-1 UF
Calcuae C & R3 Tom O &
om D
Date
Page
A= C TT
C2
C -A. C2
15x O. UE
C S uf
GOin
from
bR -15
2x Ecox I07
band
V
toooxIo 2-6 k
200TT
HOSl Fc Goo Hz
* Banc Pass
IE iSthe et tolucu pouse a band of
L en cie thCLt me ns Qain is Conttant
in a baudof eque niee and the two
CutOFE P quen utL OTe known ou Cowet
cuto FE tquency and upp
CutOFF!requenc
Arma
D.o7
Apna PL-a*pA00HXTEC
F2
Mw-
VI
Vo
Page
2TTR2 Cz
27T RI C
Conne Cted
1mpedeMU
olepeudon
The Qain
in the teinal
Ousuwe
Ous'uMe cz
C l Cz
TO odegn the ciYCut OlCuwate
cuU ate RI & Ra
RL &Ra
o.001uf Cal
OLAf to
pOvide.
poU 5EeL to pooide
D u t g n a baMo do HT
Do Hz to
to
TOYM4
of friQuenci
band of-1O
Of-10
hoo KHz _with a 9 a i n
fiyoOHT
F24ODRHz
Ro yo0 ep
A-Ob AAA-
C2 O1UME
2RnLHeon
bno
27T RC
A l O 6
RI
2TTA ACr 2TTX H OO O o-106 2 5 1 e
A C 3.9go x l0 2
= 3. 9g kA
Re
2TT Pa C2 f 1
Ama
Basic DACTechmiq us
di Sse
n-bit DAC Vo
binaauyy On
dn se)
ig O Schemaiic a DAC
h e inbut to ho
he OAC us a n-bzt binaauy Oord D
Lshese digit e d d , da, d4 Li-c. D=d,,d,-- dn]
Cund Combined Loith a uleaence Ve io give
Voltagee
an analop oP Stynal
he olp. a ISAC Can be either a Vottoge Ceesenl
he analoq l e Velbage i
No = k Vrs l3, 2 + d, 22 + d s 2 +
In 2 29e glR Ne No
dn da
Dse
-oVe
fia A Siple Loeighked sezien AC
he DAC Useb n 6urmn@ng op-amp Loith: a binaae
LOeighle3 SesiatotH 'R, 2R 2R,- 2 e a3 BhoLon
To Va d+ Y dz t3R ds +--
2R 22R T2R
Lshene d, da - ,dn. may be erthe O
en da,
,
lo Ve | d,27+ d, 27 + dn OD
Ole Yottage
Vo To R
Bub &a, Tn Cq
No Veee1[ d, 2%--
R=R
No Ve Ia, 2+ d*+ - - - + dn 2"J|
Por 3-blt DAC
Oigital TIP Analog Olp
Vo
O
1 Vel8
2/8 Ve
318 NR
O Hle Ve
5l8 Ve
6lg Ve
4l Ve
Analog
oIP
lgNe
Sieve
4ieVe
NM
21elet
eVe
ODO CoI O10 o Otoo olor Ouo o
Drqfkal TlP Cole
R-2R Lodder OAC
ith a
Sketëh, cxplotn he LOothfng R-2R
ladde DAC
wwww.-
2R 2 R 2R
LSG 2R
MSB
d=t
-Ne
hg s R-2R ladaes DAC
R-2R laddex DAC vodletes
Sesiste1 and hence t ses onuy too
is easyo JobaRcote all rassölo
en a
Ch LIC].
The pfcol Yalue Ronges om 2 25kalo
e 1Ok
Sesistoys [R-2R) ane So aaanged as
toom a
Jadder retiwok shocon n g
o Bmblicili,, Censicer
o -bit OAC as Shown în
Lha digital npt e a -bu binaay
Loerd 9ven os D IOO.
d i l , da =O and da -
O
2R 2R 2R
bve
Ptg
To Calaudote
equtualent Velbag to
he
e
e
ot node 3CV
lelt
Calcclale the
node a
3
2.R
2P .
e 2Ru25
R+R =2R
2R I12R R
T R R = 2R
ja
ig
The Yotioge ad ode s ven
Ve R_
2R+2R
= -Ve
Rg is Siedaason belouo.
Vo2RYR
Vo Ve
2
Since, NeVr
No Ves [Ves-ullSale olp V]
In generod, Oiqibal IP riolog OP
di da da V
2la Ve
ajg Ve
Slg Ne
61g Ye
48 Ve
ojP
Sioy
41get
d MSB
da
Pinadog
IIP Va HDC oP
TVe
fhg : Fincionol diagaam o_ROC-
RDC. TL acetile
Frg O Shotos the block Schenalic
and oduces an Olp
CEn anci m p voltage Va -»
ERnaaey ooid dn Eo h a t ,
+dn2
D-d2 d2 d 2
bt Cs and
LShee di o the mest Eqritcord
dn 19 tha Jeast SigniEcant bat Lse
Dined ype
2Trdeznotarng pe Rocs.
Cemvenercs
OtaelkP used vikegaaling agpe
2
Chaage bolanc?g ROC
Da
Lope ROC.
dn CLGe
oIP DAC do
DAC
Opesation
Sh Sc Signal inilioles the paocess gnal.
Seosch he SAR Sals the MeB d , = l , a s Soen as
the START 8ignol asuives, and all othen Eb aae
Set to O, 01the Conveater G O B-brt ComVealerr
o 2 i a Bdttaq o o l d be LOo0o0o0.
The olP DAC oi ths r a l Code i e
Compcked 9ith hhe anolega Tle v T thhe analoq IP
than t h e OAC OlP C-e,W a ] , t
he J i a l Code LOOOOooo Jass han
Hhe Cenect drgtdo aepeteriotion V. The M9B a
bit Lett
ect
ct
ot
and
and
thre m e n t
the
Duoer 6ignzTcard
te 1, poioce TS ebeodeá.
On he
other
he
the DAC OP
OLP Na,
WA
har TiP V is Jess
Trnpltes hot 4he bias Code he
thod
10000000 s gpeslerr than tha Ceinect drgttal ebrezen
tatzen . In Such an event, the S B i 8et
'o he nend Lones eranitcard but re Bat
to 1 and. he peces i npealed. lie010000o0
above ce Coponaten epesied
Lirne iunkl al
osition fave been J t e d
We Compaaáler Changes the,. stole Konenexres
OP
the
Guese 4Es ackawcdas f e 5OC
Comnand
101100Lo 10000OOO.
11000cO00
101 00000
1bI10000
10Ll0oo
10t1OL00
10LtoolO
104 o l
T TCn+1D
Lohexe Te dens the Convenalen dime
Advantages:
1 Conversion time is very small.
2 Conversion time is constant and independent of the amplitude of the analog input signal VA.
Disadvantages:
1 Circuit is complex.
Binsr
nbe grata
Compa rwo
CLOGIK
LSSH M5a
eupul
ag1
-
M-- SIope
Vokage Sope
RC
nC.
F 1- ef Auol alope
doagaam
the block
8heras
g
The
ange
Fntenaotes
erdt e
Boit
betuoeen
Le>ence
Cenbroil e
be n a g d v e
he
ied
Ceiooe
Celtoge nbegc
p
oler pud Euoite
+he
Hee te ve oltage
Fha CAn
l h e n
ferneel Boteb i s an
binanu Couritee
h h theinpd
Lohih 4
htch en
LohEch
the
Vollaastih appliea
doser
nd he,vottage
Soitch cleses en
OpexaLion
SLoitch CLose
ss apted
anole9
tunvteaf altage
4he Trilegsotot
n J oool
Cnicaaatet p Ppied od. he Te
do S 3ttCollags gven
=
The
Coxnpooalet - Tndegrto
ha
OtP
Votta9
the g e
Corpasale
an å ho
te Peliea
hrgh T t enablas
goez
e e z áeath tha Couaiter
the end peEcda, the S3 h
hegodire
Swsnioneo eltag
Ssleaere Vetaae
btnca eOlP Counte
ahich
the
mou
SAezat
foitngaatot
as h e TpD
Io he ntriolei
Lineasr
ocxea bes ewe, th Conpaaote Orp
Lonen eacke He NDrelis d e
goes oo and Caase
e 2coch
hhe c i e k piulaes
the Counlese- Couri Cemespending
a lime
at a
he Cou+lex* stop
nlewol
i e h g e loltoge
Chosge Voltoge
a ace. Hee
Ve -
T above eguo 1 sto he a l ebre
it-The
aopedionat
eamre
a
daedly
b e n c e
ootbog Cena
e Countese alao
-
pmepodional Ao tha
tta arelog
arelog
Ogta otp o the
Coundan- a t eec]
Pavandages
T posesses
ts chaoP
a .high degaeee
Pexor ance
actnoeg
Chore not aGnzeley aqu.ctca
VN D-
T
Start Digital output
ADC
Fig. 19.49 : Single slope
ltconsists of comparator, AND gate, counter, Ramp
&control
source &control
When start signal is applied to control circuit Vin analog input voltage is
1n
The control circuit resets Ramp source & binary counter. After reset
reset the
the
applrampied
comparo p
will
voltage will go on rising linearly from 0V. The comparator analog
voltage output ofcomms
nput with ramp voltage, as V is greater than ramp Comparato
will be +Vent: which will enable AND gate & will pass clock pulses to count
unter&
counter will start counting pulses.
of 1 V/ms & V = 2V, The output of comna,
If we select a ramp source parator
will be high for & after that ramp source will
2 ms
2V&
be greater than
2V &so
disable AND gate & clock
lock Dule
output of comparator will be V sat which will
-
pulses
are stopped from reaching counter.
In 2 ms with 1 MH clock source 2000 clock pulses will reach counter, if we
We
will be available
properly adjust the decimal point the analog input voltage in