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Cie-III Verilog HDL QP

The document is an online internal assessment for a Verilog HDL course. It contains: 1) Instructions for students on how to answer the assessment questions, including writing their name and USN, numbering pages, scanning answers to PDF, and naming the file correctly. 2) 5 questions related to Verilog concepts like multiplexers, full adders, operators, tasks vs functions, and computer-aided logic synthesis. 3) Information about the course outcomes related to abstraction levels, writing programs effectively using Verilog features, and interpreting logic synthesis constructs.

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vijayarani.katkam
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90 views2 pages

Cie-III Verilog HDL QP

The document is an online internal assessment for a Verilog HDL course. It contains: 1) Instructions for students on how to answer the assessment questions, including writing their name and USN, numbering pages, scanning answers to PDF, and naming the file correctly. 2) 5 questions related to Verilog concepts like multiplexers, full adders, operators, tasks vs functions, and computer-aided logic synthesis. 3) Information about the course outcomes related to abstraction levels, writing programs effectively using Verilog features, and interpreting logic synthesis constructs.

Uploaded by

vijayarani.katkam
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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US

Department of Electronics & Communication Engineering


H.K.E.S’s S.L.N College of Engineering
Yeramaraus Camp, Raichur - 584135
ONLINE INTERNAL ASSESMENT – III (Academic Year: 2020-21)
Sub with Code: verilog HDL (18EC56)
Semester: V Max Marks: 30 Time: 2:00PM–3:00PM

Instructions:
 Descriptive Assessment evaluated for 30 marks.
 Write your name, USN & subject on the front page of the answer sheet.
 All sheets must have page numbers.
 Answers must be written in sheets neatly, upon completion all the sheets must
be scanned using camscanner and then need to be saved in PDF format.
 The scanned PDF file need to be named as shown here - (eg: 3SL18EC001-18EC56).
 Assessment duration is 90mins (including writing and uploading).
 Maintain the hardcopy of the answer sheet and need to submit once you report back to
college.
 Use only black ink.

Answer the following questions

CO RBT
Qn. Max
Question Mappe Level
No. Marks
d
Write the behavioral description of 8 to 1 multiplexer
L1,
1 using case statement and illustrate the use of Repeat and 06 CO3
L2
Forever loop statement with suitable example.
Write Verilog dataflow description for 4-bit full adder L1,
2 06 CO3 L2
with carry look ahead.
A)What would be the output for the following
a=4’b0111 b=4’b1001 i)&b ii)a<<<2 iii){a,b} iv) {2{b}}
3 v)a^b vi)a|b 03+03 CO3 L1,L2
B)With the help of example explain the difference
between logical, relational and bitwise operators.
L1,
4 Bring out the difference between task and functions. 06 CO4
L2
With a neat flow chart explain Computer-Aided logic L1,
5 06 CO6
synthesis process. L2

Course Outcomes:
.
CO3:Identify the suitable Abstraction level for a particular digital design.
CO4:Write the programs more effectively using Verilog tasks, functions and directives.
CO6:Interpret the various constructs in logic synthesis.
Department of Electronics & Communication Engineering, SLNCE, Raichur
US
N

Department of Electronics & Communication Engineering, SLNCE, Raichur

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