Course Course Course L T P C

19PECC22J VLSI Design C Professional Core

Code Name Category 3 0 2 4

Pre-requisite Co-requisite Progressive

Nil Nil Nil
Courses Courses Courses
Course Offering Department Electronics and Communication Engineering Data Book / Codes/Standards Nil

Course Learning Rationale (CLR): The purpose of learning this course is to: Learning Program Learning Outcomes (PLO)
CLR-1 : Use Verilog HDL as a design-entry language for FPGA in electronic design automation of digital circuits 1 2 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CLR-2 : Design, construct and simulate VLSI adders and multipliers.
CLR-3 : Understand MOSFET operation

PSO–1: Professional Achievement

CLR-4 : Implement a given logic function using appropriate logic styles for improved performance

PSO – 2: Project Management

PSO – 3: Analyze & Research

Environment & Sustainability
Analysis, Design, Research
Understand the basic processes in IC fabrication, steps in the fabrication of MOS ICs, and as well the layout design

Level of Thinking (Bloom)

CLR-5 :

Expected Proficiency (%)

Expected Attainment (%)

Individual & Team Work

Engineering Knowledge
rules.

Design & Development

Project Mgt. & Finance

Use modern engineering tools such as HSPICE / Modelsim / Xilinx to carry out design experiments and gain experience

Modern Tool Usage

Life Long Learning

CLR-6 :

Problem Analysis

Society & Culture

with the design and analysis of MOS circuits and systems.

Communication

Techniques
Ethics
Course Learning Outcomes (CLO): At the end of this course, learners will be able to:
CLO-1 : Design and implement digital circuits using Verilog HDL to simulate and verify the designs. 3 85 75 - H H - H - - - - - - - - - -
CLO-2 : Design general VLSI system components, adder cells and multipliers to address the design of datapath subsystem. 3 85 75 - H H - H - - - - - - - - - -
CLO-3 : Examine the characteristics of MOS transistors 2 80 70 H M - - - - - - - - - - - - -
CLO-4 : Examine CMOS inverter and other complex logic gates designed using different logic styles 2 80 70 - L L - - - - - - - - - - - -
CLO-5 : Explain how the transistors are built, and understand the physical implementation of circuits. 2 80 70 - L L - - - - - - - - - - - -
CLO-6 : Use HSPICE computer analysis program and Verilog HDL for simulation and analysis of MOS circuits and building blocks 3 85 75 - - - - - - - - H M L M - L M

Learning Unit / Module 4:

Learning Unit / Module 1: Learning Unit / Module 2: Learning Unit / Module 3: Learning Unit / Module 5:
CMOS Inverter and Circuit Design
Duration (hour) Introduction to Verilog HDL & Coding Subsystem Design MOS Transistor
Styles
15 15 15 15 15
CMOS Inverter Characteristics:
General VLSI System Components: Generic overview of the MOS device: Properties of basic materials used in
SLO-1 Introduction to HDL & Verilog HDL Operation and properties of static CMOS
Multiplexers MOS transistor symbols microelectronics: Silicon, Silicon dioxide
inverter
MOS structure demonstrating (a)
S-1
accumulation, (b) depletion, and
Introduction to Verilog HDL, modules and
SLO-2 Decoders (c) inversion; VTC of static CMOS inverter Polysilicon and Silicon Nitride
ports
nMOS transistor demonstrating cutoff,
linear, and saturation regions of operation
Basic Processes in Integrated-Circuit
Lexical Conventions: White Space and MOS Transistor under Static Fabrication: Wafer Formation,
SLO-1 Comparators DC Inverter Calculations
Comments, Operators Conditions: The threshold voltage Photolithography, Well and Channel
S-2
Formation
Numbers, Strings, Identifiers, System Silicon Dioxide (SiO2), Isolation, Gate
SLO-2 priority encoder Resistive operation Symmetrical Inverter
Names, and Keywords Oxide
Gate and Source/Drain Formations,
Verilog Data Types: Nets, Register
SLO-1 shift and rotate operations Saturation region Inverter switching characteristics Contacts and Metallization, Passivation,
Variables, Constants
Metrology
S-3
Some Recurring Process
SLO-2 Referencing Arrays of Nets or Regs Adders: Standard adder cells Current-voltage characteristics Output capacitance Steps:Diffusion and Ion Implantation,
Deposition, Etching, Planarization
S-4, 5 SLO-1 Lab-0: Verilog Operators: Lab-3:Design using FSM and ASM charts Lab-6: Realization of VLSI multipliers - I Lab-9:Design and Analysis of CMOS Lab-12: Design and Analysis of 4-input

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 Arithmetic Operators, Bitwise Operators, Inverter using HSPICE Dynamic NAND gate using HSPICE
Reduction Operators, Logical Operators,
Relational Operators, Shift Operators,
SLO-2
Conditional Operator, Concatenation
Operator, Expressions and Operands,
Operator Precedence
Dynamic behavior: MOSFET
Secondary Parasitic Effects:Leakage
SLO-1 Verilog modelling: Gate-level modelling Ripple Carry Adder (RCA) Capacitances, viz., MOS structure
Currents, Parasitic Resistances
S-6 capacitances Simplified CMOS Process flow
Realization of Combinational and Channel capacitance and Junction (or,
SLO-2 Carry Look-Ahead Adder (CLA) Inverter layout
sequential circuits depletion) capacitances
Compilation and simulation of Verilog Parasitic Resistances, viz., Drain and Power-Delay Product: Static Power Layout design rules: Well rules,
SLO-1 Carry Select Adder (CSL)
code Source Resistance, Contact Resistance Consumption transistor rules
S-7
Non-ideal I-V effects: Mobility Dynamic Power Consumption, Total Contact rules, metal rules, via rules and
SLO-2 Test bench Carry Save Adder (CSA)
Degradation, Velocity Saturation Power Consumption, PDP other rules
Channel Length Modulation, Threshold CMOS Circuit Design Styles:Static
SLO-1 Dataflow modelling Carry Skip Adder (CSK) Gate Layouts
Voltage Effects CMOS logic styles
S-8 Leakage, Temperature Dependence,
Realization of Combinational and CMOS circuits, pseudo-nMOS, tristate
SLO-2 Carry Bypass Adder (CBA) Geometry Dependence, Subthreshold Stick diagrams
sequential circuits circuits, clocked CMOS circuits
Current
SLO-1 Lab-1:Realization of combinational and Lab-10: (a) Design and Analysis of
complex CMOS gate using HSPICE
S-9, 10 sequential circuits using gate-level and Lab-4:Realization of VLSI adders - I Lab-7: Realization of VLSI multipliers - II Lab-13: Model Practical Examination
SLO-2 dataflow modeling (b) Design and Analysis of Pseudo-NMOS
gates using HSPICE
Multipliers: Overview of multiplication
(unsigned multiplication, shift/add CMOS Process Enhancements:
Short-channel MOSFETS: Hot carriers, Differential Cascade Voltage Switch Logic
SLO-1 Behavioral modelling multiplication algorithms, multiplication of Transistors (Multiple Threshold Voltages
Lightly-Doped Drain (LDD) (DCVSL), Pass Transistor Logic (PTL)
S-11 signed numbers, types of multiplier and Oxide Thicknesses, Silicon-on-
architectures) Insulator, High-k Gate Dielectrics, Higher
Realization of Combinational and Dynamic CMOS logic styles: Basic Mobility, Plastic Transistors,)
SLO-2 Braun multiplier MOSFET scaling
sequential circuits dynamic logic
Short-channel effects: Negative Bias
SLO-1 Switch-level modelling Baugh-Wooley multiplier Temperature Instability (NBTI), oxide Signal integrity issues in dynamic design Interconnects
breakdown
S-12
Drain-Induced Barrier Lowering (DIBL),
SLO-2 Realization of MoS circuits Wallace Tree multiplier Gate-Induced Drain Leakage (GIDL), Signal integrity issues in dynamic design Circuit elements
Gate Tunnel Current
Domino Logic Circuits: Differential
SLO-1 Design using FSM Booth multiplier Tutorials Beyond conventional CMOS
S-13 Domino logic, multiple-output domino
SLO-2 Realization of sequential circuits Booth multiplier Tutorials Compound domino, NORA, TSPC Tutorials
SLO-1 Lab-2: (a) Realization of digital circuits Lab-11: (a) Design and Analysis of
AND/NAND gate in DCVSL using SPICE
using behavioral modeling Lab-14: End-Semester Practical
S-14, 15 Lab-5:Realization of VLSI adders - II Lab-8: Realization of RAM & ROM (b) Design and Analysis of Pass-
SLO-2 (b) Realization of MOS circuits using Transistor gates and CPL gates using
Examination
switch-level mdeling
HSPICE

9. Jan Rabaey, Anantha Chandrakasan, B Nikolic, “Digital Integrated Circuits: A Design 12. R. Jacob Baker, “CMOS Circuit Design, Layout, and Simulation”, Wiley, (3/e), 2010.
Perspective”. Second Edition, Feb 2003, Prentice Hall of India. 13. John P. Uyemura, “CMOS Logic Circuit Design”, Kluwer, 2001.
Learning
10. Weste, Harris, “CMOS VLSI Design: A Circuits and Systems Perspective”, 4th edition, Addision- 14. S. Palnitkar , Verilog HDL – A Guide to Digital Design and Synthesis, Pearson , 2003
Resources
Wesley, 2011. 15. Paul. R.Gray, Robert G. Meyer, “Analysis and Design of Analog Integrated Circuits”, Wiley, (4/e), 2001.
11. Wayne Wolf, “Modern VLSI Design: IP-based Design”, 4th edition, PHI, 2009. 16. M.D.Ciletti , Modeling, Synthesis and Rapid Prototyping with the Verilog HDL, Prentice Hall, 1999

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