IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 65, NO.

6, JUNE 2018 2647

Layout Design Correlated With Self-Heating

Effect in Stacked Nanosheet Transistors
Linlin Cai , Wangyong Chen , Gang Du, Member, IEEE , Xing Zhang,
and Xiaoyan Liu, Member, IEEE

Abstract — With technology node scaling down to 5 nm, choice of the width of nanosheets (Wshs) for device per-
the narrow device geometry confines the material thermal formance optimizations [5]–[7]. Nevertheless, the nanosheet
conductivity and further aggravates the self-heating effect FETs suffer from serious self-heating effects (SHEs) with size
in gate-all-around (GAA) transistors. In this paper, we inves-
tigate the self-heating of horizontally stacked three-layer scaling down. The major reasons are listed as follows.
GAA nanosheet transistors by 3-D finite-element model- 1) Confined dimensional structure increases the phonon-
ing (FEM) simulation. The anisotropic thermal conductivity boundary scattering, which makes the thermal conduc-
of nanosheets with the dependence of silicon thickness tivity decrease rapidly [8].
and temperature is implemented in the FEM simulator to 2) Low material thermal conductivity results in lattice tem-
evaluate thermal behavior accurately. The impact of layout
design on thermal properties is investigated comprehen- perature rise, which in turn degrades the temperature-
sively from single device to device arrays with implica- dependent thermal conductivity [9].
tion on electrical performance. The results indicate that 3) Increasing power density adds the burden of SHE on
the width of nanosheet is the key parameter to make the device.
tradeoffs between self-heating and electrical characteristic. 4) Stacked topological structure makes the heat dissipation
Meanwhile, the optimizations of layout design are given
to suppress the thermal effects, including self-heating, become more difficult.
nonuniformity of temperature, and thermal crosstalk at With multilayer staked nanosheets wrapped all-round by
device level. This paper will provide guidelines for lay- gate oxide and dielectric layers, it will be a long path
out design, thermal management, device performance, and from heat source to bulk substrate or contacts.
thermal-aware reliability prediction in the GAA-stacked In addition, the self-heated lattice temperature makes the
structure.
degradation of carrier mobility and the skewing of thresh-
Index Terms — Gate-all-around (GAA) transistor, layout old voltage [10]–[12], which further introduce the thermal-
design, nanosheet, self-heating effect (SHE), thermal
crosstalk. aware reliability issues such as bias temperature instability,
hot carrier injection, and time-dependent dielectric break-
I. I NTRODUCTION down [13], [14]. Hence, SHE evaluation is important to design

T HE GATE-all-around (GAA) transistors have been exten-

sively accepted to improve the electrical characteristics
with the higher drive current due to excellent short-channel
and optimize the performance and reliability of the nanosheet
transistors. Another problem in device design is the thermal
crosstalk, which indicates that SHE not only affects lifetime
controls and stacked structure for high-density integration of single device, but also exacerbates the degradation of
[1]–[3]. Nanosheet field effect transistor (FET) as a great neighbors [15], [16]. Recently, many efforts have been made
candidate, compared with nanowire FET [4], has a flexible about the exploration of electrostatics, integration process, and
parasitic components in horizontally stacked nanosheet FETs
Manuscript received November 16, 2017; revised March 5, 2018 and
April 3, 2018; accepted April 6, 2018. Date of publication April 23, 2018; [5]–[7], [17]. Similar structures such as trigate or nanowire
date of current version May 21, 2018. This work was supported in transistors about self-heating have been reported [18]–[21].
part by the National Natural Science Foundation of China under Grant However, few works focus on thermal effects in the stacked
2016YFA0202101, Grant 61674008, and Grant 61421005, and in part by
National High-Tech Research and Development Program (863 Program) nanosheet structure for sub-7-nm technology nodes. In this
under Grant 2015AA016501. The review of this paper was arranged by paper, we investigate the SHE of nanosheet FETs and the
Editor J. Knoch. (Corresponding authors: Xing Zhang; Xiaoyan Liu.) impact of layout design on thermal effects and device per-
L. Cai, W. Chen, G. Du, and X. Liu are with the Institute of
Microelectronics, Peking University, Beijing 100871, China (e-mail: formance. Material thermal conductivity which depends on
[email protected]; [email protected]; [email protected]; temperature and silicon thickness, as well as anisotropy in
[email protected]). channel regions are considered into 3-D finite-element mod-
X. Zhang is with the Institute of Microelectronics, Peking University,
Beijing 100871, China, and also with the National Key Laboratory of eling (FEM) simulation to assess accurately temperature dis-
Science and Technology on Micro/Nano Fabrication, Beijing 100871, tribution in nanoscale devices.
China (e-mail: [email protected]). This paper is organized as follows. In Section II, we describe
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org. basic device structure, related parameters and the simulation
Digital Object Identifier 10.1109/TED.2018.2825498 approach used in this paper. Section III shows the systematic

0018-9383 © 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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2648 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 65, NO. 6, JUNE 2018

TABLE I
D IMENSIONAL PARAMETERS AND T HERMAL C ONDUCTIVITIES

Fig. 1. Schematic of 3-D horizontally stacked GAA nanosheet FETs.

investigation of layout design correlated with self-heating in

nanosheet FETs from single stack and multiple stacks to
device arrays with implication on the device performance.
Some suggestions are given for mitigating the nonunifor-
mity of temperature profile and thermal crosstalk. Finally,
Section IV summarize this paper.

II. D EVICE S TRUCTURE AND M ETHOD

and temperature are used as follows [24]:
 π/2   
A. Device Structure l
κ (z) = κ0 (T ) sin θ 1 − exp −
3
2λ (T ) cos θ
Fig. 1 illustrates the schematic of 3-D horizontally stacked 0 
l − 2z
GAA nanosheet FETs with related dimensional parameters. × cosh dθ (1)
2λ (T ) cos θ
We use the 7-nm ground rule in this paper, referring to [5]  
and [17]. The length of channel (Lg) is set as 12 nm with 300
λ (T ) = λ0 (2)
the p-type doping concentration of 1016 cm−3 . The n-type T
doping concentration in source and drain regions is 1020 cm−3 . 100
κ0 (T ) = (3)
As a key parameter in nanosheet structure, the Wshs is varying a + bT + cT 2
from 5 to 50 nm to evaluate the impacts on thermal effects.
Three layers nanosheets are stacked vertically with the 10-nm where κ(z) is the in-plane thermal conductivity varying with
height spacing. The 5-nm thickness of inner spacer between the thickness of silicon film. κ0 (T ) is the bulk silicon thermal
source/drain and metal gate has been verified as an optimum conductivity which depends on the lattice temperature. Here,
value, ensuring no degradation in electrostatics [5]. Multiple a = 0.03 K · m/W, b = 1.56 × 10−3 K2 · m/W, and c =
stacks nanosheet FETs are also considered in this simulation to 1.65 × 10−6 K3 · m/W · l is the thickness of silicon film. λ(T )
investigate the differences of self-heating in each stack. Table I is the phonon mean free path of temperature dependence.
summarizes the values of symbols marked in Fig. 1, which will λ0 is equal to 300 nm at 300-K condition. Meanwhile, due
be a baseline in the following analysis. to heat conduction capability in perpendicular plane is much
lower than the in-plane [25], [26], we consider anisotropic
thermal conductivity in 5-nm thickness nanosheets by tensors
mathematic expression [κx , κ y , κz ]. The calculated thermal
B. Simulation Method
conductivity in different regions is shown in Fig. 2, and the
For thermal simulation, we integrate silicon thickness and values at 300 K are listed in Table I. It can be seen that the
temperature-dependent thermal conductivities into 3-D FEM substrate thermal conductivity (Ksub) reduce 50% when the
simulator COMSOL. In nanometer scale nonplanar devices, lattice temperature rise 200 K, which indicates that temper-
phonon-boundary scattering restricts the phonon mean free ature dependence cannot be ignored during device thermal
path, which is responsible for remarkably reducing material evaluations. Before the simulation, we define the boundary
thermal conductivity of thin films [8], [22]. The reported data conditions on the bottom of the substrate with the 300-K
have confirmed the silicon thermal conductivity in 10-nm heat sink. To simplify the complex interconnects of actual IC,
thickness film decreases almost an order of magnitude than the simulated transistors are covered with single-level back-
bulk silicon [23]. In addition, temperature dependence is also end-of line with 0.8-μm interconnect height and 300-K heat
the major issue that limits the thermal conductivity. The sink at the top of interconnects. The 2 × 10−8 K · m 2 /W
relationships of thermal conductivity between silicon thickness interface resistance is used to connect the top interconnects

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CAI et al.: LAYOUT DESIGN CORRELATED WITH SHE 2649

Fig. 2. Thermal conductivities with temperature dependence in dif-

ferent silicon regions of nanosheet FETs. (channel, source/drain, and
substrate).

and heat sink [27]. Other external boundary conditions are set
as thermal isolation.
To further investigate the degradation of electrical per-
formance by SHE, quantum hydrodynamic (QHD) mod-
els including extended Canali mobility model and Stratton
transport model [28] with equation of lattice temperature Fig. 3. (a) Heat flux diffusion in nanosheet FETs. (b) Asymmetrical
are used to obtain the current degradation. Based on [29], temperature differences in three layers along a–a’ direction. (c) Lattice
temperature profile along the channel direction. Peak temperature differ-
hydrodynamic method provide accurate results by taking into ence is about 7 K between layer 2 and layer 1.
account density-gradient correction model [30] for quantum
confinement effects in solving self-consistently the Poisson
equation, continuity equations, and energy balance equations.
In comparison to drift-diffusion and Monte Carlo methods,
QHD models reproduce velocity overshoot and provide the
better compromise between accuracy and computation time
for the sub-7-nm technology nodes.

III. R ESULTS AND D ISCUSSION

A. Device Performance Correlated With SHE
Self-heating induced the spatial temperature distribution
in stacked nanosheet FET is demonstrated in Fig. 3. The
rise of maximum lattice temperature reaches to 136 K in
the channel near drain regions under 67.5-μW heat power. Fig. 4. Id–Vg characteristics of nanosheet FET compared between with
Fig. 3(a) shows the heat flux diffusion of operating area SHE and without SHE in log-scale on the left axis and linear-scale on
the right axis.
in three-layer nanosheet FETs, which implies that the mid-
dle layer has the longer dissipation path to the heat sink.
The detailed temperature in different layers is illustrated in nanosheet FET correlated with SHE and without SHE. The
Fig. 3(b) with a slice along the a–a’ direction. The results results indicate that self-heating induces apparent current
show that the highest temperature is located in the middle degradation at high Vd. We take ON-state current as an
layer (layer 2), the second is in the top layer (layer 3), and indicator to evaluate the degree of degradation, (4) is used
the temperature of bottom layer (layer 1) is the lowest. The as below
differences of peak temperature in each layer at the interface Ion,w/oSHE − Ion,w/SHE
between channel and drain extension are about 7 K, as shown η= × 100% (4)
Ion,w/oSHE
in Fig. 3(c). The simulated data (not given in Fig. 3) show that
over 40% thermal energy transfers to the substrate, making where Ion,w/oSHE is the ON-state current without SHE.
layer 1 is much easily cooling down than layer 3, close to Ion,w/SHE is the ON-state current considering SHE. The data
interconnects. The asymmetrical temperature profile in the show that 136-K self-heated temperature rise causes about
stacked structure may induce the local hot spot; eventually 18.5% ON-state current degradation at Vg = Vd = 0.7 V.
influence the reliability of device.
The lattice temperature increase caused by SHE diminishes B. Layout Design for Single Device Correlated With SHE
the carrier mobility and results in the electrical performance From Section III-A, we conclude that stacked nanosheet
degradation. Fig. 4 shows the Id–Vg characteristics of the FET is facing two main thermal problems: one is the high

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2650 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 65, NO. 6, JUNE 2018

Fig. 7. Differences of peak temperature (ΔT ) between layer 2 and

layer 1 with a different Wsh and height of stacked nanosheets (H_NS).

Fig. 5. Lattice temperature in nanosheet FETs with a different Wsh. aggravates heat generation. To sum up, below the turning
(a) Wsh=5 nm. (b) Wsh=15 nm. (c) Wsh=25 nm. (d) Wsh=50 nm. The point, with the same current density, nanosheet FETs have
substrate, interconnects, source, and gate contacts are hid deliberately
for clarity. advantages in both thermal properties and driving current
compared to nanowire FETs, see region I. Over the turning
point, although the increased Wsh enhances the current, SHE
becomes severe, as illustrated in region II. Therefore, Wsh
provides a choice to make tradeoffs between thermal properties
and electrical performance.
The asymmetrical distribution of temperature in multilayer-
stacked nanosheets is also investigated. Fig. 7 shows the
impacts of Wsh and the height of stacked nanosheets (H_NS)
on temperature differences. The higher H_NS has the longer
dissipation path from the middle layer to heat sink, which
increases the thermal resistance, thus elevating the lattice
temperature. Therefore, optimizations strategy in layout for
minimizing differences is decreasing Wsh and H_NS for less
self-heating and better heat dissipation.
Fig. 6. Peak temperature rise in nanosheet FETs with increased Wsh.
Inset: related mechanism. C. Layout Design for Multiple Stacks Correlated
With SHE
lattice temperature by SHE and another is the asymmetrical To achieve the target ON-state current, such as multifin in
temperature profile. In this section, the impact of layout FinFETs, the stacked nanosheet transistors are also fabricated
design on thermal behavior of single device is investigated. with multiple stacks. However, increased number of stacks
The temperature distribution in nanosheet FETs with fixed will aggravate the self-heating due to the rising drive current,
Hsh = 5 nm and a different Wsh is illustrated in Fig. 5. as shown in Fig. 8. The temperature trends to saturation when
The substrate, interconnects, source, and gate contacts are hid the number of stacks gets beyond 25. Whereas, the certain
deliberately for clarity. number depends on the device configuration and spacing
Fig. 5(a)–(d) shows that the continuously increased Wsh of stacks in layout design. It is important to note that the
aggravates SHE due to higher drive current. With the identical nonuniform temperature distribution exists in multiple stacks.
current density, 2 × Wsh may lead to about 40 K higher than From Fig. 8, it can be seen that temperature in center stack
1 × Wsh, as shown in Fig. 6. The self-heating of stacked is higher than that in corner stack. The differences are always
nanowire with the same 5-nm width and thickness is compared existent unless the number of stacks reduces to two stacks as
in Fig. 6. It is interesting to note that the self-heating of a result of symmetry.
nanowire FETs is much severer than the nanosheet FETs with Taking a 12-stack nanosheet FET as an example, we inves-
Wsh less than 20 nm. Here, a turning point can be observed tigate the lattice temperature nonuniformity with the impact
at Wsh = 18 nm, where the peak temperature in nanosheet of Wsh. Fig. 9 demonstrates that the thermal crosstalk affects
is equal to that in nanowire. The inset shows that the lattice the neighbor stacks, as a result, compared to corner stack,
temperature is attributed to the process of heat generation and the center stack with the worse heat dissipation to pad suffers
heat dissipation. With larger Wsh, thermal resistance (Rth) from the more heating, easily causing the problem of perfor-
decreases due to the better heat dissipation and the power mance degradation, and lifetime reduction in devices. What is
increases as a result of the improvement of drive current which more, adjusting the Wsh has slight effect on the temperature

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CAI et al.: LAYOUT DESIGN CORRELATED WITH SHE 2651

Fig. 8. Average temperature rise in stacks trends to saturation with the

increased number of stacks.
Fig. 10. Temperature differences between center and corner stacks in
multiple stacks with varying spacing of stacks (Stack_S).

Fig. 11. ON-state current degradation induced by SHE with a different

lattice temperature.
Fig. 9. (a) Nonuniform temperature distribution in 12-stack nanosheet
FETs with Wsh = 25 nm. (b) Wsh has slight effect on alleviating the
differences between center and corner stacks.

differences in multiple stacks. Only 3 K decreases between

center stack and corner stack when reducing the Wsh from
50 to 15 nm. Nevertheless, a more effective method to alleviate
the nonuniform temperature profile is increasing the spacing
of stacks, as shown in Fig. 10. Nearly, half of temperature
differences are suppressed if the spacing of stacks expands
to 65 nm, compared with 38 nm. In addition, the differences
also trend to saturation with the number of stacks increased Fig. 12. Mechanism and elementary cell defined to evaluate the thermal
crosstalk in device arrays. The arrows stand for the heat diffusion paths.
on account of lattice temperature saturation. Initial values of Psti and Hsti are 20 and 100 nm, respectively.
Based on the earlier simulations, the lattice temperature can
increase ranging from 80 to 200 K induced by self-heating thermal crosstalk in different devices. First, the device arrays
of nanosheet FETs. The corresponding current degradation are divided into some equivalent elementary cells, as shown
at Vd = Vg = VDD (0.7 V) is plotted in Fig. 11. The in Fig. 12. In each cell, only one FET input heat power
data illustrate that 200-K lattice temperature rise cause about and another without power are solely investigated the thermal
22% ON-state current degradation. Again, effective thermal effect. Second, assuming that the two devices are fabricated on
management is necessary for achieving great performance. the same substrate without connection, the thermal crosstalk
ratio (TCR) is defined as follows:
D. Layout Design for Device Arrays Correlated With SHE
Q neighbor,in
Self-heating not only affects the performance in heat- TCR = (5)
Q total,out
generating device, but also disturbs the operation in adjacent
device, which may cause the problem of thermal crosstalk where Q neighbor,in is the thermal energy flow into the neighbor
in integrated circuits. We provide a method to quantify the device. Q total,out is the total thermal outflow in heat-generating

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2652 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 65, NO. 6, JUNE 2018

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degrees in microelectronics from the Shaanxi
[30] M. G. Ancona and G. J. Iafrate, “Quantum correction to the equation
Microelectronics Institute, Xi’an, China, in 1989
of state of an electron gas in a semiconductor,” Phys. Rev. B, Condens.
and 1993, respectively.
Matter, vol. 39, no. 13, pp. 9536–9540, 1989.
He is currently a Professor with the Institute
of Microelectronics, Peking University, Beijing,
Linlin Cai received the B.S. degree from Wuhan China. His current research interests include
University, Wuhan, China, in 2016. She is cur- CMOS process engineering and nanoscale
rently pursuing the Ph.D. degree with the Institute device modeling.
of Microelectronics, Peking University, Beijing,
China.

Wangyong Chen received the B.S. degree from Xiaoyan Liu (M’01) received the B.S., M.S., and
Hunan University, Changsha, China, in 2016. He Ph.D. degrees in microelectronics from Peking
is currently pursuing the Ph.D. degree with the University, Beijing, China, in 1988, 1991, and
Institute of Microelectronics, Peking University, 2001, respectively.
Beijing, China. She is currently a Professor with the Institute
of Microelectronics, Peking University. Her cur-
rent research interests include nanoscale device
physics, device simulation, and nanoscale device
modeling.

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