Addition and Subtraction with signed-magnitude data Everyday Multiplication Signed-magnitude representation For this representation,

arithmetic calculations with paper and pencil for signed binary numbers are multiplication is done by a process of successive shift and adds operations
straight forward and are helpful on deriving hardware algorithm. When two Successively accumulate partial products and shift it right.  Q  multiplier
signed numbers A and B are added are added are subtracted, we find 8 and Qs  sign.  SC  no. of bits in multiplier (magnitude only).  SC is
different conditions to consider as described in following table: Addition decremented after forming each partial product. When SC is 0, process
(subtraction) algorithm: when the signs of A and B are identical halts and final product is formed.  B  multiplicand, Bs  sign  Sum of A
(different), add magnitudes and attach the sign of A to result. When the and B forms a partial product
signs of A and b are different (identical), compare the magnitudes and
subtract the smaller form larger

Block Diagram Description: hardware above consists of registers A and B

and sign flip-flops A s and B s . subtraction is done by adding A to the 2’s
complement of B. Output carry is transferred to flip-flop E, where it can be
checked to determine the relative magnitude of two numbers. Add-overflow
flip-flop AVF holds overflow bit when A and B are added. Addition of A
and B is done through the parallel adder. The S output of adder is applied to
A again. The complementer provides an output of B or B’ depending on
mode input M. Recalling unit 2, when M = 0, the output of B is transferred
to the adder, the input carry is 0 and thus output of adder is A+B. when
M=1, 1’s complement of B is applied to the adder, input carry is 1 and
output is S = A+B’+1 (i.e. A-B)

Array Multiplier Checking the bits of the multiplier one at a time and
forming partial products is a sequential operation requiring sequence of add
and shift microoperations . The multiplication of two binary numbers can
be done with one microoperation by using combinational circuit that forms
product bits all at once. This is a fast way of multiplying two numbers since
all it takes is the time to propagate through the gates that form the
multiplication array. Consider multiplication of two 2-bit numbers:
Multiplicand = b1b0, Multiplier = a1a0, Product = c3c2c1c0
Booth multiplication Algorithm Booth algorithm gives a procedure for Division Algorithms Division of fixed-point binary numbers in signed-
multiplying binary integers in signed 2’s complement notation. magnitude representation is done with successive compare, shift and
Inspiration: String of 1’s in the multiplier from bit weight 2k to weight 2m subtract operations.
can be treated as 2k+1-2m . As an example, binary number 001110 (+14) Hardware Implementation for Signed-Magnitude Data While implementing
has string of 1’s from 23 to 21 (k=3, m=1). So, this number can be division in digital system, we adopt slightly different approach. Instead of
represented as 2k+1 - 2m= 24 - 21 = 16 – 2 = 14 (case is similar for -14 shifting divisor right, the partial remainder (or dividend) is shifted left.
(110010) = -24 +22 -21 ). Thus, M * 14 = M * 24 – M * 2 1 ; product can Hardware is similar to multiplication algorithm (not booth). Register EAQ
be obtained by shifting multiplicand M four times left and subtracted M is now shifted left with 0 inserted into Qn (Obviously, previous value of E
shifted left once. As in other multiplication schemes, Booth algorithm also is lost). (I am not redrawing the diagram guys, it’s all same as
requires examination of multiplier bits and shifting of the partial product. multiplication but EAQ is shifted left so change the direction of arrows at
Prior to shifting multiplicand may be: Subtracted <-- upon the encountering bottom).
first least significant 1 in the string of 1’s in the multiplier.
Added <-- upon encountering first 0 (left of it must be 1) in string of 0’s in Divide Overflow  Division operation may result in a quotient with an
the multiplier. overflow when working with finite size registers.  Storing divisor in n-bit
Unchanged <-- when multiplier bit (Qn) is identical to previous multiplier resister and dividend in 2 n-bit registers, then if quotient occupies n+1 bits,
bit (Qn+1) we say divide-overflow has occurred (since n+1 bit quotient can not be
stored in standard n-bit Qregister and/or memory word).  Talking about
special case: size (dividend) = 2 * size (divisor). Divide-overflow condition
will occur if high-order half bits of the dividend >= divisor. This condition
is detected by DVF (Divide-overflow Flip-flop
Handling of overflow: its programmer’s responsibility to detect DVF and
take corrective measure. The best way is to use floating point data