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ECEN 3130: Switching Circuits Theory: Lab5: Two Decade Counter

This document provides instructions for a lab assignment to design a two-decade BCD counter in Verilog that counts from 00 to 99. It explains that the circuit will use two instances of a BCD counter module, one for the units digit and one for the tens digit. The tens digit counter should only advance every 10 counts of the units digit counter. Students are asked to implement this two-decade counter in Verilog and generate a waveform showing the output counting from 00 to 99 to 00.

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33 views2 pages

ECEN 3130: Switching Circuits Theory: Lab5: Two Decade Counter

This document provides instructions for a lab assignment to design a two-decade BCD counter in Verilog that counts from 00 to 99. It explains that the circuit will use two instances of a BCD counter module, one for the units digit and one for the tens digit. The tens digit counter should only advance every 10 counts of the units digit counter. Students are asked to implement this two-decade counter in Verilog and generate a waveform showing the output counting from 00 to 99 to 00.

Uploaded by

Daniyal Asif
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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ECEN 3130: Switching Circuits Theory

Lab5: Two Decade Counter


Due Date: Mon, 3/15/2021

Design Problems
• To build a Two-Decade BCD counter which counts from 00-99. Since each display
can show numbers from 0-9 (a decade), this circuit is called a Two-Decade BCD
counter.
Instructions & Tips:

1. BCD Counter
This is the basic building block of the circuit. Name the module BCDCounter.
Inputs:
CLOCK: The counter advances on the rising edge of the clock if ENABLE is high.
RESET: Asynchronous reset. Counter is cleared when the RESET input is high.
ENABLE: Enable the counter. Does not affect the RESET.
Outputs:
BCD[3:0]: Four-bit BCD counter value. BCD[3] is the MSB and BCD[0] is the LSB.
TC: Terminal Count is high when the counter value is 9 and ENABLE is high.
2. Two Decade Counter
Name this module TwoDecadeCounter. It will utilize two instances of
BCDCounter.
Inputs:
CLK: The counter advances on the rising edge of the CLK if EN is high.
RESET: Asynchronous reset. Counter is cleared when the RESET input is high.
EN: Enables counter. Does not affect the RESET.
Outputs:
A3,A2,A1,A0: BCD outputs of the first counter (units digit).
A7,A6,A5,A4: BCD outputs of the second counter (tens digit).

From the above information, it is clear that the instance of the BCD Counter in your Verilog code
controlling the tens digit should only become active once every 10 counts of the units digit.
Example code:
module TwoDecadeCounter(…);
input …;
output …;
wire …;
…
BCDCounter digit1 (…);
BCDCounter digit10 (…);
endmodule

module BCDCounter(…);
…
always @(posedge CLOCK or posedge RESET)
…
if(RESET)
…
else if (ENABLE)
…
endmodule

➢ Block diagram is not required in this lab. Implement the TwoDecadeCounter


using Verilog and generate the corresponding waveform. Your waveform
should involve at least 00-99-00.

➢ Before you leave the Zoom room, ask TA to check off. If you cannot finish the
lab by the end of class, email screenshots of your results to TA to check off.

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