DLD Course Outline Spring 2021
DLD Course Outline Spring 2021
PROGRAM (S) TO BE
BS (CS)
EVALUATED
A. Course Description
1 NCEAC.FORM.001.C
and Log
2 NCEAC.FORM.001.C
Oral and Written
Communications
Evaluation
Week Lecture Topics Covered References
Instrument
Digital and Analog quantities, Signals
1 Sampling using ADC&DAC, Binary digits, Logic Levels, Floyd
Digital waveforms
1 Introduction to Logic Gates, Truth tables for 2,3,and 4
inputs, Logic symbols, Boolean expressions,
2 Floyd
Fundamental Gates AND, OR and NOT gates.
Importance of XOR, XNOR gates.
3 NCEAC.FORM.001.C
2 lines to 4 lines decoder
3 lines to 8 lines decoder
4 lines to 16 lines decoder
BCD to Decimal Decoder
BCD to 7 Segment decoder with Table
implementation.
Combinational logic design for Encoders
4 lines to 2 lines encoder
8 lines to 3 lines encoder
16 lines to 4 lines encoder
Decimal to BCD encoder (Key Pad) Assignment 2
13 Floyd
Priority Encoder (Morris Mano)
Example( Full adder implementation with decoder and
OR gate)
7
Example (Importance of Encoders and Decoders in
Digital communication systems)
Combinational logic design for Multiplexers (PISO)
4 line to 1 line MUX or (1-Of-4 MUX)
8 line to 1 line MUX or (1-Of-8 MUX) Quiz 4
14 Floyd
16 line to 1 line MUX or (1-Of-16 MUX)
10 line to 1 line MUX or (1-Of-10 MUX)
Canonical function implementation with MUX
Combinational logic design for DEMultiplexers (SIPO).
1 line to 4 lines DEMUX
1 line to 8 lines DEMUX
15 1 line to 16 line DEMUX Floyd
8 1 line to 10 line DEMUX
Combinational logic implementation using MUX Folding
Technique & DEMUX with active high and active low
enable inputs
16 Review
MID TERM WEEK
BCD Adder design, 2 bit, 3 bit and 4 bit Magnitude
17 Morris
Comparator design
9 Sequential circuits, Function of Latch, SR latch using
18 NAND and NOR gates, Active high and active low latch Morris
design,
Quiz 5
SR Flip-Flop, D Flip-Flop, JK Flip-Flop and T Flip Flop,
19 Project Morris
Clocking
10 Proposal
Flip- Flop Applications (Counters, Frequency divider,
20 Floyd
Registers and Memory)
Excitation tables for SR, JK, T and D Flip-Flops using Quiz 6
21 Morris
11 their characteristics tables
22 Flip Flop conversions SR to D, JK to D Morris
4 NCEAC.FORM.001.C
Sequential logic design process, State diagram and State Assignment 3
23 Floyd
tables, Steps to design sequential circuit.
12
4 Bit Up/Down Synchronous Counters design with clock
24 Floyd
diagram
4 Bit Asynchronous Counters design with clock diagram, Quiz 7
25 Up/Down and Auto reset operations using NAND gate Floyd
13 (Truncated sequence)
Design 2 bit,3 bit up-down counter with gray code Quiz 8
26 Floyd
sequence,
5 NCEAC.FORM.001.C