UEEA/UEEP 1323 Digital Electronics

Results and Summary for Laboratory 2

Name LAU LOK BIN ID 1902064

Program MH Date 24/03/2021

Group * Ignore this for OTL

members

Experiment 1

1. State Diagram (4 Marks)

001

111 010

100

2. State Table (4 Marks)

PRESENT STATE NEXT STATE INPUT

A B C A+ B+ C+ DA DB DC
0 0 0 - - - X X X
0 0 1 0 1 0 0 1 0
0 1 0 1 0 0 1 0 0
0 1 1 - - - X X X
1 0 0 1 1 1 1 1 1
1 0 1 - - - X X X
1 1 0 - - - X X X
1 1 1 0 0 1 0 0 1
UEEA/UEEP 1323 Digital Electronics

3. Karnaugh maps (6 Marks)

DA
AB\C 0 1

00 X 0
01 1 X
11 X X
10 1 0
DA = C’

DB
AB\C 0 1
00 X 1
01 0 X
11 X 0
10 1 X
DB = B’

DC
AB\C 0 1
00 X 0
01 0 X
11 X 1
10 1 X
DC = A
UEEA/UEEP 1323 Digital Electronics

4. Logic circuit diagram (4 Marks)

DA QA DB QB DC QC

CLK QA’ CLK QB’ CLK QC’

CLK
UEEA/UEEP 1323 Digital Electronics

Experiment 2

1. State Diagram (4 Marks)

001 010 011

000 100

111 110 101

2. State table (4 Marks)

PRESENT STATE NEXT STATE INPUT

A B C A+ B+ C+ JA KA JB KB JC KC
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 0 1 1 0 X X 0 1 X
0 1 1 1 0 0 1 X X 1 X 1
1 0 0 1 0 1 X 0 0 X 1 X
1 0 1 1 1 0 X 0 1 X X 1
1 1 0 1 1 1 X 0 X 0 1 X
1 1 1 0 0 0 X 1 X 1 X 1
UEEA/UEEP 1323 Digital Electronics

3. Karnaugh maps (6 Marks)

JA 0 1 JB 0 1 JC 0 1
00 0 0 00 0 1 00 1 x
01 0 1 01 x x 01 1 x
11 x x 11 x x 11 1 x
10 x x 10 0 1 10 1 x
JA = BC JB = C JC = 1

KA 0 1 KB 0 1 KC 0 1
00 x x 00 X X 00 X 1
01 x x 01 0 1 01 X 1
11 0 1 11 0 1
11 X 1
10 0 0 10 X X
10 X 1
KA = BC KB = C
KC = 1
UEEA/UEEP 1323 Digital Electronics

4. Logic circuit diagram (4 Marks)

J Q J Q J Q

A B C

K Q’ K Q’ K Q’

1
CLK
UEEA/UEEP 1323 Digital Electronics

Summary and Discussion (4 Marks)

The sequence for experiment 1 was illustrated with the state diagram as 001,010,100,111
which translates to 1,2,4,7 in decimal. The equation for D-flip flop is Qn+1 = D where Qn+1
is the next state and D is the input. While the sequence for experiment 2 was illustrated
with the state diagram as 001,010,011,100,101,110,111,000 which translates to
1,2,3,4,5,6,7,0 in decimal, the equation for JK flip flop is Qn+1 = Qn’*J+ Qn*K’ where Qn+1
is the next state, Qn is the present state, J and K are inputs.

Option 1 Physical: (either Experiment 1 or 2)

Demonstration of Prototype (10 marks)

Prototype 1 2 3 4 5 Comment
Functionality

Workmanship

Check by: _________________________

Rubric for Demonstration of Prototype

UEEA/UEEP 1323 Digital Electronics

1 2 3 4 5
Scale/Score Poor Unsatisfactory Satisfactory Good Excellent
The prototype The prototype The prototype The prototype The prototype
has no any has few relevant has all the has all the has complete,
functionality functionality, but functions functions clear and obvious
required to occasionally required to meet required to meet functionality to
meet the adjustment is the objectives, the objectives meet the
Functionality objectives. required. but minor and operates objectives and it
adjustment is repeatedly operates
required. without excellently
adjustment or without
repair. adjustment or
repair.
Use of Unsatisfactory Satisfactory Good Excellent quality
improper workmanship workmanship workmanship of prototype with
gates/IC, poor with unfirmed with proper with proper firm and tidy
Workmanship wire cuts and gates/IC, messy gates/IC, wires gates/IC, cleanly circuit, Proper
messy wires wires and and cuts, proper gates/IC, wires,
arrangement. arrangement. arrangement. wires and wire’s colour
arrangement. usage.

Option 2 OTL: (Experiment 2)

Design Simulation (10 marks)

Simulation 1 2 3 4 5 Comment
Functionality and
performance
Clarity and systematic

Rubric for Design Simulation

1 2 3 4 5
Scale/Score Poor Unsatisfactory Satisfactory Good Excellent
The design The design has The design has The design has The design has
has no any few relevant all the all the complete, clear
Functionality
functionality functionalities, functionality functionality, and obvious
and
required to but occasionally required to meet and advanced advanced all the
performance
meet the make some the objectives. few of the functionality.
objectives. errors. functions.

The design is The design is The design is The design is The design is
not systematic systematic but systematic systematic with very systematic
and messy, not easy to design, easy to all the labeling, with all the
Clarity and hard to understand and understand and easy to labeling, very
systematic understand. use. use. understand and easy to
use. understand and
convenient to
use.