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Lab 12 DLD

This document describes a lab experiment on modeling digital logic circuits to implement a full adder using 2, 2x4 decoders. The objectives are to implement a full adder using a 2x4 decoder. It introduces flip-flops including SR, JK, and D flip-flops. The procedure describes designing the circuit on a logic trainer and observing the outputs. Results show the truth tables for SR, JK, and D flip-flops. Circuit diagrams of the different flip-flops are also presented. The conclusions discuss learning about different types of flip-flops, their truth tables, and implementing a D flip-flop in the lab.

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Noman Khan
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162 views4 pages

Lab 12 DLD

This document describes a lab experiment on modeling digital logic circuits to implement a full adder using 2, 2x4 decoders. The objectives are to implement a full adder using a 2x4 decoder. It introduces flip-flops including SR, JK, and D flip-flops. The procedure describes designing the circuit on a logic trainer and observing the outputs. Results show the truth tables for SR, JK, and D flip-flops. Circuit diagrams of the different flip-flops are also presented. The conclusions discuss learning about different types of flip-flops, their truth tables, and implementing a D flip-flop in the lab.

Uploaded by

Noman Khan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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LAB NUMBER 12

 TITLE
 Model Digital Logic Circuits For Implementation of Full Adder with 2, 2X4 Decoders
 OBJECTIVES
 Implementation of Full Adder Using 2X4 Decoder
 INTRODUCTION
Flip Flop
A flip flop, on the other hand, is synchronous and is also known as gated or clocked SR latch.
The output is changed (i.e. the stored data is changed) only when you give an active clock signal.
Otherwise, even if the S or R is active the data will not change. Let’s look at the types of flip-
flops to understand better.
SR Flip Flop
There are majorly 4 types of flip flops, with the most common one being SR flip flop. This simple
flip flop circuit has a set input (S) and a reset input (R). In this circuit when you Set “S” as active
the output “Q” would be high and “Q‘‘” will be low. Once the outputs are established, the wiring
of the circuit is maintained until “S” or “R” go high, or power is turned off. As shown above, it is
the simplest and the easiest to understand. The two outputs, as shown above, are the inverse of
each other.
JK Flip-flop
Due to the undefined state in the SR flip flop, another flip flop is required in electronics. The JK
flip flop is an improvement on the SR flip flop where S=R=1 is not a problem.
D Flip Flop
D flip flop is a better alternative that is very popular with digital electronics. They are commonly
used for counters and shift-registers and input synchronisation.
 PROCEDURE
 In the lab first ic is taken and circuit is designed on logic trainer and then inputs are given and
respective output is taken from toggling the inputs.
 In the lab we have only performed D flip flop.
 RESULTS
SR Flip Flop

S R Q Q’
0 0 0 1
0 1 0 1
1 0 1 0
1 1 Invalid Invalid
JK Flip-flop

J K Q Q’
0 0 0 0
0 1 0 0
1 0 0 1
1 1 0 1
0 0 1 1
0 1 1 0
1 0 1 1
1 1 1 0

D Flip Flop

Clock D Q Q’
0 0 0 1
1 0 0 1
0 1 0 1
1 1 1 0

 CIRCUIT
Flip Flop

SR Flip Flop
JK Flip-flop

D Flip Flop

 CONCLUSIONS
In this lab we have learned about flip flop ,SR flip flop, JK flipflop and D flip flop and observed
how actually they work and we have determined their truth tables and there circuit diagrams.
And in the end we have implemented practically D flipflop in lab and determined its truth tables
etc
 REFRENCE
https://electronicsforu.com/resources/learn-electronics/flip-flop-rs-jk-t-d

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