COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

LESSON 1 – SIGNALS
SIGNAL
- energy applied to a circuit to cause it to perform an intended action, such as
transmission or reception of information

1. ANALOG SIGNAL
- any continuous signal for which the time varying feature (variable) of the signal
is a representation of some other time varying quantity
- nominally continuous electrical signal that varies in amplitude or frequency in
response to changes in sound, light, heat, position, or pressure
- continuously varying representation of a condition, physical phenomenon, or
quantity such as flow, pressure, or temperature, transmitted as electrical,
mechanical, or pneumatic energy
- EXAMPLES:
 THERMOMETERS
 CLASSICAL MECHANICS
o used for describing the motion of macroscopic objects, from projectiles
to parts of machinery, as well as astronomical objects, such as
spacecraft, planets, stars, and galaxies
 PNEUMATICS
o the use of pressurized gas to affect mechanical motion
o Pneumatic power is used in industry, where factory machines are
commonly plumbed for compressed air; other compressed. Pneumatics
also has applications in dentistry, construction, mining, and other areas

2. DIGITAL SIGNAL
- in computer architecture, and other digital systems, a DIGITAL SIGNAL is a
waveform that switches between two voltage levels that represents two
states (0 and 1)
- EXAMPLES:
 LAPTOP / LCD MONITOR
 CAMCORDER / DIGITAL CAMERAS
 HANDHELD PC / BLACKBERRY PDA
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

DIGITAL SYSTEMS AND SWITCHING CIRCUITS

DESIGN OF DIGITAL SYSTEMS
 SYSTEM DESIGN
- involves breaking the overall system into subsystems and specifying the
characteristics of each subsystem
- EXAMPLE:
The design of a computer system may involve specification of the following:
o number & type of memory units
o arithmetic units
o input-output devices
o connection & control of subsystems

 LOGIC DESIGN
- involves determining on how to interconnect basic logic building blocks to
perform specific functions
- EXAMPLE:
o Determining the interconnection of logic gates and flip-flops required
to perform binary addition
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

 CIRCUIT DESIGN
- involves specifying the interconnection of certain components (resistors,
diodes, transistors, etc.) to form a gate, flip-flop, or other logic building
block using appropriate computer-aided design tools
- EXAMPLE:
o Laying out and interconnection of components on a silicon chip

SWITCHING FUNCTIONS
- Many things can be described by two distinct
states; for example, a light can be ``on'' or ``off;'' a
door can be ``open'' or ``closed;'' a statement can
be ``true'' or ``false.''
- A number system which has only two digits, 0 and
1, can be defined to represent any number (the binary number system.)
- A typical electronic device with 2 states is a switch, which can be ``on''
(switch closed) or ``off'' (switch open).
- Switching functions can be implemented using simple switches. In digital
electronic circuits, transistors are used as simple switches in circuits very
similar those which follow.
- The functions NOT, AND and OR can be easily implemented with two simple
switches.
- Any set that is restricted to a finite number of elements contain discrete
information
- EXAMPLES OF DISCRETE SETS:
o 10 decimal digits o 52 playing cards
o 26 letters of the alphabet o 64 squares of a chessboard
- Early digital computers were used mostly for numeric computations. In this
case, the discrete elements used were the digits. From such an application,
the term digital computer emerged.
- Discrete elements of information are represented in a digital system by
physical quantities called signals.
- EXAMPLES:
o Voltage
o Current
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

- Electronic devices called transistors predominate in the circuitry that

implements these signals. The signals in most present-day electronic digital
systems use just two discrete values and are therefore said to be binary.

NUMBER SYSTEMS AND CONVERSIONS

DECIMAL Numbering System
- In writing decimal (base 10) numbers, the positional notation is used. Each
digit is multiplied by the appropriate power of 10 depending on its position
in the number.
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

Decimal Binary Octal Hexadecimal

(Base 10) (Base 2) (Base 8) (Base 16)
00 0 0 0 0 00 0
01 0 0 0 1 01 1
02 0 0 1 0 02 2
03 0 0 1 1 03 3
04 0 1 0 0 04 4
05 0 1 0 1 05 5
06 0 1 1 0 06 6
07 0 1 1 1 07 7
08 1 0 0 0 10 8
09 1 0 0 1 11 9
10 1 0 1 0 12 A
11 1 0 1 1 13 B
12 1 1 0 0 14 C
13 1 1 0 1 15 D
14 1 1 1 0 16 E
15 1 1 1 1 17 F
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DECIMAL to BINARY RULES:

1. Divide the given decimal number by 2, placing the first remainder on the
lowest-order binary digit position of the partial result.
2. Continue dividing the quotient by 2, placing the next remainder on the next
higher-order binary digit position of the partial result.
3. Operation stops when quotient is no longer divisible by 2, placing the last
remainder on the highest-order binary digit position.

SPECIAL NOTES: (DECIMAL NUMBERS)

- Fractional decimal numbers can be converted to binary by multiplying the
fraction by 2 and then placing the portion of the product (to the right of the
decimal point) on the highest-order binary digit position.
- Continue multiplying the fractional portion of the previous product by 2
placing the portion of the new product on the next lower-order binary digit
position until the desired degree of accuracy is attained.

SPECIAL NOTES: (MIXED NUMBERS)

- To convert a mixed number to binary, split the number into its whole and
fractional components and solve each one separately.
- When the conversion of each is completed, recombine it with the radix
(base) point.
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

EXAMPLES:
1. Convert 1310 to binary (base 2)

2. Convert 0.2510 to its binary equivalent

3. Convert 13.2510 to its binary equivalent

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BINARY to DECIMAL RULES:

1. Multiply the digit on the highest-order binary digit position by 2.
2. Add the digit on the next lower-order binary digit position to the product.
3. Multiply the sum by 2.
4. Repeat the process down to the lowest-order binary digit position.
NOTE: LAST STEP MUST BE ADDITION.

EXAMPLE: Convert 1 0 1 12 to decimal (base 10)

DECIMAL to OCTAL RULES:

1. Divide the given decimal number by 8, placing the first remainder on the
lowest-order octal digit position of the partial result.
2. Continue dividing the quotient by 8, placing the next remainder on the next
higher-order octal digit position of the partial result.
3. Operation stops when quotient is no longer divisible by 8, placing the last
remainder on the highest order octal digit position.

SPECIAL NOTES: (DECIMAL NUMBERS)

- Fractional decimal numbers can be converted to octal by multiplying the
fraction by 8 and then placing the portion of the product (to the right of the
decimal point) on the highest-order octal digit position.
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

- Continue multiplying the fractional portion of the previous product by 8

placing the portion of the new product on the next lower-order octal digit
position until the desired degree of accuracy is attained.

EXAMPLE: Convert 34.52510 to octal (base 8)

DECIMAL to HEXADECIMAL RULES:

1. Divide the given decimal number by 16, placing the first remainder on the
lowest-order hexadecimal digit position of the partial result.
2. Continue dividing the quotient by 16, placing the next remainder on the next
higher-order hexadecimal digit position of the partial result.
3. Operation stops when quotient is no longer divisible by 16, placing the last
remainder on the highest-order hexadecimal digit position.
NOTE: IF THE REMAINDER EXCEEDS 9, CONVERT IT TO ITS CORRESPONDING
HEXADECIMAL EQUIVALENT (A to F)

EXAMPLE: Convert 2773.8510 to hexadecimal (base 16)

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HEXADECIMAL TO DECIMAL RULES:

1. Multiply the highest-order hexadecimal digit by 16.
2. Add the digit on the next lower-order hexadecimal digit position to the
product.
3. Multiply the sum by 16.
4. Repeat the process down to the lowest-order hexadecimal digit position.
NOTES:
1. LAST STEP MUST BE ADDITION.
2. IF THE HEXADECIMAL NUMBER IS REPRESENTED BY A LETTER (A to F),
CONVERT IT TO ITS CORRESPONDING DECIMAL EQUIVALENT (10 to 15)

BINARY TO OCTAL RULES:

1. Starting from the LSB, group three (3) digits at a time.
2. Replace the 3-bit group by their decimal equivalent
NOTE: For fractions, grouping of bits starts from MSB.

EXAMPLE: Convert 1 1 1 0 1 0 1 0 . 0 1 1 12 to octal (base 8)

EXAMPLE: Convert 3 5 2 . 3 4 8 to binary (base 2)

HEXADECIMAL TO BINARY RULES:

1. Simply get the corresponding equivalent of each hexadecimal digit to
binary.
2. Conversion can start at either end.
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

EXAMPLE: Convert 81AD.1D16 to binary (base 2)

BINARY TO HEXADECIMAL RULES:

1. Just group the binary digits into 4-bit group starting from the right, then give
the corresponding hexadecimal equivalent of each group.
2. Conversion can start at either end.
NOTE: For fractions, grouping starts from left to right

EXAMPLE: Convert 101011001110.111011112 to base 16

OCTAL TO HEXADECIMAL RULES:

1. Convert the given octal number to binary
2. Form groups of 4 bits then get the hexadecimal equivalent of each 4-bit
group

EXAMPLE: Convert 36.5328 into an equivalent hexadecimal number

 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

HEXADECIMAL TO OCTAL RULES:

1. Convert the given hexadecimal number to binary
2. Form groups of 3 bits then get the octal equivalent of each 3-bit group

EXAMPLE: Convert 1E.AD016 into an equivalent octal number

 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

LESSON 2 – ARITHMETIC OPERATIONS

Arithmetic Operations
- Arithmetic operations in digital systems are usually done in binary because
design of logic circuits to perform binary arithmetic is much easier than for
decimal.

BINARY ADDITION RULES:

0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 0 w/ a carry of 1 on the next higher-order binary digit position

EXAMPLE:

Octal Addition
RECALL:
In the octal numbering system, the lowest digit is 0 and the highest is 7.If
the result is greater than 7, divide it by 8, placing the quotient (as a
“carry”) on the next higher-order octal digit position, and the remainder
as part of the sum. Repeat the process up to the most significant bit of
the operands.

EXAMPLE:
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

Hexadecimal Addition
RECALL:
In the hexadecimal numbering system, the lowest digit is 0 and the
highest is F. If the result is greater than 15, divide it by 16, placing the
quotient (as a “carry”) on the next higher-order hexadecimal digit
position, and the remainder as part of the sum. Repeat the process up to
the most significant bit of the operands.

EXAMPLE:

BINARY SUBTRACTION RULES:

0 — 0 = 0
1 — 0 = 1
1 — 1 = 0
0 — 1 = 1 w/ a borrow of 1 from the next higher-order binary digit position

EXAMPLES:

Subtraction of Decimal Numbers

 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

The 9's Complement

- The 9’s complement of a decimal number is the new number obtained by
subtracting the given decimal number from a series of 9s.
-
EXAMPLES:

The 10's Complement

- The 10’s complement of a decimal number is the new number obtained by
adding 1 to the 9’s complement of the given decimal number.
RULES:
• Make the number of digits in the subtrahend and minuend equal by padding
zeros to the left of the operands whenever necessary.
• Get the 10’s complement of the subtrahend and then add it to the minuend.
NOTES:
 If the sum has an overflow, it means that the result is positive, simply
discard the overflow to get the final answer.
 If the sum has no overflow, then the result is negative, simply get the 10’s
complement of the result and affix the negative (-) sign for the final answer.

EXAMPLES:
Find the 10’s complement of 7. Find the 10’s complement of 75.

.
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

EXAMPLES:
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

REPRESENTATION OF NEGATIVE NUMBERS

- Positive integers (including zero) can be represented as unsigned numbers.
However, to represent negative integers, a notation is needed for negative
values. It is customary to represent the sign with a bit placed in the leftmost
position of the number.

EXAMPLE: Let X represent an 8-bit signed binary integer which follows the format
X7X6X5X4X3X2X1X0

EXAMPLE: Let X represent an 8-bit signed binary fraction which follows the format
X7X6X5X4X3X2X1X0
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COMPARISON OF SIGNED 4-Bit BINARY INTEGER REPRESENTATION

DECIMAL SIGN
1’s COMPLEMENT 2’s COMPLEMENT
VALUE MAGNITUDE
+7 0111 0111 0111
+6 0110 0110 0110
+5 0101 0101 0101
+4 0100 0100 0100
+3 0011 0011 0011
+2 0010 0010 0010
+1 0001 0001 0001
+0 0000 0000 0000
-0 1000 1111 0000
-1 1001 1110 1111
-2 1010 1101 1110
-3 1011 1100 1101
-4 1100 1011 1100
-5 1101 1010 1011
-6 1110 1001 1010
-7 1111 1000 1001
-8 not possible not possible 1000
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

THE 1’s COMPLEMENT

- The 1’s complement of a binary number is the new number obtained by
subtracting the given binary number from a series of 1s, or by simply
complementing each bit in the given binary number.

EXAMPLES:
Find the 1’s complement of 10012. Find the 2’s complement of 00012.

THE 2’s COMPLEMENT

- The 2’s complement of a binary number is the new number obtained by
adding 1 to the 1’s complement of the given binary number.
RULES:
 Make the number of digits in the subtrahend and minuend equal by padding
zeros to the left of the operands whenever necessary.
 Get the 2’s complement of the subtrahend and then add it to the minuend.
NOTES:
 If the sum has an overflow, it means that the result is positive. Simply discard
the overflow to get the final answer.
 If the sum has no overflow, then the result is negative. Simply get the 2’s
complement of the result and affix the negative (-) sign for the final answer.

SEATWORK: PERFORM THE ARITHMETIC OPERATIONS USING THE 2’s COMPLEMENT METHOD:
11111111 00001010 00000001
-10101010 -11101111 -11111111
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

EXAMPLE: Perform the following arithmetic operations using the 2’s complement
method:
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

LESSON 3 – DATA REPRESENTATION

DATA CONVERSION
- BYTE
o the smallest addressable location in the computer’s memory
- BIT
o stands for BInary digiT
- NIBBLE
o 4-bit group (ex.: 0001, 1010)
- 1 byte = 2 nibbles = 8 bits

BASIC TYPES OF INFORMATION

UNPACKED PACKED
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

The UNPACKED Format (. . . D2D1D0)

- zone-decimal format
- uses 1 byte for each digit of the decimal number

EXAMPLE: Represent the decimal number +789 in the unpacked decimal format.

The PACKED Format (. . . D4D3D2D1D0)

- The PACKED format uses 1 byte to represent numeric value of two digits.
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

EXAMPLE: Represent the decimal number +789 in the packed decimal format.
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

The HOLLERITH Code

- A coding system wherein data are stored by punching holes on the output
medium (IBM card)
- American inventor Herman Hollerith developed the punch card system of
recording data, an important step in the development of computers. In 1896
he organized the Tabulating Machine Corporation, which became the
International Business Machines Corporation (IBM) in 1924.

THE IBM CARD

- Made of heavy, stiff, stock paper, it measured 3-1/4" high by 7-3/8" wide with
80 columns numbered left to right and 12 rows from top to bottom.

Coding Techniques
NUMERIC CHARACTERS : One punch in a column (digit portion)
ALPHABETIC CHARACTERS : Two punches in a column (zone and digit portions)
SPECIAL CHARACTERS : One, two or more punches in a column

 THE IBM CARD PUNCH MACHINE

- card punch has 12 keys corresponding to the rows in a standard Hollerith card
- several keys can be pushed at the same time
- additional keys are for shifting the card
- actual punching is done by an electromagnet-actuated mechanism
 M-1000 CARD READER
 THE IBM Model 129: REPRODUCING CARD PUNCH
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The HOLLERITH Table

Zone zone portion
Digit 12 11 10

1 A J /
2 B K S
3 C L T
digit portion 4 D M U
5 E N V
6 F O W
7 G P X
8 H Q Y
9 I R Z

EXAMPLE: Starting in column 5 of an IBM card, store the number 179.

 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

EXAMPLE: Starting in column 1 of an IBM card, store the word KATRINA.

The EBCDIC Table

- EBCDIC = Extended Binary Coded Decimal Interchange Code
- IBM’s 8-bit extension of the 4-bit Binary Coded Decimal encoding of digits 0-9
(0000-1001).
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

The ASCII Character Code

- The standard binary code for the alphanumeric characters is called ASCII
(American Standard Code for Information Interchange)
- 74 bits represents 128 characters: 94 printable and 34 non-printable

The PARITY Bit

- A parity check is based on the use of an additional bit, known as Parity Bit, in
each code group. If a single error occurs in transmitting a code group to the
outside world, the parity bit will indicate an error has occurred.
- To detect errors in data communication and processing, an 8th bit is sometimes
added to the ASCII character to indicate its parity. The bytes are traveling in an
asynchronous manner (with no regular spaced pattern), from the transmitter
to the receiver.
EXAMPLE: The rate data is being typed into the keyboard.
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

BINARY CODES
- The binary system is the most natural system Bit 3 Bit 2 Bit 1
for a computer, but people are accustomed to
the decimal system. One way to resolve this 0 0 0
difference is to convert decimal numbers to 0 0 1
binary, perform all arithmetic calculations in
0 1 0
binary, and then convert the binary results
back to decimal. 0 1 1
- An n-bit binary code is a group of n bits that 1 0 0
assume up to 2n distinct combinations of 1’s
and 0’s, with each combinations representing 1 0 1
one element of the set being coded . 1 1 0
- Each element is assigned a unique binary bit
1 1 1
combination, and no two elements can have
the same value; otherwise, the code A 2-bit code uses 2 bits that
assignment is ambiguous. 2
can assume up to 4 (2 ) distinct
- A set of 4 elements can be coded with a 2-bit combinations of 0’s and 1’s
binary code.
- A set of 8 elements requires a 3-bit code, and
a set of 16 elements requires a 4-bit code.
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

The BCD Code

Decimal BCD Digit Decimal BCD Digit
Symbol Symbol
0 0000 5 0101
1 0001 6 0110
2 0010 7 0111
3 0011 8 1000
4 0100 9 1001

EXAMPLE: Show the BCD representation of the decimal 396.

BCD Addition
- When the binary sum is less than 1010 (without a carry), the corresponding
BCD digit is correct. When the binary sum is greater than or equal to 1010, the
result is an invalid BCD digit.
- The addition of binary 6 (0110)2, to the sum converts it to the correct digit, and
also produces a decimal carry as required.
EXAMPLE: Perform the required BCD addition. BCD = 448 + 489
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

LESSON 4 – BOOLEAN ALGEBRA

- basic mathematics needed for the study of the logic design of digital systems
- a mathematical notation that generally specifies gate operations
- used to describe the interconnection of digital gates and to design logic
circuits through the manipulation of Boolean expressions

Binary Logic
- deals with binary variables that take on 2 discrete value and with the
operations of mathematical logic applied to these variables

Truth Table
- a table of combination of the binary variables showing the relationship
between the values that the variables take on and the values of the result of
the operation

THE 3 BASIC LOGIC OPERATIONS:

 NOT GATE
- represented by an apostrophe after a variable, or a bar over a variable
- EXAMPLE: Z = X’

X Z
0 1
1 0
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 AND GATE
- represented by a dot ( . ) or by the absence of the operator
- EXAMPLE: Z = X .Y or Z = XY

X Y Z
0 0 0
0 1 0
1 0 0
1 1 1

SWITCH REPRESENTATION OF AN AND GATE

 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

 OR GATE
- represented by a plus ( + ) symbol
- EXAMPLE: Z = X + Y

X Y Z
0 0 0
0 1 1
1 0 1
1 1 1

SWITCH REPRESENTATION OF AN AND GATE

 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

 TRUTH TABLE OF LOGIC GATES

NOT AND
GATE GATE OR GATE
X Y X Y Z X Y Z
0 1 0 0 0 0 0 0
1 0 0 1 0 0 1 1
1 0 0 1 0 1
1 1 1 1 1 1

NOR NAND GATE XOR XNOR GATE

GATE Z = (XY)’ GATE Z = (X + Y)’
Z = (X + Y)’ 𝑍 = ̅̅̅̅
𝑋𝑌 Z=X+Y 𝑍 = ̅̅̅̅̅̅̅̅
𝑋+𝑌
𝑍 = ̅̅̅̅̅̅̅̅
𝑋+𝑌
X Y Z X Y Z X Y Z X Y Z
0 0 1 0 0 1 0 0 0 0 0 1
0 1 0 0 1 1 0 1 1 0 1 0
1 0 0 1 0 1 1 0 1 1 0 0
1 1 0 1 1 0 1 1 0 1 1 1

NOR GATE XOR GATE

NAND GATE XNOR GATE

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Boolean Expressions
- A BOOLEAN ALGEBRA is an algebra dealing with binary variables (A, B, C, …)
and logic operations (AND, OR, NOT).
- A BOOLEAN FUNCTION consists of a binary variable denoting the function, an
equal sign, and an algebraic expression formed by using binary variables,
the constants 0 and 1, the logic operation symbol, and parentheses (added as
needed to specify the order in which the operations are performed).
EXAMPLE:

- A Boolean function can be transformed from an algebraic expression into a

circuit diagram composed of logic gates.
EXAMPLE: Determine the circuit diagram of F = X + Y’Z
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LAWS & THEOREMS OF BOOLEAN ALGEBRA

Operations with 0 & 1
1. X + 0 = X 1D. X · 1 = X
2. X + 1 = 1 2D. X · 0 = 0
Idempotent Law
3. X + X = X 3D. X · X = X
Involution Law
4. (X’)’ = X
Laws of Complimentary
5. X + X’ = 1 5D. X · X’ = 0
Commutative Laws
6. X+Y=Y+X 6D. X·Y=Y·X
Associative Laws
7. (X + Y) + Z = X + (Y + Z) 7D. (XY)Z = X(YZ)
Distributive Laws
8. X(Y + Z) = XY + XZ 8D. X + YZ = (X +Y) (X + Z)
Simplification Theorems
9. XY + XY’ = X 9D. (X + Y) (X + Y’) = X
10. X + XY = X 10D. X(X + Y) = X
11. (X + Y’)Y = XY 11D. XY’ + Y = X + Y
DeMorgan’s Laws
12. (X + Y + Z + …)’ = X’Y’Z’… 12D. (XYZ…)’ = X’ + Y’ + Z’ + …
Duality
13. (X + Y + Z + …)D = XYZ… 13D. (XYZ…)D = X + Y + Z + …
Theorems for Multiplying Out & Factoring
14. (X + Y) (X’ + Z) = XZ + X’Y 14D. XY + X’Z = (X + Z) (X’ + Y)
Consensus Theorem
15. XY + YZ + X’Z = XY + X’Z 15D. (X + Y) (Y + Z) (X’ + Z) = (X + Y) (X’ + Z)
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

Proof of Identity 8D:

X + YZ = (X + Y) (X + Z)
X + YZ = XX +XZ + YX + YZ but XX = X
X + YZ = X + XZ + XY + YZ since X = X · 1
X + YZ = X · 1 + XZ + XY + YZ but X · 1 + XZ + XY = X(1 + Z + Y)
X + YZ = X (1 + Z + Y) + YZ but 1 + Z = 1 and 1 + Y = 1
X + YZ = X · 1 + YZ since X · 1 = X
X + YZ = X + YZ

Proof of De Morgan’s Law:

Boolean algebra is a useful tool for simplifying digital circuits.

IN ALGEBRA, Y = ABC + ABD + ABE + ABF
Y = AB (C + D + E + F)

Algebraic Manipulation
EXAMPLE: Derive circuit diagram of the Boolean expression F = X’YZ + X’YZ’ + XZ
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

LESSON 5 – APPLICATIONS OF BOOLEAN ALGEBRA

CONVERSION OF ENGLISH SENTENCES TO BOOLEAN EQUATIONS
3 MAIN STEPS IN DESIGNING SINGLE-OUTPUT COMBINATIONAL SWITCHING CIRCUIT
1. Find a switching function which specifies the desired behavior of the circuit
2. Find a simplified algebraic expression for the function
3. Realize the simplified function using available logic elements

- Logic design problems are often stated in terms of one or more English
sentences.
- The first step in designing a logic circuit is to translate these sentences into
Boolean equations by breaking down each sentence into phrases and associate
a Boolean variable with each phrase.
Example:
MARY watches TV if it is Monday night and she has finished her homework.
F X Y

A B C f
0 0 0 0
0 0 1 0
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F = 1 if “Mary watches TV” is true; otherwise, F = 0 0 1 0 0

X = 1 if “it is Monday night” is true; otherwise, X = 0 0 1 1 1
Y = 1 if “she has finished her homework” is true; else, Y = 0
1 0 0 1
EXAMPLE: A switching circuit has three inputs and one output as 1 0 1 1
shown. The input signals A, B, and C represent the first, second, and 1 1 0 1
third bits respectively of a binary number N and f represents the
output signal of the circuit. The output f = 1 if N is equal to or greater 1 1 1 1
than 011(3) and f = 0 if N is less than 011(3).

LOGIC DESIGN USING A TRUTH TABLE

f = A’BC + AB’C’ + AB’C + ABC’ + ABC
f = A’BC + AB’ + AB = A’BC + A = A + BC via Theorem 11D
f = A + BC

MINTERM AND MAXTERM EXPANSION

- A LITERAL is a variable or its complement.
- EXAMPLE: W, X, Y, Z, W’, X’, Y’, Z’, etc…
MINTERM EXPANSION
- In general, a MINTERM of n variables is
a product of n literals in which each
variable appears exactly once in either true
form or complemented form.
When a function f is written as a sum of
minterms, this is referred to as a minterm
expansion or a standard sum of products.
- If f = 1 for row i of the truth table, then mi must
be present in the expansion because mi = 1 only
for the combination of values of the variables
corresponding to row i of the table.
f = A’BC + AB’C’ + AB’C + ABC’ + ABC
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

f (A, B, C) = m3 + m4 + m5 + m6 + m7
f (A, B, C) = ∑ m(3, 4, 5, 6, 7)
MAXTERM EXPANSION
- A MAXTERM of n variables is the
sum of n literals in which each
variable appears exactly once in either
true or complemented form.
Each maxterm has a value of 0 for exactly one
combination of values for A, B, and C
- When a function f is written as a product of
maxterms, this is referred to as a maxterm
expansion or standard product of sums.
- If f = 0 for row i of the truth table, then Mi
must be present in the maxterm expansion
because Mi = 0 only for the combination of
values of the variables corresponding to row
i of the table.
f = (A + B + C)(A + B + C’)(A + B’ + C) = M0M1M2
f (A, B, C) = ∏ M(0, 1, 2)
Each maxterm is the complement of the corresponding minterm, that is, Mi = m’i.
Given the minterm or maxterm expansions for f, the minterm or maxterm
expansions for the complement of f are easy to obtain. Because f’ = 1 when f = 0,
the minterm expansion for f’ contains the minterms not present in f.
EXAMPLES:
f (A, B, C) = m3 + m4 + m5 + m6 + m7
f’ = (m3 + m4 + m5 + m6 + m7)’ = m’3 m’4 m’5 m’6 m’7 = M3M4M5M6M7
f (A, B, C) = ∏ M(0, 1, 2) = M0M1M2
f’ = (M0M1M2)’ = M’0 + M’1 + M’2 = m0 + m1 + m2
Find the minterm expansion of the function f(X, Y, Z) based on the given truth table
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

f(X, Y, Z) = X’ Y’ Z’ + X’ Y Z’ + X Y’ Z + X Y Z
f(X, Y, Z) = m0 + m2 + m5 + m7
f(X, Y, Z) = ∑ m(0, 2, 5, 7)

Find the minterm expansion of f’ on the given truth table of the function f(X, Y, Z)

f’(X, Y, Z) = X’ Y’ Z + X’ Y Z + X Y’ Z’ + X Y Z’
f’(X, Y, Z) = m1 + m3 + m4 + m6
f’(X, Y, Z) = ∑ m(1, 3, 4, 6)
Taking the complement of f’:
f(X, Y, Z) = (m1 + m3 + m4 + m6)’ = m’1 m’3 m’4 m’6 but m’i = Mi
f(X, Y, Z) = M1 M3 M4 M6
f(X, Y, Z) = (X + Y + Z’)(X + Y’ + Z’)(X’ + Y + Z)(X’ + Y’ +Z)
f(X, Y, Z) = ∏ M(1, 3, 4, 6)

EXAMPLE: Find the minterm expansion of f(a,b,c,d) = a’(b’ + d) + acd’

f = a’(b’ + d) + acd’ = a’b’ + a’d + acd’
f = a’b’(c + c’)(d + d’) + a’d(b + b’)(c + c’) + acd’(b + b’)
f = a’b’(cd + cd’ + c’d + c’d’) + a’d(bc + bc’ + b’c + b’c’) + abcd’ + ab’cd’
f = a’b’cd + a’b’cd’ + a’b’c’d + a’b’c’d’ + a’bcd + a’bc’d + a’b’cd + a’b’c’d + abcd’ + ab’cd’

0011 0010 0001 0000 0111 0101 1110 1010

3 2 1 0 7 5 14 10
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

f(a,b,c,d) = ∑ m(0,1,2,3,5,7,10,14)

EXAMPLE: Design an adder which adds two 2-bit binary numbers to give a 3-bit
binary sum. Find the truth table for the circuit. The circuit has four inputs and three
outputs as shown. Express the output signals as minterm expansions.

INCOMPLETELY SPECIFIED FUNCTION

- A large digital system is usually divided into many sub circuits
- If it is assumed that there are no values for w,
x, y, and z which will cause A, B, and C to
assume values of 001 or 110, the function F
is then INCOMPLETELY SPECIFIED.
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

LESSON 6 – KARNAUGH MAP

KARNAUGH MAP
- The KARNAUGH MAP is a useful tool for simplifying and manipulating
switching functions of three or four variables, but it can be extended
to functions of five or more variables.
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

-
Problems in using Algebraic Procedures:
- Procedures are difficult to apply in a systematic way
- Difficult to tell when you have arrived at a minimum solution

MAP
- a diagram made up of squares, with each square representing one minterm of
the function
o A Boolean function is recognized graphically by those squares whose
minterms are included in the function.
- presents a visual diagram of all possible ways a function may be expressed in
a standard form
o By recognizing various patterns, the user can derive alternative
algebraic expressions for the same function.
NOTE: The simplified expressions produced by the map are always in the sum-
of-products or product-of-sums form.

2-VARIABLE MAP
- consists of 4 squares, one for each minterm
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

EXAMPLE: Derive the equation of the Boolean function F based on the given map.
F = m1 + m2 + m3
F = X’Y + X Y’ + X Y
F = X’Y + X Y’ + X Y = X’Y + X (Y’ + Y but (Y’ + Y) = 1
F = X’Y + X = (X + X’) (X + Y) but (X’ + X) = 1
F= X+Y

3-VARIABLE MAP
- consists of 8 squares, one for each minterm
- BASIC PROPERTIES OF ADJACENT SQUARES
Any two(2) adjacent squares placed horizontally or
vertically (but not diagonally) to form a rectangle
correspond to minterms that differ in only a single
variable.
- SIMPLIFICATION PROCESS:
One square represents a minterm of 3 literals
A rectangle of 2 squares is a product term of 2 literals
A rectangle of 4 squares represents a product term of 1 literal
A rectangle of 8 squares yields a function that is equal to 1
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

EXAMPLE:
m5 + m7 = X Y’ Z + X Y Z
m5 + m7 = X Z(Y’ + Y) but (Y’ + Y) = 1
m5 + m7 = X Z

EXAMPLE: Simplify the Boolean function F (X,Y,Z) =  m(2,3,4,5) using a map.

F = (m2 + m3) + (m4 + m5)
F = [X’YZ’ + X’YZ] + [XY’Z’ + XY’Z]
F = [X’Y(Z’ + Z)] + [XY’(Z’ + Z)]
F = X’Y + XY’

EXAMPLE: Simplify the Boolean function F (X,Y,Z) =  m(0,2,4,6) using a map.

F = (m0 + m2) + (m4 + m6)
F = [X’Y’Z’ + X’YZ’] + [XY’Z’ + XYZ’]
F = [X’Z’(Y’ + Y)] + [XZ’(Y’ + Y)]
F = X’Z’ + XZ’
F = Z’ (X’ + X)
F = Z’

OTHER WAY:
F = (m0 + m2 + m4 + m6)
F = (X’Y’Z’ + X’YZ’ + XY’Z’ + XYZ’)
F = X’Z’(Y’ + Y) + XZ’(Y’ + Y)
F = X’Z’ + XZ’
F = Z’ (X’ + X)
F = Z’

4-VARIABLE MAP
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

- consists of 16 squares, one for each minterm

- SIMPLIFICATION PROCESS IN A 4-VARIABLE MAP:
One square represents a minterm of 4 literals
A rectangle of 2 squares represents a product term of 3 literals
A rectangle of 4 squares represents a product term of 2 literals
A rectangle of 8 squares represents a product term of 1 literal
A rectangle of 16 squares yields a function that is equal to 1

EXAMPLE: Simplify the Boolean function F (W,X,Y,Z) = m

(0,1,2,4,5,6,8,9,12,13,14) using a map.

PRIME IMPLICANT
- a product term obtained by combining the maximum possible number of adjacent
squares in the map
- Four adjacent 1’s form a prime implicant if they are not within a group of 8 adjacent
squares.
NOTE: A single 1 on a map is a prime implicant if it is not adjacent to any other 1’s.
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

EXAMPLE: Simplify the Boolean function F (A,B,C,D) = ∑ m(1,3,4,5,6,7,12,14) using a map.

EXAMPLE: Simplify the Boolean function F (A,B,C,D) = ∑ m(0,5,10,11,12,13,15) using a map.

 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

PRODUCT-OF-SUM SIMPLIFICATION
- The procedure for obtaining a simplified expression from sum-of-product to
the product-of-sum form can be obtained from the basic properties of Boolean
functions.
- The 1’s placed in the squares of the map represent the minterms of the
function. The minterms not included in the function represents the
complement of the function.
- The minterms not included in the function is represented in the map by the
squares not marked by 1’s.
- The simplified expression of the function is obtained by marking the empty
squares with 0’s and combining them into valid rectangles.
- To obtain the function F as a product of sums, take the complement of F’ (by
taking the dual and complementing each literal).
EXAMPLE: Simplify the Boolean function F (W,X,Y,Z) = ∑ m(0,1,2,5,8,9,10) using a
map.
F’ = YZ + WX + XZ’
Take the dual of the OR operation
(YZ) (WX) (XZ’)
Take the dual of the logical operations
inside the parentheses
(Y+Z) (W+X) (X+Z’)
Complement each literal
F = (Y’+Z’) (W’+X’) (X’+Z)

DON’T CARE CONDITIONS

- The minterms of a Boolean function specify all combinations of variable values
for which a function is equal to 1. The function is assumed to be equal to 0 for
the rest of the minterms.
- This assumption, however, is not always valid, since there are applications n
which the function is not specified for certain variable combinations.
o CASE 1: THE INPUT COMBINATIONS NEVER OCCUR.
The 4-bit binary code for the decimal digit has six combinations
that are not used and not expected to occur.
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

o CASE 2: THE INPUT COMBINATIONS ARE EXPECTED TO OCCUR, BUT WE

DO NOT CARE WHAT THE OUTPUTS ARE IN RESPONSE TO THESE
COMBINATIONS
- Functions that have unspecified outputs for some input combinations are
called INCOMPLETELY UNSPECIFIED FUNCTIONS.
- It is customary to call the unspecified minterms of a function don’t-care
conditions.
- A don’t-care condition is represented by X.
- In choosing adjacent squares to simplify the function in the map, the don’t-
care minterms may be assumed to be either 0 or 1.

EXAMPLE: Consider the incompletely unspecified function F that has three (3) don’t-
care conditions: F(W,X,Y,Z) = ∑ m(1,3,7,11,15) d(W,X,Y,Z) = ∑ m(0,2,5)

5-VARIABLE MAP
- consists of 32 squares, one for each minterm
- consists of two(2) 4-variable maps (V,W,X,Y,Z)
- Variable V distinguishes between the two maps.
- One 4-variable map represents the 16 squares
where V = 0.
- The other 4-variable map represents the other
16 squares where V = 1.
- Minterms 0 through 15 belong with V = 0.
- Minterms 16 through 31 belong with V = 1.
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

- Each 4-variable map retains the previously

defined adjacency when taken separately.
- Each square in the V = 0 map is adjacent to
the corresponding square in the V = 1 map

EXAMPLE: Simplify Boolean function F (V,W,X,Y,Z)

= ∑ m(0,2,4,6,9,13,21,23,25,29,31) using a map.

6-VARIABLE MAP
- consists of 64 squares, one for each minterm
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

LESSON 7 – QUINE-MCCLUSKY MINIMIZATION TECHNIQUE

QUINE-MCCLUSKY MINIMIZATION TECHNIQUE
- The Quine-McClusky algorithm is useful for minimizing Boolean expressions
and therefore logic gates.
- It is easily implemented as an automated computer aided design (CAD) tool
while the Karnaugh map method is not.
PARTS OF QUINE - McCLUSKY METHOD
- Determination of prime implicants
- Selection of a set of prime implicants that covers the given function and has
the lowest cost
PROCEDURE:
1. Obtain a binary representation of each minterm that
produces a one or don't care output (binary input
patterns that produce either an output of one or an
output of don't care) then organize these binary values
into groups where the elements in each group have the
same number of one's. The groups are also ordered from
least to most one's in a group.
EXAMPLE: Determine the minimized expression of the given function.

f(A,B,C,D) = Σ m(0,2,4,5,6,9,10) + Σ d(7,11,12,13,14,15)

 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

2. Compare each term of a group with every term of the next group. If two terms
are logically adjacent combine the two terms to make a new term. The new
term has the same bit values as the original two terms except the one bit that
was different is replaced with the hyphen (-) symbol.

3. Repeat the process of combining and marking with the new combined terms
until no more combinations are
possible.
- If the resulting term cannot be
reduced further, then the term is
considered to be a prime implicant.

4. Construct a prime implicant chart

where the columns are labeled with the
minterms that produce an output of
one and the rows are labeled with the
prime implicants.
- The don't cares are not used
during this phase of the process.
Place an X in the row/column
intersection where a prime
implicant covers a minterm.
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

Find the essential prime implicants by locating

columns in the chart containing a single X. These
essential prime implicants must be included in the
final result.

6. Each time a prime implicant is selected for

inclusion in the minimum sum, the corresponding
row should be crossed out.
- The columns which correspond to all
minterms covered by the prime implicant
should also be crossed out

7. Choose a set of prime implicants that covers the minterms (columns) not
covered by the prime implicants.
 When constructing prime implicant chart, some
minterms may be covered by two or more prime
implicants.
 If the essential prime implicant do not cover all of the
minterms, then additional prime implicants are
needed.
 The non-essential implicants needed to form the
minimum solution may be selected by trial and error.
 Some functions may have two or more minimum
sum-of-products expressions, having the same number of terms and literals.

EXAMPLE: Simplify the Boolean expression for the function

f(a,b,c,d) = ∑ m(0,1,2,5,6,7,8,9,10,14).
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

Organize these binary values into groups where the elements in each group have the
same number of one's. The groups are also ordered from least to most one's in a
group.
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

Determination of Prime Implicants

Prime Implicant Chart

- minterms that produce a 1 or a don’t care output
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

LESSON 8 – COMBINATIONAL CIRCUITS

BINARY INFORMATION
1. DATA
- Information that are manipulated to perform some operation/s
- EXAMPLES:
Arithmetic (adders, counters, etc…)
Logic (decoders, etc…)
Shifting (shift register, etc…)
other similar ops (multiplexers, etc…)

2. CONTROL INFORMATION
- Provides command signals that supervise operations in the data section to
meet required data processing tasks
DIGITAL DESIGN OF LOGIC CIRCUITS
- Design of digital circuits that perform data-processing operations
- Design of control circuits that supervise the operations and their sequence
Control and Data Processor Interaction
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

COMBINATIONAL CIRCUIT
- consist of logic gates whose outputs at any given time are determined by the
combining values of the applied inputs using logic operations

SEQUENTIAL CIRCUIT
- outputs depend not only on the presently applied values of the inputs, but also
on past inputs, and the behavior of the circuit must be specified by a sequence
in time of inputs and internal stored bit values

DESIGN PROCEDURE
- The design of a combinational circuit starts from the specification of the
problem and culminates in a logic diagram or set of Boolean equations from
which the logic diagram can be obtained.
PROCEDURE:
1. From the specification of the circuit, determine the required number of inputs and
outputs, and assign a letter symbol to each.
2. Derive the truth table that defines the required relationship between inputs and
outputs.
3. Obtain the simplified Boolean functions for each output as a function of the input
variable.
4. Draw the logic diagram.
5. Verify the correctness of the design.
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

EXAMPLE: Design a combinational circuit with 3 inputs and 1

X Y Z F m
output. The output must be logic 1 when the binary value of the
inputs is less than 011(3) and logic 0 otherwise. Use NAND gates 0 0 0 1 m0
only. Assume that the complement of the signals are directly 0 0 1 1 m1
available.
For NAND Gate No. 1 0 1 0 1 m2
(X’Y’)’ = X’’ + Y’’ = X + Y 0 1 1 0 m3
For NAND Gate No. 2
(X’Z’)’ = X’’ + Z’’ = X + Z 1 0 0 0 m4
For NAND Gate No. 3 1 0 1 0 m5
[(X+Y)][X+Z)]’ = (X+Y)’ + (X+Z)’ = X’Y + X’Z’
1 1 0 0 m6
1 1 1 0 m7

CODE CONVERTER
- a circuit that translates information from one binary code to another
INPUTS
- provide the bit combination of the elements as specified by the first code
OUTPUTS
- generate the corresponding bit combination of the second code

EXAMPLE: Design a logic circuit that can convert 4-bit binary digits in BCD Code to Excess-3
Code. Decimal digits that can be represented under the BCD coding system.
COE117 - LOGIC CIRCUITS AND SWITCHING THEORY
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

LESSON 9 – BINARY ADDERS

- Arithmetic circuits are combinational circuits that performs arithmetic
operations such as addition, subtraction, multiplication, and division with
binary numbers or with decimal numbers in a binary code.
HALF ADDER
- arithmetic circuit that generates the sum of two binary digits
- input variables are the augend and addend bits to be added, and the output
variables produce the sum and carry

FULL ADDER
- forms the sum of three input bits
- third input bit, Z, represents the carry from the previous lower significant
position
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

DESIGN PROCESS
- Given a desired range of behavior and a set of available components,
determine a structure (design) formed from these components that achieves
the desired behavior with acceptable cost and performance.

- OTHER DESIGN CONSTRAINTS

High reliability
Low power consumption
Compatibility with existing system

WHY INITIAL VERSIONS OF NEW SYSTEMS FAIL IN MEETING DESIGN OBJECTIVE

- Incomplete design specifications
- Errors made by human designers
- Errors made by design tools
- Unanticipated interactions between structure, performance, and cost
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

THE INTERACTIVE PROCESS

DESIGN LEVELS OF A COMPLEX SYSTEM

 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

FULL ADDER CIRCUIT

 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

FULL ADDER CIRCUIT

 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

LESSON 10 – BINARY ADDERS INPUTS OUTPUTS

EXAMPLE: X = 1 0 1 1 X = + x3x2x1x0 = + 1 0 1 1 X Y Z S C
Y=0010 +Y = + y3y2y1y0 = + 0 0 1 0
0 0 0 0 0
SUM = + s3s2s1s0 = + 1 1 0 1
Design a binary adder circuit that can add the two 4-bit binary 0 0 1 1 0
numbers. 0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Circuit Modification 1:
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

Circuit Modification 2:
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

MULTIPLEXER
- A multiplexer is a combinational circuit that selects binary information from
one of many input lines and directs the information to a single output line.
The selection of the input line is controlled by a set of input variables.
- NOTE:
If the number of data sources is k and each I/O data line carries m bits,
the multiplexer is referred to as k-input, m-bit multiplexer.
COE117 - LOGIC CIRCUITS AND SWITCHING THEORY
COE117 - LOGIC CIRCUITS AND SWITCHING THEORY
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

NOTE #1: As long as e = 0, the circuit is disabled

NOTE #2: As long as e = 1 and S = 0, Z = A
NOTE #3: As long as e = 1 and S = 1, Z = B
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

LOGIC EQUATION FOR A 4-to-1 MUX

Z = S0’S1’X0 + S0’S1X1 + S0S1’X2 + S0S1X3
COE117 - LOGIC CIRCUITS AND SWITCHING THEORY
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

LESSON 11 – DECODERS AND ENCODERS

A COMBINATIONAL CIRCUIT WITH n INPUT LINE X AND 2n OUTPUT LINES Z
SUCH THAT EACH OF THE 2n POSSIBLE INPUT COMBINATIONS Ai APPLIED TO
X ACTIVATES OUTPUT LINES Z.

Common Applications
- Address decoding, where Ai is interpreted as an address that selects a specific
output line zi or some circuit attached to zi
- For routing data from a common source to one of several destination.

1-TO-4 DECODER CIRCUIT

 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

Basic Construction of a 1-of-4 Decoder Circuit

3-TO-8 DECODER CIRCUIT

 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

7 SEGMENT DISPLAY
COE117 - LOGIC CIRCUITS AND SWITCHING THEORY
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

ENCODERS
- An encoder is a digital function that performs the inverse operation of a
decoder. An encoder has 2n (or fewer) input lines and n output lines. The
output lines generate the binary code corresponding to the input value.
Priority Encoder
- A combinational circuit that implements a priority function.
- If two or more input signals are equal to 1 at the same time, the input having
the highest priority takes precedence.
- OUTPUT SIGNALS
a = C + A + (B + D)’
b = B + (C + D)’
c = B + C’ + D
d = A + CD’ + B’C + BC’D + B’D’
e = D’(B’ + C)
f = A + C’D’ + BC’ + BD’
g = A + CD’ + (B C)

Pushed Buttons Output Display

0 0
1 1
2 2
3 3
0, 3 3
0, 1, 3 3
0, 1, 2, 3 3
COE117 - LOGIC CIRCUITS AND SWITCHING THEORY
COE117 - LOGIC CIRCUITS AND SWITCHING THEORY
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

LESSON 12 – SEQUENTIAL CIRCUITS

SEQUENTIAL CIRCUITS
- use elements that store bit values
- the storage elements are circuits that are capable of storing binary
information, and are interconnected to form the sequential circuit
- the binary information stored in the storage elements at any given time
defines the state of the sequential circuit at that time
- the outputs of a sequential circuit depend not only from on the presently
applied values of the inputs from its environment, but also on past inputs, and
the behavior of the circuit must be specified by a sequence in time of inputs
and internal stored bit values
- determine the values used to specify the next state of the storage element

LATCHES
- A storage element can maintain a binary state indefinitely (as long as power
is delivered to the circuit), until directed by an input signal to switch states.
- The major differences among the various types of latches and flip-flops are
the number of inputs they possess and the manner in which the inputs
affect the binary state.
- The most basic storage elements are latches, from which flip-flops are
usually constructed.
- A latch is a storage element that has no clock input
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

S-R LATCHES

S-R LATCHES WITH CONTROL INPUT

D LATCHES
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

Flip-Flops
- basic circuit for storing information in a digital machine is called a FLIP-FLOP
- has 2 output signals
- state is taken to be the state of the Q output
- is given a name
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

Edge-Triggered Flip-Flops
- An edge-triggered flip-flop ignores the pulse while it is at a constant level and
triggers only during the transition of the clock signal.

The Clock
SETUP TIME (tsetup)
 The minimum time for which the input signal must be maintained at a
constant value prior to the occurrence of the clock transition.
HOLD TIME (thold)
 The minimum time for which the input signal must not change after the
application of the positive transition of the pulse.
PROPAGATION DELAY TIME (tpd)
 The delay time for the change in value of a signal to propagate from input
to output.
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

LESSON 13 – SEQUENTIAL CIRCUIT ANALYSIS

The part of the combinational circuit that generates the signals for the input
of flip-flops can be described by a set of Boolean function called flip- flop input
equation.

Logic Diagram of a Sequential Circuit

EXAMPLE: Illustrate the logic diagram of a positive edge-triggered sequential circuit
that has a single J-K flip-flop whose output lines are A and A’. The input equation for
the J-K flip-flop is given below.
JA = (XB + Y’C)
KA = (YB’ + C)

Implementing Input Equations

STATE TABLE
- The functional relationship between the inputs, outputs, and flip-flop state of
a sequential circuit can be enumerated in a state table.
- The state table usually consists of four sections, labeled present state, input,
next state, and output.
 PRESENT-STATE Section
- shows the states of flip-flops at any given time t
 INPUT Section
- gives each value of X for each possible present state
 NEXT-STATE Section
- shows the states of the flip-flops one clock period later (time t+1)
 OUTPUT Section
- gives the value of Y at time t for each combination of present-state and input
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

EXAMPLE: Show the state table of the given circuit.

DA = AX + BX
DB = A’X
Y = (A + B)X’

J K Q Operation
(t+1)
0 0 Q(t) No charge
0 1 0 Reset
1 0 1 Set
1 1 Q’(t) Toggle

Obtaining Next-State Values for J-K Flip-flops

1. Obtain the binary values of each flip-flop input equation in terms of the
present-state and input variables.
2. Use the corresponding flip-flop characteristic from the appropriate table to
determine the next state.

EXAMPLE: Show the state table of a sequential circuit with two J-K flip-flops A and
B and one input X specified by the following input equations:
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

STATE DIAGRAM
- The information available in the state table may be represented graphically in
the form of a state diagram.
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STATE DIAGRAM MODELS

MEALY MODEL MORE MODEL

EXAMPLE: Using the Mealy Model, derive the state diagram of a sequential circuit
whose behavior is characterized by the given state table.

Present State = 2 bits

No. of Flip-flops = 2
No. of States = 22 = 4 states
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LESSON 14 – SEQUENTIAL CIRCUIT DESIGN

- The design of clocked sequential circuits starts from a set of specifications
and culminates in a logic diagram or a list of Boolean functions from which
the logic diagram can be obtained.
- The design of synchronous sequential circuit consists of choosing the flip-
flops and finding a combinational circuit structure which, together with
the flip-flops, produces a circuit that fulfills the stated specification.
- The combinational circuit is derived from the state table by evaluating the
flip-flop input equations and output equations .
Design Procedure
1. Obtain either the state diagram or the state table from the statement of the
problem.
2. If only the state diagram is available, obtain the state table
3. Assign binary codes to the states.
4. Derive the flip-flop input equations from the next-state entries in the
encoded state table.
5. Derive the output equations from the output entries in the state table.
6. Simplify the flip-flop input equations and output equations.
7. Draw the logic diagram with D flip-flops and combinational gates, as specified
by the flip-flop input equations and output equations.
Designing w/ D Flip-flops: Design a clocked sequential circuit that operates
according to the given state diagram and binary codes.
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LOGIC DIAGRAM FOR SEQUENTIAL CIRCUIT w/ D FLIP-FLOPS

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Designing w/ J-K Flip-flops Present Next Inputs

- The design for sequential circuits with JK flip-flops State State
is the same as that of the sequential circuits with D Q(t) Q(t+1) J K
flip-flops, except that the input equations must be 0 0 0 X
evaluated from the present-state to next-state 0 1 1 X
transition derived from the excitation table. 1 0 X 1
1 1 X 0
EXAMPLE: Design a clocked sequential circuit that
operates according to the given state
table below.
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STATE REDUCTION
- The reduction of the number of flip-flops in a sequential circuit is referred to
as the state reduction problem.
- State-reduction algorithms are concerned with procedures for reducing the
number of states in a state table.
- Since m flip-flops produce 2m states, a reduction in the number of states may
(or may not) result in a reduction in the number of flip-flops.
- An unpredictable effect in reducing the number of flip-flops is that the
equivalent circuit may require more combinational gates.
Original State Diagram
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Original State Diagram to Reduced State Diagram

Reduced State Diagram

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LESSON 15 – SEQUENTIAL CIRCUITS

Register
- An n-bit register is an ordered set of n flip-flops which is capable of
storing n bits of information (word).
- Used extensively for temporary storage (at least 32 bits) of data in
areas aside from the main memory.
- Each bit of the word is stored in a separate flip-flop, but the flip-
flops have common control lines.

Block Diagram
LOADING
- the process of transferring information into the register
Parallel Loading
- all of the bits of the register are loaded simultaneously with a common clock
pulse
Serial Loading
- transferring the content of the register one bit at a time

4-Bit Register w/ Parallel I/O

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4-Bit Register with Parallel Loading

Shift Register
- is capable of shifting its stored bits literally in one or both directions

Block Diagram
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Counters
- A register that goes through a prescribed sequence of states upon the application
of input pulses is called a counter.
- The input pulses may be clock pulses or may originate from other sources, and
they may occur at fixed intervals of time or at random intervals.
- A counter that follows the binary number sequence is called a binary counter.
- An n-bit binary counter consists of n flip-flops and can count in binary from 0 to
2n – 1.
Categories of Counters:
RIPPLE
- The flip-flop output transition serves as a source for triggering other flip-flops.
- The clock input of some or all of the flip-flops is triggered not by the common
clock pulses, but rather by the transition that occurs in other flip-flop outputs
SYNCHRONOUS
- The clock inputs of all the flip-flops receive the common clock pulses, and the
change of state is determined from the present state of the counter.

Design of Binary Counters

- The design procedure for a synchronous counter is the same as with any other
synchronous sequential circuit.
- A counter may operate without an external input, except for the clock pulses. The
output of the counter is taken from the outputs of the flip-flops without any
additional outputs from gates.
- In the absence of the inputs, the state table of a counter will consist of columns
for the present state and next state only. The outputs will be implicitly represented
by the present –state columns.
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- Binary counters are most efficiently constructed with complementing T or JK flip-

flops. They can also be designed with D flip-flops.
Synchronous Binary Counter Present Next Inputs
State State
Q(t) Q(t+1) J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
J-K Flip-flop Excitation Table
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 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

Negative Edge-Triggered Ripple Counter

Time Q2 Q1 Q0
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1

Exercise #1: A SEQUENTIAL CIRCUIT HAS 3 D FLIP-FLOPS A, B, & C AND ONE INPUT X. THE CIRCUIT IS DESCRIBED
BY THE FOLLOWING INPUT EQUATIONS:
DA = (BC’ + B’C)X + (BC + B’C’)X’ DB = A DC = B
 Draw the state diagram of the circuit (one for X = 0 and one for X = 1)
 Derive the state table for the circuit

Exercise #2: A SEQUENTIAL CIRCUIT HAS 2 J-K FLIP-FLOPS A & B, TWO INPUTS X & Y, AND ONE OUTPUT Z. THE
FLIP-FLOP INPUT EQUATIONS AND OUTPUT FUNCTION ARE:
JA = BX + B’Y’ JB = A’X
KA = B’XY’ KB = A + XY’ Z = AXY + BX’Y’
 Draw the state diagram of the circuit
 Derive the state table of the circuit
 Draw the logic diagram of the circuit
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LESSON 16 – ALGORITHM STATE MACHINES

BINARY INFORMATION
- Data
o Information that are manipulated to perform some operation/s
o EXAMPLES:
Arithmetic adders
Logic counters
Shifting decoders
Other similar ops shift registers
multiplexers

- Control Information
o Provides command signals that activate various micro-operations in the data path to
perform the specified data-processing tasks
o Determines the sequence in which various actions are performed
The Clock
- The timing of all registers in a synchronous digital system is controlled by a
master clock.
- The clock pulses are applied to all flip-flops and registers in the system,
including those in the control unit.

LEVEL CLOCKING
o the FF responds to the LEVEL (high or low) of the clock signal
- EDGE TRIGGERING
o the FF can only respond on the rising or falling edge of the clock

Block Diagram of a Register w/ LOAD Signal

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The Clock 8284 Generator

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ALGORITHM
- consists of a finite number of procedural steps that specify how to obtain a
solution to a problem
- HARDWARE ALGORITHM
- specifies the control sequence and data-processing tasks of a digital system
- a procedure for implementing the problem with a given piece of equipment

Control and Data Processor Interaction

Control Logic
- Initiates properly sequenced commands to data-processor
- Uses status conditions from data processor and some external inputs which
serve as decision variables in determining sequence of control signals
Data Processor
- Manipulates data in registers according to system requirements

The ALGORITHMIC STATE MACHINE (ASM)

STATE MACHINE
- another term for a sequential circuit

ALGORITHMIC STATE MACHINE

- a special flow chart that define digital hardware algorithm
- translates the word statement to an information diagram (enumerates
sequence of operations, conditions necessary for their execution)
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FLOWCHART
- A conventional flow chart describes the sequence of procedural steps and
decision paths for an algorithm without concern for their time relationship.
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The ASM Chart

- resembles a conventional flowchart, but is interpreted somewhat differently
- describes the sequence of events as well as the timing relationship between the
states of the sequential controller and the events that occur while going from one
state to the next
- specifies the control sequence and data-processing operations in a digital system,
taking into consideration the constraints of the digital hardware
Elements:
 State Box
- specifies a set of actions to be taken during a single clock cycle
- correspond to a node in a state diagram, or to the value stored in a state register
in a sequential circuit

 Decision Box
- describes the effect of an input signal on the control subsystem
- input condition to be tested is written inside the box
- value of the signal being tested (either 1 [true] or 0 [false]) determines which of
the decision box’s two exit paths is to be followed in the current clock cycle
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 Conditional Box
- input path to the conditional box comes from one of exit paths of a decision box
that tests some condition
- conditional operations that are contained in a conditional box are only invoked
when the path containing the conditional box is selected by the decision box

o If the ASM is in the state IDLE, R is reset for every clock pulse
o the ASM is in the state IDLE, PC is cleared to 0 as well, but
only if the variable E = 1
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The ASM Block

- a structure composed of one or more interconnected blocks
- consists of one state box and all the decision and conditional boxes connected to its path
- one entrance and any number of exit paths represented by the structure of the decision
boxes
- Each block in the ASM chart describes the state of the system during one clock-pulse
interval.
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The ASM Chart & State Diagram

- The ASM chart is similar to a state diagram.
- Each state block is equivalent to a state in a sequential circuit.
- The decision box is equivalent to the binary information written along the
directed lines that connect two states in a state diagram.
- It is sometimes convenient to convert ASM charts into state diagrams, and then
use the sequential-circuit procedures to design the control logic.

State Diagram

Equivalent ASM Chart

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Control Implementation
From the ASM chart, we may obtain:
 The Controller Logic (via State Table/Diagram)
- determined from the decision boxes and the required state transitions
 Architecture/Data Processor
- can be obtained from the operations specified with the state and conditional
boxes

Design Procedure for the Control Section

- The control section of a digital system is essentially a sequential circuit that can
be designed by considering the following steps:
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Techniques in Controller Design

Once state table is obtained, the controller can be implemented using:
1. Traditional Method: With J-K Flip-flops
- Design is done at gate level.
- Suitable for small controllers.
- Procedure:
1. Prepare state table
2. Use K-maps to obtain next-state/output functions
2. Decoder with D Flip-flops
- Suitable for moderately large controllers
- Procedure:
1. Use decoder to obtain individual states;
2. From the state table, obtain the next-state functions by inspection
3. One flip-flop per state
- Also known as One-Hot Spot Method of ASM synthesis.
Procedure:
1. Allocate one flip-flop per state;
2. From state table, determine the formula to set each flip-flop; must
ensure that controller is properly initialized.
4. Multiplexers
- More structured approach to implement controller
- Suitable for moderately large controllers
Three level structure:
1. First level consists of multiplexers that define the next state of the
register;
2. Second level is a register that holds the present state;
3. Third level has a decoder to provide separate output for each
controller state.
5. PLA/ROM
- Highly regular approach.
- ROM approach uses a very simple table lookup technique but suffers from large
number of don’t care states.
- PLA can handle don’t care states well but design method is still at gate-level.
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

CONTROLLER DESIGNUSING J-K FLIP-FLOPS

EXAMPLE: Design a digital system wherein the Datapath Unit consists of two J-K flip-
flops, E and F, and one 4-bit binary counter, A . The individual flip-flops in counter A
are denoted by A3, A2, A1, and A0, with A3 holding the most significant bit of the
count. A start signal START initiates the system operation by clearing counter A and
flip-flop F. The counter is then incremented by 1 starting from the next clock pulse
and continues to increment until operations stop.

Counter bits A2 and A3 determine the sequence of operation:

If A2 = 0, E is cleared to 0 and the count continues
If A2 = 1, E is set to 1; then if A3 = 0, the count continues,
but if A3 = 1, F is set to 1 on the next clock pulse and the system stops counting.
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

EXAMPLE: Design a digital system wherein the Datapath Unit consists of two J-K flip-
flops, E and F, and one 4-bit binary counter, A.

ASM CHART
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Sequence of Operation
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- To design the sequential circuit with D flip-flops, it is necessary to go over the

next-state column in the state table and derive all the conditions that must set
each flip-flop to 1.
- From the state table, the next-state column of G1 has a single 1 in the 5th row.
The D input of the flip-flop G1 must be equal to 1 during the present-state T1 when
both inputs A3 and A4 are equal to 1.
- The D input function  DG1 = G1’G2A3A4

- From the table, the next-state column of G2 has 1s in the 2nd, 3rd, 4th, and 5th row.
- The D input of flip-flop G2 must be equal to 1 during the present states T0 & T1
- The D input function:
DG2 = G1’G2’S + G1’G2A3’ + G1’G2A3A4’ + G1’G2A3A4
= G1’G2’S + G1’G2A3’ + G1’G2A3 (A4’ + A4)
= G1’G2’S + G1’G2A3’ + G1’G2A3
= G1’G2’S + G1’G2 (A3’ + A3)
= G1’G2’S + G1’G2
DG2 = G1’G2’S + G1’G2
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OBTAINING THE OUTPUTS

- To obtain the necessary 3 outputs, T0, T1, and T2, a decoder can be inserted at
the output of the flip-flops.
- Then, instead of using the flip-flop’s outputs as the present-state condition, the
outputs of the decoder can be used to supply this information.

The input function of the D flip-flop can be expressed as:

DG1 = G1’G2A3A4 but G1’G2 = T1
Therefore, DG1 = T1A3A4
Similarly, DG2 = G1’G2’S + G1’G2 but G1’G2’ = T0 and G1’G2 = T1
Therefore, DG2 = T0S + T1
LOGIC DIAGRAM OF CONTROL USING D FLIP-FLOP AND A DECODER
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

CONTROLLER DESIGN USING ONE FLIP-FLOP PER STATE

- Another possible method of control logic design is to use one flip-flop per State
in the sequential circuit. Only one flip-flop is set at a time; all others are cleared
to 0. The single bit is made to propagate from one flip-flop to the other under the
control of the decision logic. In such an array, each flip-flop represents a state
that is activated only when the control bit is transferred to it.
- A control organization that uses one flip-flop per state has the convenient
characteristic that the circuit can be derived directly from the state diagram
without the need of state or excitation table. Considering the state diagram of
the previous sample problem:
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

- Since the state diagram has 3 states, assign 3 flip-flops to the circuit and label
them T0, T1, and T2.
- The Boolean function for setting the flip-flop is determined from the present-
state and the input conditions along the directed lines.

EXAMPLE: Flip-flop T0 is set with the next clock pulse of present-state T2 = 1 or if

present-state T0 = 1 and S = 0. This condition is defined by the flip-flop input
function: DT0 = T2 + S’T0 where DT0 is the D input of flip-flop T0.
The conditions for setting the flip-flop to 1 is obtained directly from the state diagram from
the conditions specified in the directed line going to the corresponding flip-flop state
ANDed with the previous flip-flop state. If there is more than one directed line going into
a state, then all conditions must be ORed.

Therefore, in obtaining the input functions using the specified procedure:

DT1 = ST0 + A3’T1 + A3A4’T1
= ST0 + T1 (A3’ + A3A4’)
= ST0 + T1 (A3’ + A3) (A3’ + A4’)
= ST0 + T1 (A3’ + A4’)
= ST0 + T1 (A3A4)’
DT1 = ST0 + T1 (A3A4)’
DT2 = A3A4T1
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Logic Diagram of Control Using 0ne Flip-flop Per State

Notes:
- Initially, flip-flop T0 must be set to 1 and all other FFs cleared to 0 so that the FF
representing the initial state is equal to 1 and all other states equal to 0.
- Once started, the FF per state controller will propagate itself from state to state
in the proper manner.
- For a register with a common asynchronous clear input, all FFs including the Q
output of T0, are cleared to 0.
- Taking the output of T0 from the complement output Q’ provides the required
initial signal for T0.
 COE117 - LOGIC CIRCUITS AND SWITCHING THEORY

- In order to keep Q’ as the output of T0, it is necessary that the input function to
the D input be complemented. This is done by the extra inverter that is placed at
the D input of FF T0.

DESIGN WITH MULTIPLEXERS

- One major goal of control-logic design is the development of a circuit that
implements the desired control sequence in a logical and straightforward
manner.
- The sequence of states in the control should be clearly evident from the circuit
configuration even if this requires additional components and results in a non-
minimal circuit. The multiplexer method is such an implementation

COMPONENTS OF SAMPLE CONTROL CIRCUIT

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Example of ASM chart with 4 control inputs

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