Experiment No.: 1.

Title: Design of half adder and full adder circuit using LTSPICE software.

Abstract: Computer uses binary numbers 0 and 1.An adder circuit uses these binary numbers
and calculates the addition. A binary adder made 2 gates using Ex-OR and AND .The
summation of output provides two elements, first is Sum and second one is Carry.

Introduction: There are 2 types of circuit

1. Half Adder

2. Full Adder

Theory and Methodology:

I. Half Adder:

A half adder is a type of adder, an electronic circuit that performs the addition of numbers. The
half adder is able to add two single binary digits and provide the output plus a carry value. It has
two inputs, called A and B, and two outputs S (sum) and C (carry).

In half adder we can add 2-bit binary number but we cannot add carry bit in half adder along
with the two binary numbers.

Boolean Expression:

SUM = A⊕B;

CARRY = A*B;

Block Diagram:

Truth Table:
 A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Software: LT SPICE

LT SPICE:

First i/p Second

V initial(v) 0 0
V on(v) 5 5
T delays(s) 10m 20
T rise(s) 1n 1n
T fall 1n 1n
T on 10m 20m
Tperiod 20m 40m

Circuit Diagram:
Simulation Result:

II. Full Adder:

Full Adder is the adder which adds three inputs and produces two outputs. The first two inputs
are A and B and the third input is an input carry as C-IN. The output carry is designated as C-
OUT and the normal output is designated as S which is SUM.

In full adder circuit,we can add carry in bit along with the two binary numbers.we can also add
multiple bits binary numbers by casecading the full adder circuit.

Boolean Expression:

S=A⊕B⊕Cin
Cout=(A*B)+(Cin*(A⊕B)).

Block Diagram:

Truth Table:

A B C-in Sum C-out

First i/p Second Third

V initial(v) 0 0 0
V on(v) 5 5 5
T delays(s) 10m 20 40
T rise(s) 1n 1n 1n
T fall 1n 1n 1n
T on 10m 20m 40m
Tperiod 20m 40m 80m

Circuit Diagram:

Software: LT SPICE
Simulation Result:

Discussion and Conclusion: When I used this software I faced some problems while drawing
the schematic diagram .When I draw in Circuit diagram A or B in Simulations result I see Cin
.Sometimes it interchange the positions of value. This is what I faced. Overall it is good.
Experiment No.:1.2 .MUX-2X1 and MUX-4X1

Title: Design of MUX-2X1 and MUX-4X1 circuit using LTSPICE software.

Abstract: Computer uses binary numbers 0 and 1. A MUX is data selection/ logic circuit that
accepts several digital data inputs and select one of them at any given time to pass on the
output. In 2*1 MUX we use two AND gates, one OR gate and NOT gate. And MUX-4*1 circuit
we use four AND gates and two NOT gates and one OR gate. Introduction: The main objectives
of the experiment is to study the gate login behavior of different MUX circuits as follows: 1. MUX
2*1 circuit 2. MUX 4*1 circuit

A multiplexer also known as a data selector, is a device that selects between several analog or
digital input signals and forwards the selected input to a single output line.

Introduction:

The main objective of the experiment is to study the behavior of different MUX as follows:

1. MUX-2X1

2. MUX-4X1

Theory and Methodology:

MUX-2X1: A 2X1 multiplexer uses one control switch (S) to connect one of two input data lines
(D0 or D1) to a single output (Y). Only one of the input data lines can be aligned to the output of
the multiplexer at any given time.

Boolean Expression:
Block Diagram:

Truth Table:

S D0 D1 Y

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 0

1 1 1 1

Software: LT SPICE

LT SPICE:

First i/p Second Third

V initial(v) 0 0 0
V on(v) 5 5 5
T delays(s) 10m 20 40
T rise(s) 1n 1n 1n
T fall 1n 1n 1n
 T on 10m 20m 40m
Tperiod 20m 40m 80m

Circuit Diagram:
Simulation Result:

4X1 MUX: A 4-to-1 multiplexer consists four data input lines as D0 to D3, two select lines as S0
and S1 and a single output line Y. The select lines S1 and S2 select one of the four input lines
to connect the output line. The particular input combination on select lines selects one of input
(D0 through D3) to the output.

Boolean expression:

Y = D0S0’S1’ + D1S0’S + D2S0S1’ + D3S0S1

Block Diagram:
Truth Table:

S0 S1 Y

0 0 D0

0 1 D1

1 0 D2

1 1 D3

Software: LT SPICE

LT SPICE:

First i/p Second Third Fourth Fifth sixth

V initial(v) 0 0 0 0 0 0
V on(v) 5 5 5 5 5 5
T delays(s) 10m 20m 40m 80m 160m 320m
T rise(s) 1n 1n 1n 1n 1n 1n
T fall 1n 1n 1n 1n 1n 1n
T on 10m 20m 40m 80m 160m 320m
Tperiod 20m 40m 80m 160m 320m 640m
Circuit Diagram:

Simulation Result:

Discussion and conclusion:This program is not 100% accurate . I did it so many times . I
made wrong connection lines and also it gave me wrong output .Then I fixed it with taking 2
input values.