Serial Peripheral Interface

• What is it?

• Basic SPI

• Capabilities

Serial Peripheral Interface

• Protocol http://upload.wikimedia.org/wikipedia/commons/thumb/e/ed/
SPI_single_slave.svg/350px-SPI_single_slave.svg.png

• Pros and Cons

• Uses

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What is SPI?

• Serial bus protocol

• Fast, easy to use, and simple
• Very widely used
• Not “standardized”

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SPI Basics

• A 4-wire communications bus

• Typically communicate across short distances
• Supports
– Single master
– Multiple slaves
• Synchronized
– Communications are “clocked”

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SPI Capabilities

• Always full-duplex
– Communicates in both directions simultaneously
– Transmitted (or received) data may not be meaningful
• Multiple Mbps transmission speeds
– 0-50 MHz clock speeds not uncommon
• Transfer data in 4 to 16 bit characters
• Supports multiple slaves

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SPI bus wiring

• Bus wires
– Master-Out, Slave-In (MOSI)
– Master-In, Slave-Out (MISO)
– System Clock (SCLK)
– Slave Select/Chip Select (SS1#, …, SS#n or CS1, …, CSn)
• Master asserts slave/chip select line
• Master generates clock signal
• Shift registers shift data in and out

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SPI signal functions

• MOSI – carries data out of master to slave

• MISO – carries data out of slave to master
– Both MOSI and MISO are active during every transmission
• SS# (or CS) – unique line to select each slave chip
• SCLK – produced by master to synchronize transfers

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SPI uses a “shift register” model of communications

Master shifts out data to Slave, and shifts in data from Slave
http://upload.wikimedia.org/wikipedia/commons/thumb/b/bb/SPI_8-bit_circular_transfer.svg/400px-SPI_8-bit_circular_transfer.svg.png

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Two bus configuration models

Some wires have been renamed

Master and multiple daisy-

chained slaves
Master and multiple independent http://www.maxim-ic.com/appnotes.cfm/an_pk/3947

slaves
http://upload.wikimedia.org/wikipedia/commons/thumb/f/fc/SPI_three_sla
ves.svg/350px-SPI_three_slaves.svg.png

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SPI clocking: there is no “standard way”

• Four clocking “modes”

– Two phases
– Two polarities
• Master and selected slave must be in the same mode
• During transfers with slaves A and B, Master must
– Configure clock to Slave A’s clock mode
– Select Slave A
– Do transfer
– Deselect Slave A
– Configure clock to Slave B’s clock mode
– Select Slave B
– Do transfer
– Deselect Slave B
• Master reconfigures clock mode on-the-fly!
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SPI timing diagram

Timing Diagram – Showing Clock polarities and phases

http://www.maxim-ic.com.cn/images/appnotes/3078/3078Fig02.gif

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SPI tradeoffs: the pros and cons

• Pros
– Fast for point-to-point connections
– Easily allows streaming/constant data inflow
– No addressing in protocol, so it’s simple to implement
– Broadly supported

• Cons
– Slave select/chip select makes multiple slaves more complex
– No acknowledgement (can’t tell if clocking in garbage)
– No inherent arbitration
– No flow control (must know slave speed)

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SPI is used everywhere!

• Peripherals
– LCDs
– Sensors
– Radios
– Lots of other chips

• Microcontrollers
– Almost all MCUs have SPI masters
– Some have SPI slaves

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SPI summary

• SPI – a 4-wire serial bus (but not official “standard”)

– MOSI, MISO, SS/CS, and SCLK signals
• Full-duplex operation
• One master
• Multiple slaves
• Best for point-to-point data transfers
• Easily supported
• Broadly used

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SPI bus architecture

• Shared bus
• SCK
• MOSI
• MISO
• Chip selects

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SPI bus architecture

• Compact shared bus

• SCK
• MOSI
• MISO
• Chip selects

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I2C bus

• Inter-Integrated Circuit
• Pronounced “eye-squared-see”
• Sometimes called “eye-two-see”
• Two wire serial bus specification
• Invented by Philips in the early 1980s
• The division is now NXP
• Was a patented protocol, but patent has now expired

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I2C uses

• Originally used by Philips inside television sets

• Now a very common peripheral bus standard
• Intended for use in embedded systems
• Philips, National, Xicor, Siemens, … all use
• Also used in PCs
• RTC
• Temperature sensors
• Variant is the SMBus (system management bus)

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I2C bus architecture

• I2C
• Standardizes peripheral classes
• SCK, SDA
• Philips/NXP

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I2C details

• Two-wire serial protocol with addressing capability

• Speeds up to 3.4 Mbps

• Discussion: what limits I2C to such small speeds?
• Multi-master architecture
• Open collector bus driver
• Pull-up resistors

• Multi-master, Multi-slave
• Uses bus arbitration

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I2C wiring

• Two lines
• SDA (serial data)
• SCL (serial clock)
• Open collector design
• Simple interfacing in for multi-voltage
• Supports bus arbitration

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I2C clock

• Not a “traditional” clock

• Normally is kept “high” using a pull-up
• Pulsed by the master during data transmission
• Master could be either the transmitter or
receiver
• Slave device can hold clock low if needs more time
• Allows for flow control

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I2C transaction

• Transmitter/receiver differs from master/slave

• Master initiates transactions
• Slave responds
• Transmitter sets data on SDA line, slave acks
• For a read, slave is transmitter
• For a write, master is transmitter

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I2C start condition

• Master pulls SDA low while SCL is high

• Normal SDA changes only happen when SCL is low

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I2C address transmission

• Data is always sampled on the rising clock edge

• Address is 7 bits
• An 8-th bit indicated read or write
• High for read
• Low for write
• Addresses assigned by Philips/NXP
• For a fee
• Was covered by patent

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I2C data transmission

• Transmitted just like address (8 bits)

• For a write, master transmits, slave acknowledges
• For a read, slave transmits, master acknowledges
• Transmission continues
• Subsequent bytes sent
• Continue until master creates stop condition

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I2C stop condition

• Master pulls SDA high while SCL is high

• Also used to abort transactions

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I2C bus transactions: start and stop conditions

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I2C bus transactions: data transfer

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I2C bus transactions: data transfer

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