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EXPERIMENT 3: N-CHANNEL JFET CHARACTERISTICS

APPARATUS: JFET (BFW-11), Bread board, resistor (1KΩ, 100KΩ), connecting wires,
Ammeters (0‐10mA), DC power supply (0‐30V) and multimeter.

CIRCUIT DIAGRAM:

THEORY:

Construction & Characteristics of JFET

The basic construction of n-channel FET is as shown in figure. The major part of JEET is the
channel between embedded P types of material. The top of the n-channel is connected to an ohmic

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contact called as ‘Drain’ (D) & lower end of Channel is called as ‘Source’ (S). The two p types of
materials are connected together & to the ‘Gate’ terminal (G).

Characteristic:-

1. VGS = 0V , VDS - Some +ve Value:-

As shown in the figure the gate is directly connected to source to achieve VGS = 0V, this is
similar to no bias condition. The instant the voltage VDD (=VDS) is applied, the electrons will be
drawn to the drain terminal, causing ID & IS to flow (i.e. ID = IS). Under this condition the flow of
charge is limited solely by resistance of the n channel between drain & source. It is important to
note that the depletion region wider at the top of both p type of material. Since the upper terminal
is more R .B. than the lower terminal (source - S).

As voltage VDS is increased from 0 to few volts, the current will increase as determined by
ohm’s law. If still VDS is increased & approaches a level referred as VP, the depletion region will
widen, causing a noticeable reduction in channel width. The reduced path of conduction causes
the resistance to increase. The more the horizontal curve, the higher resistance.

If VDS is increase to a level where it appears that the two depletion region would touch each
other, the condition referred as ‘pinch–off’ will result. The level of VDS that establish this condition
is called as ‘pinch off voltage’ (VP). At VP, ID should be zero, but practically a small channel still
exists & very high density current still flows through the channel.

As VDS is increased beyond VP, the saturation current will flow through the channel (i.e IDSS).

IDSS – Drain to source current with short cut connection from source to Gate.

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2. VGS < 0V:-

As VGS will become more & more –ve biased, the depletion layer pinch off occur at the less &
less value of VDS. Eventually, when VGS = - VP, will be sufficiently –ve to establish a saturation
level, i.e. essentially 0 mA & for all practical purpose the device has been ‘turned OFF’.

The region to the right of the pinch–off locus is typically employed in linear amplifiers
(Amplifier with minimum distortion at applied signal) is commonly referred as the constant
current, saturation or linear amplification region.

Voltage controlled region:-

The region left of pinch–off locus is called as ohmic or voltage controlled region. In this region
the JEET can actually be employed as a variable register whose resistance is controlled by V GS.
As VGS becomes more & more –ve, the slope of the curve becomes more and more horizontal,
corresponding with an increasing resistance level.

ro
rd  2
 VGS 
1 - 
 VP 

where,
ro – the resistance with VGS = 0V ,
rd – the resistance at particular value of VGS.

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Transfer characteristic:-

The relation between ID & VGS, is given by Shockley’s equation.

𝑉𝐺𝑆 2
𝐼𝐷 = 𝐼𝐷𝑆𝑆 (1 − )
𝑉𝑃

The squared term of equation will result in a non–linear relationship between ID & VGS.

PROCEDURE:

OUTPUT CHARACTERISTICS:
1. Connect the circuit as per given diagram properly.
2. Keep VGS = 0V by varying VGG
3. Vary VDS in step of 1V up to 10 volts and measure the drain current ID. Tabulate all the readings.
5. Repeat the above procedure for VGS as -0.5, -1V, -1.5V, -2V, -2.5V, -3V, -3.5V etc

TRANSFER CHARACTERISTICS:
1. Connect the circuit as per given diagram properly.
2. Set the voltage VDS constant at 10 V.
3. Vary VGS by varying VGG in the step of 0.5 up to 3.5V and note down value of drain current ID.
Tabulate all the readings.
7. Plot the output characteristics VDS vs ID and transfer characteristics VGS vs ID.
8. Calculate IDSS, VP, gm , rd or ro from the graphs and verify it from the data sheet

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OBSERVATION TABLE:

OUTPUT CHARACTERISTICS
VGS = 0 V VGS = -0.5 V VGS = -1 V VGS = -1.5 V VGS = -2 V
….. upto -3.5 V
VDS (V) ID (mA) VDS (V) ID (mA) VDS (V) ID (mA) VDS (V) ID (mA) VDS (V) ID (mA)
0 0 0 0 0
1 1 1 1 1
2 2 2 2 2
. . . . .
. . . . .
. . . . .
Upto 10 Upto 10 Upto 10 Upto 10 Upto 10

TRANSFER CHARACTERISTICS
VDS = 10 V
VGS (V) ID (mA)
0
-0.5
-1
-1.5
-2
-2.5
-3
-3.5

CALCULATION:

1. Drain saturation current IDSS: Maximum current flowing through JFET when gate to
source voltage is zero.

2. Pinch-off voltage VP : Gate to source voltage at which, drain current becomes zero.

3. Transconductance gm : Ratio of small change in drain current (Δ ID) to the corresponding

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gm = Δ ID / ΔVGS at constant VDS

4. Output resistance : It is given by the relation of small change in drain to source voltage
(Δ VDS) to the corresponding change in Drain Current (Δ ID) for a constant VGS, when the
JFET is operating in pinch-off region.

rd or ro = ΔVDS / Δ ID at a constant VGS

RESULTS:
1. IDSS : ________
2. VP : ________
3. gm : ________
4. ro : ________

CONCLUSION:

POST LAB QUESTIONS:

1. What are the advantages of FET?

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