High-Speed Board Design Techniques

(Introduction to CAD)

[email protected]
March 5, 1999

1 Introduction
 Speed is one of the most important design factor

– Hundreds of MHz processors are available

 Demand for short propagation delay

– Fast edge rate is required

– Results in ringing, reflections, and crosstalk

2 What to cover
 Power distribution system

 Transmission line and associated design rules

 Crosstalk and its elimination

 Electromagnetic interference

Reference: High-Speed Board Design Techniques, Vantis, Aug., 1997.

1
Dept. of Computer Engineering, Seoul National University 2

Vcc

V+ Load

a) Ideal power source: zero line impedance

Load
V+

b) Realistic power source: non-zero line impedance

Figure 1: The power source

3 Power distribution system

 Noise-free power distribution network

 Vcc is as important as Ground

 For AC purpose, Vcc is ground

 The design goal ! Reduce the power distribution network impedances as

much as possible

3.1 Power plane versus power bus

3.2 Line noise filtering
 Power plane alone does not eliminate line noise

 Generally, 1uF to 10uF across the power input

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Power Bus Power plane

Figure 2: Power distribution system: power bus vs. power plane

a) Ideal

b) real condition

Figure 3: Capacitor: ideal and real condition

 Generally, 0.01uF to 0.1uF across every power pin of active devices

 Larger capacitors:  10F

– Filter low frequencies (60Hz) that usually are generated off the board

 Small capacitors:  0.1F

– High frequencies (100MHz and higher)

 Equivalent-series resistance (ESR) and equivalent-series inductance (ESL)

 Resonant frequency
fR = p 1
LC
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Z Z
C C

Inductive Inductive
Capacitive Capacitive

f f
R R

Figure 4: Capacitance impedance versus frequency and the effect of lowering

capacitance while using the same type of construction (constant ESL)

– fR of large capacitors ( F) is generally less than 1MHz

 ESL and ESR result from the construction of the capacitor and dielectric
material used, rather than from capacitance value

3.3 Bypass capacitor placement

 Lead extensions on non-power planes

 Internally separated power pins must be decoupled individually

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Table 1: Bypass capacitor group

Type Range of Interest Applications

Electrolytic 1 F to > 20 F Power supply connection on board
Ceramic 0.01 F to 0.1 F At the chip
C0G < 0.1 F Noise-sensitive devices

100.000

10.000

1.000
Z
C
0.100

0.010

0.001
0.1 1.0 10.0 100.0 1K MHz

f f
R R

Figure 5: Frequency response of X7R and C0G type construction

100.000

10.000

1.000

0.100

0.010

0.001
0.1 1.0 10.0 100.0 1K MHz

f f
R R

Figure 6: Frequency response of two capacitors in parallel

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Figure 7: Bypass capacitor placement

3.4 Power distribution network as a signal return path

 Natural path of the signal-return line

 Current loop inductance can be thought of as single-turn coils

 Current loop inductance increases with loop size

 Minimize loop size ! minimize problems

 The inductance of a signal line and its return line increases with the separa-
tion of the two paths. ! The path of least impedance is the path bringing
the signal-return line closest to the signal line.

 In multiple layer boards, “as close as possible” means in a ground or Vcc

plane above or below the signal trace.

 Bus vs. planes for a signal-return path

L = Kl ln d ,r r

3.5 Layout rules with power distribution consideration

 Be careful with feedthroughs or vias

 Ground cable sufficiently

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Vcc

Signal current loop

GND

Vcc

Signal current loop

GND

Signal current loop

AC
GND

Figure 8: Current loop of a signal on the board

l
r

i
d

Figure 9: Inductance caused by the signal return path

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Signal line

Out
In

Return signal plane

Figure 10: Increase loop size due to a break in the power plane

Power plane gap

Signal Noise-sensitive
lines device

Power plane

Figure 11: Isolation of a noise-sensitive device

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Signal A

Return path A
Signal B

Return path B

Common paths of signal return due to vias

Connector configurations

Figure 12: Return path examples of a backplane and a connector

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GND isolation

Digital GND plane Analog GND plane

Filter

DAC

Analog signal
Ground bridge to
complete current
loop

Figure 13: Ground isolation and a ground bridge

 Separate analog and digital power planes

 Avoid overlapping separated planes

 Isolate sensitive components

 Place power buses near signals lines

4 Signal lines as transmission lines

 Return signal’s tendency to take the path of the least impedance

 Controlled-impedance lines: constant impedance along the signal line

 Signal delay is greater than a significant portion of the transition time !

The signal line must be treated as a transmission line

 improperly terminated transmission line is subject to reflections

 Ringing
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Figure 14: Providing the optimal signal-return path with a bus-power distribution
system

Figure 15: Reflection on a signal line

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L L L L
0 0 0 0

C C C C
C 0 0 0 0
0

L L L L
0 0 0 0

Figure 16: Transmission line

 Controlled-impedance signal line

– Inductance and capacitance are evenly distributed along the length of

the line
– Z0: AC resistance, unit is

s
Z0 = CL0
0

L0 : Signal line inductance in Henrys per unit length

C0: Signal line capacitance in Farads per unit length
– tPD : propagation delay
q
tPD = L0 C0

4.1 Transmission line categories

 Stripline
Z0 = p60" ln 4h

R 0:67w(0:8 + t )
p w
tPD = 1:017 " ns=ft
C0 = 1000 tZPD pF=ft
0

L0 = Z0 C0 pH=ft
2
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t
Stripline
h

w
h t

Microstripline

Figure 17: Signal line construction on a circuit board

 Microstripline
Z0 = p" 87 ln 5:98h

R + 1:41 0:8w + t
p
tPD = 1:017 0:457"R + 0:67 ns=ft
C0 = 1000 tZPD pF=ft
0

L0 = Z0 C0 pH=ft
2

A common material is epoxy-laminated fiberglass, which has an average "R

of 5

4.2 Example
 Copper thickness  1 mil

 Track width is 8 mils (typically 8 to 15 mils)

 Layer separation is 30 mils

Z0 = p 87 5:98  0:03
= 67:05

ln 0:8  0:001 + 0:01

5 + 1:41
p
tPD = 1:017 0:457  5 + 0:67 ns=ft = 1:75 ns=ft
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Z0

ZL

CL CL CL CL

CL CL CL CL

Figure 18: A lumped load and a distributed load

1:75 pF=ft = 26:1 pF=ft

C0 = 1000 67 :05
L0 = 67:052  26:1 pF=ft = 117 pH=ft

4.3 Distributed load calculations

 Lumped load and distributed load

 New parameter CL : added capacitance in Farads per unit length

Z0 = s Z0

1 + CCL
0
s
tPD = tPD 1 + CCL ns=ft
0

 Common in memory banks

 Typical input capacitance of DRAM is 4 pF to 12 pF

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 Example: input capacitance is 5 pF, and clearance is 200 mil

CL = 5 pF = 120 pF=ft
0:5 in 121 ftin
Z0 = s 67:05 = 28:34

120 pF=ft
1 + 26:1 pF=ft
v
u
u 120 pF=ft = 4:14 ns=ft
tPD = 1:75 ns=ftt1 + 26 :1 pF=ft

4.4 Reflection
 Maximum transfer of energy requires that the load impedance is equal the
source impedance: Z0 ZL =
 The waveform at the load: sum of originally generated signal and the re-
flection from the load

 Appearance of the waveform depends on i) mismatch of the load, ii) line

impedance Z0 , and iii) the ratio of the signal-transition time, tR to the prop-
agation delay of the line,  :
tR

 The amount of overshoot usually varies proportionally with the signal-line
=
length until tR  ; the overshoot is as much as the original transition

 A signal line is considered as a transmission line when tR  4

 More conservative rule is tR  8
 tR ranges from 1(.5) ns to 5 ns
 Distributed load in the above example
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t R

Signal at Source

Signal at Load

Figure 19: Propagation delay versus transition time

Table 2: Transition time tR is four times of the propagation delay  , i.e. tR = 4

tR (ns) Line length (in)
5 8.5
4 6.9
3 5.1
2 3.4
1 1.7

Table 3: Transition time tR is four times of the propagation delay  , i.e. tR = 4

tR (ns) Line length (in)
Lumped load Distributed load
5 8.5 3.6
3 5.1 2.17
2 3.4 1.4
1 1.7 0.75
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4.5 Quantifying reflection

 Reflection coefficient: KR
ZL , Z0
KR = ZL +Z 0

 For an open load:

KR = 1 , Z0 = 1
1+Z 0


KR = 00 ,
For a short load:
Z0 = ,1
+Z 0

 Example

– Z0 ranges from 30
to 150

– Input impedances range from 10 K to 100 K

– CMOS GAL PALCE16V8 and micropipeline

 Driver’s output impedance, ZS :
0:2 V = 8:3

ZS = VI OL = 24
OL mA


Since input impedance  100K , KR at load = 1

 Since Z0 = 67
, KR at source:

KR = 88::33 , 67 = ,0:78
+ 67
 Driver generates 3.5 V ! 0.2 V

V = (0:2 VZ 0,+3:Z5 V )Z0 = ,673:3

V+8:67
3

= ,2:94 V
s
 Resultant signal, VS :

VS = 3:5 V +
V = 0:56V
 At the load, VL1 = 3:5(VL,) ,
V by the source, and VR = ,
V
by reflection (coefficient = 1). V L = VL1 + VRL = 3:5 V ,
2:94 V , 2:94 V = ,2:38 V
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VS VL
0.56 V 3.5 V
-2.94 V

-2.38 V
-2.94 V

-0.11 V
2.27 V

2.16V

Figure 20: Time representation of a reflected signal

 The reflection, VRL goes to the source with KR = ,0:78

VRS = KRVRL = 2:27 V
VS = 0:56(VS,)+VRL +VRS = 0:56 V +(,2:94 V )+2:27 V = ,0:11 V
 The reflection, VRS goes again to the load
VL = ,2:38(VL,)+VRS +VRL = ,2:38 V +2:27 V +2:27 V = 2:16 V
 It takes five complete cycles for the signal strength to drop below
the input threshold
 For tPD =3 ns, 6-inch line induces 1.5 ns delay; five cycles are
13.5 ns

4.6 Termination
 Reflections are eliminated when ZL = Z0
 How to make ZL = Z0 ?
– Reduce ZL to Z0 : eliminate the first reflection
 placing parallel register with the load
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Source voltage

0
τ 3τ 5τ 7τ 9τ 11τ
-1
time (unit delay)

Load voltage

2 Input threshold

0
τ 3τ 5τ 7τ 9τ 11τ
-1
time (unit delay)

Figure 21: Propagation delay versus transition time

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R
H

R R = Z
H L 0

R = Z R
T 0 L

R = Z
T 0
V
vias R = Z
T 0

C
T

Z + R V
S T S
R
T V
S

Z V Z
0
S 0
Z
0

Figure 22: Terminations

 current drain is high for the HIGH-output state

 terminating to Vcc helps since IOL is usually high than IOH , but
normally not enough
 Termination to a DC reference voltage: 50 register to 3 V ref-

erence ! DC voltage is AC ground but difficult to find DC refer-

ence that can switch from sinking current to sourcing current fast
enough to respond to the transition.
 RC-series termination: AC termination
– Increase ZS to ZL : placing a series register with the source: eliminate
the second reflection
 best for a lumped load
 ZS + RT = Z0
VS = ZS Z+ RT V0
0
RT = 67
, RS = 67
, 8
= 59

V = (0Z:2 V+ ,Z 3+:559V )
Z0 = 8
,3+:367V
+6759

= ,1:65 V
S 0
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VS = 3:5 V +
V = 1:85 V

V reflects from the load to the source:
Since the load is open,
VS = 1:85 V ,
V = 0:2 V
 There is no second reflection
 Risky approach for a distributed load because of the intermediate
voltage
 The device close to the driver has a valid input after a return trip
 However, it is popular for a DRAM array
 +
Choose RT such that RT ZS < Z0 ! reduce the additional delay
by making the intermediate voltage below the threshold level

VS = 3:5 V + (0Z:2 V+ , 3:3 V )Z0 = 3:5 V + ,3:3 V  67

= 1:17V
Z + 20
8
+ 67
+ 20

S 0
This is not an exact match, thus inducing ringing, but tolerable
 Generally, exact match is difficult, because HIGH-impedance and
LOW-impedance are different: for PALCE16V8, 50 and 8 ,

respectively

4.7 Layout rules for transmission lines

4.7.1 Do not make discontinuity
 Discontinuities are points where the impedance of the signal line changes
abruptly ! cause reflections
 The formula of KR is valid as well for the discontinuities
 Bend of tracks and vias
 Smoothing the bends
 Reduce excessive vias

4.7.2 Do not use stubs or Ts

 Stub or Ts can be noise sources
 Terminate individually long stubs
 Do not make stubs
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Source voltage

0
0 τ 2τ
-1
time (unit delay)

Load voltage

2 Input threshold
1

0
0 τ 2τ
-1
time (unit delay)

Figure 23: Series termination

Figure 24: Smoothing the bends

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w w

w w w
w

Figure 25: Smoothing the bends

Figure 26: Stubs off of transmission lines and correction

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Noise source

C
trace

i i
Noise receiver S L

Z ∆ = i Z ∆ = i Z Z
S V S S V L L L

Noise source
Trace Noise source
Trace

Noise receiver
Trace Noise receiver
Trace

R > 10K Ω
IN R > 10K Ω
R < 150 Ω IN
T

Figure 27: Capacitive crosstalk and solution

5 Crosstalk
5.1 Capacitive crosstalk
 Capacitive coupling induced by closely located lines

 Current injection to a transmission line

 Termination reduces the noise

 Separation helps to reduce the crosstalk

 Isolation: put a ground trace between the coupled traces

– should be a solid ground

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λ/4

Ground trace

Figure 28: Isolating traces with a ground trace

– apply a tap every a quarter of wavelength

 = velocity  period = t 1 freq

1
PD
– In digital signals, the highest significant frequency harmonic of inter-
est is usually assumed to be
1
tR
1
fMAX = 1:25 ns   = 255 MHz
– The distributed load delay in the above example is 4.14 ns/ft
1
 = 255 MHz 1 12 in = 11:4 in
4:14 ns=ft ft
=4 = 11:44 in = 2:8 in

5.2 Inductive crosstalk

 Coupling of signals between the primary and secondary coils

 Natural loops by signals and their return paths

 Artificial loops

 Amount of the coupled signal depends on the i) size of the loops and ii)
their proximity

 The size of the signal at the load, increases with the load impedance
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Z
S
Signal line

i
S
R
IN

Ground return path

Figure 29: Series inductive loop

 Solution

– Artificial loop: open it

– Natural Loop: Keeping the load impedance low
– RT is usually 30
to 150
; this reduce the voltage at least two orders
of magnitude

 Summary

– Both capacitive and inductive crosstalk increase with load impedance

! should be terminated
– Keeping the signal separated reduces capacitive coupling
– Capacitive coupling can be reduced by isolation with ground trace
– Inductive crosstalk can be reduced by minimizing loop size
– Inductive crosstalk is induced by shared common path

6 Electro-magnetic interference
 Even you board accept glitches, FCC does not

 EMI can be reduced by shielding, filtering, eliminating current loop and

reducing device speed
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Feedthrough capacitor: Inductor: Low impedance

high-impedance Large difference between line and load

PI filter: line and load impedance are high

T filter: line and load impedance are low
High level attenuation

Figure 30: Line filters

6.1 Loops
 Acts as antenna
 Use ground plane: minimize natural loops

6.2 Filtering
 Standard for power lines
 Last resort for signal lines
 EMI filters
– Suppress high frequency noise
– Capacitors: high-impedance node
– inductors: low-impedance node
– Ferrite noise suppressor
 adding inductance in series
loss (dB) = 20 log10 Zs Z+ Z+L Z+ ZF
S L
 without DC resistance
 for signal lines: i) error prone and ii) edge rate


100 at tens of MHz to hundreds of MHz

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tL

tF
tR

1 1 1

πt L πtR or πt F

Figure 31: Pulse and its frequency components

6.3 Device speed

 Frequency components: rise time (tR ), fall time (tF ) and pulse width (tL )

 Usually tF is the shortest components

 PALCE16V8: tF = 2 ns
f =   11:25 ns = 255MHz
Regardless of the clock frequency