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Assignment Coa Wase Wims2019

This document provides instructions for submitting a lab assignment involving 3 questions on WIMS and WASE. It details the requirements for submitting solutions, screenshots, and student IDs. It also provides hints for the assignment questions, which involve tasks like moving values between registers, using the hardware stack, memory addressing modes, and cache configuration. Students are asked to write assembly code, observe register and memory values, and fill out tables to analyze cache performance under different configurations.

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RAHUL KUMAR R
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
409 views8 pages

Assignment Coa Wase Wims2019

This document provides instructions for submitting a lab assignment involving 3 questions on WIMS and WASE. It details the requirements for submitting solutions, screenshots, and student IDs. It also provides hints for the assignment questions, which involve tasks like moving values between registers, using the hardware stack, memory addressing modes, and cache configuration. Students are asked to write assembly code, observe register and memory values, and fill out tables to analyze cache performance under different configurations.

Uploaded by

RAHUL KUMAR R
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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COA Lab Assignment WIMS & WASE 2019 (Oct20-April21)

Instructions for submitting the LAB assignment


1. There are total 3 lab assignment questions with sub parts. Marks distribution is shown
against the question
2. All students are to upload the solution on e-learning portal
3. Students are expected to take the snap shot of the result.
4. The students must write the BITS ID on all the snap shots.
5. Appended is the hint to assignments
Fig1
COA Lab Assignment WIMS & WASE 2019 (Oct20-April21)

Assignment1 14 X 0.25= 3.5


1. Write an instruction, which moves number 7 to register R01.
2. Execute the above instruction
3. Create an instruction, which moves number 8 to register R02.
4. Create an instruction, which adds the contents of R01 and R02.
5. Execute it and show the register that holds the result
6. Create an instruction, which pushes the above result to the top of the hardware stack, and then
execute it.
7. Create an instruction to push number ‐2 on top of the stack and execute it.
Show the value in Program Stack
8. Create an instruction to pop the value on top of the Program Stack into register R03.Execute it
and observe the value in SP register
9. Create an instruction to pop the value on top of the Program Stack into register R04.Execute it
and observe the value in SP register
COA Lab Assignment WIMS & WASE 2019 (Oct20-April21)
10. Execute the last instruction again. What happens? Explain
11. Manually insert decimal values in registers R05 and R06 and write an instruction to reflect the
status of OV/Z/N flags making N flag set. Show the status
12. Store one byte of data 65 in a memory location 20. (all numbers are in decimal) . Show the
addressing mode used here.
13. Create an instruction to move decimal number 22 to register R07 and make a note of it below.
Execute this instruction and verify the result in R07.
14. Execute an instruction to store decimal number 51 in memory location the address of which is
currently stored in register R07. Show the addressing mode used here. Show the content of Data
memory.

2. Assignment 2 [0.5+0.5 X7 + 0.5 X 5= 6.5]


Create a new program, call it CacheTest1 and enter the following code
MOV #40, R02
TRANS:
STB R02, @R02
CMP #103, R02
JEQ STOP
INC R02
JMP $TRANS
STOP:
HLT
1. Show the content of Data Memory
2. Now chose the following configuration in instruction cache and fill in the following table
Block Size = 4
Cache Type = Direct Mapped
Cache Size = 16
Write Policy = FIFO, RAM Speed: super fast

Sl Mapping Cache Block %Hit %miss Questions to be answered


no size size
1 Direct 16 4 Reason for the difference in result
2 8
3 2- 16 4 Compare between 1 and 3 and write
wayAssociative your explanation why result is same
or different?
4 8 Compare between 2 and 4 and write
your explanation why result is same
or different?
5 Fully 16 8 Compare between 4 , 2, 5 and explain
associative for the observation
COA Lab Assignment WIMS & WASE 2019 (Oct20-April21)
6 2- 32 16 Does the hit rate increase or
wayAssociative decrease ? explain the reason

Remove the LABEL and instead edit the instruction JEQ and write the destination address and
then execute the program
Configure the instruction cache as given below
Block Size = 8
Cache Type = Fully associative
Cache Size = 16
Write Policy = FIFO, RAM Speed: super fast
Mapping Cache Block %Hit %miss Questions to be answered
size size
7 Fully 16 8 Compare between 5 and explain for
associative the observation

3. Now insert the following code below the instruction JMP TRANS: in the above code:

LDB 44, R03


LDB 45, R04
LDB 46, R05
LDB 47, R06
4. Configure the Data cache with the following settings:

Block Size = 4
Cache Type = Direct Mapped
Cache Size = 16
Write Policy = Write-Back
Execute all the instructions one by one and fill in the following table

Addr Data Hits Block %Hits % Miss

5. Now the instruction below the jump instruction by following instruction and execute them
maintaining the same cache configuration
LDB 40, R03
COA Lab Assignment WIMS & WASE 2019 (Oct20-April21)
LDB 45, R04
LDB 48, R05
LDB 53, R06

Addr Data Hits Block %Hits % Miss

6. Configure the cache to the following


Block Size = 8
Cache Type = Direct Mapped
Cache Size = 16
Write Policy = Write-Back
Execute all the instructions one by one and fill in the following table
Addr Data Hits Block %Hits % Miss

7. Why there is the difference in hit rate of 5 & 6? Briefly explain your observation between them.
below.

3. Assignment [ 12 X 0.4+0.2 = 5]
1. Enter the following source code, compile it and load in simulator’s memory:}
program Ex1
for n = 1 to 20
p = p + 1
next
end
COA Lab Assignment WIMS & WASE 2019 (Oct20-April21)
2. Open the CPU pipeline window and list the names of stages here.

3. Check the box titled Stay on top and make sure No instruction pipeline check box is selected. And
run the program. Run the program and observe the pipeline. Wait for the program to complete.
Now make a note of the following values

CPI
SF
Inst counts
Clks

Verify that Instruction count= CPI X clks

4. Next, uncheck the No instruction pipeline checkbox, reset and run the above program again and
wait for it to complete.
5. Note down your observation on how the pipeline visually behaved differently

6. Now make a note of the following values

CPI
SF
COA Lab Assignment WIMS & WASE 2019 (Oct20-April21)
Inst counts
Clks

𝐶𝑃𝐼𝑢𝑛𝑝𝑖𝑝𝑒𝑙𝑖𝑛𝑒𝑑
Verify that Instruction count= CPI X clks And 𝑆𝐹 =
𝐶𝑃𝐼𝑃𝑖𝑝𝑒𝑙𝑖𝑛𝑒𝑑

7. Briefly explain why you think there is a difference in the two sets of values:

8. Enter the following program and compile it with ONLY the Enable optimizer and Remove
redundant code check boxes selected. Load the compiled program in the CPU.
program jmpprdct
i=0
for p = 1 to 40
i=i+1
if i = 10 then
i=0
r=i
end if
next
end

9. Run the program and make a note of the following pipeline stats:

CPI
SF
Inst counts
Clks
COA Lab Assignment WIMS & WASE 2019 (Oct20-April21)

10. Now, in the pipeline window select the Enable jump prediction check box. Reset the program and
run it again. Make a note of the following pipeline stats:

CPI
SF
Inst counts
Clks

11. Explain the difference


[Grab your reader’s attention with a great quote from the document or use this space to
emphasize a key point. To place this text box anywhere on the page, just drag it.]

12. Show the jump table and explain the terms

V
JInstAddr

JTarget

PStat

Count

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