Scribd
Upload
41 views1 page

Machine Model CSVGN6

This document provides information about Machine Model CSVGN6, which is a static var compensator model. It includes: 1) Key signals and parameters for the static var compensator model including voltage, maximum and minimum limits, and time constants. 2) Details on the regulator states and equations for calculating the thyristor firing angle based on the voltage error. 3) Override and delay logic that describes how the thyristor switch will operate based on the voltage error exceeding thresholds.

Uploaded by

Manuel
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
41 views1 page

Machine Model CSVGN6

This document provides information about Machine Model CSVGN6, which is a static var compensator model. It includes: 1) Key signals and parameters for the static var compensator model including voltage, maximum and minimum limits, and time constants. 2) Details on the regulator states and equations for calculating the thyristor firing angle based on the voltage error. 3) Override and delay logic that describes how the thyristor switch will operate based on the voltage error exceeding thresholds.

Uploaded by

Manuel
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 1

Machine Model CSVGN6

Machine Model CSVGN6


Static Var Compensator CSVGN6
Other
Signals
VOTHSG ( I ) VMAX VEMAX
VOLT(IBUS)
Filter
or +
VOLT(ICON(M)) 1 − + 1 + sTS 2 1 + sTS 4 BR
1 + sTs1 Σ Σ 1 + sTS 3 1 + sTS 5
K SVS
1 + 2 3
VREF VMIN VEMIN

BIAS
VERR BR BMAX

If VERR > DVLO : BR' = '


BMAX + K SD (VERR − DV ) 1 4
+
+
States:
1 – Filter
If DVHI < VERR < DVLO : BR' = BR
BR' 1 + 𝑠𝑇𝑆6 BSVS
Σ
2 – Regulator1 If VERR < DVHI : BR =
' '
BMIN + Y
3 – Regulator2
4 – Thyristor Fast Override BMIN
1 2 BSHUNT
Thyristor Delay
Position 1 is normal (open)
If DV = 0, If DV > 0, If VERR > DV 2, switch will
DVLO = BMAX
'
/ K SVS DVLO = DV close after TDELAY cycles.

DVHI = BMIN
'
/ K SVS DVHI = − DV

Model supported by PSSE

You might also like