Teaching Computer Organization/Architecture With Limited

Resources Using Simulators*

Gregory S. Wolffe William Yurcik Hugh Osborne Mark A. Holliday

Comp. Sci & Info. Sys. Applied C. Sci. Sch. Of C. & Math. Math. & Comp. Sci.
Grand Valley St. Univ. Illinois St. Univ. U. of Huddersfield W. Carolina Univ.
Allendale, MI USA Normal, IL USA W. Yorkshire U.K. CuIIowhee, NC USA
[email protected] [email protected] [email protected] [email protected]

Abstract
A s the c o m p l e x i t y and v a r i e t y o f c o m p u t e r s y s t e m W h i l e the p r o c e s s o f a b s t r a c t i o n is a natural p r o g r e s s i o n ,
h a r d w a r e increases, its s u i t a b i l i t y as a p e d a g o g i c a l tool in students m u s t still b e e x p o s e d to a certain l e v e l o f detail.
c o m p u t e r o r g a n i z a t i o n / a r c h i t e c t u r e courses d i m i n i s h e s . A s C o i n c i d e n t w i t h this g r o w t h o f k n o w l e d g e in the field is the
a c o n s e q u e n c e , m a n y instructors are t u r n i n g to s i m u l a t o r s i n c r e a s i n g c o n t e n t i o n for l i m i t e d t e a c h i n g r e s o u r c e s . This
as t e a c h i n g aids, often u s i n g v a l u a b l e t e a c h i n g / r e s e a r c h applies n o t o n l y to l a b o r a t o r y facilities b u t also to factors
t i m e to c o n s t r u c t them. M a n y o f these s i m u l a t o r s h a v e such as expertise, p r e p a r a t i o n t i m e , a n d the n e e d to p r o v i d e
b e e n m a d e f r e e l y a v a i l a b l e o n the Interact, p r o v i d i n g a resource availability to non-traditional students.
useful a n d t i m e - s a v i n g r e s o u r c e for o t h e r instructors. M a i n t a i n i n g a n u p - t o - d a t e l a b o r a t o r y infrastructure is an
H o w e v e r , f i n d i n g the fight s i m u l a t o r for a p a r t i c u l a r c o u r s e o n g o i n g and e x p e n s i v e p r o c e s s ; m a k i n g it a c c e s s i b l e to
o r t o p i c c a n i t s e l f h e a t i m e - c o n s u m i n g p r o c e s s . T h e goal g e o g r a p h i c a l l y d i s p e r s e d a n d e m p l o y e d students is a n o t h e r
o f this p a p e r is to p r o v i d e an e a s y - t o - u s e s u r v e y o f free and p r o b l e m altogether. L i k e w i s e , instructors m a y h a v e a w i d e
I n t e r n e t - a c c e s s i b l e c o m p u t e r s y s t e m s i m u l a t o r s as a r a n g e o f b a c k g r o u n d s f r o m n o v i c e to e x p e r t d e p e n d i n g o n
r e s o u r c e for all instructors o f c o m p u t e r o r g a n i z a t i o n a n d the topic, b u t it is a c o m m o n c h a l l e n g e to r e m a i n current.
c o m p u t e r architecture courses.
T h e m o s t i m p o r t a n t d e v e l o p m e n t a d d r e s s i n g b o t h o f these
trends ( e v e r - e x p a n d i n g material, l i m i t e d r e s o u r c e s ) is the
1 Introduction a d v e n t o f the C P U s i m u l a t o r [4]. A s students in the
1970s/g0s u s e d p a p e r a n d p e n c i l to d e s i g n C P U
T h e a m o u n t o f m a t e r i a l c o m p r i s i n g the f i e l d o f c o m p u t e r
components using Boolean algebra and Karnaugh maps,
architecture is c o n t i n u o u s l y e x p a n d i n g ; hence, the m a t e r i a l
students t o d a y c a n u s e a C P U s i m u l a t o r to s t u d y c o m p u t e r
can o n l y b e p a r t i a l l y c o v e r e d in a t y p i c a l u n i v e r s i t y course.
o p e r a t i o n b y v i s u a l i z i n g the interrelated, s i m u l t a n e o u s
A c o m m o n r e s p o n s e to this p r o b l e m is an a n a l o g o f
events that o c c u r d u r i n g p r o g r a m e x e c u t i o n . Interactive
M o o r e ' s L a w for e d u c a t o r s : instructors h a v e p r o g r e s s i v e l y
C P U s i m u l a t o r s e n a b l e active l e a r n i n g b y a l l o w i n g students
r e v i s e d their c o u r s e s to use i n c r e a s i n g l y h i g h e r levels o f
to d e s i g n t h e i r o w n h y p o t h e t i c a l m a c h i n e s , to p r o g r a m ,
a b s t r a c t i o n [4]. F o r ( g e n e r a l i z e d ) e x a m p l e , students
e x e c u t e and d e b u g s y s t e m software, a n d to u s e s i m u l a t i o n
learning how computers operated:
to u n d e r s t a n d the o p e r a t i o n o f real m a c h i n e s .
• in the 1950s studied the physics of vacuum tubes
Two common problems were identified during a recent
• in the 1960s studied transistor circuits
s u r v e y [3] o f instructors o f c o m p u t e r o r g a n i z a t i o n and
• in the 1970s studied digital logic gates architecture courses: (1) instructors are n o t a w a r e that
• in t h e 1 9 8 0 s studied integrnted circuits c a p a b l e C P U s i m u l a t o r s e x i s t a n d (2) i f a w a r e o f C P U
• in the 1990s studied networked computer systems. s i m u l a t o r s in general, instructors are n o t a w a r e o f p a r t i c u l a r
s i m u l a t o r s that m e e t t h e i r p e d a g o g i c a l needs. T h e g o a l o f
this p a p e r is to p r o v i d e an e a s y - t o - u s e s u r v e y of free a n d
*Some of the work presented here was supported by the National Internet-accessible c o m p u t e r s y s t e m s i m u l a t o r s as a
Science Foundation under grant DUE-9850534. r e s o u r c e for all instructors o f c o m p u t e r o r g a n i z a t i o n a n d
c o m p u t e r architecture courses. W e are a w a r e o f o n l y t w o
Permission to make digital or hard copies of all or part of this work for l i m i t e d p r i o r attempts to p r o v i d e such a s e r v i c e [15,17]. T o
personal or classroom use is granted without fee provided that copies are our knowledge, this work represents the most
n o t made or distributed for profit or commercial advantage and that
copies bear this notice and the frith citation on the first page. To copy c o m p r e h e n s i v e effort to d o c u m e n t C P U s i m u l a t o r s across
otherwise, or republish, to post on screw's or to rcdisstdbu~ to lists, the w i d e r a n g e s o f t o p i c areas and i n t e n d e d a u d i e n c e s .
requires prior specific permission and/or a fee.
SIGCSE"02, February 27- March 3, 2002, Covington, Kentucky, USA.
Copyright 2002 ACM 1-58113-473-8/02/0002...$5.00.

176
The remainder o f this paper is organized as follows: The historical machine simulators and digital logic
Section 2 provides a context by briefly describing the simulators fill distinct educational voids and automate
benefits o f CPU simulation. In Section 3 we present the concepts once explored exclusively by hand on paper. The
rationale used for grouping the CPU simulators. Sections 4 simple / intermediate / advanced categories generally match
through 9 describe different categories o f CPU simulators. the introductory, computer organization, and computer
To round out the presentation we include in Section 10 architecture courses found in many CS curricula. Multi-
examples o f simulators that have been developed for processor simulators extend the advanced microarchitecture
memory subsystem visualization and analysis. We close category by focusing on parallel architectures with multiple
with a summary and ideas for future work in Section 11. CPUs. The memory subsystem category includes
simulators that focus on interactions between the CPU and
cache memory.
2 Educational Benefits of Simulation
Recent papers [1,9] have documented the value o f using 4 Historical Machine Simulators
simulation as a tool for teaching computer architecture. As
The study of computer operation can often be enhanced by
a support tool, simulators are attractive in the following
using examples o f machines that either no longer
ways: (1) students learn the underlying details o f computer
physically exist (other than in a museum), or if they do
operation at multiple levels o f abstraction; (2) students exist, are too expensive to justify solely for educational
have pervasive access to content when and where they want purposes [15]. The use o f simulation allows an educator to
it, significantly increasing availability to non-traditional
teach concepts on any machine for which a simulator has
students utilizing asynchronous learning; (3) state-of-the-
been constructed. Ot~entimes a machine o f historical
art content is available for many, if not all, topics; (4) many
interest is the best example o f an architectural concept, or it
simulators are closely linked with textbooks; and (5) little may have the best available tutorials and documentation.
or no infrastructure cost is incurred.
Using simulation renders obsolescence less o f a factor
Many CS programs with limited resources are unable to
since machines can be virtually recreated and indefinitely
provide dedicated laboratories with examples o f computer
maintained. However, in some cases the substitution o f a
architecture; the simulators documented here are free and
simulator for a real machine may require careful analysis
available for a variety o f platforms. Internet-accessible
and simulation modeling expertise. For example, it has
simulators allow student experiments ranging from
been found that non-validated simulators o f real machines
programming historical machines to creating their own new
axe likely to underestimate performance [6].
architectures. The interplay o f performance tradeoffs and
design constraints becomes real when students attempt to TABLE l : HISTORICALMACHINE SIMULATORS
simulate a novel computer system. Lastly, creating a Analytical Engine Babbage's machine.
computer system simulation in software is a cathartic www.fourmilab.ch]babbage/applet.html Web-based Java applet
educational experience similar to building a real computer Apple lie Classic 65C02.
in hardware - but less expensive, more flexible in allowing
quark.netfront.neI:6502/ Unix w/X Windows
students to make mistakes and recover, and more extensible
in building additional functionality upon a core design [16]. Atafi ST MC68000 and chipsets_
www.complang.tuwien.ac.at/nino/stonx.html Unix/X, MSDOS, Win 95
Commodore Amiga MC680x0 and chipsets.
3 Categorization of Simulation Tools
www.fTeiburg.linux.de/-uae/ Unix, DOS, Win32, Mac
The focus o f this paper is exclusively on free and Interact- Commodore 64 (www.uni- Popular game system.
accessible computer system simulators that can be easily mainz.de/-bauec002/FRM ain.html) Multiple platforms
integrated into computer organization/architecture courses.
Early simulators were all text-based. Current computer DEC PDP-8 First retail computer.
system simulators have graphical interfaces that make it www.cs.uiowa.edu/-jones/pdp8/ Unix w/X Windows
possible to provide visual metaphors representing the DEC PDP-11 Influential CPU family.
internal operation o f a computer. flp://flp.upd ate_uu.se/pub/ibmpc/emulators/ DOS

EDSAC 1~tstored-program service

We divide these free and Internet-accessible computer
http://www.dcs.warwick.ac.uk/~edsac/ Win32, Mac
system simulators into seven different categories
summarized in the accompanying tables. Unless otherwise Enigma ( www.ugrad.cs.jhu.edu/ Nazi encryption machine.
noted all listed URLs are websites (http://). For each -russell/classes/enigma/) Web-based Java applet
specific type o f system we give only one representative Sinclair QL (www.geocities.cnm/ 1984 MC68008 machine.
simulator. Some systems have multiple simulators; the SiliconValley/Heights/1296/q-emulator.html Windows NT/95, MacOS
complete list can be found on the maintained webpage Turing Machine (www.cs.brandeis.edu/ Finite state machine.
whose URL is given at the end o f this paper.
--'paulq[Turing/TuringAppletMae.html) Web-based Java applet

177
5 Digital Logic Simulators intricacies o f data representation; the set o f essential
Modem computers consist of an extremely large number of instructions; the process o f instruction translation; the
very simple structures. Whether an instructor chooses to fetch-execute cycle; and the use of registers. In short,
begin with MOS transistors, boolean logic gates or hypothetical simulators allow educators to selectively focus
combinational logic circuits, the goal is the same: a bottom- attention on important concepts without getting lost in
up learning foundation. complex machine-dependent details.

The digital logic simulators in this category depict the Because o f the simplicity o f the machines they simulate,
operation o f the following hardware features: basic logic the tools in this category are particularly well-suited for
elements with switching theory; circuit analysis adaptation to the Web. An example is that most enduring
(implementation, minimization); timing systems simple hypothetical machine: the Little Man Computer
(propagation delays, hazards); flip-flops/latches/registers; (LMC) that dates back to M I T in the 1960s. A recent paper
logic structures (multiplexers, decoders, comparators, [16] describes the evolution o f five different L M C
adders); and storage elements (ROM, PROM, RAM). simulators from their text-based origins to the current
graphical and Web-based versions.
TABLE 2: DIGITAL LOGIC SIMULATORS
TAB LE 3: S[MPLE HYPOTHETICAL MACHINE S[MULATORS
6.111 Digital Simulator Set o f macros and C libraries that
can be used to create a program CASLE H T M L forms tool. Experiments
(www.mit.edu/people/ that simulates a circuit. shay.ecn.putdue.¢duI-casle/ with registers, instruction
eichin/thesis/usrdoc.html) latencies and optimization.
Digital Logic Simulator Web-based point-click-drag logic CPU Sire Emulator for building at the
(www.cs.gordon.cdu/courses/ gate simulator illustrating the www.cs.colby.eduJ-djskrien/ register-transfer level. MacOS
module7/Iogic-simlexamplel.html) operationof simple circuits.
Digital Workshop Displays execution of pre-built EasyCPU (www.cteh.ac.il/ Animated basic and advanced
and customizablelogic circuits. departments/education/cpu,htm) Intel 80x86 operation.
(www.cise.ufl.edu/-fishwick/
dig/DigSim.html) Web-basedJava applet. Little Man Computer Visualization of LMC paradigm
described in [7].
esim Simulator Advanced tool to build www.acs.ilstu.eduffaculty/javila/Imc/
Web-based Java applet
(www.cse.ucsc.edu/-elm/Software/ arbitrarilycomplex digital logic
Esim/index.htrnl) designs using hierarchical design PIPPIN Binary and symbolic mode CPU
techniques. Unix with Tcl/Tk (www.cs.gordon.edu/courses/cs I l I/ simulatorhighlighting data paths.
module6/cpu-sim/cpusim.html) • Web-basedapplet
Interactive Full-Adder Interactive and intuitive
(www.acs.ilstu.edu/faculty/javila/ demonstrationof the oisc & urisc (www.pdc.kth.se/-jas ExtremeRISC - a computer with
acs254/fullAdder/FullAdder.html) implementationof full adder with /retro/retromuseum.html) a single instruction.
logic gates. Web-based. Simple Computer Emulator I Machine emulator with memory
Iowa Logic Simulator Simulator based on specification Beachstudios.com/sc/ cells and I/O cards. Javascdpt
www.cs.uiowa.edu/-jones//Iogicsim/ languagefor digital systems from
TTL/gates to large CPUs. Pascal
MIT Digital Logic Simulator Point-and-click simulator with 7 Intermediate Instruction Set Simulators
web.mit.edu/ara/www/ds.html gates, flip-flops, & logic analyzer.
Win NT/95/3.1 The machine simulators described above are designed to
Multimedia Logic Kits Visual design system for design use only simple addressing, a limited instruction set, and a
and testing of simple circuits. very simple m e m o r y model. Intermediate simulators, in
www.sottronix.com/Iogic.html Win32
contrast, tend to include a more realistic set o f addressing
Simcir- the circuit simulator Intuitive point-and-clickdigital modes, a more complete instruction set, a more realistic
www.tt.rim.or.jp/-kazz/simcir/ logic gate simulator, Web-based m e m o r y hierarchy, and sometimes an interrupt mechanism.
Java applet or executable. As a result o f this attention to completeness, m u c h more
realistic programming application is possible.
6 Simple Hypothetical Machine Simulators A secondary benefit o f using a simulator with a fairly
The authors agree with critics' claims that learning via a complete instruction set is the opportunity it provides to
explore computer science concepts that are important
simulator is not the same as experience with a real machine
- simulators can be even better! As real machines b e c o m e throughout the broader curriculum [5]. Many students
understand high-level concepts better after studying the
more complex, they become less suitable for teaching the
low-level mechanisms upon which they are based. For
concepts typically found in introductory computer
example, understanding register transfer language indirect
organization courses. Simple hypothetical machine
addressing clarifies the concept o f using pointers in C,
simulators can serve an important role by giving students
studying the cache protocols used to hide m e m o r y transfer
access to the intemal operation o f a system (which is not
latencies helps explain the operation o f web/browser cache
possible with real CPUs). When properly designed,
management protocols, and examining CPU architectural
hypothetical machine simulators excel at illustrating core
support for high-level languages reinforces language and
concepts such as: the yon Neumann architecture; the stored
program concept; the pnneiple o f sequential execution; the compiler concepts.

178
 TABLE 4: INTERMEDIATE INSTRUCTION SET SIMULATORS 9 Multi-Processor Simulators
LC2 Described in [I 1]. Simulators o f multiprocessors are significantly different
www.mhhe.com/patrt/ Unix & Windows from uniprocessor simulators. One difference is that
Relatively Simple Computer Describedin [2], dual-mode control multiprocessor simulation requires the emulation o f
System Simulator unit. Web-based or downloadable. features that do not exist in uniprocessors (e.g. shared
www.awl.com/carpinelli interconnection networks and shared memory). Another
SIMHCI2 (www.aracnet.com/ Simulatorfor the MC68HC812A4 difference is the result o f simultaneous execution; a correct
-tomalmy/6ghc 12.html) microcontroller.Java simulation must reflect the fact that instructions on
AMD SimNow! Intel x86 simulator. different processors are occurring at the same time. A third
difference is in the amount o f time required to complete a
www.x86-64.org/dawnloads GNU/Linux
simulation - this is technically challenging since simulation
SPIM (www.cs.wisc.edu/ Used with [12], MIPS simulator with time tends to grow at least proportionally to the number o f
-larus/spim.html) visual GUI. Unix/Linux/DOS/Win
processors being simulated.
SPIMSAL (www_cs.wisc.edu/ Describedin [8l; uses SAL - extended Consequently, developing accurate multiprocessor
-larus/spim.html) instruction set. Win3.1 & MacOS simulators with good performance is a research area unto
itself. The multiprocessor simulators that are useful
instructional aids are also ones that are actively used in
8 Advanced Microarchitecture Simulators
computer architecture research. Using these simulators can
The microarchitecturc simulators are designed to allow the be more complex than using the uniprocessor simulators in
observation o f machine language execution at the the other categories, so they are most appropriate for
microcode level (e.g. data paths, control units). Advanced advanced computer architecture courses. Note that the last
simulators can be used to investigate the advantages and link listed for this category is actually a link to a web page
disadvantages (e.g. efficiency, complexity) o f performance- listing many o f the multiprocessor simulators currently
enhancing techniques such as pipelining, branch prediction used in research.
and instruction-level parallelism. Some o f these simulators
TABLE 6: MULTI-PROCESSORSIMULATORS
are microprogrammable, allowing students to experiment
with the design o f instruction sets. ABSS (arithmetic.Stanford.edu/ SPARC-basedmultiprocessors
-lemon/abss.html)
Most o f the simulators included in this category are MINT MIPS-based shared-memory
associated with a textbook and would be appropriate for an www.cs.rochester/u/veenstra/ multiprocessors
advanced course in computer architecture. Note that there Proteus (www.ee.lsu.edu/Bothshared-memory and
is often supplemental material available (e.g. compilers, koppel/proteus.html) message-passing multiprocessors
execution traces, instruction set handbooks). RSIM Shared-memory multiprocessors
TABLE 5: ADVANCED MICROARCHITECTURESIMULATORS rsim.cs.uiuc.edu/rsim/ using processors with
instmction-level parallelism
DLX Bundled with [ I 0], implements the SimOS MIPS and Alpha-based
(ftp://max.stanford.edu/pub/max/ DLX CPU. Unix simos.stanford.edu/intmduction.html uni/multiprocessors;US boot
pub/hennessy-patterson.soflware)
DLXview (yara.ecn.purdue.edu/ Interactivegraphical extension of Wisconsin Simulator Page Has links to many multiprocessm
www.cs.wisc.edu/arch/www/tools.html simulators used for research
-teamaaa/dlxview) DLXsim. Unix
Mic-I Simulator Described in [14] (earlier 1988
www.ontko.com/micl/ edition). Java, Unix, Win 10 Memory Subsystem Simulators
Micro Architecture Simulator Microprogrammed processor The simulators most appropriate for introductory courses
www.kagi.com/fab/msim.html similar to that in [14]. MacOS tend to be descriptive, illustrating concepts by depicting
computer operation. But advanced students arc prepared
MipSim (mouse.vlsivie.tuwien. C++ source code for a simulator
ac.at/lehre/rechnerarchitekturen/ emulatinga pipelined processor for detailed performance statistics that allow meaningful
based on [10]. analysis, evaluation and comparison. A n early lesson these
download/Simulatoren) students learn is that factors other than the C P U (e.g. cache
SimpleScalar Described in [13], toolset for hit ratio) affect performance. Our final category includes
www.simplescalar.org instruction-level parallelism & examples o f simulators that arc used to model and analyze
branch prediction. Unix
various m e m o r y hierarchies and cache configurations.
SuperScalar DLX (www.rs.e- Pipelinedsuperscalar mixed
Iechnik.tu-darmstadt.de/TUD/res/ behavior/RTLmodel of the DLX The simulators listed in the table below encourage
dhdocu/SuperscalarDLX.html) processor. experimentation with different cache m e m o r y levels, sizes
and degrees o f associativity. Several o f them operate by
WinDLX Windows front-end for DLX
ttp://Rp.mkp.com/pub/dl~ simulator. DOS 3.3+, Win3.0+ "executing" m e m o r y reference trace tapes and reporting
cumulative m e m o r y access metrics.

179
 TABLE 7: MEMORY SUBSYSTEMSIMULATORS Simulation (SCS), 1999.
Cacheprof Tool to quantify cache [2] Carpinelli, J.D. Computer Systems Organization &
behavior. Linux on x86 Architecture, Addison Wesley, 2001.
www.cacheprof.org
Cache Simulator (www.ece.gatech.edu/ Specify a cache configuration; [3] Cassel, L., Kumar, D. et. al., Distributed Expertise for
research/labs/reveng/cachesim/) analyze results. Web-based Teaching Computer Organization & Architecture,
CACTI (www.research.compaq.com/ Model cache access and cycle A C M SIGCSE Bulletin, Vol. 33, No. 2, June 2001, pp.
times for different memories, 111-126.
wrl/people/j ouppi/CACTI.html)
Dinero IV Cache hierarchy simulator for [4] Clements, A. Guest Editor's Introduction: Computer
www.cs.wisc.edul-markhill/DinerolV/ memory reference traces. Unix Architecture Education, IEEE Micro, Vol. 20. No. 3,
PRIMA (www.dsi.unimo.it/ Trace-driven cache simulator. May/June 2000, pp. 10-12.
staff/st36/imagelab/prima.html) Unix [5] Clements, A. The Undergraduate Curriculum in
Xcache Cache performance profiling. Computer Architecture, IEEE Micro, Vol. 20. No. 3,
Unix w/X Windows
www.prism, uvsq.frlarchilsofts/X Caehel May/June 2000, pp. 13-22.
[6] Desikan, R., Burger D. and S.W. Keckler. Measuring
11 Summary Experimental Error in Microprocessor Simulation, Intl.
Symp. on Computer Architecture (ISCA), 2001.
The availability of free and Internet-accessible simulators
provides instructors with a means of effectively and [7] Englander, I. The Architecture o f Hardware and
efficiently presenting the expanding field of computer Systems Software 2nd edition, Wiley, 2000.
organization/architecture, despite limited resources. In this [8] Goodman, J. and K. Miller, A Programmer's View o f
paper, we have surveyed and characterized simulator Computer Architecture, Oxford U. Press, 1993.
teaching tools that can be easily integrated into a wide [9] Grunbacher, H. Teaching Computer Architecture/
range of courses. They represent a conceptual breadth and Organisation Using Simulators, IEEE Frontiers in
level of interactivity that is difficult to achieve with other Education Conference (FIE), 1998, pp. 1107-1112.
teaching techniques.
[10] Hennessy, J. and D. Patterson, Computer Architecture:
One idea for future work in this area involves researching A Quantitative Approach 2 "d edition, Morgan
the potential for interoperability between simulators. A Kaufrnann, 1996_
related idea is identifying individual simulators that can be
gracefully extended through the different categories we [ll]Patt, Y. and S. Patel. Introduction to Computing
have identified. These options would aid instructors by Systems, McGraw-Hill, 2001.
broadening the areas in which simulation could be [12] Patterson, D. and J. Hennessy, Computer Organization
employed and by reducing the learning curve. See the and Design 2 "d edition, Morgan Kaufmann, 1998.
following URL for future contributions and for a [13] Stallings, W. Computer Organization and Architecture
maintained set of the links reported in this paper: 5 th edition, Prentice Hall, 2000.
< h t t p : / / w w w . acs. i l s t u , e d u / f a c u l t y / d l d o s s / y u r c i k /
c a a l e / c a a l e s imul a t o r s , h t m l >. [14] Tanenbaum, A. Structured Computer Organization 4 Ih
edition, Prentice Hall, 1999.
12 Acknowledgments [15]Yehezkel, C., Yurcik W., and M. Pearson, Teaching
The authors would like to thank the following members o f
Computer Architecture with a Computer-Aided
the ITiCSE 2000 working group for helping to motivate Learning Environment: State of the Art Simulators,
this work: (in alphabetical order) Kevin Boulding/Seattle Intl. Conf. on Simulation and Multimedia in
Pacific Univ., Co-Chair Boots Cassel/Villanova Univ., Jim Engineering Education (ICSEE), Society for Computer
Davies/Univ. of Oxford, John Impagliazzo/Hofstra Univ., Simulation (SCS), 2001
Co-Chair Deepak Kumar/Bryn Mawr Univ. and Murray [16] Yurcik, W. and H. Osborne. A Crowd of Little Man
Pearson/Univ. of Waikato. We would also like to Computers: Visual Computer Simulator Teaching
acknowledge intellectual contributions from Cecile Tools, Winter Simulation Conference (WSC), 2001.
Yehezkel/Weizmann Institute and Ed Gehringer/N.C. State [17] Yureik, W., Wolffe, G. S., and M. A. Holliday. A
(creator of the Computer Architecture Course Database Survey of Simulators Used in Computer
<hi tp :/ / w w w a s s i g n . p h y s i c s . ncsu. e d u / c o m p a r c h / > ) . Organization/Architecture Courses, Summer Computer
Simulation Conference (SCSC), Society for Computer
References Simulation (SCS), 2001.
[1] Bruschi, S. M. et. al., Simulation as a Tool for
Computer Architecture Teaching, Summer Computer
Simulation Conference (SCSC), Society for Computer

180