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922 CHAPTER 9 OPERATIONAL-AMPLIFIER AND DATA-CONVERTER CIRCUITS

9.7 DATA CONVERTERS—AN INTRODUCTION

In this section we begin the study of another group of analog IC circuits of great importance;
namely, data converters.

9.7.1 Digital Processing of Signals

Most physical signals, such as those obtained at transducer outputs, exist in analog form.
Some of the processing required on these signals is most conveniently performed in an
analog fashion. For instance, in instrumentation systems it is quite common to use a high-
input-impedance, high-gain, high-CMRR differential amplifier right at the output of the
transducer. This is usually followed by a filter whose purpose is to eliminate interference.
However, further signal processing is usually required, which can range from simply obtain-
ing a measurement of signal strength to performing some algebraic manipulations on this
and related signals to obtain the value of a particular system parameter of interest, as is usu-
ally the case in systems intended to provide a complex control function. Another example of
signal processing can be found in the common need for transmission of signals to a remote
receiver.
Many such forms of signal processing can be performed by analog means. In earlier
chapters we encountered circuits for implementing a number of such tasks. However, an
attractive alternative exists: It is to convert, following some initial analog processing, the
signal from analog to digital form and then use economical, accurate, and convenient digital
ICs to perform digital signal processing. Such processing can in its simplest form provide
us with a measure of the signal strength as an easy-to-read number (consider, e.g., the digital
voltmeter). In more involved cases the digital signal processor can perform a variety of
arithmetic and logic operations that implement a filtering algorithm. The resulting digital
filter does many of the same tasks that an analog filter performs—namely, eliminate inter-
ference and noise. Yet another example of digital signal processing is found in digital com-
munications systems, where signals are transmitted as a sequence of binary pulses, with the
obvious advantage that corruption of the amplitudes of these pulses by noise is, to a large
extent, of no consequence.
Once digital signal processing has been performed, we might be content to display the
result in digital form, such as a printed list of numbers. Alternatively, we might require an
analog output. Such is the case in a telecommunications system, where the usual output may
be audible speech. If such an analog output is desired, then obviously we need to convert the
digital signal back to an analog form.
It is not our purpose here to study the techniques of digital signal processing. Rather, we
shall examine the interface circuits between the analog and digital domains. Specifically, we
shall study the basic techniques and circuits employed to convert an analog signal to digital
form (analog-to-digital or simply A/D conversion) and those used to convert a digital
signal to analog form (digital-to-analog or simply D/A conversion). Digital circuits are
studied in Chapters 10 and 11.

9.7.2 Sampling of Analog Signals

The principle underlying digital signal processing is that of sampling the analog signal.
Figure 9.36 illustrates in a conceptual form the process of obtaining samples of an analog
signal. The switch shown closes periodically under the control of a periodic pulse signal
(clock). The closure time of the switch, τ, is relatively short, and the samples obtained are
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9.7 DATA CONVERTERS—AN INTRODUCTION 923

vO

vI
C


(a)

(b) vI

(c) vS

T t

(d) vO

FIGURE 9.36 The process of periodically sampling an analog signal. (a) Sample-and-hold (S/H) circuit.
The switch closes for a small part (τ seconds) of every clock period (T). (b) Input signal waveform. (c) Sam-
pling signal (control signal for the switch). (d) Output signal (to be fed to A/D converter).

stored (held) on the capacitor. The circuit of Fig. 9.36 is known as a sample-and-hold (S/H)
circuit. As indicated, the S/H circuit consists of an analog switch that can be implemented
by a MOSFET transmission gate (Section 10.5), a storage capacitor, and (not shown) a
buffer amplifier.
Between the sampling intervals—that is, during the hold intervals—the voltage level on
the capacitor represents the signal samples we are after. Each of these voltage levels is then
fed to the input of an A/D converter, which provides an N-bit binary number proportional to
the value of signal sample.
The fact that we can do our processing on a limited number of samples of an analog
signal while ignoring the analog-signal details between samples is based on the Shannon’s
sampling theorem [see Lathi (1965)].
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924 CHAPTER 9 OPERATIONAL-AMPLIFIER AND DATA-CONVERTER CIRCUITS

9.7.3 Signal Quantization

Consider an analog signal whose values range from 0 to +10 V. Let us assume that we wish
to convert this signal to digital form and that the required output is a 4-bit digital signal.4 We
know that a 4-bit binary number can represent 16 different values, 0 to 15; it follows that the
resolution of our conversion will be 10 V ⁄ 15 = 2--3- V. Thus an analog signal of 0 V will be
represented by 0000, --23- V will be represented by 0001, 6 V will be represented by 1001, and
10 V will be represented by 1111.
All these sample numbers are multiples of the basic increment ( --23- V). A question now
arises regarding the conversion of numbers that fall between these successive incremental
levels. For instance, consider the case of a 6.2-V analog level. This falls between 18/ 3 and
20 / 3. However, since it is closer to 18 / 3 we treat it as if it were 6 V and code it as 1001. This
process is called quantization. Obviously errors are inherent in this process; such errors are
called quantization errors. Using more bits to represent (encode or, simply, code) an analog
signal reduces quantization errors but requires more complex circuitry.

9.7.4 The A/D and D/A Converters as Functional Blocks

Figure 9.37 depicts the functional block representations of A/D and D/A converters. As indi-
cated, the A/D converter (also called an ADC) accepts an analog sample vA and produces an
N-bit digital word. Conversely, the D/A converter (also called a DAC) accepts an n-bit
digital word and produces an analog sample. The output samples of the D/A converter are
often fed to a sample-and-hold circuit. At the output of the S/H circuit a staircase waveform,
such as that in Fig. 9.38, is obtained. The staircase waveform can then be smoothed by a

FIGURE 9.37 The A/D and D/A converters as circuit blocks.

vA

FIGURE 9.38 The analog samples at the output of a D/A converter are usually fed to a sample-and-hold
circuit to obtain the staircase waveform shown. This waveform can then be filtered to obtain the smooth
waveform, shown in color. The time delay usually introduced by the filter is not shown.

4
Bit stands for binary digit.
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9.8 D/A CONVERTER CIRCUITS 925

low-pass filter, giving rise to the smooth curve shown in color in Fig. 9.38. In this way an
analog output signal is reconstructed. Finally, note that the quantization error of an A/D con-
verter is equivalent to ± 1--2- least significant bit (bN).

EXERCISE

9.31 An analog signal in the range 0 to +10 V is to be converted to an 8-bit digital signal. What is the resolu-
tion of the conversion in volts? What is the digital representation of an input of 6 V? What is the represen-
tation of an input of 6.2 V? What is the error made in the quantization of 6.2 V in absolute terms and as
a percentage of the input? As a percentage of full scale? What is the largest possible quantization error
as a percentage of full scale?
Ans. 0.0392 V; 10011001; 10011110; −0.0064 V; −0.1%; −0.064%; 0.196%

9.8 D/A CONVERTER CIRCUITS

9.8.1 Basic Circuit Using Binary-Weighted Resistors

Figure 9.39 shows a simple circuit for an N-bit D/A converter. The circuit consists of a ref-
erence voltage VREF, N binary-weighted resistors R, 2R, 4R, 8R, . . . , 2N−1R, N single-pole
double-throw switches S1, S2, . . . , SN, and an op amp together with its feedback resistance
Rf = R / 2.
The switches are controlled by an N-bit digital input word D,
b b b
D = -----11 + -----22 + . . . + -----NN- (9.109)
2 2 2
where b1, b2, and so on are bit coefficients that are either 1 or 0. Note that the bit bN is the
least significant bit (LSB) and b1 is the most significant bit (MSB). In the circuit in
Fig. 9.39, b1 controls switch S1, b2 controls S2, and so on. When bi is 0, switch Si is in posi-
tion 1, and when bi is 1 switch Si is in position 2.
Since position 1 of all switches is ground and position 2 is virtual ground, the current
through each resistor remains constant. Each switch simply controls where its corresponding
current goes: to ground (when the corresponding bit is 0) or to virtual ground (when the cor-
responding bit is 1). The currents flowing into the virtual ground add up, and the sum flows

VREF

FIGURE 9.39 An N-bit D/A converter using a binary-weighted resistive ladder network.
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926 CHAPTER 9 OPERATIONAL-AMPLIFIER AND DATA-CONVERTER CIRCUITS

through the feedback resistance Rf. The total current iO is therefore given by
V REF V REF V REF
i O = ----------
- b + ---------- - b + . . . + ---------------
- bN
R 1 2R 2 N –1
2 R
2V REF  b 1 b 2 . . . b N
= -------------- ----- + ----- + + -----N-
R  21 22 2 
Thus,
2V REF
i O = --------------D (9.110)
R
and the output voltage vO is given by
vO = −iORf = −VREF D (9.111)
which is directly proportional to the digital word D, as desired.
It should be noted that the accuracy of the DAC depends critically on (1) the accuracy of
VREF, (2) the precision of the binary-weighted resistors, and (3) the perfection of the switches.
Regarding the third point, we should emphasize that these switches handle analog signals;
thus their perfection is of considerable interest. While the offset voltage and the finite on
resistance are not of critical significance in a digital switch, these parameters are of immense
importance in analog switches. The use of MOSFETs to implement analog switches will be
discussed in Chapter 10. Also, we shall shortly see that in practical circuit implementations of
the DAC, the binary-weighted currents are generated by current sources. In this case the
analog switch can be realized using the differential-pair circuit, as will be shown shortly.
A disadvantage of the binary-weighted resistor network is that for a large number of bits
(N > 4) the spread between the smallest and largest resistances becomes quite large. This
implies difficulties in maintaining accuracy in resistor values. A more convenient scheme
exists utilizing a resistive network called the R-2R ladder.

9.8.2 R-2R Ladders

Figure 9.40 shows the basic arrangement of a DAC using an R-2R ladder. Because of the
small spread in resistance values, this network is usually preferred to the binary-weighted
scheme discussed earlier, especially for N > 4. Operation of the R-2R ladder is straightfor-
ward. First, it can be shown, by starting from the right and working toward the left, that the

VREF

FIGURE 9.40 The basic circuit configuration of a DAC utilizing an R-2R ladder network.
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9.8 D/A CONVERTER CIRCUITS 927

resistance to the right of each ladder node, such as that labeled X, is equal to 2R. Thus the
current flowing to the right, away from each node, is equal to the current flowing downward
to ground, and twice that current flows into the node from the left side. It follows that
I1 = 2I2 = 4I3 = . . . = 2N−1IN (9.112)
Thus, as in the binary-weighted resistive network, the currents controlled by the switches
are binary weighted. The output current iO will therefore be given by
V REF
i O = ----------
-D (9.113)
R

9.8.3 A Practical Circuit Implementation

A practical circuit implementation of the DAC utilizing an R-2R ladder is shown in Fig. 9.41.
The circuit utilizes BJTs to generate binary-weighted constant currents I1, I2, . . . , IN, which
are switched between ground and virtual ground of an output summing op amp (not shown).
We shall first show that the currents I1 to IN are indeed binary-weighted, with I1 correspond-
ing to the MSB and IN corresponding to the LSB of the DAC.
Starting at the two rightmost transistors, QN and Qt , we see that if they are matched, their
emitter currents will be equal and are denoted (IN /α). Transistor Qt is included to provide
proper termination of the R-2R network. The voltage between the base line of the BJTs and
node N will be
I
VN = VBE N +  ----N- ( 2R )
 α

To virtual ground
of output op amp
···
··· iO

VREF S1 S2 S3 SN
IREF

RREF
0 A
I1 I2 I3 IN 1 IN
0 V

QREF Q1 Q2 Q3 B QN  1 QN Qt
A1 ···

IREF I1 I2 I3 IN 1 IN IN
      

2R 2R 2R 2R 2R 2R 2R

R R R R
···
1 2 3 N1 N
2IN

VEE

FIGURE 9.41 A practical circuit implementation of a DAC utilizing an R-2R ladder network.
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928 CHAPTER 9 OPERATIONAL-AMPLIFIER AND DATA-CONVERTER CIRCUITS

where VBEN is the base–emitter voltage of QN. Since the current flowing through the resistor
R connected to node N is (2IN /α), the voltage between node B and node (N − 1) will be

2I 4I N
VN – 1 = VN +  --------N R = VBEN + --------R
 α  α
Assuming, for the moment, that VBE N –1 = VBE N , we see that a voltage of (4IN /α)R appears
across the resistance 2R in the emitter of QN−1. Thus QN−1 will have an emitter current of
(2IN /α) and a collector current of (2IN), twice the current in QN. The two transistors will have
equal VBE drops if their junction areas are scaled in the same proportion as their currents,
which is usually done in practice.
Proceeding in the manner above we can show that

I1 = 2I2 = 4I3 = . . . = 2N−1IN (9.114)

under the assumption that the EBJ areas of Q1 to QN are scaled in a binary-weighted fashion.
Next consider op amp A1, which, together with the reference transistor QREF, forms
a negative-feedback loop. (Convince yourself that the feedback is indeed negative.) A
virtual ground appears at the collector of QREF forcing it to conduct a collector current IREF =
VREF / RREF independent of whatever imperfections QREF might have. Now, if QREF and Q1 are
matched, their collector currents will be equal,
I1 = IREF
Thus, the binary-weighted currents are directly related to the reference current, independent
of the exact values of VBE and α. Also observe that op amp A1 supplies the base currents of
all the BJTs.

9.8.4 Current Switches

Each of the single-pole double-throw switches in the DAC circuit of Fig. 9.41 can be imple-
mented by a circuit such as that shown in Fig. 9.42 for switch Sm. Here Im denotes the current
flowing in the collector of the mth-bit transistor. The circuit is a differential pair with the

iO

VBIAS VBIAS

FIGURE 9.42 Circuit implementation of switch Sm in the DAC of Fig. 9.41. In a BiCMOS technology, Qms
and Qmr can be implemented using MOSFETs, thus avoiding the inaccuracy caused by the base current of BJTs.
sedr42021_ch09.fm Page 929 Wednesday, October 15, 2003 9:11 AM

9.9 A/D CONVERTER CIRCUITS 929

base of the reference transistor Qmr connected to a suitable dc voltage VBIAS, and the digital
signal representing the mth bit bm applied to the base of the other transistor Qms. If the volt-
age representing bm is higher than VBIAS by a few hundred millivolts, Qms will turn on and
Qmr will turn off. The bit current Im will flow through Qms and onto the output summing line.
On the other hand, when bm is low, Qms will be off and Im will flow through Qmr to ground.
The current switch of Fig. 9.42 is simple and features high-speed operation. It suffers,
however, from the fact that part of the current Im flows through the base of Qms and thus does
not appear on the output summing line. More elaborate circuits for current switches can be
found in Grebene (1984). Also, in a BiCMOS technology the differential-pair transistors
Qms and Qmr can be replaced with MOSFETs, thus eliminating the base current problem.

EXERCISES

9.32 What is the maximum resistor ratio required by a 12-bit D/A converter utilizing a binary-weighted
resistor network?
Ans. 2048
9.33 If the input bias current of an op amp, used as the output summer in a 10-bit DAC, is to be no more than
that equivalent to 1--4- LSB, what is the maximum current required to flow in Rf for an op amp whose bias
current is as great as 0.5 µA?
Ans. 2.046 mA

9.9 A/D CONVERTER CIRCUITS

There exist a number of A/D conversion techniques varying in complexity and speed. We
shall discuss four different approaches: two simple, but slow, schemes, one complex (in
terms of the amount of circuitry required) but extremely fast method, and, finally, a method
particularly suited for MOS implementation.

9.9.1 The Feedback-Type Converter

Figure 9.43 shows a simple A/D converter that employs a comparator, an up/down counter,
and a D/A converter. The comparator circuit provides an output that assumes one of two

FIGURE 9.43 A simple feedback-type A/D converter.

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930 CHAPTER 9 OPERATIONAL-AMPLIFIER AND DATA-CONVERTER CIRCUITS

distinct values: positive when the difference input signal is positive, and negative when
the difference input signal is negative. We shall study comparator circuits in Chapter 13. An
up/down counter is simply a counter that can count either up or down depending on the
binary level applied at its up/down control terminal. Because the A/D converter of Fig. 9.43
employs a DAC in its feedback loop it is usually called a feedback-type A/D converter. It
operates as follows: With a 0 count in the counter, the D/A converter output, vO, will be zero
and the output of the comparator will be high, instructing the counter to count the clock
pulses in the up direction. As the count increases, the output of the DAC rises. The process
continues until the DAC output reaches the value of the analog input signal, at which point
the comparator switches and stops the counter. The counter output will then be the digital
equivalent of the input analog voltage.
Operation of the converter of Fig. 9.43 is slow if it starts from zero. This converter how-
ever, tracks incremental changes in the input signal quite rapidly.

9.9.2 The Dual-Slope A/D Converter

A very popular high-resolution (12- to 14-bit) (but slow) A/D conversion scheme is illus-
trated in Fig. 9.44. To see how it operates, refer to Fig. 9.44 and assume that the analog
input signal vA is negative. Prior to the start of the conversion cycle, switch S2 is closed,
thus discharging capacitor C and setting v1 = 0. The conversion cycle begins with opening
S2 and connecting the integrator input through switch S1 to the analog input signal. Since vA
is negative, a current I = vA/R will flow through R in the direction away from the integrator.
Thus v1 rises linearly with a slope of I/ C = vA/RC, as indicated in Fig. 9.44(b). Simulta-
neously, the counter is enabled and it counts the pulses from a fixed-frequency clock. This
phase of the conversion process continues for a fixed duration T1. It ends when the counter
has accumulated a fixed count denoted nREF. Usually, for an N-bit converter, nREF = 2N.
Denoting the peak voltage at the output of the integrator as VPEAK, we can write with reference
to Fig. 9.44(b)
V PEAK vA
-------------- = -------
- (9.115)
T1 RC
At the end of this phase, the counter is reset to zero.
Phase II of the conversion begins at t = T1 by connecting the integrator input through
switch S1 to the positive reference voltage VREF. The current into the integrator reverses
direction and is equal to VREF / R. Thus v1 decreases linearly with a slope of (VREF/RC). Simul-
taneously the counter is enabled and it counts the pulses from the fixed-frequency clock.
When v1 reaches zero volts, the comparator signals the control logic to stop the counter.
Denoting the duration of phase II by T2, we can write, by reference to Fig. 9.44(b),
V PEAK V REF
- = ----------
------------- - (9.116)
T2 RC
Equations (9.115) and (9.116) can be combined to yield
vA 
T2 = T1  ----------
- (9.117)
 VREF 
Since the counter reading, nREF, at the end of T1 is proportional to T1 and the reading, n, at
the end of T2 is proportional to T2, we have
vA 
n = n REF  ----------
- (9.118)
 V REF 
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9.9 A/D CONVERTER CIRCUITS 931

VREF

(a)

VPEAK
VREF
RC

FIGURE 9.44 The dual-slope A/D conversion method. Note that vA is assumed to be negative.
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932 CHAPTER 9 OPERATIONAL-AMPLIFIER AND DATA-CONVERTER CIRCUITS

Analog Bit 1
Comparator
input
1
VR 1

Comparator Bit 2
2 Digital
VR 2 Logic
output

···

···
Comparator Bit N
2N  1
VR (2 N  1)

FIGURE 9.45 Parallel, simultaneous, or flash A/D conversion.

Thus the content of the counter,5 n, at the end of the conversion process is the digital equiv-
alent of vA.
The dual-slope converter features high accuracy, since its performance is independent of
the exact values of R and C. There exist many commercial implementations of the dual-
slope method, some of which utilize CMOS technology.

9.9.3 The Parallel or Flash Converter

The fastest A/D conversion scheme is the simultaneous, parallel, or flash conversion process
illustrated in Fig. 9.45. Conceptually, flash conversion is very simple. It utilizes 2N − 1
comparators to compare the input signal level with each of the 2N − 1 possible quantization
levels. The outputs of the comparators are processed by an encoding-logic block to provide
the N bits of the output digital word. Note that a complete conversion can be obtained within
one clock cycle.
Although flash conversion is very fast, the price paid is a rather complex circuit imple-
mentation. Variations on the basic technique have been successfully employed in the design
of IC converters.

9.9.4 The Charge-Redistribution Converter

The last A/D conversion technique that we shall discuss is particularly suited for CMOS
implementation. As shown in Fig. 9.46, the circuit utilizes a binary-weighted capacitor
array, a voltage comparator, and analog switches; control logic (not shown in Fig. 9.46) is
also required. The circuit shown is for a 5-bit converter; capacitor CT serves the purpose
of terminating the capacitor array, making the total capacitance equal to the desired value
of 2C.
Operation of the converter can be divided into three distinct phases, as illustrated in
Fig. 9.46. In the sample phase (Fig. 9.46a) switch SB is closed, thus connecting the top plate
of all capacitors to ground and setting vO to zero. Meanwhile, switch SA is connected to the
analog input voltage vA. Thus the voltage vA appears across the total capacitance of 2C,
resulting in a stored charge of 2CvA. Thus, during this phase, a sample of vA is taken and a
proportional amount of charge is stored on the capacitor array.

5
Note that n is not a continuous function of vA, as might be inferred from Eq. (9.118). Rather, n takes
on discrete values corresponding to one of the 2N quantized levels of vA.
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9.9 A/D CONVERTER CIRCUITS 933

SB vO  0 Comparator

Control
C C C C C  logic
C CT
2 4 8 16 16

S1 S2 S3 S4 S5 ST

SA
vA

VREF
(a)

SB vO   vA


C C C C C 
C CT
2 4 8 16 16

S1 S2 S3 S4 S5 ST

SA
vA

VREF
(b)

SB vO  0


C C C C C 
C CT
2 4 8 16 16

S1 S2 S3 S4 S5 ST

SA
vA

VREF
(c)

FIGURE 9.46 Charge-redistribution A/D converter suitable for CMOS implementation: (a) sample phase,
(b) hold phase, and (c) charge-redistribution phase.

During the hold phase (Fig. 9.46b), switch SB is opened and switches S1 to S5, and ST are
thrown to the ground side. Thus the top plate of the capacitor array is open-circuited while
their bottom plates are connected to ground. Since no discharge path has been provided, the
capacitor charges must remain constant, with the total equal to 2CvA. It follows that the volt-
age at the top plate must become −vA. Finally, note that during the hold phase, SA is con-
nected to VREF in preparation for the charge-redistribution phase.
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934 CHAPTER 9 OPERATIONAL-AMPLIFIER AND DATA-CONVERTER CIRCUITS

Next, we consider the operation during the charge-redistribution phase illustrated in

Fig. 9.46(c). First, switch S1 is connected to VREF (through SA). The circuit then consists of
VREF, a series capacitor C, and a total capacitance to ground of value C. This capacitive divider
causes a voltage increment of VREF ⁄ 2 to appear on the top plates. Now, if vA is greater than
VREF ⁄ 2 , the net voltage at the top plate will remain negative, which means that S1 will be left
in its new position as we move on to switch S2. If, on the other hand, vA was smaller than
VREF ⁄ 2 , then the net voltage at the top plate would become positive. The comparator will
detect this situation and signal the control logic to return S1 to its ground position and then to
move on to S2.
Next, switch S2 is connected to VREF, which causes a voltage increment of VREF ⁄ 4 to
appear on the top plate. If the resulting voltage is still negative, S2 is left in its new position;
otherwise, S2 is returned to its ground position. We then move on to switch S3, and so on
until all the bit switches S1 to S5 have been tried.
It can be seen that during the charge-redistribution phase the voltage on the top plate will
be reduced incrementally to zero. The connection of the bit switches at the conclusion of this
phase gives the output digital word; a switch connected to ground indicates a 0 value for the
corresponding bit, whereas connection to VREF indicates a 1. The particular switch configu-
ration depicted in Fig. 9.46(c) is for D = 01101. Observe that at the end of the conversion
process, all the charge is stored in the capacitors corresponding to 1 bits; the capacitors of
the 0 bits have been discharged.
The accuracy of this A/D conversion method is independent of the value of stray capaci-
tances from the bottom plate of the capacitors to ground. This is because the bottom plates are
connected either to ground or to VREF; thus the charge on the stray capacitances will not flow
into the capacitor array. Also, because both the initial and the final voltages on the top plate are
zero, the circuit is also insensitive to the stray capacitances between the top plates and ground.6
The insensitivity to stray capacitances makes the charge-redistribution technique a reasonably
accurate method capable of implementing A/D converters with as many as 10 bits.

EXERCISES

9.34 Consider the 5-bit charge-redistribution converter in Fig. 9.46 with VREF = 4 V. What is the voltage
increment appearing on the top plate when S5 is switched? What is the full-scale voltage of this con-
verter? If vA = 2.5 V, which switches will be connected to VREF at the end of conversion?
Ans. 1--8- V; 31
------ V; S1 and S3
8
9.35 Express the maximum quantization error of an N-bit A/D converter in terms of its least-significant bit
(LSB) and in terms of its full-scale analog input VFS.
N
Ans. ± 1--2- LSB; VFS ⁄ 2(2 – 1 )

9.10 SPICE SIMULATION EXAMPLE

We conclude this chapter with an example to illustrate the use of SPICE in the simulation of
the two-stage CMOS op amp.

6
More precisely, the final voltage can deviate from zero by as much as the analog equivalent of the
LSB. Thus, the insensitivity to top-plate capacitance is not complete.