Review of Digital Design

Fundamentals
□ Bit: A binary digit; can have a value of 0 or 1

□ Logic gate: A digital circuit that manipulates bits. A logic

gate takes one or more bits as input(s) and generates one bit
as the output.
■ A logic gate can be represented pictorially by its logic symbol. The
function performed by a logic gate can also be expressed
algebraically, or in terms of a Truth Table.

□ Logic diagram: A diagram showing an interconnection of

logic symbols.
Truth table
□ Truth table: The truth table gives the input-output
relation of a logic gate or logic circuit in tabular
form.
□ It specifies the output bit(s) for each possible input
bit combination.
□ A circuit with n binary inputs has 2n different input
combinations.
□ A binary value of 0 is sometimes referred to as L
(low) or F (false).
□ A binary value of 1 is sometimes referred to as H
(high) or T (true).
Minterm
□ Minterm: One specific combination of input
bits, out of the 2n different input
combinations.
□ A truth table of n binary inputs has 2n
minterms and an output is specified for each
minterm.
Logic Gates
Logic Symbols:

A out
0 1
1 0
A B Out
0 0 0
0 1 0
1 0 0
1 1 1
Logic Gates
A B Out
0 0 0
0 1 1
1 0 1
1 1 1
A B Out
0 0 0
0 1 1
1 0 1
1 1 0
Logic Gates
A B Out
0 0 1
0 1 1
1 0 1
1 1 0

A B Out
0 0 1
0 1 0
1 0 0
1 1 0
Logic Gates

A B Out
0 0 1
0 1 0
1 0 0
1 1 1
Digital Circuit Representation
□ The truth table, logic diagram and algebraic expression are
three different ways of representing a digital circuit and given
one form the other representations of the circuit can be
derived.

□ The truth table representation of a Boolean function is unique,

but the same function may have more than one logic or
algebraic representation.

□ EXAMPLE: Given the following logic diagram, obtain the

corresponding truth table and algebraic expression.
Digital Circuit Representation

A B C Out
0 0 0 1
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 0
Basic Identities of Boolean algebra
K-Map
□ The complexity of a digital circuit depends on
the complexity of the corresponding algebraic
expression.
□ The karnaugh map (k-map) provides a simple
straightforward procedure for simplifying
Boolean expressions and thereby obtaining
simpler digital circuits.
K-Map
□ A diagram made up of squares, where each
square represents a minterm.
□ The output (0 or 1) for a specific minterm is
inserted in the corresponding square in the
k-map.
□ A function with n variables has a kmap with
2n squares.
Properties of k-maps
□ Each row (or column) in the k-map is labelled
by one or more bits, representing the values of
the corresponding variables for that row (or
column).
□ The minterm corresponding to a particular
square in the k-map (belonging to the ith
column and jth row) is obtained by taking the
values of the variables associated with the ith
column and jth row.
 AB AB
CD 00 01 11 10
C 00 01 11 10
00
0
01
1
11

10

For example the shaded squares in figure 1 (a) and (b) correspond to minterms
111 and 0110 respectively.
Rules for simplifying k-maps
1. Plot a Boolean function on to a k-map by inserting
1’s in those squares where the corresponding
minterm has an output of 1.

2. Combine adjacent 1’s into groups such that:

i) a group contains only 1’s
ii) the number of squares in a group is a power of 2
iii) the group is not part of a single larger group
Rules for simplifying k-maps
3.Keep choosing additional groups until all the
1’s in the k-map are covered i.e. each 1 is part
of at least one group. Choose the groups in
such a way that the total number of groups
needed to cover all the 1’s is minimized.
4.Obtain an algebraic product term for each
group.
5.Obtain the final solution by a logical OR of all
the terms from step 4.
Some definitions:
□ Implicant: A group of 2k adjacent 1’s in a
k-map.
□ Prime Implicant (PI): An implicant which is
not completely covered by a single larger
implicant.
□ Essential Prime Implicant: A prime implicant
where at least one minterm is not covered by
any other prime implicant.
Examples

AB
C 00 01 11 10
A B C F
0 0 0 1 0 1 1 0 0
1
0 0 1 1 1 0 0 1
0 1 0 1
0 1 1 0
A`B` F=A`C`+B`C
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 0
Essential PI Non-Essential PI
Example
AB
A B C D F
0 0 0 0 0 CD 00 01 11 10
0 0 0 1
0 0 1 0
0
1
00 0 1 1 1
0 0 1 1
0 1 0 0
0
1
01 0 0 1 1
0 1 0 1 0
0 1 1 0 1 0 0 1 1
0 1 1 1 0
11
1 0 0 0 1
1 0 0 1 1 10 1 1 0 1
1 0 1 0 1
1 0 1 1 1
F=AD+AB`+BC`D`+A`CD`
1 1 0 0 1
OR F=AD+ AC`+ A`BD`+B`CD`
1 1 0 1 1
1 1 1 0 0
1 1 11 1 Non-Essential PI Essential PI
Don’t Cares
□ A truth table can be expressed in compact form by simply
specifying the minterms for which the output is 1.
□ For some functions, there may be certain input conditions for
which we don’t care what output is. This situation is
represented by putting a “d” in the output for the
corresponding minterms.
□ Don’t care outputs may be treated as either a 0 or a 1, in order
to obtain a minimized circuit.
□ All minterms which are not in the given list(s) are assumed
to have an output of 0.
Function with Don’t cares

a) F has three inputs A,B, and C.

b) The outputs corresponding to minterms 0,2,6
are 1.
c) The outputs corresponding to minters 1,3,5 are
don’t cares
d) The outputs for all remaining minterms (4 and 7)
are 0.
Examples:

□ Obtain a minimized SOP expression for the

following functions. Also, list all the prime
implicants and indicate which ones are
essential.
 F
AB
00 01 11 10
C Prime Implicants
0 1 1 1 0
A’(essential)
1 d d 0 d
BC’(essential)

F=
A’+BC’
 AB

CD 00 01 11 10 Prime Implicants
00
0 1 1 0 BC’D’(Essential)
01 A’B’C(Essential)
1 d 0 d B’D
11 A’BC’
d 0 0 d A’C’D
10
1 0 0 0
F = B’D + BC’D’ + A’B’C
Product of sums (POS)

□ A POS expression for a function F can be

obtained by grouping the 0,s in the k-map for
F and then
(i) Obtain a SOP expression for F’ and
complement it OR
(ii) Directly obtain the POS expression by
examining the selected groups.
 Prime Implicants of F’
AB (Essential)
AB CD(Essential)
A’B’D
CD 00 01 11 10
00 1 1 0 1 F’=AB+CD
F’’=(AB+CD)’
01 d 1 0 1 F=(AB)’.(CD)’
F=(A’+B’).(C’+D’)
11 0 d 0 0

10 1 1 0 1
Final POS expression

The same final expression can also be obtained by directly examining the groups.
 Prime Implicants of F’
A’B (Essential)
AB B’CD(Essential)
A’CD
CD 00 01 11 10
00 1 0 1 1 F’=A’B+B’CD

01 1 0 1 1 F’’=(A’B+B’CD)’
F=(A’B)’.(B’CD)’
11 0 0 1 0 F=(A+B’).(B+C’+D’)

10 1 0 1 1

Final POS expression

The same final expression can also be obtained by directly examining the groups.
Multi-output functions

□ A multi-output function is treated similar to a

single output function,
□ A separate k-map and Boolean expression
needs to be derived for each of the outputs.
□ Example: full adder (FA) circuit which has 3
inputs - the 2 bits (A and B) to be added and a
carry in (Cin) and has 2 outputs a sum (S) and
a carry out to the next stage (Cout).
Half Adder
□ Performs 1-bit addition. Truth Table
□ Inputs: A0, B0 A0 B 0 S0 C1
□ Outputs: S0, C1 0 0 0 0
□ Index indicates significance,
0 1 1 0
0 is for LSB and 1 is for the
next higher significant bit. 1 0 1 0
□ Boolean equations: 1 1 0 1
■ S0 = A0B0’+A0’B0 = A0 ⊕ B0
■ C1 = A0B0
Half Adder (cont.)
□ S0 = A0B0’+A0’B0 = A0⊕ B0
□ C1 = A0B0

Block Diagram Logic Diagram

A0 B0
A0
S0
1 bit B0
C
half
1
adder
C
S0
1
n-bit Addition
□ Design an n-bit binary adder which performs the
addition of two n-bit binary numbers and generates a
n-bit sum and a carry out.

□ Example: Let n=4

Cout C3 C2 C1 C0 1 1 0 1 0
A3 A2 A1 A0 1 1 0 1
+ B 3 B2 B1 B0 +1 1 0 1
--------------------- ----------
S3 S2 S1 S0 1 0 1 0
Full Adder
S AB
00 01 11 10
C
0 1 0 1
0
A B Cin Cout S
1 1 0 1 0
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0 Cout AB
1 0 0 0 1 00 01 11 10
1 0 1 1 0 C
0 0 0 1 0
1 1 0 1 0 1 0 1 1 1
1 1 1 1 1
S=A’B’C +
A’BC’+AB’C’+ABC
S= A B C
Cout=AB+BC+AC
Full Adder using 2 Half Adders
■ A full adder can also be realized with two half adders and
an OR gate, since Ci+1 can also be expressed as:
■ Ci+1 = AiBi + AiBi’Ci + Ai’BiCi
= AiBi + (AiBi’ + Ai’Bi)Ci
= AiBi + (Ai ⊕ Bi)Ci
■ and Si = Ai ⊕ Bi ⊕ Ci

A
B Si
i
i
Ci
C +1
n-bit Ripple Carry Adder
□ Constructed using n 1-bit full adder blocks
in parallel.
□ Cascade the full adders so that the carry out
from one becomes the carry in to the next
higher bit position.
Example: 4-bit Ripple Carry Adder
C4 C3 C2 C1 C0
A3 A2 A1 A0
+B3 B2 B1 B0
--------------
S3 S2 S1 S0
Decoder
□ Converts binary information from n inputs to
upto 2n outputs.
□ If some input combinations are unused, the
number of outputs may be less.
□ For each input combination, only one output
is active and all other outputs are inactive.
A decoder may also have an enable input (E), as shown below.

Examples: Design a 2-4 decoder (without enable input).

a) Truth Table

A1 A0 D0 D1 D2 D3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
 b) K-maps
A1
D0 A1 0 1
0 1 D1
A0
A0 0 0 0
0
1 0 1 1 0
1
0 0
D0=A1’A0’ D1=A1’A0
D2
A1 D3
0 1 A1
0 1
A0 A0
0 0 1
0 0 0
1 0 0
1 0 1
D2=A1A0’
D3=A1A0
 Combinational Logic Circuits
DECODER
2-to-4 Decoder

E A 1 A 0 D 0 D1 D2
0 0 0 D03 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0
1 d d 1 1 1
1 D0

A D1
0
D2

A D3
E
1
Decoder Expansion:
□ Smaller decoders can be combined to form a larger one.
□ Example: Construct a 3-8 decoder using 2-4 decoders.
Multiplexer
□ A combinational circuit which takes information from one of
2n input lines and transfers it to a single output line.
□ The particular input line chosen is determined by n select
lines.
What is a Multiplexer (MUX)?
□ A MUX is a digital switch that
Multiplexer
has multiple inputs (sources) Block
and a single output Diagram
(destination).

MUX
□ The select lines determine 2 1 Outp
which input is connected to the Inp N
output. uts ut
(sources (destinatio
□ MUX Types ) n)

2-to-1 (1 select line) N

4-to-1 (2 select lines) Sel
8-to-1 (3 select lines)
ect
16-to-1 (4 select lines)
Lin 44
Example
Design a 2-to-1 multiplexer with two input lines and one select line
S I1 I0 F
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1

Truth table
k-maps
f
S,I1
0 0 01 11 10
I0
0 0 0 1 0
1
1 1 1 0

f = SI1 + S’I0
 Combinational Logic Circuits
MULTIPLEXER
4-to-1 Multiplexer

Select Output
S1 S 0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
I0

I1
Y
I2

I3

S0
S1
4-to-1 Multiplexer (MUX)
D0

UX
D1

M
Y
D2

D3

B
A

B A Y

0 0 D0

0 1 D1

1 0 D2

1 1 D3

49
Multiplexer Expansion
□ Smaller multiplexers can be combined to form a larger one.
□ Example: Construct a 4-to-1 multiplexer using 2-to-1 multiplexers.
What is a Demultiplexer (DEMUX)?
□ A DEMUX is a digital switch Demultiplexe
with a single input (source) and r
a multiple outputs Block Diagram
(destinations).
□ The select lines determine
Inp 1 2 Outp

MU
DE
which output the input is N

X
connected to. ut uts
(source (destination
□ DEMUX Types )

1-to-2 (1 select line)

N s)

1-to-4 (2 select lines) Sel

1-to-8 (3 select lines) ect
1-to-16 (4 select lines)
Lin 51
Typical Application of a DEMUX
Single Selec Multiple
Source tor Destination
B/W
Laser
s Printer

Fax
Machin
e
D0

MU
X D1

DE
D2 Color

X
Inkjet
D3
Printer

B A Selected Destination
0 0 B/W Laser Printer Pen
Plotte
0 1 Fax Machine
r
1 0 Color Inkjet Printer
1 1 Pen Plotter
52
1-to-4 De-Multiplexer (DEMUX)
D0

D1

MU
DE
X
D2

X
D3

B
A

B A D0 D1 D2 D3

0 0 X 0 0 0

0 1 0 X 0 0

1 0 0 0 X 0

1 1 0 0 0 X

53
Encoders
□ An encoder performs the inverse operation of
a decoder.
□ It has (up to) 2n inputs and n outputs.
□ Each input line is mapped to a specific
combination of output lines.
□ Only one input line can be high at any given
time.
Example:

I3 I2 I1 I0 A0 A1
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1

A 4-to-2 encoder
 Combinational Logic Circuits
ENCODER/

Octal-to-Binary Encoder

D1 A
D2
0
A
D3
D4 1
D5 A
D6
2
D7
Flipflops and Sequential Circuits
□ Combinational circuits: Digital circuits
where the output depends only on the current
inputs. They consist of a interconnection of
logic gates.

□ Sequential circuits: Output depends on the

previous output state as well as the current
inputs.
Flipflops and Sequential Circuits
□ Flipflops: Basic storage element, capable of
storing previous state (0 or 1). A flipflop can
store 1 bit of information and is the basic
building block of sequential circuits.
Flipflops and Sequential Circuits
□ Edge-triggered flipflop: State changes occur only during a
positive (0 to1) or negative (1 to 0) clock transition. The
corresponding flipflops are called positive or negative
edge-triggered flipflops respectively.

The output (Next State) of a flipflop depends on

■ Present State and
■ Current inputs and is described in a characteristics table.

Characteristic table: Specifies the next state, based on present

state and current inputs.
SR-FLIPFLOP

Input Present Next

SR StateQ(t) State Q(t+1)

00 0 0
00 1 1
01 0 0
01 1 0
10 0 1
10 1 1
11 Indeterminate
JK-FLIPFLOP

Input Present Next

S R StateQ(t) State Q(t+1)
00 0 0
00 1 1
01 0 0
01 1 0
10 0 1
10 1 1
11 0 1

11 1 0
D-FLIPFLOP
Input Present Next
D StateQ(t) State
Q(t+1)
0 0 0
0 1 0
1 0 1
1 1 1
T-FLIPFLOP

Input Present Next

T StateQ(t) State Q(t+1)
0 0 0
0 1 1
1 0 1
1 1 0
 Sequential Circuit Analysis
Complete the state table, for the following circuit.
present state input flipflop inputs next state
A B X DA DB A B
0 0 0 0 0 0 0
0 0 1 0 1 0 1
0 1 0 1 0 1 0
0 1 1 1 1 1 1
1 0 0 0 1 0 1
1 0 1 1 1 1 1 DA = AX +B; DB = X + A;
1 1 0 1 1 1 1
1 1 1 1 1 1 1
Sequential Circuit Analysis
present state input flipflop inputs next state
A B X TA TB A B

0 0 0 0 0 0 0
0 0 1 0 1 0 1
0 1 0 1 0 1 1
0 1 1 1 1 1 0
1 0 0 0 1 1 1
1 0 1 1 1 0 1
1 1 0 1 1 0 0
1 1 1 1 1 0 0

(ii) Complete the state table If T-flipflops are used.

. TA = AX +B; TB = X + A;
SR-FLIPFLOP JK-FLIPFLOP

Excitation Tables

Present Next Inputs Present Next state Inputs

State state State Q(t+1) J K
S R
Q(t) Q(t+1) Q(t)

0 0 0 d 0 0 0 d

0 1 1 0 0 1 1 d

1 0 0 1 1 0 d 1

1 1 d 0 1 1 d 0
D-FLIPFLOP T-FLIPFLOP

Excitation Tables

Present Next Inputs Present Next state Inputs

State state State Q(t+1) T
D
Q(t) Q(t+1) Q(t)

0 0 0 0 0 0

0 1 1 0 1 1
1 0 1
1 0 0
1 1 0
1 1 1
Sequential Circuit Design
□ The excitation tables give the required inputs to the flipflop
for a specific change of state. The steps to be followed in the
design of sequential circuits are as follows:

1. Draw the state diagram from the problem specification

2. Choose the type of flipflop to be used.
3. Fill in the excitation table of the circuit using the selected flipflops.
4. Obtain k-maps for each flipflop input.
5. Simplify the k-maps to obtain Boolean expressions for each flipflop input.
6. Draw the logic diagram of the circuit (if required).
 Example
□ Design a sequential circuit going through the following sequence of states: 0 -> 1
-> 3 -> 5 -> 6 -> 2 -> 7 -> 4 -> 0

000 001 011

100 101

111 010 110

(a) Draw the state diagram of the circuit.

Excitation Table

Present state Next State FlipFlop inputs

A B C A B C T A T B TC

0 0 0 0 0 1 0 0 1
0 0 1 0 1 1 0 1 0
0 1 0 1 1 1 1 0 1
0 1 1 1 0 1 1 1 0
1 0 0 0 0 0 1 0 0
1 0 1 1 1 0 0 1 1
1 1 0 0 1 0 1 0 0
1 1 1 1 0 0 0 1 1
 K-Map
TA
AB
C 00 01 11 10
0
0 1 1 1
Present state Next State FlipFlop inputs
1 0 1 0 0 A B C T A T B TC
A B C
TB TA=A’B + AC’ 0 0 0 0 0 1 0 0 1
AB 0 0 1 0 1 1 0 1 0
C 00 01 11 10
0 1 0 1 1 1 1 0 1
0 0 0 0 0
1 0 1 1 1 0 1 1 1 0
1 1 1 1
1 0 0 0 0 0 1 0 0
TB= C 1 0 1 1 1 0 0 1 1
TC
1 1 0 0 1 0 1 0 0
AB
00 01 11 10 1 1 1 1 0 0 0 1 1
C
0 1 1 0 0
1 0 0 1 1

TC=A’C’+AC
More examples of sequential circuit synthesis.

□ Design a two bit

X=0
sequential circuit 00 01
00
with an external X=1
input x, such that
the circuit counts
up when x=0 and X=1 X=0
X=0 X=1
counts down when
x=1. Use D X=1
flipflops.
11 10
■ a) Draw state
X=0
diagram
Excitation Table

Present Next State FlipFlop Inputs

state
A B DA DB X=0
A B x 00 01
00
0 0 0 0 1 0 1 X
=
0 0 1 1 1 1 1 1
X=1 X=1 X=0
0 1 0 1 0 1 0 X=0
0 1 1 0 0 0 0
X=1
1 0 0 1 1 1 1
11 10
1 0 1 0 1 0 1
X=0
1 1 0 0 0 0 0
1 1 1 1 0 1 0
 K-maps

DA
AB Present Next FlipFlop
00 01 11 10
state State Inputs
x
0 0 1 0 1 A B x A B DA DB
1 1 0 1 0 0 0 0 0 1 0 1
0 0 1 1 1 1 1
DA= A’B’x+ A’Bx’+AB’x’+ABx 0 1 0 1 0 1 0
0 1 1 0 0 0 0
DB
1 0 0 1 1 1 1
AB 00 01 11 10
x 1 0 1 0 1 0 1
0 1 0 0 1
1 1 0 0 0 0 0
1 1 0 0 1
1 1 1 1 0 1 0

DB= B’
Draw the logic diagram.
2. Design a sequential circuit, using T flipflops, that has the following
state diagram

1/0 A = 00
1/0
A B B = 01
0/0 C = 10
D = 11

0/1 1/0 0/0 0/0

C
D
1/0
Fill in the excitation table corresponding to the above sequential
circuit, using T flipflops.

Present State Next State FlipFlop Inputs Output

Q1 Q2 X Q1 Q2 T1 T2

0 0 0 0 0 0 0 0 1/0 1/0
0 0 1 0 1 0 1 0 A B
0/0
0 1 0 1 0 1 1 0
0 1 1 0 1 0 0 0 0/1 1/0 0/0 0/0
1 0 0 0 0 1 0 0
1 0 1 1 1 0 1 0 C
D
1 1 0 0 0 1 1 1 1/0

1 1 1 0 1 1 0 0
 Fill in the K-maps and obtain a Boolean expression for each flipflop
input.

T1 Present Next FlipFlop Output

Q1Q2
State State Inputs
x 00 01 11 10
0 0 1 1 1 T1 T2
Q1 Q2 X Q1
1 0 0 1 0 Q2
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0
T1= Q1Q2 + Q1x’ + Q2x’
0 1 0 1 0 1 1 0
T2 0 1 1 0 1 0 0 0
Q1Q2
00 01 11 10 1 0 0 0 0 1 0 0
x
1 0 1 1 1 0 1 0
0 0 1 1 0
1 1 0 0 1 1 1 0 0 0 1 1 1
1 1 1 0 1 1 0 0
T2= Q2x’ + Q2’x
Draw the logic diagram.
Registers
□ A group of flipflops, where each flipflop stores 1 bit of
information.
□ A n-bit register consists of n flipflops and can store any
binary information of n bits.
□ May have combinational circuits associated with each
flipflop, for simple data processing operations such as LOAD,
INR, INV etc.
□ The flipflops hold binary information and the combinational
circuits control how and when new information is transferred
to the register.
Registers
□ Figure 1 shows a simple 4-bit register with parallel load. A positive clock
transition will load all 4 values I3 - I0 into the register.
□ In a digital system a clock generator supplies a
continuous set of clock pulses.
□ A separate control signal (LOAD) is required to
determine which clock pulse affects the data in a
register.
□ When LOAD = 1, a new value is loaded into the
register.
□ When LOAD = 0, the contents of the register
remains unchanged.
Shift Registers
□ A register capable of shifting binary information in
one or both directions.
□ It consists of a chain of flipflops in cascade, with the
output of one stage connected to the input of the next
stage.
□ All flipflops receive a common clock pulse.
□ A shift register that can shift in both directions is
called a bidirectional shift register.
Shift registers
Counters
□ A register that can go through a
predetermined sequence of states upon the
application of input pulses is called a counter.
□ Counters are widely used in digital systems
for counting number of occurrences of events,
generating timing and control information etc.
Binary Counters
□ A binary counter is one which follows a
simple binary sequence.
□ A n-bit binary counter can count from 0 to 2n -
1.
□ A down counter counts in the reverse order.
Capacity of Memory
□ Total number of bytes that can be stored in the
memory.
□ Capacity = no. of words X no. of bytes per
word.
□ Address lines are used to select one particular
word in memory.
□ A memory with 2k locations requires k
address lines.
Examples
(i) How many address and data lines* are needed for a 64k X
8 bit memory.
64k = 26 X 210 = 216.
So, 16 address lines are needed.
wordlength = 8 bits. So, 8 data lines are needed.
(ii) How many address and data lines are needed for a 16M X
4 byte memory.
16M = 24 X 220 = 224.
So, 24 address lines are needed.
wordlength = 4 bytes = 32 bits. So, 32 data lines are needed
*
Assume the entire word is accessed as a unit.
Random Access Memory (RAM)
□ Memory cells from any location can be
accessed directly.
□ Process of locating a word in memory is the
same and takes the same amount of time for
each location.
□ RAM is capable of both READ and WRITE
operations.
Steps for accessing a memory location
in a RAM
□ 1) Apply address to address lines
□ 2) Apply data bits to input data lines (for
WRITE operation only)
□ 3) Activate READ/WRITE control line
□ 4) Read data from data output lines (for
READ operation only)