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LAB 5: Encoders, MUX AND Demux: Name: Date: Regd-No

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0% found this document useful (0 votes)
195 views

LAB 5: Encoders, MUX AND Demux: Name: Date: Regd-No

Uploaded by

Muhammad Shess
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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LAB 5: ENCODERS, MUX AND DEMUX

Name : Date :
Regd-No :
OBJECTIVES:
 To investigate the operation of an Encoder circuit.
 To investigate the operation of a Multiplexer (MUX) circuit.
 To investigate the operation of a Demultiplexer (DEMUX) circuit.
SUGGESTED READING:
 Chapter 5: MSI and PLD components, Digital Logic Design by Morris
Mano.
 Chapter 6: Functions of Combinational Logic, Digital Fundamentals by
Floyd.
EQUIPMENT AND COMPONENTS:
 74LS147 IC – Decimal-to-BCD priority encoder
 74LS151 IC – 8-line to 1-line Multiplexer/data selector
 74LS155 IC – 3-to-8 line decoder / 1-to-8 line DEMUX
 Digital Trainer Board
 DMM / Palm Scope
 Logic Analyzer
 Logic probe
 Circuit Simulator (Proteus ISIS® Professional or an equivalent)

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INTRODUCTION:
There are Medium Scale Integration (MSI) devices developed to perform a variety
of digital logic functions. These functions include but are not limited to Decoders,
Encoders, Multiplexers, De-multiplexers, Parity Checkers, Magnitude Comparators,
Adders, Multipliers, and Counters. These logic functions form the building blocks
in digital systems.

1. Encoders
An encoder is a logic circuit that produces a binary value output based upon the
active input(s). For 2N inputs there will be N outputs. A standard encoder circuit
allows one input to be active at a time. Priority encoders allow multiple inputs to
be activated and will generate an output code based upon the highest numbered
input.

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LAB 5 MCT-212: Digital Logic Design
Department of Mechatronics and Control Engineering, U.E.T Lahore
2. Multiplexers
A multiplexer is a logic circuit that routes a one of several inputs, which is selected,
to a single output. The input channeled to the output is determined by a set of select
input lines. For N select lines there will be 2N input lines, only one of which will be
selected to output.

3. Demultiplexer
A Demultiplexer is a logic circuit that reads a binary value represented on a set of
inputs and activates one of the outputs that corresponds to the binary value using
select data lines. For N inputs there will be 2N outputs. Only one output can be active
at any given time.

TASK 1: Study the Logic Analyzer function of the DSO 320E. It should be on the
page 11 of the user’s manual.
 Connect the logic analyzer probe and monitor the logic level triggering using
toggle switches from the digital trainer board.

TASK 2:
The 74147 is a priority encoder that will output the binary equivalent value of the
active or highest priority input.

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LAB 5 MCT-212: Digital Logic Design
Department of Mechatronics and Control Engineering, U.E.T Lahore
 Using the datasheet, connect the correct circuit and verify the operation of the
Encoder. Use toggle switches for the input signals.

TASK 3:
The 74151 is a multiplexer that will output one line of data from eight input lines.

 Measure and record the output logic level in the following table for the given
input combinations. Use toggle switches for the input signals.

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LAB 5 MCT-212: Digital Logic Design
Department of Mechatronics and Control Engineering, U.E.T Lahore
TASK 4:
The 74155 is a demultiplexer that will output eight lines of data from one input line.
 Using the datasheet, connect the correct circuit and verify the operation of the
Encoder. Use toggle switches for the input signals.

REVIEW QUESTION:
Q1. Explain why it is not possible for more than 1 output to be active at one time using a
74LS155 decoder/DEMUX?

Q2. The Encoder circuit evaluated in this lab is not operating properly. A technician makes the
measurements shown in the following table.

What is the most probable cause(s) of this failure?

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LAB 5 MCT-212: Digital Logic Design
Department of Mechatronics and Control Engineering, U.E.T Lahore
Q3. The following circuit is an example of how a MUX can be used to implement a logic
function. Complete the truth table.

CONCLUSIONS:

RECOMMENDATIONS:

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LAB 5 MCT-212: Digital Logic Design
Department of Mechatronics and Control Engineering, U.E.T Lahore
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LAB 5 MCT-212: Digital Logic Design
Department of Mechatronics and Control Engineering, U.E.T Lahore
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LAB 5 MCT-212: Digital Logic Design
Department of Mechatronics and Control Engineering, U.E.T Lahore
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LAB 5 MCT-212: Digital Logic Design
Department of Mechatronics and Control Engineering, U.E.T Lahore
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LAB 5 MCT-212: Digital Logic Design
Department of Mechatronics and Control Engineering, U.E.T Lahore
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LAB 5 MCT-212: Digital Logic Design
Department of Mechatronics and Control Engineering, U.E.T Lahore
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LAB 5 MCT-212: Digital Logic Design
Department of Mechatronics and Control Engineering, U.E.T Lahore
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LAB 5 MCT-212: Digital Logic Design
Department of Mechatronics and Control Engineering, U.E.T Lahore

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