College of Computer Science

Department of Computer Science

Chapter 2: Instruction Set Architecture (ISA)

Part II: Instruction Formats & MIPS
Instructions

2018-2019
Contents

 Instruction formats
 Instruction types
 MIPS instructions
 Examples

1
 Instruction Set Architecture (ISA)
 Critical Interface between hardware and software
 An ISA includes the following …
 Instructions and Instruction Formats
• Data Types, Encodings, and Representations
• Addressing Modes: to address Instructions and Data
• Handling Exceptional Conditions (like division by zero)
 Programmable Storage: Registers and Memory
 Examples (Versions) First Introduced in
 Intel (8086, 80386, Pentium, ...) 1978
 MIPS (MIPS I, II, III, IV, V) 1986
 PowerPC (601, 604, …) 1993
 Instructions

 Instructions are the language of the machine

 We will study the MIPS instruction set architecture
 Known as Reduced Instruction Set Computer (RISC)
 Elegant and relatively simple design
 Similar to RISC architectures developed in mid-1980’s
and 90’s
 Very popular, used in many products
• Silicon Graphics, ATI, Cisco, Sony, etc.
 Comes next in sales after Intel IA-32 processors
• Almost 100 million MIPS processors sold in 2002 (and
increasing)
 Alternative design: Intel IA-32
 Known as Complex Instruction Set Computer (CISC)
 Overview of the MIPS Processor

...

4 bytes per word Memory

Up to 232 bytes = 230 words
...

EIU $0 Execution & FPU F0 Floating

32 General $1 Integer Unit F1 Point Unit
Purpose $2 (Main proc) F2 (Coproc 1) 32 Floating-Point
Registers Registers
$31 F31
Arithmetic & Integer FP
ALU
Logic Unit mul/div Arith
Floating-Point
Arithmetic Unit
Hi Lo
TMU BadVaddr Trap &
Status Memory Unit
Cause (Coproc 0)
Integer EPC
Multiplier/Divider
 MIPS General-Purpose Registers
 32 General Purpose Registers (GPRs)
 Assembler uses the dollar notation to name registers
• $0 is register 0, $1 is register 1, …, and $31 is register 31
 All registers are 32-bit wide in MIPS32
$0 = $zero $16 = $s0
 Register $0 is always zero $1 = $at $17 = $s1

• Any value written to $0 is discarded $2 = $v0

$3 = $v1
$18 = $s2
$19 = $s3
 Software conventions $4 = $a0 $20 = $s4

 There are many registers (32)

$5 = $a1 $21 = $s5
$6 = $a2 $22 = $s6
 Software defines names to all registers $7 = $a3 $23 = $s7

• To standardize their use in programs $9 = $t1 $25 = $t9

$8 = $t0 $24 = $t8

 Example: $8 - $15 are called $t0 - $t7 $10 = $t2 $26 = $k0

• Used for temporary values

$11 = $t3 $27 = $k1
$12 = $t4 $28 = $gp
$13 = $t5 $29 = $sp
$14 = $t6 $30 = $fp
$15 = $t7 $31 = $ra
 MIPS Register Conventions

 Assembler can refer to registers by name or by number

 It is easier for you to remember registers by name
 Assembler converts register name to its corresponding number
Name Register Usage
$zero $0 Always 0 (forced by hardware)
$at $1 Reserved for assembler use
$v0 – $v1 $2 – $3 Result values of a function
$a0 – $a3 $4 – $7 Arguments of a function
$t0 – $t7 $8 – $15 Temporary Values
$s0 – $s7 $16 – $23 Saved registers (preserved across call)
$t8 – $t9 $24 – $25 More temporaries
$k0 – $k1 $26 – $27 Reserved for OS kernel
$gp $28 Global pointer (points to global data)
$sp $29 Stack pointer (points to top of stack)
$fp $30 Frame pointer (points to stack frame)
$ra $31 Return address (used by jal for function call)
 Instruction Formats
 All instructions are 32-bit wide. Three instruction formats:
 Register (R-Type)
 Register-to-register instructions
 Op: operation code specifies the format of the instruction

Op6 Rs5 Rt5 Rd5 sa5 funct6

 Immediate (I-Type)
 16-bit immediate constant is part in the instruction
Op6 Rs5 Rt5 immediate16
 Jump (J-Type)
 Used by jump instructions

Op6 immediate26
 Instruction Categories
 Integer Arithmetic
 Arithmetic, logical, and shift instructions
 Data Transfer
 Load and store instructions that access memory
 Data movement and conversions
 Jump and Branch
 Flow-control instructions that alter the sequential sequence
 Floating Point Arithmetic
 Instructions that operate on floating-point registers
 R-Type Format

Op6 Rs5 Rt5 Rd5 sa5 funct6

 Op: operation code (opcode)

 Specifies the operation of the instruction
 Also specifies the format of the instruction
 funct: function code – extends the opcode
 Up to 26 = 64 functions can be defined for the same opcode
 MIPS uses opcode 0 to define R-type instructions
 Three Register Operands (common to many instructions)
 Rs, Rt: first and second source operands
 Rd: destination operand
 sa: the shift amount used by shift instructions
 Integer Add /Subtract Instructions
Instruction Meaning R-Type Format
add $s1, $s2, $s3 $s1 = $s2 + $s3 op = 0 rs = $s2 rt = $s3 rd = $s1 sa = 0 f = 0x20
addu $s1, $s2, $s3 $s1 = $s2 + $s3 op = 0 rs = $s2 rt = $s3 rd = $s1 sa = 0 f = 0x21
sub $s1, $s2, $s3 $s1 = $s2 – $s3 op = 0 rs = $s2 rt = $s3 rd = $s1 sa = 0 f = 0x22
subu $s1, $s2, $s3 $s1 = $s2 – $s3 op = 0 rs = $s2 rt = $s3 rd = $s1 sa = 0 f = 0x23

 add & sub: overflow causes an arithmetic exception

 In case of overflow, result is not written to destination register
 addu & subu: same operation as add & sub
 However, no arithmetic exception can occur (Add Unsigned )
 Overflow is ignored
 Many programming languages ignore overflow
 The + operator is translated into addu
 The – operator is translated into subu
 Addition/Subtraction Example
 Consider the translation of: f = (g+h) – (i+j)
 Compiler allocates registers to variables
 Assume that f, g, h, i, and j are allocated registers $s0 thru
$s4
 Called the saved registers: $s0 = $16, $s1 = $17, …, $s7 =
$23
 Translation of: f = (g+h) – (i+j)
addu $t0, $s1, $s2 # $t0 = g + h
addu $t1, $s3, $s4 # $t1 = i + j
subu $s0, $t0, $t1 # f = (g+h)–(i+j)
 Temporary results are stored in $t0 = $8 and $t1 = $9
 Translate: addu $t0,$s1,$s2 to binary code

 Solution: op rs = $s1 rt = $s2 rd = $t0 sa func

000000 10001 10010 01000 00000 100001
 Logical Bitwise Operations
 Logical bitwise operations: and, or, xor, nor
x y x and y x y x or y x y x xor y x y x nor y
0 0 0 0 0 0 0 0 0 0 0 1
0 1 0 0 1 1 0 1 1 0 1 0
1 0 0 1 0 1 1 0 1 1 0 0
1 1 1 1 1 1 1 1 0 1 1 0
 AND instruction is used to clear bits: x and 0 = 0
 OR instruction is used to set bits: x or 1 = 1
 XOR instruction is used to toggle bits: x xor 1 = not x
 NOR instruction can be used as a NOT, how?
 nor $s1,$s2,$s2 is equivalent to not $s1,$s2
 Logical Bitwise Instructions

Instruction Meaning R-Type Format

and $s1, $s2, $s3 $s1 = $s2 & $s3 op = 0 rs = $s2 rt = $s3 rd = $s1 sa = 0 f = 0x24
or $s1, $s2, $s3 $s1 = $s2 | $s3 op = 0 rs = $s2 rt = $s3 rd = $s1 sa = 0 f = 0x25
xor $s1, $s2, $s3 $s1 = $s2 ^ $s3 op = 0 rs = $s2 rt = $s3 rd = $s1 sa = 0 f = 0x26
nor $s1, $s2, $s3 $s1 = ~($s2|$s3) op = 0 rs = $s2 rt = $s3 rd = $s1 sa = 0 f = 0x27

 Examples:
Assume $s1 = 0xabcd1234 and $s2 = 0xffff0000

and $s0,$s1,$s2 # $s0 = 0xabcd0000

or $s0,$s1,$s2 # $s0 = 0xffff1234
xor $s0,$s1,$s2 # $s0 = 0x54321234
nor $s0,$s1,$s2 # $s0 = 0x0000edcb
 Examples

Multiply $s1 by 26, using shift and add instructions

Hint: 26 = 2 + 8 + 16

sll $t0, $s1, 1 ; $t0 = $s1 * 2

sll $t1, $s1, 3 ; $t1 = $s1 * 8
addu $s2, $t0, $t1 ; $s2 = $s1 * 10
sll $t0, $s1, 4 ; $t0 = $s1 * 16
addu $s2, $s2, $t0 ; $s2 = $s1 * 26

Multiply $s1 by 31, Hint: 31 = 32 – 1

sll $s2, $s1, 5 ; $s2 = $s1 * 32

subu $s2, $s2, $s1 ; $s2 = $s1 * 31
 I-Type Format
 Constants are used quite frequently in programs
 The R-type shift instructions have a 5-bit shift amount
constant
 What about other instructions that need a constant?
 I-Type: Instructions with Immediate Operands
Op6 Rs5 Rt5 immediate16

 16-bit immediate constant is stored inside the instruction

 Rs is the source register number
 Rt is now the destination register number (for R-type it was
Rd)
 Examples of I-Type ALU Instructions:
 Add immediate: addi $s1, $s2, 5 # $s1 = $s2 + 5
 OR immediate: ori $s1, $s2, 5 # $s1 = $s2 | 5
 I-Type ALU Instructions

Instruction Meaning I-Type Format

addi $s1, $s2, 10 $s1 = $s2 + 10 op = 0x8 rs = $s2 rt = $s1 imm16 = 10
addiu $s1, $s2, 10 $s1 = $s2 + 10 op = 0x9 rs = $s2 rt = $s1 imm16 = 10
andi $s1, $s2, 10 $s1 = $s2 & 10 op = 0xc rs = $s2 rt = $s1 imm16 = 10
ori $s1, $s2, 10 $s1 = $s2 | 10 op = 0xd rs = $s2 rt = $s1 imm16 = 10
xori $s1, $s2, 10 $s1 = $s2 ^ 10 op = 0xe rs = $s2 rt = $s1 imm16 = 10
lui $s1, 10 $s1 = 10 << 16 op = 0xf 0 rt = $s1 imm16 = 10

 addi: overflow causes an arithmetic exception

 In case of overflow, result is not written to destination register

 addiu: same operation as addi but overflow is ignored

 Immediate constant for addi and addiu is signed
 No need for subi or subiu instructions

 Immediate constant for andi, ori, xori is unsigned

 Examples: I-Type ALU Instructions
 Examples: assume A, B, C are allocated $s0, $s1, $s2

A = B+5; translated as addiu $s0,$s1,5

C = B–1; translated as addiu $s2,$s1,-1
op=001001 rs=$s1=10001 rt=$s2=10010 imm = -1 = 1111111111111111

A = B&0xf; translated as andi $s0,$s1,0xf

C = B|0xf; translated as ori $s2,$s1,0xf
C = 5; translated as ori $s2,$zero,5
A = B; translated as ori $s0,$s1,0
 No need for subi, because addi has signed immediate
 Register 0 ($zero) has always the value 0
 32-bit Constants
 I-Type instructions can have only 16-bit constants

Op6 Rs5 Rt5 immediate16

 What if we want to load a 32-bit constant into a register?
 Can’t have a 32-bit constant in I-Type instructions 
 We have already fixed the sizes of all instructions to 32 bits
 Solution: use two instructions instead of one 
 Suppose we want: $s1=0xAC5165D9 (32-bit constant)
 lui: load upper immediate
load upper clear lower
16 bits 16 bits
lui $s1,0xAC51 $s1=$17 0xAC51 0x0000
ori $s1,$s1,0x65D9 $s1=$17 0xAC51 0x65D9
 Conditional Branch Instructions
 MIPS compare and branch instructions:
beq Rs,Rt,label branch to label if (Rs == Rt)
bne Rs,Rt,label branch to label if (Rs != Rt)
 MIPS compare to zero & branch instructions
Compare to zero is used frequently and implemented efficiently
bltz Rs,label branch to label if (Rs < 0)
bgtz Rs,label branch to label if (Rs > 0)
blez Rs,label branch to label if (Rs <= 0)
bgez Rs,label branch to label if (Rs >= 0)
 No need for beqz and bnez instructions. Why?
 Set on Less Than Instructions

 MIPS also provides set on less than instructions

slt rd,rs,rt if (rs < rt) rd = 1 else rd = 0
sltu rd,rs,rt unsigned <
slti rt,rs,im16 if (rs < im16) rt = 1 else rt = 0
sltiu rt,rs,im16 unsigned <
 Signed / Unsigned Comparisons
Can produce different results
Assume $s0 = 1 and $s1 = -1 = 0xffffffff
slt $t0,$s0,$s1 results in $t0 = 0
stlu $t0,$s0,$s1 results in $t0 = 1
 More on Branch Instructions
 MIPS hardware does NOT provide instructions for …
blt, bltu branch if less than (signed/unsigned)
ble, bleu branch if less or equal (signed/unsigned)
bgt, bgtu branch if greater than (signed/unsigned)
bge, bgeu branch if greater or equal (signed/unsigned)
Can be achieved with a sequence of 2 instructions
 How to implement: blt $s0,$s1,label
 Solution: slt $at,$s0,$s1
bne $at,$zero,label
 How to implement: ble $s2,$s3,label
 Solution: slt $at,$s3,$s2
beq $at,$zero,label
 Translating an IF Statement

 Consider the following IF statement:

if (a == b) c = d + e; else c = d – e;
Assume that a, b, c, d, e are in $s0, …, $s4 respectively

 How to translate the above IF statement?

beq $s0, $s1,

addu $s2, $s3, $s4

j exit
else: subu $s2, $s3, $s4
exit: . . .
 Compound Expression with AND
 Programming languages use short-circuit evaluation
 If first expression is false, second expression is skipped

if (($s1 > 0) && ($s2 < 0)) {$s3++;}

# One Possible Implementation ...

bgtz $s1, L1 # first expression
j next # skip if false
L1: bltz $s2, L2 # second expression
j next # skip if false
L2: addiu $s3,$s3,1 # both are true
next:
 Load and Store Instructions
 Instructions that transfer data between memory & registers

 Programs include variables such as arrays and objects

 Such variables are stored in memory

 Load Instruction:
load
 Transfers data from memory to a register
Registers Memory
 Store Instruction: store

 Transfers data from a register to memory

 Memory address must be specified by load and store