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Lab 6 Implementation of MUX: 2: 1 Multiplexer

The document discusses implementing multiplexers using logic gates and equations. It covers a 2:1 multiplexer, implementing a 2:1 mux with logic gates and equations, and implementing a 4:1 mux with logic gates.

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umair khan
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63 views3 pages

Lab 6 Implementation of MUX: 2: 1 Multiplexer

The document discusses implementing multiplexers using logic gates and equations. It covers a 2:1 multiplexer, implementing a 2:1 mux with logic gates and equations, and implementing a 4:1 mux with logic gates.

Uploaded by

umair khan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Lab 6

Implementation of MUX
Introduction:
A multiplexer (or “mux”) is a digital switch that has 2M data inputs, M select (control) inputs, and a
single output. It routes data from one of 2M data inputs to its single output.

2: 1 Multiplexer

A 2: 1 multiplexer has two data inputs, one select input, and a single output. The function of a 2: 1
multiplexer.

TASK 1:

Implementation of 2x1 mux by logic gates.

TASK 2: Implement 2x1 mux by equations.


TASK 3: Implement 4x1 by logic gates.

Conclusion:
In this lab we learn how to implement mux in ISE design suite.

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