.ThinkPad X260 - NM-A531 Schematic

5 4 3 2 1
www.xinxunwei.com 400-800-9990
WV-3 FVT LOGIC SCHEMATICS WV-3
VER0.1
3/19/2015
001.TITLE PAGE 036.BLANK
D
002.EC HISTORY
003.CPU(1/16) : DDI/EDP
004.CPU(2/16) : DDR4
005.CPU(3/16) : DDR4
037.RF COMPONENT
038.LCD/LID/MIC/CAMERA/PWR SW
039.BLANK
040.HDMI CONNECTOR
071.THINK ENGINE(1/2)
072.THINK ENGINE(2/2)
n ly D
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073.DC-IN
006.CPU(4/16) : MISC/JTAG 041.DISPLAY PORT CONNECTOR 074.BATTERY INPUT
007.CPU(5/16) : LPC/SPI/SMBUS/C-LINK 042.BLANK 075.BATTERY CHARGER(BQ24760)
008.CPU(6/16) : LPSS/ISH
009.CPU(7/16) : AUDIO/SDXC
010.CPU(8/16) : PCIE/USB/SATA
043.SATA HDD CONN
044.USB POWER/CONN
045.USB POWER/CONN
076.BLANK
077.BLANK
io
078.DC/DC VCC5M/VCC3M(TPS51285B) n
C
011.CPU(9/16) : CSI-2/EMMC
012.CPU(10/16) : CLOCK SIGNALS
013.CPU(11/16) : SYSTEM PM
046.GBE CLARKVILLE
047.GBE LAN SWITCH
048.GBE MAGNETICS
a t
079.DC/DC IMVP8(NCP81208)
080.DC/DC CPUCORE(NCP81382)
081.DC/DC VCCGFXCORE_I(NCP81381)
C
014.CPU(12/16) : CPU POWER

015.CPU(13/16) : CPU POWER
049.RJ45 CONNECTOR
050.PCIE MINI CARD SLOT
i c 082.DC/DC VCCSA(NCP81380)
if
083.DC/DC VCC1R0_SUS(TPS51367R)
016.CPU(14/16) : PCH POWER 051.MEDIA CARD CONTROLLER 084.BLANK
t
017.CPU(15/16) : GND 052.MEDIA CARD INTERFACE 085.DC/DC VCC1R2A(TPS51716)
r
018.CPU(16/16) : CFG/RESERVED 053.SMART CARD I/F 086.DC/DC VCC1R8_SUS(TPS62065)
019.XDP CONNECTOR 054.AUDIO ALC3245-GRT
e
087.BLANK
020.RTC BATTERY 055.AUDIO CONNECTOR 088.DC/DC VCC2R5A(TPS62065)
B
021.SPI FLASH
022.DDR4 SO DIMM
023.BLANK
y c
056.AUDIO JACK SENSE
057.AUDIO EXT MIC I/F
058.AUDIO SPEAKER
089.BLOCK DIAGRAM
090.BLANK
091.BLANK
B
t
024.BLANK 059.AUDIO BEEP 092.LOAD SW PCH SUS/TRACK POINT
f
025.BLANK 060.DOCKING CONNECTOR 093.LOAD SW LAN
026.BLANK 061.MEC1653(1/3)
a
094.LOAD SW CPU
027.BLANK 062.MEC1653(2/3)
s
095.LOAD SW B
028.DP SWITCH 063.MEC1653(3/3) 096.LOAD SW WWAN & WLAN
r
029.DP DEMUX 064.KEYBOARD/TRACK POINT 097.BLANK
030.BLANK 065.TOUCH PAD/NFC/FPR 098.PTH FOR SCREW HOLES
A
031.BLANK
032.BLANK
033.BLANK
034.BLANK
035.BLANK F o 066.BLANK
067.FAN CONNECTOR
068.G-SENSOR
069.TPM
099.BLANK
100.NEC LED BOARD
Security Classification
070.SMBUS SW/LPC DEBUG PORT Issued Date 2014/08/10

LC Future Center Secret Data
Deciphered Date 2015/8/10
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Title
TITLE PAGE
Size Document Number

Custom C
WOLVERINE3 UMA
Rev
0.1
A
Date: Thursday, August 20, 2015 Sheet 1 of 100

5 4 3 2 1
5 4 3 2 1
Date
EC Modify History
EC version File name
n ly D
n o
t io
a
C C
i c
r t if
B
ce B
f t y
s a
A
o r A
5
F 4 3
Issued Date 2014/08/10
2
Title
Custom
Date:
EC HISTORY

WOLVERINE3 UMA
Thursday, August 20, 2015
1
Sheet 2 of 100
Rev
0.1
5 4 3 2 1
VCCCPUIO
n ly D
o
2
RC1
24.9_0201_1%
?
SKYLAKE_ULT
U1A
1
Mini DP
DDIP1_0N E55 C47 EDP_TXN0
41 DDIP1_0N DDIP1_0P F55 DDI1_TXN[0] EDP_TXN[0] C46 EDP_TXP0 EDP_TXN0 38
n
41 DDIP1_0P DDIP1_1N E58 DDI1_TXP[0] EDP_TXP[0] D46 EDP_TXN1 EDP_TXP0 38
41 DDIP1_1N DDIP1_1P F58 DDI1_TXN[1] EDP_TXN[1] C45 EDP_TXP1 EDP_TXN1 38
41 DDIP1_1P DDIP1_2N F53 DDI1_TXP[1] EDP_TXP[1] A45 EDP_TXP1 38
41 DDIP1_2N DDIP1_2P G53 DDI1_TXN[2] EDP_TXN[2] B45
41 DDIP1_2P DDIP1_3N DDI1_TXP[2] EDP_TXP[2]
o
F56 A47
41 DDIP1_3N DDIP1_3P G56 DDI1_TXN[3] EDP_TXN[3] B47
41 DDIP1_3P DDI1_TXP[3] EDP_TXP[3]
i
C50 E45 EDP_AUXN
28 DDIP2_0N D50 DDI2_TXN[0] DDI EDP EDP_AUXN F45 EDP_AUXP EDP_AUXN 38
28 DDIP2_0P C52 DDI2_TXP[0] EDP_AUXP EDP_AUXP 38
t
28 DDIP2_1N D52 DDI2_TXN[1] B52
28 DDIP2_1P A50 DDI2_TXP[1] EDP_DISP_UTIL
28 DDIP2_2N B50 DDI2_TXN[2] G50 DDIP1_AUXN
28 DDIP2_2P D51 DDI2_TXP[2] DDI1_AUXN F50 DDIP1_AUXP DDIP1_AUXN 41
28 DDIP2_3N DDI2_TXN[3] DDI1_AUXP DDIP1_AUXP 41
a
C51 E48 DDIP2_AUXN
28 DDIP2_3P DDI2_TXP[3] DDI2_AUXN F48 DDIP2_AUXP DDIP2_AUXN 28
DDI2_AUXP G46 DDIP2_AUXP 28
C DISPLAY SIDEBANDS DDI3_AUXN F46 C
DDIP1_CTRLCLK L13 DDI3_AUXP
if c
41 DDIP1_CTRLCLK DDIP1_CTRLDATA L12 GPP_E18/DDPB_CTRLCLK L9 DDIP1_HPD
41 DDIP1_CTRLDATA GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 L7 DDIP2_HPD DDIP1_HPD 41
DDIP2_CTRLCLK N7 GPP_E14/DDPC_HPD1 L6 DDIP2_HPD 28
28 DDIP2_CTRLCLK DDIP2_CTRLDATA N8 GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2 N9
28 DDIP2_CTRLDATA GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 L10 EDP_HPD
N11 GPP_E17/EDP_HPD EDP_HPD 38
N12 GPP_E22/DDPD_CTRLCLK R12 VGA_BLON
GPP_E23/DDPD_CTRLDATA EDP_BKLTEN R11 PANEL_BKLT_CTRL VGA_BLON 61
EDP_COMP EDP_BKLTCTL PANEL_POWER_ON PANEL_BKLT_CTRL 38
i
E52 U13
EDP_RCOMP EDP_VDDEN PANEL_POWER_ON 72
1 OF 20
rt
SKYLAKE-U_BGA1356
REV = 1 ?
1
RC2 RC3 RC4 RC5
100K_0201_5% 100K_0201_5% 100K_0201_5% @ 100K_0201_5%
2
B
y c B
a f t
r s
A
F o Security Classification
Title
CPU(1/16) : DDI/EDP
Size Document Number R ev

A
WOLVERINE3 UMA
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
5 4 3 2 1
5 4 3 2 1
www.xinxunwei.com 400-800-9990 ?
SKYLAKE_ULT
U1B
22 M_A_DQ[63:0]
M_A_DQ0 AL71 AU53 -M_A_DDRCLK0_1866M
M_A_DQ1 AL68 DDR0_DQ[0] DDR0_CKN[0] AT53 M_A_DDRCLK0_1866M -M_A_DDRCLK0_1866M 22
M_A_DQ2 AN68 DDR0_DQ[1] DDR0_CKP[0] AU55 -M_A_DDRCLK1_1866M M_A_DDRCLK0_1866M 22
M_A_DQ3 AN69 DDR0_DQ[2] DDR0_CKN[1] AT55 M_A_DDRCLK1_1866M -M_A_DDRCLK1_1866M 22
y
M_A_DQ4 AL70 DDR0_DQ[3] DDR0_CKP[1] M_A_DDRCLK1_1866M 22
M_A_DQ5 AL69 DDR0_DQ[4] BA56 M_A_CKE0
M_A_DQ6 DDR0_DQ[5] DDR0_CKE[0] M_A_CKE1 M_A_CKE0 22
l
AN70 BB56
M_A_DQ7 AN71 DDR0_DQ[6] DDR0_CKE[1] AW56 M_A_CKE1 22
M_A_DQ8 AR70 DDR0_DQ[7] DDR0_CKE[2] AY56
D M_A_DQ9 AR68 DDR0_DQ[8] DDR0_CKE[3] D
M_A_DQ10 AU71 DDR0_DQ[9] AU45 -M_A_CS0
M_A_DQ11 DDR0_DQ[10] DDR0_CS#[0] -M_A_CS1 -M_A_CS0 22
n
AU68 AU43
M_A_DQ12 AR71 DDR0_DQ[11] DDR0_CS#[1] AT45 -M_A_ODT0 -M_A_CS1 22
M_A_DQ13 AR69 DDR0_DQ[12] DDR0_ODT[0] AT43 -M_A_ODT1 -M_A_ODT0 22
M_A_DQ14 AU70 DDR0_DQ[13] DDR0_ODT[1] -M_A_ODT1 22
M_A_DQ15 AU69 DDR0_DQ[14] BA51 M_A_A5 M_A_A0 M_A_A[0..13] 22
DDR0_DQ[15] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
o
M_A_DQ16 AF65 BB54 M_A_A9 M_A_A1
M_A_DQ17 AF64 DDR1_DQ[0]/DDR0_DQ[16] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] BA52 M_A_A6 M_A_A2
M_A_DQ18 AK65 DDR1_DQ[1]/DDR0_DQ[17] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] AY52 M_A_A8 M_A_A3
M_A_DQ19 AK64 DDR1_DQ[2]/DDR0_DQ[18] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] AW52 M_A_A7 M_A_A4
M_A_DQ20 AF66 DDR1_DQ[3]/DDR0_DQ[19] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AY55 M_A_BG0 M_A_A5
M_A_DQ21 AF67 DDR1_DQ[4]/DDR0_DQ[20] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] AW54 M_A_A12 M_A_BG0 22 M_A_A6
M_A_DQ22 AK67 DDR1_DQ[5]/DDR0_DQ[21] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] BA54 M_A_A11 M_A_A7
M_A_DQ23 AK66 DDR1_DQ[6]/DDR0_DQ[22] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] BA55 M_A_ACT_N M_A_A8
n
M_A_DQ24 AF70 DDR1_DQ[7]/DDR0_DQ[23] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# AY54 M_A_BG1 M_A_ACT_N 22 M_A_A9
M_A_DQ25 AF68 DDR1_DQ[8]/DDR0_DQ[24] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] M_A_BG1 22 M_A_A10
M_A_DQ26 AH71 DDR1_DQ[9]/DDR0_DQ[25] AU46 M_A_A13 M_A_A11
M_A_DQ27 AH68 DDR1_DQ[10]/DDR0_DQ[26] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] AU48 -M_A_CAS M_A_A12
M_A_DQ28 DDR1_DQ[11]/DDR0_DQ[27] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] -M_A_WE -M_A_CAS 22 M_A_A13
o
AF71 AT46
M_A_DQ29 AF69 DDR1_DQ[12]/DDR0_DQ[28] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] AU50 -M_A_RAS -M_A_WE 22
M_A_DQ30 AH70 DDR1_DQ[13]/DDR0_DQ[29] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] AU52 M_A_BS0 -M_A_RAS 22
DDR1_DQ[14]/DDR0_DQ[30] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] M_A_BS0 22
i
M_A_DQ31 AH69 AY51 M_A_A2
M_A_DQ32 BB65 DDR1_DQ[15]/DDR0_DQ[31] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] AT48 M_A_BS1
M_A_DQ33 AW65 DDR0_DQ[16]/DDR0_DQ[32] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] AT50 M_A_A10 M_A_BS1 22 -M_A_DQS0 -M_A_DQS[0..7] 22
t
M_A_DQ34 AW63 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] BB50 M_A_A1 -M_A_DQS1
M_A_DQ35 AY63 DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] AY50 M_A_A0 -M_A_DQS2
M_A_DQ36 BA65 DDR0_DQ[19]/DDR0_DQ[35] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] BA50 M_A_A3 -M_A_DQS3
M_A_DQ37 AY65 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[3] BB52 M_A_A4 -M_A_DQS4
DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[4]
a
M_A_DQ38 BA63 -M_A_DQS5
M_A_DQ39 BB63 DDR0_DQ[22]/DDR0_DQ[38] AM70 -M_A_DQS0 -M_A_DQS6
M_A_DQ40 BA61 DDR0_DQ[23]/DDR0_DQ[39] DDR0_DQSN[0] AM69 M_A_DQS0 -M_A_DQS7
C M_A_DQ41 AW61 DDR0_DQ[24]/DDR0_DQ[40] DDR0_DQSP[0] AT69 -M_A_DQS1 C
M_A_DQ42 BB59 DDR0_DQ[25]/DDR0_DQ[41] DDR0_DQSN[1] AT70 M_A_DQS1 M_A_DQS0 M_A_DQS[0..7] 22
c
M_A_DQ43 AW59 DDR0_DQ[26]/DDR0_DQ[42] DDR0_DQSP[1] AH66 -M_A_DQS2 M_A_DQS1
M_A_DQ44 BB61 DDR0_DQ[27]/DDR0_DQ[43] DDR1_DQSN[0]/DDR0_DQSN[2] AH65 M_A_DQS2 M_A_DQS2
M_A_DQ45 DDR0_DQ[28]/DDR0_DQ[44] DDR1_DQSP[0]/DDR0_DQSN[2] -M_A_DQS3 M_A_DQS3
i
AY61 AG69
M_A_DQ46 BA59 DDR0_DQ[29]/DDR0_DQ[45] DDR1_DQSN[1]/DDR0_DQSN[3] AG70 M_A_DQS3 M_A_DQS4
M_A_DQ47 AY59 DDR0_DQ[30]/DDR0_DQ[46] DDR1_DQSP[1]/DDR0_DQSN[3] BA64 -M_A_DQS4 M_A_DQS5
M_A_DQ48 AT66 DDR0_DQ[31]/DDR0_DQ[47] DDR0_DQSN[2]/DDR0_DQSN[4] AY64 M_A_DQS4 M_A_DQS6
if
M_A_DQ49 AU66 DDR1_DQ[16]/DDR0_DQ[48] DDR0_DQSP[2]/DDR0_DQSP[4] AY60 -M_A_DQS5 M_A_DQS7
M_A_DQ50 AP65 DDR1_DQ[17]/DDR0_DQ[49] DDR0_DQSN[3]/DDR0_DQSN[5] BA60 M_A_DQS5
M_A_DQ51 AN65 DDR1_DQ[18]/DDR0_DQ[50] DDR0_DQSP[3]/DDR0_DQSP[5] AR66 -M_A_DQS6
M_A_DQ52 AN66 DDR1_DQ[19]/DDR0_DQ[51] DDR1_DQSN[2]/DDR0_DQSN[6] AR65 M_A_DQS6
M_A_DQ53 AP66 DDR1_DQ[20]/DDR0_DQ[52] DDR1_DQSP[2]/DDR0_DQSP[6] AR61 -M_A_DQS7
t
M_A_DQ54 AT65 DDR1_DQ[21]/DDR0_DQ[53] DDR1_DQSN[3]/DDR0_DQSN[7] AR60 M_A_DQS7
M_A_DQ55 AU65 DDR1_DQ[22]/DDR0_DQ[54] DDR1_DQSP[3]/DDR0_DQSP[7]
M_A_DQ56 AT61 DDR1_DQ[23]/DDR0_DQ[55] AW50 M_A_ALERT_N
M_A_DQ57 DDR1_DQ[24]/DDR0_DQ[56] DDR0_ALERT# M_A_PARITY M_A_ALERT_N 22
r
AU61 AT52
M_A_DQ58 AP60 DDR1_DQ[25]/DDR0_DQ[57] DDR0_PAR M_A_PARITY 22
M_A_DQ59 AN60 DDR1_DQ[26]/DDR0_DQ[58] AY67
M_A_DQ60 AN61 DDR1_DQ[27]/DDR0_DQ[59] DDR_VREF_CA AY68 1 DDR4_VREF_CA_M3 22
M_A_DQ61 AP61 DDR1_DQ[28]/DDR0_DQ[60] DDR0_VREF_DQ BA67 @ TP17 Test_Point_40MIL
e
M_A_DQ62 AT60 DDR1_DQ[29]/DDR0_DQ[61] DDR1_VREF_DQ
M_A_DQ63 AU60 DDR1_DQ[30]/DDR0_DQ[62] AW67 DDR_PG_CTRL
DDR1_DQ[31]/DDR0_DQ[63] DDR CH - A DDR_VTT_CNTL
c
2 OF 20 VCC3M
SKYLAKE-U_BGA1356
REV = 1 ?
2
RC8
y
B 100K_0201_5% B
t
1
VCC1R2A
f
DDR_VTT_PG_CTRL
85 DDR_VTT_PG_CTRL
1
a
QC1 2
DTC015TMT2L_VMT3
s 3
2
r
RC9
10K_0201_5%
1
o
@
F
A A
Security Classification LC Future Center Secret Data Title

Issued Date 2014/08/10 Deciphered Date 2015/08/10 CPU(2/16) : DDR4
WOLVERINE3 UMA
5 4 3 2 1
5 4 3 2 1
?
SKYLAKE_ULT
U1C
AY39 AN45
AW39 DDR0_DQ[32]/DDR1_DQ[0] DDR1_CKN[0] AN46
AY37 DDR0_DQ[33]/DDR1_DQ[1] DDR1_CKN[1] AP45
y
AW37 DDR0_DQ[34]/DDR1_DQ[2] DDR1_CKP[0] AP46
BB39 DDR0_DQ[35]/DDR1_DQ[3] DDR1_CKP[1]
DDR0_DQ[36]/DDR1_DQ[4]
l
BA39 AN56
BA37 DDR0_DQ[37]/DDR1_DQ[5] DDR1_CKE[0] AP55
BB37 DDR0_DQ[38]/DDR1_DQ[6] DDR1_CKE[1] AN55
D AY35 DDR0_DQ[39]/DDR1_DQ[7] DDR1_CKE[2] AP53 D
AW35 DDR0_DQ[40]/DDR1_DQ[8] DDR1_CKE[3]
n
AY33 BB42
AW33 DDR0_DQ[42]/DDR1_DQ[10] DDR1_CS#[0] AY42
BB35 DDR0_DQ[43]/DDR1_DQ[11] DDR1_CS#[1] BA42
BA35 DDR0_DQ[44]/DDR1_DQ[12] DDR1_ODT[0] AW42
BA33 DDR0_DQ[45]/DDR1_DQ[13] DDR1_ODT[1]
o
BB33 AY48
AU40 DDR0_DQ[47]/DDR1_DQ[15] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] AP50
AT40 DDR1_DQ[32]/DDR1_DQ[16] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] BA48
AT37 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] BB48
AU37 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] AP48
AR40 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AP52
AP40 DDR1_DQ[36]/DDR1_DQ[20] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] AN50
AP37 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AN48
n
AR37 DDR1_DQ[38]/DDR1_DQ[22] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] AN53
AT33 DDR1_DQ[39]/DDR1_DQ[23] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# AN52
AU33 DDR1_DQ[40]/DDR1_DQ[24] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
AU30 DDR1_DQ[41]/DDR1_DQ[25] BA43
DDR1_DQ[42]/DDR1_DQ[26] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
o
AT30 AY43
AR33 DDR1_DQ[43]/DDR1_DQ[27] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] AY44
AP33 DDR1_DQ[44]/DDR1_DQ[28] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] AW44
DDR1_DQ[45]/DDR1_DQ[29] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]
i
AR30 BB44
AP30 DDR1_DQ[46]/DDR1_DQ[30] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] AY47
AY31 DDR1_DQ[47]/DDR1_DQ[31] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] BA44
t
AW31 DDR0_DQ[48]/DDR1_DQ[32] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] AW46
AY29 DDR0_DQ[49]/DDR1_DQ[33] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] AY46
AW29 DDR0_DQ[50]/DDR1_DQ[34] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] BA46
BB31 DDR0_DQ[51]/DDR1_DQ[35] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] BB46
DDR0_DQ[52]/DDR1_DQ[36] DDR1_MA[3]
a
BA31 BA47
BA29 DDR0_DQ[53]/DDR1_DQ[37] DDR1_MA[4]
BB29 DDR0_DQ[54]/DDR1_DQ[38] BA38
C AY27 DDR0_DQ[55]/DDR1_DQ[39] DDR0_DQSN[4]/DDR1_DQSN[0] AY38 C
AW27 DDR0_DQ[56]/DDR1_DQ[40] DDR0_DQSP[4]/DDR1_DQSP[0] AY34
c
AY25 DDR0_DQ[57]/DDR1_DQ[41] DDR0_DQSN[5]/DDR1_DQSN[1] BA34
AW25 DDR0_DQ[58]/DDR1_DQ[42] DDR0_DQSP[5]/DDR1_DQSP[1] AT38
DDR0_DQ[59]/DDR1_DQ[43] DDR1_DQSN[4]/DDR1_DQSN[2]
i
BB27 AR38
BA27 DDR0_DQ[60]/DDR1_DQ[44] DDR1_DQSP[4]/DDR1_DQSP[2] AT32
BA25 DDR0_DQ[61]/DDR1_DQ[45] DDR1_DQSN[5]/DDR1_DQSN[3] AR32
BB25 DDR0_DQ[62]/DDR1_DQ[46] DDR1_DQSP[5]/DDR1_DQSP[3] BA30
if
AU27 DDR0_DQ[63]/DDR1_DQ[47] DDR0_DQSN[6]/DDR1_DQSN[4] AY30 VCC1R2A
AT27 DDR1_DQ[48] DDR0_DQSP[6]/DDR1_DQSP[4] AY26
AT25 DDR1_DQ[49] DDR0_DQSN[7]/DDR1_DQSN[5] BA26
AU25 DDR1_DQ[50] DDR0_DQSP[7]/DDR1_DQSP[5] AR25
DDR1_DQ[51] DDR1_DQSN[6]
2
AP27 AR27
t
AN27 DDR1_DQ[52] DDR1_DQSP[6] AR22 RC10
AN25 DDR1_DQ[53] DDR1_DQSN[7] AR21 470_0201_5%
AP25 DDR1_DQ[54] DDR1_DQSP[7]
DDR1_DQ[55]
r
AT22 AN43
Place near to CPU
1
AU22 DDR1_DQ[56] DDR1_ALERT# AP43
AU21 DDR1_DQ[57] DDR1_PAR AT13 1 2
AT21 DDR1_DQ[58] DRAM_RESET# AR18 SM_RCOMP0 -DRAMRST 22
RC11 1 2
0.1U_0201_6.3V6K
121_0201_1% RC154 0_0201_5%
AN22 DDR1_DQ[59] DDR_RCOMP[0] AT18 SM_RCOMP1 RC12 1 2 80.6_0201_1%
e
DDR1_DQ[60] DDR_RCOMP[1] 2
AU18 SM_RCOMP2
CC76
AP22 RC13 1 2 100_0201_1%
AP21 DDR1_DQ[61] DDR_RCOMP[2]
AN21 DDR1_DQ[62] DDR CH - B @
DDR1_DQ[63] 1
c
3 OF 20
SKYLAKE-U_BGA1356
REV = 1 ?
y
B B
a f t
r s
A
Fo Security Classification
Deciphered Date
2015/08/10
Title
CPU(3/16) : DDR4

A
WOLVERINE3 UMA
5 4 3 2 1
5 4 3 2 1
y
Update description
For DCI debug

RC113 OP, RC148
n l short(XDP_TDO→ PCH_TDO)
D
o
RC138 OP, RC145 short(XDP_TMS→ PCH_TMS)
RC137 OP, RC147 short(XDP_TRST→ PCH_TRST)
RC142 OP, RC143 short(XDP_TCK0→ JTAGX)
RC139 OP, RC146 short(XDP_TDI→ PCH_TDI)
io n
C
a t C
i c
if
VCCSTG VCCST
VCC1R0_SUS VCC1R0_SUS
t
2
RC14 RC15
r
1K_0201_5% 1K_0201_5%
1
1
TP50 @ U1D ?
SKYLAKE_ULT RC139 RC138
Test_Point_40MIL 51_0201_5% 51_0201_5%
1 D63
e
62 PECI A54 CATERR#
1 2 -PROCHOT_R C65 PECI
9 -PROCHOT JTA G
2
RC16 510_0201_5% C63 PROCHOT#
A65 THERMTRIP#
c
SKTOCC# B61 XDP_TCK0
CPU MISC PROC_TCK XDP_TCK0 19
C55 D60 XDP_TDI
D55 BPM#[0] PROC_TDI A61 XDP_TDO XDP_TDI 19
B54 BPM#[1] PROC_TDO C60 XDP_TMS XDP_TDO 19
C56 BPM#[2] PROC_TMS B59 -XDP_TRST XDP_TMS 19
BPM#[3] PROC_TRST# -XDP_TRST 19
A6 B56 PCH_TCK
GPP_E3/CPU_GP0 PCH_JTAG_TCK PCH_TDI PCH_TCK 19
y
B A7 D59 B
BA5 GPP_E7/CPU_GP1 PCH_JTAG_TDI A56 PCH_TDO PCH_TDI 19
AY5 GPP_B3/CPU_GP2 PCH_JTAG_TDO C59 PCH_TMS PCH_TDO 19
t
GPP_B4/CPU_GP3 PCH_JTAG_TMS C61 PCH_TMS 19
1 2 AT16 PCH_TRST# A59 -PCH_TRST 19
RC17 49.9_0201_1%
RC18 1 2 49.9_0201_1% AU16 PROC_POPIRCOMP JTAGX JTAGX 19
PCH_OPIRCOMP
f
RC19 1 2 49.9_0201_1% H66
RC20 1 2 49.9_0201_1% H65 OPCE_RCOMP
OPC_RCOMP
1
RC21 RC137
4 OF 20 51_0201_5% 51_0201_5%
a
SKYLAKE-U_BGA1356
1
REV = 1 ? RC142
51_0201_5%
2
r s 2
Title
CPU(4/16) : MISC/JTAG

A
WOLVERINE3 UMA
5 4 3 2 1
5 4 3 2 1
y
VCC3_SUS
RC140 1K_0201_5%
VCC3_SUS
VCC3_SUS
n
VCC3B
l D
RC141 1K_0201_5%
VCC3B
RC27 4.7K_0201_5%
RC28 4.7K_0201_5%
RC29 8.2K_0201_5%
2
RC24 1K_0201_5%
RC25 499_0201_1%
RC26 499_0201_1%
o
THP1_SWG_SIT_EC004
2
Based on Intel information change RC140 to NA @ @
@
RC22 RC23 ?
1 SKYLAKE_ULT
1
8.2K_0201_5% 10K_0201_5% U1E
1
SPI - FLASH
SMBUS, SMLINK
SPI_CLK AV2
n
21,69 SPI_CLK SPI_MISO_IO1 AW3 SPI0_CLK R7 SMB_CLK
21,69 SPI_MISO_IO1 SPI_MOSI_IO0 AV3 SPI0_MISO GPP_C0/SMBCLK R8 SMB_DATA SMB_CLK 70
21,69 SPI_MOSI_IO0 SPI_IO2 AW2 SPI0_MOSI GPP_C1/SMBDATA R10 SMB_DATA 70
21 SPI_IO2 SPI_IO3 AU4 SPI0_IO2 GPP_C2/SMBALERT#
21 SPI_IO3 -SPI_CS0 SPI0_IO3 SML0_CLK
o
AU3 R9
21 -SPI_CS0 AU2 SPI0_CS0# GPP_C3/SML0CLK W2 SML0_DATA SML0_CLK 46
-SPI_CS2 AU1 SPI0_CS1# GPP_C4/SML0DATA W1 SML0_DATA 46
69 -SPI_CS2 SPI0_CS2# GPP_C5/SML0ALERT#
i
W3 EC_SCL2
SPI - TOUCH GPP_C6/SML1CLK V3 EC_SDA2 EC_SCL2 62
t
60 DOCKID[3:0] M2 GPP_C7/SML1DATA AM7 EC_SDA2 62
DOCKID1
DOCKID2 M3 GPP_D1/SPI1_CLK GPP_B23/SML1ALERT#/PCHHOT#
DOCKID3 J4 GPP_D2/SPI1_MISO
V1 GPP_D3/SPI1_MOSI
60 -DOCK_CAP_ID GPP_D21/SPI1_IO2
a
V2
DOCKID0 M1 GPP_D22/SPI1_IO3 LPC_AD[3:0] 61,70
LPC
GPP_D0/SPI1_CS# AY13 LPC_AD0
C 65 -NFC_DTCT GPP_A1/LAD0/ESPI_IO0 BA13 LPC_AD1 C
C LINK GPP_A2/LAD1/ESPI_IO1 BB13 LPC_AD2
c
CL_CLK_WLAN G3 GPP_A3/LAD2/ESPI_IO2 AY12 LPC_AD3
50 CL_CLK_WLAN CL_DATA_WLAN G2 CL_CLK GPP_A4/LAD3/ESPI_IO3 BA12
50 CL_DATA_WLAN -CL_RST_WLAN CL_DATA GPP_A5/LFRAME#/ESPI_CS# -LPC_FRAME 61,70
i
G1 BA11
50 -CL_RST_WLAN CL_RST# GPP_A14/SUS_STAT#/ESPI_RESET# -SUS_STAT 61,70
AW13 AW9 LPCCLK_EC_24M_R RC30 1 2 22_0201_5%
if
61 -KBRC GPP_A0/RCIN# GPP_A9/CLKOUT_LPC0/ESPI_CLK AY9 LPCCLK_DEBUG_24M_R 1 2 LPCCLK_EC_24M 61
RC31 0_0201_5%
AY11 GPP_A10/CLKOUT_LPC1 AW11 LPCCLK_DEBUG_24M 70
61,70 IRQSER GPP_A6/SERIRQ GPP_A8/CLKRUN# -CLKRUN 61,70
5 OF 20
Cut in R-short
RC151 1K_0201_5%
RC150 1K_0201_5%
t
SKYLAKE-U_BGA1356
REV = 1
?
2
r
@ @
1
Follow THP1_SWG_MSIT_EC011
e
Update HW Strap at SPI Signal Pin SPI0_IO3
y c B
a f t
r s
A
Deciphered Date
2015/08/10
Title
CPU(5/16) : LPC/SPI/SMBUS/C-LINK

A
WOLVERINE3 UMA
5 4 3 2 1
5 4 3 2 1
VCC3_SUS
n ly D
RC32 10K_0201_5%
o
RC33 10K_0201_5%
RC34 1K_0201_5%
?
SKYLAKE_ULT
U1F
2
LPSS ISH
n
@
AN8 P2
AP7 GPP_B15/GSPI0_CS# GPP_D9 P3
1
AP8 GPP_B16/GSPI0_CLK GPP_D10 P4
AR7 GPP_B17/GSPI0_MISO GPP_D11 P1
GPP_B18/GSPI0_MOSI GPP_D12
o
NFC_ON AM5 M4
65 NFC_ON NFC_INT AN7 GPP_B19/GSPI1_CS# GPP_D5/ISH_I2C0_SDA N3
65 NFC_INT GPP_B20/GSPI1_CLK GPP_D6/ISH_I2C0_SCL
i
AP5
AN5 GPP_B21/GSPI1_MISO N1
GPP_B22/GSPI1_MOSI GPP_D7/ISH_I2C1_SDA N2
t
AB1 GPP_D8/ISH_I2C1_SCL
AB2 GPP_C8/UART0_RXD AD11
W4 GPP_C9/UART0_TXD GPP_F10/I2C5_SDA/ISH_I2C2_SDA AD12 WWAN_CFG2 50
AB3 GPP_C10/UART0_RTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL WWAN_CFG3 50
GPP_C11/UART0_CTS#
a
AD1 U1
AD2 GPP_C20/UART2_RXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA U2
C -EC_SCI AD3 GPP_C21/UART2_TXD GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL U3 C
61 -EC_SCI -EC_WAKE GPP_C22/UART2_RTS# GPP_D15/ISH_UART0_RTS#
AD4 U4
if c
61 -EC_WAKE GPP_C23/UART2_CTS# GPP_D16/ISH_UART0_CTS#/SML0BALERT#
AC1
U7 GPP_C12/UART1_RXD/ISH_UART1_RXD AC2
U6 GPP_C16/I2C0_SDA GPP_C13/UART1_TXD/ISH_UART1_TXD AC3
GPP_C17/I2C0_SCL GPP_C14/UART1_RTS#/ISH_UART1_RTS# AB4
U8 GPP_C15/UART1_CTS#/ISH_UART1_CTS#
U9 GPP_C18/I2C1_SDA AY8
GPP_C19/I2C1_SCL GPP_A18/ISH_GP0 BA8
GPP_A19/ISH_GP1
i
AH9 BB7
AH10 GPP_F4/I2C2_SDA GPP_A20/ISH_GP2 BA7
Add Touch_EN for touch function
GPP_F5/I2C2_SCL GPP_A21/ISH_GP3 AY7 TOUCH_EN
rt
-MIC_HW_EN AH11 GPP_A22/ISH_GP4 AW7 TOUCH_EN
-INT_MIC_DTCT AH12 GPP_F6/I2C3_SDA GPP_A23/ISH_GP5 AP13
38 -INT_MIC_DTCT GPP_F7/I2C3_SCL GPP_A12/BM_BUSY#/ISH_GP6
AF11
50 WWAN_CFG0 AF12 GPP_F8/I2C4_SDA
50 WWAN_CFG1 GPP_F9/I2C4_SCL
2
RC35 6 OF 20
e
SKYLAKE-U_BGA1356
Cut in R-short 0_0201_5% REV = 1 ?
1
y c B
a f t
r s
A
Title
CPU(6/16) : LPSS/ISH

A
WOLVERINE3 UMA
5 4 3 2 1
5 4 3 2 1
n ly D
TEST PAD
BOTTOM SIDE
VCC3_SUS
RC36 1 2 1K_0201_5% RC37 1 @ 2 0_0603_5%

PLACE ON TOP SIDE
Check
VCC3_SUS
n o
2
VCC3_SUS
DO NOT MOVE AFTER FIX @ TP1 @ TP2
o
Test_Point_40MIL Test_Point_40MIL RC38
1 1 1K_0201_5% U1G ?
SKYLAKE_ULT
1
i
AUDIO
RC39 1 2 33_0201_5% HDA_SYNC_R BA22
t
54 HDA_SYNC HDA_BCLK_R HDA_SYNC/I2S0_SFRM
RC40 1 2 33_0201_5% AY22
54 HDA_BCLK HDA_SDO_R HDA_BLK/I2S0_SCLK
RC41 1 2 33_0201_5% BB22 SDIO/SDXC
54 HDA_SDO BA21 HDA_SDO/I2S0_TXD
54 HDA_SDIN0 AY21 HDA_SDI0/I2S0_RXD AB11
HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD
a
RC42 1 2 33_0201_5% -HDA_RST_R AW22 AB13
54 -HDA_RST J5 HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0 AB12
1 GPP_D23/I2S_MCLK GPP_G2/SD_DATA1
AY20 W12
C CC5 AW20 I2S1_SFRM GPP_G3/SD_DATA2 W11 C
47P_0201_25V8 I2S1_TXD GPP_G4/SD_DATA3 W10
if c
2 AK7 GPP_G5/SD_CD# W8
AK6 GPP_F1/I2S2_SFRM GPP_G6/SD_CLK W7
AK9 GPP_F0/I2S2_SCLK GPP_G7/SD_WP
AK10 GPP_F2/I2S2_TXD BA9
GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 BB9
GPP_A16/SD_1P8_SEL
H5 AB7 RC43 1 2 200_0201_1%
D7 GPP_D19/DMIC_CLK0 SD_RCOMP
GPP_D20/DMIC_DATA0
i
D8 AF13 -SC_DTCT
29 DDI_PRIORITY1 C8 GPP_D17/DMIC_CLK1 GPP_F23 -SC_DTCT 53
rt
28 DDI_PRIORITY2 GPP_D18/DMIC_DATA1
PCH_SPKR AW5
59 PCH_SPKR GPP_B14/SPKR
7 OF 20
SKYLAKE-U_BGA1356
REV = 1 ?
ce
y
B B
a f t
r s
A
Title
CPU(7/16) : AUDIO/SDXC

A
WOLVERINE3 UMA
5 4 3 2 1
5 4 3 2 1
?
SKYLAKE_ULT
U1H
y
SSIC / USB3
PCIE/USB3/SATA
l
H8
USB3_1_RXN G8 USB3P0_RXN 44
H13 USB3_1_RXP C13 USB3P0_RXP 44
D 51 PCIE0_RXN PCIE1_RXN/USB3_5_RXN USB3_1_TXN USB3P0_TXN 44 D
G13 D13
51 PCIE0_RXP PCIE1_RXP/USB3_5_RXP USB3_1_TXP USB3P0_TXP 44
B17
51 PCIE0_TXN PCIE1_TXN/USB3_5_TXN
n
A17 J6
51 PCIE0_TXP PCIE1_TXP/USB3_5_TXP USB3_2_RXN/SSIC_1_RXN H6 SSIC_RXN 50
G11 USB3_2_RXP/SSIC_1_RXP B13 SSIC_RXP 50
45 USB3P3_RXN_SYS F11 PCIE2_RXN/USB3_6_RXN USB3_2_TXN/SSIC_1_TXN A13 SSIC_TXN 50
45 USB3P3_RXP_SYS D16 PCIE2_RXP/USB3_6_RXP USB3_2_TXP/SSIC_1_TXP SSIC_TXP 50
45 USB3P3_TXN_SYS PCIE2_TXN/USB3_6_TXN
o
C16 J10
45 USB3P3_TXP_SYS PCIE2_TXP/USB3_6_TXP USB3_3_RXN/SSIC_2_RXN H10 USB3P1_RXN 44
H16 USB3_3_RXP/SSIC_2_RXP B15 USB3P1_RXP 44
50 PCIE2_RXN PCIE3_RXN USB3_3_TXN/SSIC_2_TXN USB3P1_TXN 44
G16 A15
50 PCIE2_RXP PCIE3_RXP USB3_3_TXP/SSIC_2_TXP USB3P1_TXP 44
D17
50 PCIE2_TXN C17 PCIE3_TXN E10
50 PCIE2_TXP PCIE3_TXP USB3_4_RXN F10 USB3P3_RXN_DOCK 60
G15 USB3_4_RXP C15 USB3P3_RXP_DOCK 60
n
46 PCIE3_RXN PCIE4_RXN USB3_4_TXN USB3P3_TXN_DOCK 60
F15 D15
46 PCIE3_RXP PCIE4_RXP USB3_4_TXP USB3P3_TXP_DOCK 60
B19
46 PCIE3_TXN A19 PCIE4_TXN AB9
46 PCIE3_TXP PCIE4_TXP USB2N_1 AB10 USBP0- 44
USB2P_1 USBP0+ 44
o
F16
50 PCIE1_RXN PCIE5_RXN
E16 AD6
50 PCIE1_RXP PCIE5_RXP USB2N_2 USBP1- 44
C19 AD7
50 PCIE1_TXN PCIE5_TXN USB2P_2 USBP1+ 44
i
D19
50 PCIE1_TXP PCIE5_TXP AH3
G18 USB2N_3 AJ3 USBP2- 50
t
F18 PCIE6_RXN USB2P_3 USBP2+ 50
D20 PCIE6_RXP AD9
C20 PCIE6_TXN USB2N_4 AD10 USBP3-_DOCK 60
PCIE6_TXP USB2P_4 USBP3+_DOCK 60
a
F20 AJ1 VCC3B VCC5B
43 PCIE4_L1_RXN E20 PCIE7_RXN/SATA0_RXN USB2N_5 AJ2 USBP4- 53
43 PCIE4_L1_RXP B21 PCIE7_RXP/SATA0_RXP USB2P_5 USBP4+ 53
USB2
C 43 PCIE4_L1_TXN A21 PCIE7_TXN/SATA0_TXN AF6 C
43 PCIE4_L1_TXP PCIE7_TXP/SATA0_TXP USB2N_6 AF7 USBP3-_SYS 45
if c
USB2P_6 USBP3+_SYS 45
RC136 10K_0201_5%
RC152 10K_0201_5%
G21
43 PCIE4_L0_SATA1_RXN F21 PCIE8_RXN/SATA1A_RXN AH1
43 PCIE4_L0_SATA1_RXP PCIE8_RXP/SATA1A_RXP USB2N_7 USBP6- 50
2
D21 AH2 VCC3_SUS VCC3_SUS
43 PCIE4_L0_SATA1_TXN C21 PCIE8_TXN/SATA1A_TXN USB2P_7 USBP6+ 50
43 PCIE4_L0_SATA1_TXP PCIE8_TXP/SATA1A_TXP AF8
E22 USB2N_8 AF9 USBP7- 38
PCIE9_RXN USB2P_8 USBP7+ 38
RC44 10K_0201_5%
RC45 10K_0201_5%
RC135 10K_0201_5%
RC47 10K_0201_5%
VCC3_SUS E23
TPDL issue
1
B23 PCIE9_RXP AG1
PCIE9_TXN USB2N_9 USBP8- 65
2
i
RC153 10K_0201_5%
A23 AG2
PCIE9_TXP USB2P_9 USBP8+ 65
2
F25 AH7 @
rt
E25 PCIE10_RXN USB2N_10 AH8 USBP9- 38
D23 PCIE10_RXP USB2P_10 USBP9+ 38
1
RC49 C23 PCIE10_TXN AB6 USBCOMP
100_0201_1% PCIE10_TXP USB2_COMP AG3 USB2_ID
1
1 2 PCIE_RCOMPN F5 USB2_ID AG4 USB2_VBUSSENSE

PCIE_RCOMPP E5 PCIE_RCOMPN USB2_VBUSSENSE
PCIE_RCOMPP A9 -USB_PORT0_OC0
-XDP_PRDY D56 GPP_E9/USB2_OC0# C9 -USB_PORT1_OC1 -USB_PORT0_OC0 44
e
19 -XDP_PRDY -XDP_PREQ D61 PROC_PRDY# GPP_E10/USB2_OC1# D9 -USB_PORT1_OC2 -USB_PORT1_OC1 44
19 -XDP_PREQ -TPM_IRQ BB11 PROC_PREQ# GPP_E11/USB2_OC2# B9
69 -TPM_IRQ GPP_A7/PIRQA# GPP_E12/USB2_OC3#
E28 J1
c
E27 PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 J2 SATA1_DEVSLP
D24 PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 J3 SATA1_DEVSLP 43
C24 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2
E30 PCIE11_TXP/SATA1B_TXP H2
F30 PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0 H3
A25 PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1 G4 -PE_DTCT 43
B25 PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2
PCIE12_TXP/SATA2_TXP
y
B H1 B
GPP_E8/SATALED# SATALED# 100
Follow THP1_SWG_SIT_EC007
t
8 OF 20
SKYLAKE-U_BGA1356
Change power rail from VCC3B to VCC3_SUS
RC156
RC157
RC48
REV = 1 ?
2
f 1K_0201_5%
1K_0201_5%
113_0201_1%
Add 1K_PD to follow Intel SPEC.
s a 1
o r
F
A A

Issued Date 2014/08/10 Deciphered Date 2015/08/10 010_CPU(8/16) : PCIE/USB/SATA
WOLVERINE3 UMA
5 4 3 2 1
5 4 3 2 1
n ly D
n o
o
SKYLAKE_ULT?
U1I
i
CSI-2
t
A36 C37
B36 CSI2_DN0 CSI2_CLKN0 D37
C38 CSI2_DP0 CSI2_CLKP0 C32
D38 CSI2_DN1 CSI2_CLKN1 D32
CSI2_DP1 CSI2_CLKP1
a
C36 C29
D36 CSI2_DN2 CSI2_CLKN2 D29
A38 CSI2_DP2 CSI2_CLKP2 B26
C B38 CSI2_DN3 CSI2_CLKN3 A26 C
CSI2_DP3 CSI2_CLKP3
c
C31 E13
D31 CSI2_DN4 CSI2_COMP B7
CSI2_DP4 GPP_D4/FLASHTRIG
i
C33
D33 CSI2_DN5
A31 CSI2_DP5 EMMC
B31 CSI2_DN6 AP2 PLANARID1 RC51 1 2 0_0201_5%
if
A33 CSI2_DP6 GPP_F13/EMMC_DATA0 AP1 PLANARID2 RC52 1 @ 2 0_0201_5%
B33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP3 PLANARID3 RC53 1 2 0_0201_5%
CSI2_DP7 GPP_F15/EMMC_DATA2 AN3
A29 GPP_F16/EMMC_DATA3 AN1
B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2
t
C28 CSI2_DP8 GPP_F18/EMMC_DATA5 AM4
D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1
A27 CSI2_DP9 GPP_F20/EMMC_DATA7
CSI2_DN10
r
B27 AM2
C27 CSI2_DP10 GPP_F21/EMMC_RCLK AM3
D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4 PLANARID0 RC54 1 2 0_0201_5%
CSI2_DP11 GPP_F12/EMMC_CMD
AT1
e
EMMC_RCOMP
9 OF 20
SKYLAKE-U_BGA1356 0100
REV = 1 ?
8/17 change PLANAR ID for SVT
y c B
a f t
r s
A
Title
CPU(9/16) : CSI-2/EMMC

A
WOLVERINE3 UMA
5 4 3 2 1
5 4 3 2 1
VCC1R0_SUS
n ly D
1
RC57
2.74K_0201_1% KDS 1ZZCAA24000CC0C
2
RC55
TXC 8Y24000011
2
?
SKYLAKE_ULT
1M_0201_5% EPSON Q22FA1280021300
n
U1J
Y1 24MHZ_10PF_8Y24000011
1
CLOCK SIGNALS
RC56 1 2 0_0201_5% XTAL24_OUT_R1 3

1 3
o
D42
51 -PCIE0_CLK_100M C42 CLKOUT_PCIE_N0 GND1 GND2
51 PCIE0_CLK_100M AR10 CLKOUT_PCIE_P0
51 -CLKREQ_PCIE0 GPP_B5/SRCCLKREQ0# 2 2
i
2 4
B42 F43 CC10 CC11
50 -PCIE1_CLK_100M A42 CLKOUT_PCIE_N1 CLKOUT_ITPXDP_N E43 12P_0201_25V8-J 12P_0201_25V8J
t
50 PCIE1_CLK_100M AT7 CLKOUT_PCIE_P1 CLKOUT_ITPXDP_P 1 1
50 -CLKREQ_PCIE1 GPP_B6/SRCCLKREQ1# BA17
GPD8/SUSCLK SUSCLK_32K 50,61
D41
50 -PCIE2_CLK_100M C41 CLKOUT_PCIE_N2 E37 XTAL24_IN
50 PCIE2_CLK_100M CLKOUT_PCIE_P2 XTAL24_IN
a
AT8 E35 XTAL24_OUT
50 -CLKREQ_PCIE2 GPP_B7/SRCCLKREQ2# XTAL24_OUT Change CC12, CC13 to 12pF
D40 E42 XCLK_BIASREF
C 46 -PCIE3_CLK_100M C40 CLKOUT_PCIE_N3 XCLK_BIASREF C
46 PCIE3_CLK_100M AT10 CLKOUT_PCIE_P3 AM18 RTCX1 CC12 1 2 12P_0201_25V8-J
c
46 -CLKREQ_PCIE3 GPP_B8/SRCCLKREQ3# RTCX1 AM20 RTCX2
B40 RTCX2
43 -PCIE4_CLK_100M CLKOUT_PCIE_N4
i
A40 AN18
43 PCIE4_CLK_100M CLKOUT_PCIE_P4 SRTCRST# -SRTCRST 20
2
AU8 AM16 Y2
43 -CLKREQ_PCIE4 GPP_B9/SRCCLKREQ4# RTCRST# -RTCRST 20 8/17 SVT change TXC to KDS vendor
RC58 32.768KHZ 9PF 20PPM 9H03280012
E40
if
CLKOUT_PCIE_N5 10M_0201_5%
E38
1
AU7 CLKOUT_PCIE_P5
1
GPP_B10/SRCCLKREQ5#
CC13 1 2 12P_0201_25V8-J
t
10 OF 20
SKYLAKE-U_BGA1356
REV = 1 ?
Change CC12, CC13 to 12pF
r
8/18 SVT follow Thorpe EC_013
Delete RC160 Y2
Package compatible Cannon Lake was withdrawn. KDS_SJ100069400
e
Instead, Skylake-U and Kaby Lake-U (2+2 & 2+3e)
are intended to be package and ball compatible
y c B
a f t
r s
A
Title
CPU(10/16) : CLOCK SIGNALS

A
WOLVERINE3 UMA
5 4 3 2 1
5 4 3 2 1
51,70
43,46,50,61,69,71
-PLTRST_NEAR
-PLTRST_FAR
1
RC59
1
2
33_0201_5%
2
VCC3M
4
VCC
UC3
NC
IN_A
1
3
-PLTRST
n ly D
o
RC60 33_0201_5% OUT_Y GND
1 1 TC7SG17FE_SON5
CC14 CC15
100P_0201_25V8J 100P_0201_25V8J RTCVCC VCC3M
2 2
2
RC62 RC64
1M_0201_5% @ 10K_0201_5%
1
?
SKYLAKE_ULT
U1K
i
SYSTEM POWER MANAGEMENT
AT11
GPP_B12/SLP_S0# AP15 -PCH_SLP_S0 94
t
GPD4/SLP_S3# -PCH_SLP_S3 17,62,71,72
AN10 BA16 -PCH_SLP_S4 17,62,71,85
B5 GPP_B13/PLTRST# GPD5/SLP_S4# AY16
19 -XDP_DBR SYS_RESET# GPD10/SLP_S5# -PCH_SLP_S5 17,71
AY17
62 -RSMRST RSMRST# AN15 -PCH_SLP_SUS 62
1 CPU_PWRGD A68 SLP_SUS# AW15
a
VCCST_PWRGD PROCPWRGD SLP_LAN# -PCH_SLP_LAN
Test_Point_40MIL TP41 @ B65 BB17
VCCST_PWRGD GPD9/SLP_WLAN# -PCH_SLP_WLAN 62
AN16
SYS_PWROK GPD6/SLP_A# -PCH_SLP_M 17,71
BPWRG RC65 1 2 0_0201_5% B6
72 BPWRG PCH_PWROK SYS_PWROK
C 79 CPUCORE_PWRGD RC66 1 2 0_0201_5% BA20 BA15 -PWRSW_EC 62 C
RC67 1 2 0_0201_5% DSWPWROK BB20 PCH_PWROK GPD3/PWRBTN# AY15
72 MPWRG
if c
DSW_PWROK GPD1/ACPRESENT AC_PRESENT 62
AU13 -BATLOW 63
-SUSWARN AR13 GPD0/BATLOW#
RC68 1 2 0_0201_5% SUSACK AP11 GPP_A13/SUSWARN#/SUSPWRDNACK
GPP_A15/SUSACK# AU11
BB15 GPP_A11/PME# AP16 -INTRUDER
50 -PCIE_WAKE WAKE# INTRUDER#
AM15
46 -LANWAKE GPD2/LAN_WAKE#
AW17 AM10
46 LANPHYPC GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# -EXT_PWR_GATE 16
AT15 AM11
1 2 GPD7/RSVD GPP_B2/VRALERT#
VCC3M
1000P_0201_25V7K
i
11 OF 20
2
RC69 1K_0201_5%
CC17
SKYLAKE-U_BGA1356
1 2 REV = 1 ? @
1
rt
RC70 4.7K_0201_5%
RC71 1 2 0_0201_5% 1 2
-INTRUDER_EC 63
3
DC1 RB521CS-30GT2RA_VMN2-2
e
S1
SPVR310100_4P
c
1
4
VCC3_SUS VCC1R0_SUS
2
y
B B
RC72 RC73
10K_0201_5% 10K_0201_5%
t
1
VCCST_PWRGD
f
1
QC2 D QC3 D
2 2
a
71 CPUCORE_ON G G
LSK3541G1ET2L 1N VMT3 LSK3541G1ET2L 1N VMT3
S S
3
r s
A
Title
CPU(11/16) : SYSTEM PM
A
Size Document Number Rev
WOLVERINE3 UMA
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
5 4 3 2 1
5 4 3 2 1
VCCSTG
n ly VCCSTG_CPU
D
o
VCCCPUCORE
VCCCPUCORE VCCCPUCORE RC74 1 2 0.001_0603_5%

1U_0201_6.3V6
1U_0201_6.3V6
1U_0201_6.3V6
1U_0201_6.3V6
1U_0201_6.3V6
1U_0201_6.3V6
1U_0201_6.3V6
1U_0201_6.3V6
n
?
SKYLAKE_ULT
Change from SD00001778T to SD000016Z0T for PLM issue
2 2 2 2 2 2 2 2 U1L
CC78
CC79
CC80
CC81
CC82
CC83
CC84
CC85
CPU POWER 1 OF 4
A30 G32
1 1 1 1 1 1 1 1 VCC_A30 VCC_G32
o
A34 G33
A39 VCC_A34 VCC_G33 G35
A44 VCC_A39 VCC_G35 G37
VCC_A44 VCC_G37
i
AK33 G38 VCCSTG_CPU VCCCPUCORE VCCST
AK35 VCC_AK33 VCC_G38 G40
AK37 VCC_AK35 VCC_G40 G42
t
AK38 VCC_AK37 VCC_G42 J30
AK40 VCC_AK38 VCC_J30 J33
VCC_AK40 VCC_J33
100_0201_1%
RC76 56_0201_5%
RC77 100_0201_1%
RC161 100_0201_1%
AL33 J37
AL37 VCC_AL33 VCC_J37 J40
VCC_AL37 VCC_J40
a
AL40 K33
VCC_AL40 VCC_K33
2
AM32 K35
AM33 VCC_AM32 VCC_K35 K37
C AM35 VCC_AM33 VCC_K37 K38 @ C
AM37 VCC_AM35 VCC_K38 K40
c
VCC_AM37 VCC_K40
RC75
AM38 K42
1
G30 VCC_AM38 VCC_K42 K43
VCC_G30 VCC_K43
i
K32 E32 VCC_SENSE
VCCG0 VCC_SENSE E33 VSS_SENSE VCC_SENSE 79
VSS_SENSE VSS_SENSE 79
AK32
if
VCCG1 B63 -SVID_ALERT_R 2 1
AB62 VIDALERT# A63 SVID_CLK -SVID_ALERT 79
RC79 220_0201_5%
1 P62 VCCOPC_AB62 VIDSCK D64 SVID_DATA SVID_CLK 79
V62 VCCOPC_P62 VIDSOUT SVID_DATA 79
Test_Point_40MIL TP23 @
VCCOPC_V62 G20
t
VCCSTG_G20
1
1 H63
Test_Point_40MIL TP37 @ VCC_OPC_1P8_H63 RC82
G61 100_0201_1% Follow THP1_SWG_MSIT_EC036
VCC_OPC_1P8_G61
r
Add pull high 100 ohm
1 AC63 Change RC77 to Non-ASM
2
Test_Point_40MIL TP20 @ 1 AE63 VCCOPC_SENSE
Test_Point_40MIL TP21 @ VSSOPC_SENSE
1 AE62
e
Test_Point_40MIL TP22 @ AG62 VCCEOPIO_AE62
VCCEOPIO_AG62
1 AL63
Test_Point_40MIL TP18 @ 1 AJ62 VCCEOPIO_SENSE
c
Test_Point_40MIL TP19 @ VSSEOPIO_SENSE
12 OF 20
SKYLAKE-U_BGA1356 ?
y
B B
a f t
r s
A
Title
CPU(12/16) : CPU POWER

A
WOLVERINE3 UMA
5 4 3 2 1
5 4 3 2 1
VCC1R2A VCC1R2A
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
y
1 1 1 1 1 1 1 2 2 2
CC18
CC19
CC20
CC21
CC22
CC23
CC24
CC25
CC26
CC27
VCCST VCCST_CPU
VCCGFXCORE_I
l
@ @ @ @ @ @
2 2 2 2 2 2 2 1 1 1
D D
RC85 1 2 0.001_0603_5%
n
1U_0201_6.3V6
1U_0201_6.3V6
1U_0201_6.3V6
1U_0201_6.3V6
1U_0201_6.3V6
1U_0201_6.3V6
1U_0201_6.3V6
1U_0201_6.3V6
2 2 2 2 2 2 2 2
CC88
CC89
CC90
CC91
CC92
CC94
CC86
CC87
Change from SD00001778T to SD000016Z0T for PLM issue
o
1 1 1 1 1 1 1 1
VCCGFXCORE_I K20 A22 K21 AM40 AL23

VCCST_CPU VCCSTG_CPU VCCST_CPU VCC1R2A VCC1R2A
VCCGFXCORE_I ?
SKYLAKE_ULT
U1M
CPU POWER 2 OF 4
n
N70
VCCGT_N70
10U_0603_6.3V6M
1U_0201_6.3V6
1U_0201_6.3V6
1U_0201_6.3V6
A48 N71
0.1U_0201_6.3V6K
A53 VCCGT_A48 VCCGT_N71 R63
VCCGT_A53 VCCGT_R63 2 2 2 1 2
CC28
CC29
CC30
CC31
CC32
A58 R64
VCCGT_A58 VCCGT_R64
o
A62 R65
A66 VCCGT_A62 VCCGT_R65 R66
AA63 VCCGT_A66 VCCGT_R66 R67 1 1 1 2 1
VCCGT_AA63 VCCGT_R67
i
AA64 R68
AA66 VCCGT_AA64 VCCGT_R68 R69
t
AA70 VCCGT_AA69 VCCGT_R71 T62
AA71 VCCGT_AA70 VCCGT_T62 U65
AC64 VCCGT_AA71 VCCGT_U65 U68
VCCGT_AC64 VCCGT_U68
a
AC65 U71
AC66 VCCGT_AC65 VCCGT_U71 W63
AC67 VCCGT_AC66 VCCGT_W63 W64
C AC68 VCCGT_AC67 VCCGT_W64 W65 C
c
VCCGT_AC71 VCCGT_W68 VCC1R2A VCCCPUIO
i
J43 W69
J45 VCCGT_J43 VCCGT_W69 W70 TP26
J46 VCCGT_J45 VCCGT_W70 W71 Test_Point_40MIL
J48 VCCGT_J46 VCCGT_W71 Y62
if
J50 VCCGT_J48 VCCGT_Y62 ?
U1N SKYLAKE_ULT
J52 VCCGT_J50 VCCSA
CPU POWER 3 OF 4
1
J53 VCCGT_J52 AK42
J55 VCCGT_J53 VCCGTX_AK42 AK43 @ AU23 AK28
J56 VCCGT_J55 VCCGTX_AK43 AK45 AU28 VDDQ_AU23 VCCIO_AK28 AK30
t
J58 VCCGT_J56 VCCGTX_AK45 AK46 AU35 VDDQ_AU28 VCCIO_AK30 AL30 VCCSA
J60 VCCGT_J58 VCCGTX_AK46 AK48 AU42 VDDQ_AU35 VCCIO_AL30 AL42
K48 VCCGT_J60 VCCGTX_AK48 AK50 BB23 VDDQ_AU42 VCCIO_AL42 AM28
VCCGT_K48 VCCGTX_AK50 VDDQ_BB23 VCCIO_AM28
1U_0201_6.3V6
1U_0201_6.3V6
1U_0201_6.3V6
1U_0201_6.3V6
K50 AK52 BB32 AM30
K52 VCCGT_K50 VCCGTX_AK52 AK53 BB41 VDDQ_BB32 VCCIO_AM30 AM42
VCCGT_K52 VCCGTX_AK53 VDDQ_BB41 VCCIO_AM42 2 2 2 2
CC93
CC95
CC96
CC97
K53 AK55 BB47
K55 VCCGT_K53 VCCGTX_AK55 AK56 BB51 VDDQ_BB47 AK23
K56 VCCGT_K55 VCCGTX_AK56 AK58 VCCSTG_CPU VCCST_CPU VDDQ_BB51 VCCSA_AK23 AK25
e
K58 VCCGT_K56 VCCGTX_AK58 AK60 VCCSA_AK25 G23 1 1 1 1
K60 VCCGT_K58 VCCGTX_AK60 AK70 AM40 VCCSA_G23 G25 VCCCPUIO VCCSA
L62 VCCGT_K60 VCCGTX_AK70 AL43 VDDQC VCCSA_G25 G27
L63 VCCGT_L62 VCCGTX_AL43 AL46 A18 VCCSA_G27 G28
c
L64 VCCGT_L63 VCCGTX_AL46 AL50 VCCST VCCSA_G28 J22
VCCGT_L64 VCCGTX_AL50 VCCSA_J22
2
L65 AL53 A22 J23
L66 VCCGT_L65 VCCGTX_AL53 AL56 VCCSTG_A22 VCCSA_J23 J27 RC86 RC87
L67 VCCGT_L66 VCCGTX_AL56 AL60 AL23 VCCSA_J27 K23
VCCGT_L67 VCCGTX_AL60 VCCPLL_OC VCCSA_K23 100_0201_1% 100_0201_1%
VCCGFXCORE_I L68 AM48 K25
L69 VCCGT_L68 VCCGTX_AM48 AM50 K20 VCCSA_K25 K27
1
L70 VCCGT_L69 VCCGTX_AM50 AM52 K21 VCCPLL_K20 VCCSA_K27 K28
VCCGT_L70 VCCGTX_AM52 VCCPLL_K21 VCCSA_K28
y
B L71 AM53 K30 B
M62 VCCGT_L71 VCCGTX_AM53 AM56 VCCSA_K30
VCCGT_M62 VCCGTX_AM56
2
N63 AM58 AM23
t
RC88 N64 VCCGT_N63 VCCGTX_AM58 AU58 VCCIO_SENSE AM22
N66 VCCGT_N64 VCCGTX_AU58 AU63 VSSIO_SENSE
100_0201_1% VCCGT_N66 VCCGTX_AU63
N67 BB57 H21 VSSSA_SENSE
VCCGT_N67 VCCGTX_BB57 VSSSA_SENSE VCCSA_SENSE VSSSA_SENSE 79
f
N69 BB66 H20
VCCSA_SENSE 79
1
VCCGT_N69 VCCGTX_BB66 VCCSA_SENSE

VCCGT_SENSE J70 AK62 1
79 VCCGT_SENSE VSSGT_SENSE J69 VCCGT_SENSE VCCGTX_SENSE AL61 1 14 OF 20
@ TP24 Test_Point_40MIL
79 VSSGT_SENSE VSSGT_SENSE VSSGTX_SENSE SKYLAKE-U_BGA1356
2
@ TP25 Test_Point_40MIL ?
a
RC90 RC91
13 OF 20
1
SKYLAKE-U_BGA1356 100_0201_1% 100_0201_1%

RC92 ?
s
100_0201_1%
1
2
o r
F
A A

Issued Date 2014/08/10 Deciphered Date 2015/08/10 CPU(13/16) : CPU POWER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom
WOLVERINE3 UMA 0.1

5 4 3 2 1
5 4 3 2 1
VCC3_SUS
VCC1R0_SUS VCCMPHY_GATE
y
VCC1R0_SUS VCCMPHY_GATE
2
R431
l
RC134 1 2
20K_0201_5%
D VCC3_SUS 0_0402_5% D
1
@
UC4
n
1 4
RC155 1 @ 2 0_0201_5% 7 VDD S1 5
13 -EXT_PWR_GATE ON S2
o
add RC155 for EXT_PWR_GATE Enable signal 3 D1 6
D2 GND
SLG59M1470VTR_FC-TDFN9_1P5X2
n
VCC1R0_SUS
VCC1R0_SUS
AB19
U1O
SKYLAKE_ULT
CPU POWER 4 OF 4
?
VCC3_SUS
VCC1R8_SUS
t io
a
AB20 VCCPRIM_1P0_AB19 AK15 VCC3_SUS
P18 VCCPRIM_1P0_AB20 VCCPGPPA AG15 VCC1R0_SUS
C VCCPRIM_1P0_P18 VCCPGPPB Y16 C
AF18 VCCPGPPC Y15
AF19 VCCPRIM_CORE_AF18 VCCPGPPD T16
VCCPRIM_CORE_AF19 VCCPGPPE
if c
VCCMPHY_GATE V20 AF16 2 2 2 RC95 1 2 0_0603_5%
V21 VCCPRIM_CORE_V20 VCCPGPPF AD15 VCC1R0_SUS
VCCPRIM_CORE_V21 VCCPGPPG CC33 CC34 CC35
AL1 V19 0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 1U_0201_6.3V6
DCPDSW_1P0 VCCPRIM_3P3_V19 1 1 1 2 2
RC97 1 2 0_0603_5% VCCMPHY_GATE K17 T1 CC36 CC37
L1 VCCMPHYAON_1P0_K17 VCCPRIM_1P0_T1 @ 22U_0603_6.3V6M @ 22U_0603_6.3V6M
VCCMPHYAON_1P0_L1
2
AA1 1 1
CC38 N15 VCCATS_1P8 RTCVCC VCC1R0_SUS
2 2 1 VCCMPHYGT_1P0_N15
1U_0402_6.3V6K N16 AK17
1
CC39 CC40 CC41 N17 VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3
i
@ 22U_0603_6.3V6M @ 22U_0603_6.3V6M P15 VCCMPHYGT_1P0_N17 AK19
1U_0201_6.3V6 VCCMPHYGT_1P0_P15 VCCRTC_AK19
1 1 @2 P16 BB14 RC96 1 2 0_0603_5%
VCCMPHYGT_1P0_P16 VCCRTC_BB14 2
VCC1R0_SUS NEAR K15
rt
K15 BB10 2 1 CC43
L15 VCCAMPHYPLL_1P0_K15 DCPRTC CC42 0.1U_0201_6.3V6K 1U_0201_6.3V6
VCCAMPHYPLL_1P0_L15 1 2 2
A14
VCCCLK1
RC98 1 2 0_0603_5% V15 CC44 CC45
VCCAPLL_1P0 K19 @ 22U_0603_6.3V6M @ 22U_0603_6.3V6M
VCC3M AB17 VCCCLK2 1 1
Y18 VCCPRIM_1P0_AB17 L21 VCC1R0_SUS
2 2 2 VCCPRIM_1P0_Y18 VCCCLK3
CC46 CC47 CC99 VCC3_SUS AD17 N20
@ 22U_0603_6.3V6M @ 22U_0603_6.3V6M 0.1U_0201_6.3V6-K AD18 VCCDSW_3P3_AD17 VCCCLK4
e
1 1 1 AJ17 VCCDSW_3P3_AD18 L19 RC99 1 2 0_0603_5%
VCCDSW_3P3_AJ17 VCCCLK5
AJ19 A10
VCCHDA VCCCLK6
2 2
AJ16 AN11
c
VCCSPI GPP_B0/CORE_VID0 AN13 CC48 CC49
Add Cap pad on VCC1R0_SUS_PLL AF20 GPP_B1/CORE_VID1 @ 22U_0603_6.3V6M @ 22U_0603_6.3V6M
AF21 VCCSRAM_1P0_AF20 1 1
T19 VCCSRAM_1P0_AF21
T20 VCCSRAM_1P0_T19
VCCSRAM_1P0_T20
AJ21
B VCCPRIM_3P3_AJ21 B
AK20
VCCPRIM_1P0_AK20
y
N18
VCCAPLLEBB
t
15 OF 20
SKYLAKE-U_BGA1356
REV = 1 ?
f
VCC1R0_SUS VCC1R0_SUS VCC3_SUS VCCMPHY_GATE VCCMPHY_GATE VCC3_SUS VCC1R8_SUS VCC1R0_SUS
a
2 2 2 2 2 2 2 2 2 2 2 2 2 2
CC50 CC51 CC52 CC53 CC54 CC55 CC56 CC57 CC58 CC59 CC60 CC61 CC62 CC63
1U_0201_6.3V6 1U_0201_6.3V6 1U_0201_6.3V6 1U_0201_6.3V6 1U_0201_6.3V6 47UF_0805_6.3V 1U_0201_6.3V6 1U_0201_6.3V6 1U_0201_6.3V6 1U_0201_6.3V6 1U_0201_6.3V6 1U_0201_6.3V6 1U_0201_6.3V6 1U_0201_6.3V6
1 1 1 1 1 1 1 1 1 1 1 1 1 1
NEAR AB19 NEAR K17 NEAR AF18 NEAR AJ19 NEAR N15@ NEAR N15 NEAR AF20 NEAR N18 @ NEAR AG15@ NEAR Y16@ NEAR T16 NEAR V19 NEAR AA1 NEAR A10
s
@ @ @ @ @ @
r
VCC3_SUS VCC1R8_SUS VCC1R0_SUS VCC1R0_SUS
o
2 2 2 2
CC64 CC65 CC66 CC67
47UF_0805_6.3V 47UF_0805_6.3V 47UF_0805_6.3V 47UF_0805_6.3V
1 1 1 1
A A
5
F 4 3
Deciphered Date
2
2012/12/01
Title
Custom
Date:
CPU(6/16) : PCH POWER

WOLVERINE3 UMA
1
Sheet 16 of 100
Rev
0.1
5 4 3 2 1
U1P ?
SKYLAKE_ULT
U1Q ?SKYLAKE_ULT
GND 1 OF 3
GND 2 OF 3
A5 AL65
APS/PETS interface
y
A67 VSS_A5 VSS_AL65 AL66 AT63 BA49
A70 VSS_A67 VSS_AL66 AM13 AT68 VSS_AT63 VSS_BA49 BA53
VSS_A70 VSS_AM13 VSS_AT68 VSS_BA53
l
AA2 AM21 AT71 BA57
AA4 VSS_AA2 VSS_AM21 AM25 AU10 VSS_AT71 VSS_BA57 BA6 Test_Point_40MIL TP49 @ 1 J41
AA65 VSS_AA4 VSS_AM25 AM27 AU15 VSS_AU10 VSS_BA6 BA62 VCC3_SUS VCC3M FCI_10051922-1810ELF
D AA68 VSS_AA65 VSS_AM27 AM43 AU20 VSS_AU15 VSS_BA62 BA66 D
VSS_AA68 VSS_AM43 VSS_AU20 VSS_BA66 Test_Point_40MIL TP46 @ 1
AB15 AM45 AU32 BA71 18 20
VSS_AB15 VSS_AM45 VSS_AU32 VSS_BA71 Test_Point_40MIL TP45 @ NC1 PEG2
n
AB16 AM46 AU38 BB18 1 17 19
VSS_AB16 VSS_AM46 VSS_AU38 VSS_BB18 16 NC2 PEG1
AB18 AM55 AV1 BB26
AB21 VSS_AB18 VSS_AM55 AM60 AV68 VSS_AV1 VSS_BB26 BB30 15 NC3
VSS_AB21 VSS_AM60 VSS_AV68 VSS_BB30 94 -PCH_SLP_S0 14 SLP_S0#
AB8 AM61 AV69 BB34
AD13 VSS_AB8 VSS_AM61 AM68 AV70 VSS_AV69 VSS_BB34 BB38 13 GND1
VSS_AD13 VSS_AM68 VSS_AV70 VSS_BB38 19 -XDP_DBR SYS_RESET#
o
AD16 AM71 AV71 BB43 12
AD19 VSS_AD16 VSS_AM71 AM8 AW10 VSS_AV71 VSS_BB43 BB55 11 GND2
VSS_AD19 VSS_AM8 VSS_AW10 VSS_BB55 38,60,70 -PWRSWITCH 10 PWRBTN#
AD20 AN20 AW12 BB6
AD21 VSS_AD20 VSS_AN20 AN23 AW14 VSS_AW12 VSS_BB6 BB60 9 GND3
VSS_AD21 VSS_AN23 VSS_AW14 VSS_BB60 20 -RTCRST 8 RTCRST#
AD62 AN28 AW16 BB64 1
AD8 VSS_AD62 VSS_AN28 AN30 AW18 VSS_AW16 VSS_BB64 BB67 1 7 GND4
AE64 VSS_AD8 VSS_AN30 AN32 AW21 VSS_AW18 VSS_BB67 BB70 Test_Point_40MIL TP47 @ 6 +V3.3DS
AE65 VSS_AE64 VSS_AN32 AN33 AW23 VSS_AW21 VSS_BB70 C1
13 -PCH_SLP_M 5 SLP_A# CONNECTOR Planar Only BOX
n
VSS_AE65 VSS_AN33 VSS_AW23 VSS_C1 13,85 -PCH_SLP_S4 4 SLP_S4#
AE66 AN35 AW26 C25
VSS_AE66 VSS_AN35 VSS_AW26 VSS_C25 13 -PCH_SLP_S5 3 SLP_S5#
AE67 AN37 AW28 C5
AE68 VSS_AE67 VSS_AN37 AN38 AW30 VSS_AW28 VSS_C5 D10 2 VccDSW3_3
AE69 VSS_AE68 VSS_AN38 AN40 AW32 VSS_AW30 VSS_D10 D11
13 -PCH_SLP_S3 1 SLP_S3# J41 ASM NO ASM
VSS_AE69 VSS_AN40 VSS_AW32 VSS_D11 VccSus3_3
o
AF1 AN42 AW34 D14 1
AF10 VSS_AF1 VSS_AN42 AN58 AW36 VSS_AW34 VSS_D14 D18 Test_Point_40MIL TP42 @ 1
AF15 VSS_AF10 VSS_AN58 AN63 AW38 VSS_AW36 VSS_D18 D22 Test_Point_40MIL TP43 @ 1
VSS_AF15 VSS_AN63 VSS_AW38 VSS_D22
i
AF17 AP10 D25 Test_Point_40MIL TP48 @
AF2 VSS_AF17 VSS_AP10 AP18 AW41 VSS_D25 D26
AF4 VSS_AF2 VSS_AP18 AP20 AW43 VSS_AW41 VSS_D26 D30
t
AF63 VSS_AF4 VSS_AP20 AP23 AW45 VSS_AW43 VSS_D30 D34
AG16 VSS_AF63 VSS_AP23 AP28 AW47 VSS_AW45 VSS_D34 D39
AG17 VSS_AG16 VSS_AP28 AP32 AW49 VSS_AW47 VSS_D39 D44
VSS_AG18 VSS_AP35 VSS_AW51 VSS_D45
a
AG19 AP38 AW53 D47 ?
SKYLAKE_ULT
U1R
C AG71 VSS_AG21 VSS_AP58 AP63 AW6 VSS_AW57 VSS_D53 D58 C
GND 3 OF 3
AH13 VSS_AG71 VSS_AP63 AP68 AW60 VSS_AW6 VSS_D58 D6
c
VSS_AH13 VSS_AP68 VSS_AW60 VSS_D6 F8 L18
AH6 AP70 AW62 D62 VSS_F8 VSS_L18
VSS_AH6 VSS_AP70 VSS_AW62 VSS_D62 G10 L2
AH63 AR11 AW64 D66 VSS_G10 VSS_L2
VSS_AH63 VSS_AR11 VSS_AW64 VSS_D66 G22 L20
i
AH64 AR15 AW66 D69 VSS_G22 VSS_L20
VSS_AH64 VSS_AR15 VSS_AW66 VSS_D69 G43 L4
AH67 AR16 AW8 E11 VSS_G43 VSS_L4
VSS_AH67 VSS_AR16 VSS_AW8 VSS_E11 G45 L8
AJ15 AR20 AY66 E15 VSS_G45 VSS_L8
VSS_AJ15 VSS_AR20 VSS_AY66 VSS_E15 G48 N10
AJ18 AR23 B10 E18
if
G5 VSS_G48 VSS_N10 N13
AJ20 VSS_AJ18 VSS_AR23 AR28 B14 VSS_B10 VSS_E18 E21
AJ4 VSS_AJ20 VSS_AR28 AR35 B18 VSS_B14 VSS_E21 E46
AK11 VSS_AJ4 VSS_AR35 AR42 B22 VSS_B18 VSS_E46 E50
AK16 VSS_AK11 VSS_AR42 AR43 B30 VSS_B22 VSS_E50 E53
t
G63 VSS_G60 VSS_N68 P17
G66 VSS_G63 VSS_P17 P19
H15 VSS_G66 VSS_P19 P20
VSS_AK27 VSS_AR5 VSS_B48 VSS_E71
r
AK63 AR50 B53 F1 VSS_H15 VSS_P20
VSS_AK63 VSS_AR50 VSS_B53 VSS_F1 H18 P21
AK68 AR52 B58 F13 VSS_H18 VSS_P21
VSS_AK68 VSS_AR52 VSS_B58 VSS_F13 H71 R13
AK69 AR53 B62 F2 VSS_H71 VSS_R13
VSS_AK69 VSS_AR53 VSS_B62 VSS_F2 J11 R6
AK8 AR55 B66 F22 VSS_J11 VSS_R6
VSS_AK8 VSS_AR55 VSS_B66 VSS_F22 J13 T15
AL2 AR58 B71 F23 VSS_J13 VSS_T15
e
VSS_AL2 VSS_AR58 VSS_B71 VSS_F23 J25 T17
AL28 AR63 BA1 F27 VSS_J25 VSS_T17
VSS_AL28 VSS_AR63 VSS_BA1 VSS_F27 J28 T18
AL32 AR8 BA10 F28 VSS_J28 VSS_T18
VSS_AL32 VSS_AR8 VSS_BA10 VSS_F28 J32 T2
AL35 AT2 BA14 F32 VSS_J32 VSS_T2
VSS_AL35 VSS_AT2 VSS_BA14 VSS_F32 J35 T21
AL38 AT20 BA18 F33 VSS_J35 VSS_T21
J38 T4
c
AL4 VSS_AL38 VSS_AT20 AT23 BA2 VSS_BA18 VSS_F33 F35
J42 VSS_J38 VSS_T4 U10
J8 VSS_J42 VSS_U10 U63
K16 VSS_J8 VSS_U63 U64
K18 VSS_K16 VSS_U64 U66
AL58 VSS_AL55 VSS_AT42 AT56 F68 VSS_BA36 VSS_F40 F42
AL64 VSS_AL58 VSS_AT56 AT58 BA45 VSS_F68 VSS_F42 BA41
VSS_AL64 VSS_AT58 VSS_BA45 VSS_BA41
y
B VSS_K63 VSS_U70 B
K64 V16
K65 VSS_K64 VSS_V16 V17
17 OF 20 K66 VSS_K65 VSS_V17 V18
t
16 OF 20
SKYLAKE-U_BGA1356 K67 VSS_K66 VSS_V18 W13
? K68 VSS_K67 VSS_W13 W6
SKYLAKE-U_BGA1356
REV = 1 ? K70 VSS_K68 VSS_W6 W9
f
K71 VSS_K70 VSS_W9 Y17
L11 VSS_K71 VSS_Y17 Y19
L16 VSS_L11 VSS_Y19 Y20
L17 VSS_L16 VSS_Y20 Y21
VSS_L17 VSS_Y21
s a 18 OF 20
SKYLAKE-U_BGA1356
REV = 1 ?
o r
F
A A

CPU(15/16) : GND
Issued Date 2014/08/10 Deciphered Date 2015/08/10
WOLVERINE3 UMA
5 4 3 2 1
5 4 3 2 1
TABLE 8/18 SVT follow Thorpe EC_013
Delete VCC1R8_SUS power rail
Package compatible Cannon Lake was withdrawn.
CFG0 : Stall Reset Sequence Instead, Skylake-U and Kaby Lake-U (2+2 & 2+3e)
after PCU PLL Lock until de-asserted
y
are intended to be package and ball compatible
1 : No Stall
0 : Stall
l
SKYLAKE_ULT
?
U1S U1T ?
SKYLAKE_ULT
D D
CFG4 : eDP Enable RESERVED SIGNALS-1 SPARE
1 : Disabled E68 BB68 AW69 F6
n
B67 CFG[0] RSVD_TP_BB68 BB69 AW68 RSVD_AW69 RSVD_F6 E3
0 : Enabled D65 CFG[1] RSVD_TP_BB69 AU56 RSVD_AW68 RSVD_E3 C11
CFG3 D67 CFG[2] AK13 AW48 RSVD_AU56 RSVD_C11 B11
19 CFG3 E70 CFG[3] RSVD_TP_AK13 AK12 C7 RSVD_AW48 RSVD_B11 A11
C68 CFG[4] RSVD_TP_AK12 U12 RSVD_C7 RSVD_A11 D12
CFG9 : SVID Bus Communication D68 CFG[5] BB2 U11 RSVD_U12 RSVD_D12 C12
o
1 : Enabled C67 CFG[6]
CFG[7]
RSVD_BB2
RSVD_BA3
BA3 H11 RSVD_U11
RSVD_H11
RSVD_C12
RSVD_F52
F52
2
0 : Disabled F71
RC101 RC100 G69 CFG[8]
F70 CFG[9] AU5
1K_0201_5% 1K_0201_5% CFG[10] TP5 20 OF 20
G68 AT5
H70 CFG[11] TP6 SKYLAKE-U_BGA1356
REV = 1 ?
1
CFG[12]
2
G71
@ H69 CFG[13] D5
RC102
G70 CFG[14] RSVD_D5 D4
1K_0201_5%
n
CFG[15] RSVD_D4 B2
E63 RSVD_B2 C2
1
F63 CFG[16] RSVD_C2
@ CFG[17] B3
E66 RSVD_B3 A3
F66 CFG[18] RSVD_A3
o
CFG[19] AW1
1 2 CFG_RCOMP E60 RSVD_AW1
RC103 49.9_0201_1% CFG_RCOMP E1
RSVD_E1
i
E8 E2
19 ITP_PMODE ITP_PMODE RSVD_E2
AY2 BA4
AY1 RSVD_AY2 RSVD_BA4 BB4
t
RSVD_AY1 RSVD_BB4
D1 A4
D3 RSVD_D1 RSVD_A4 C4
RSVD_D3 RSVD_C4
K46 BB5
a
K45 RSVD_K46 TP4
RSVD_K45 A69
RSVD_A69 Cut in R-short
C AL25 B69 C
AL27 RSVD_AL25 RSVD_B69
RSVD_AL27 AY3 RC104 1 2 0_0201_5%
RSVD_AY3
if c
C71
B70 RSVD_C71 D71
RSVD_B70 RSVD_D71 C70
F60 RSVD_C70
RSVD_F60 C54
A52 RSVD_C54 D54 VCCST
RSVD_A52 RSVD_D54
BA70 AY4
BA68 RSVD_TP_BA70 TP1 BB3
RSVD_TP_BA68 TP2
J71 AY71 RC107 1 2 0_0201_5%
RSVD_J71 VSS_AY71
i
J68 AR56 1
RSVD_J68 ZVM# @ TP27 Test_Point_40MIL
F65 AW71
G65 VSS_F65 RSVD_AW71 AW70
rt
VSS_G65 RSVD_AW70
F61 AP56 1
E61 RSVD_F61 MSM# C64 1 @ 2
@ TP28 Test_Point_40MIL
RSVD_E61 PROC_SELECT# RC110 100K_0201_5%
19 OF 20
Follow Intel Skylake EDS, change RC110 to NO-ASM
SKYLAKE-U_BGA1356
REV = 1 ?
ce B
f t y
s a
A
o r A
5
F 4 3
2
Title
Custom
Date:
CPU(16/16) : CFG/RESERVED

WOLVERINE3 UMA
1
Sheet 18 of 100
Rev
0.1
5 4 3 2 1
RC143 1 2 0_0201_5% XDP_TCK0
6 JTAGX
@
PCH_TCK RC144 1 2 0_0201_5% XDP_TCK1
@
PCH_TMS XDP_TMS
y
RC145 1 2 0_0201_5%
@
PCH_TDI RC146 1 2 0_0201_5% XDP_TDI
l
@
RC147 1 2 0_0201_5% -XDP_TRST
D D
6 -PCH_TRST
@
PCH_TDO RC148 1 2 0_0201_5% XDP_TDO
n
@ VCC1R0_SUS
VCC1R0_SUS
o
VCC1R0_SUS VCC3B VCCSTG VCC1R0_SUS VCC1R0_SUS
51_0201_5%
2
1
2
RC116 CC68
2
1.5K_0201_1% RC111 RC112 0.1U_0201_6.3V6K CC77
n
1K_0201_5% 51_0201_5% 1 0.1U_0201_6.3V6K
1
RC113
1
1
MOLEX_52435-2671 MOLEX_52435-2671
o
XDP_TCK0 26 PCH_TCK 26
6 XDP_TCK0 25 26 28 6 PCH_TCK 25 26 28
XDP_TCK1 24 25 GND2 27 RC149 1 2 0_0201_5% 24 25 GND2 27
XDP_TMS 24 GND1 PCH_TMS 24 GND1
i
23 23
6 XDP_TMS XDP_TDI 22 23 6 PCH_TMS PCH_TDI 22 23
6 XDP_TDI 6 PCH_TDI @
-XDP_TRST 21 22 21 22
6 -XDP_TRST XDP_TDO 20 21 PCH_TDO 20 21
t
6 XDP_TDO 20 6 PCH_TDO 20
19 19
-XDP_DBR 18 19 -XDP_DBR 18 19
13,17 -XDP_DBR 17 18 CPUCORE_PWRGD 18
RC117 1 2 1K_0201_5% 17
18 ITP_PMODE 16 17 79 CPUCORE_PWRGD 16 17
15 16 15 16
a
14 15 14 15
13 14 13 14
C 12 13 12 13 C
11 12 11 12
-RSMRST RC118 1 2 1K_0201_5% 10 11 -RSMRST RC119 1 2 1K_0201_5% 10 11
62 -RSMRST 10 10
c
9 9
CFG3 8 9 8 9
18 CFG3 7 8 7 8
6 7 6 7
i
5 6 5 6
4 5 4 5
3 4 3 4
-XDP_PRDY 2 3 2 3
if
10 -XDP_PRDY -XDP_PREQ 1 2 1 2
10 -XDP_PREQ 1 1
J8 J9
SIGNAL
TABLE: CPU ITP DEBUG PORT
REF DES Planar only BOX
e r t TABLE: PCH ITP DEBUG port
SIGNAL
TDO
REF DES
RC114
Planar only
ASM
BOX
ASM
c
TDO RC109 ASM ASM TMS RC116 ASM ASM
B TRST# RC113 ASM ASM TDI RC115 ASM ASM B
y
DBRST# RC110 ASM ASM TCK RC117 ASM ASM
t
RESET# RC111 ASM ASM CPUCORE_PWRGD RC118 ASM ASM
f
-RSMRST RC119 ASM ASM
PWRGD RC112 ASM ASM
CONNECTOR J9 ASM NO ASM
a
CONNECTOR J8 ASM NO ASM
NOTE: APPLY EACH LOGIC ACCORDING TO CONFIGURATION IN SDV
s
NOTE: APPLY EACH LOGIC ACCORDING TO CONFIGURATION IN SDV
o r A
5
F 4 3
Issued Date
2
Title
Date:
XDP CONNECTOR

Custom WOLVERINE3 UMA
1
Sheet 19 of 100
Rev
0.1
5 4 3 2 1
Update Assembly Option of RTCVCC External Circuit
VCC3SW VCC3SW RTCVCC
n ly D
2
1
DC5
RC158 RB520CS-30GT2RA_VMN2-2
1
@ 1.5K_0201_1%
2
n
1
1
RC159 CC69
2
@ 47K_0402_1% 1U_0402_10V6K
DC2
RB520CS-30GT2RA_VMN2-2 2
o
2
1
DC3
i
2 1
RB520CS-30GT2RA_VMN2-2
t
2
RC122
1K_0201_5%
a
1
C C
if c
J12 RC123
1
1 2 1 2 -RTCRST
2 -RTCRST 12,17
3 20K_0201_5%
GND1 4
GND2
i
TE_2041180-2
1
CC70
rt
1U_0402_10V6K
2
e
RC124
1 2 -SRTCRST
-SRTCRST 12
20K_0201_5%
c
1
CC71
1U_0402_10V6K
2
B B
f t y
s a
A
o r A
5
F 4 3
2
Title
Custom
Date:
RTC BATTERY

WOLVERINE3 UMA
1
Sheet 20 of 100
Rev
0.1
5 4 3 2 1
VCC3_SUS
Delete VCC3_SUS_SPI power net
n ly D
o
2
DC4
1
n
2
o
0.1u_0201_10V6K
3.3K_0201_5%
3.3K_0201_5%
RC125 Update HW Strap at SPI Signal Pin SPI0_IO3
i
10K_0201_5%
1
2
2
t
@
CC72
0.1u_0201_10V6K
2
1
1
a
RC126
RC127
CC73
UC5
-SPI_CS0 RC128 1 2 33_0201_5% -SPI_CS0_R
C 7 -SPI_CS0 SPI_CLK 1 2 SPI_CLK_R 8 1 C
RC129 33_0201_5%
7 SPI_CLK SPI_MOSI_IO0 1 2 SPI_MOSI_IO0_R VCC /CS SPI_IO2_R 1 2 33_0201_5% SPI_IO2
RC130 33_0201_5% RC131
c
7,69 SPI_MOSI_IO0 SPI_MISO_IO1 1 2 SPI_MISO_IO1_R 7 2 SPI_IO3_R 1 2 33_0201_5% SPI_IO3 SPI_IO2 7
RC132 33_0201_5% RC133
7,69 SPI_MISO_IO1 /HOLD/RESET DO SPI_IO3 7
i
6 3
GND_2
CLK /WP
5 4
DI GND_1
if
9
Keyboard feeling not good issue
Change UC5 to SA00007JG00
W25Q128FVPIQ_WSON8_6X5
e r t
c
TABLE
SF100 PIN HEADER INTERFACE (TOP VIEW)
y
B 1 VCC D12.1 GND GND 2 B
3 CS# R322.2 R681.2 CLK 4
5 MISO R694.2 R674.2 MOSI 6
t
7 (KEY) N/A N/A (RESET) 8
f
U49 SPI ROM
vPro/non-vPro Model (16MB)
s a WINBOND
MACRONIX
W25Q128FVSIQ
MX25L12875FM2I-10G
r
NA NA
Update SPI Flash Source List
Deciphered Date
2015/08/10
Title
SPI FLASH

A
WOLVERINE3 UMA
5 4 3 2 1
5 4 3 2 1
VCC1R2A VCC1R2A_DIMN
RJ2
2 1
2 1 Follow THP1_SWG_MSIT_EC017
@ JUMP_43X118 Add Decoupling Capacitors for System Memory
VCC2R5A
Follow RF suggested
y
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
VCC0R6B
CD48 0.1U_0201_6.3V6-K
CD49 0.1U_0201_6.3V6-K
0.1U_0201_6.3V6K
CD47 0.1U_0201_6.3V6-K
CD51 10U_0402_6.3V6-M
CD32 100p --> 0.1u
1U_0402_6.3V6K
RF CD33 47p --> 68p
CD11 1U_0201_6.3V6
CD12 1U_0201_6.3V6
CD15 1U_0201_6.3V6
M_A_DQ[0..63] 4
l
M_A_A[0..9] 4
D
-M_A_DQS[0..7] 4 1 1 1 1 1 1 1 1 1 2 1 1 2 2 2 1 1 2 2 2 2 2 D
2
RF@ RF@
CD32 CD33
M_A_DQS[0..7] 4
CD46
CD1
CD2
CD3
CD4
CD5
CD6
CD7
CD8
CD9
68P_0201_25V8-J
CD10
CD13
CD14
0.1U_0201_6.3V6-K
CD50
1
2 2 2 2 2 2 2 2 2 1 2 2 1 1 1 2 2 1 1 1 1 1
CD24 330U_B2_2.5VM_R9M
VCC1R2A_DIMN
VCC2R5A
o
VCC3B VCC3B VCC3B
CD16 1U_0201_6.3V6
CD17 1U_0201_6.3V6
CD18 1U_0201_6.3V6
CD19 1U_0201_6.3V6
CD20 1U_0201_6.3V6
CD21 1U_0201_6.3V6
CD22 1U_0201_6.3V6
CD23 1U_0201_6.3V6
VCC0R6B
RF
1
RD7
RF
2
1K_0201_1% 1
change RD7 form SD04110018J to SD0411001PT 2 2 2 2 2 2 2 2 RD1 RD2 RD3
+ @ @ @
2 0_0201_5% 0_0201_5% 0_0201_5%
DDR4_VREF_CA 1 2
1 2 1 2
1
4 DDR4_VREF_CA_M3 1 1 1 1 1 1 1 1 2
RD8 2_0201_1% CD34 CD35
n
100P_0201_25V8J 47P_0201_25V8J CD36 CD37 SA0 SA1 SA2
@
2
CD26 2 RF@ 2 1 100P_0201_25V8J 47P_0201_25V8J

RF@
0.022U_0201_6.3V RD9 CD25 RF@ 2 1
RF@
2
1K_0201_5% 0.1U_0201_6.3V6K
1
RD4 RD5 RD6

1 Cut in R-short
0_0201_5% 0_0201_5% 0_0201_5%
o
CD38 1U_0201_6.3V6
CD39 1U_0201_6.3V6
CD40 1U_0201_6.3V6
CD41 1U_0201_6.3V6
CD42 1U_0201_6.3V6
CD43 1U_0201_6.3V6
CD44 1U_0201_6.3V6
CD45 1U_0201_6.3V6
1
2
RD10
1
24.9_0201_1%
i
2 2 2 2 2 2 2 2
1
PLACE THE CAP CLOSE TO SODIMM
t
1 1 1 1 1 1 1 1 Follow THP1_SWG_MSIT_EC017
Add Decoupling Capacitors for System Memory SPD Address = 0H
a
C C
VCC1R2A_DIMN
VCC2R5A VCC1R2A_DIMN VCC1R2A_DIMN VCC0R6B
if c
VCC1R2A_DIMN VCC1R2A_DIMN
VCC1R2A_DIMN
1
VCC1R2A_DIMN VCC1R2A_DIMN J21B RD11
240_0201_1%
J21A
M_A_A3 131 132 M_A_A2
2
M_A_A1 133 A3 A2 134
1 2 135 A1 EVENT_n/NF 136
M_A_DQ1 3 VSS_1 VSS_2 4 M_A_DQ4 M_A_DDRCLK0_1866M 137 VDD_9 VDD_10 138 M_A_DDRCLK1_1866M
DQ5 DQ4 4 M_A_DDRCLK0_1866M CK0_t CK1_t/NF M_A_DDRCLK1_1866M 4
i
5 6 -M_A_DDRCLK0_1866M 139 140 -M_A_DDRCLK1_1866M
M_A_DQ0 7 VSS_3 VSS_4 8 M_A_DQ5 4 -M_A_DDRCLK0_1866M 141 CK0_c CK1_c/NF 142 -M_A_DDRCLK1_1866M 4
9 DQ1 DQ0 10 M_A_PARITY 143 VDD_11 VDD_12 144 M_A_A0
-M_A_DQS0 11 VSS_5 VSS_6 12 4 M_A_PARITY Parity A0
rt
M_A_DQS0 13 DQS0_C DM0_n/DBl0_n 14
15 DQS0_t VSS_7 16 M_A_DQ3 M_A_BS1 145 146 M_A_A10
M_A_DQ6 17 VSS_8 DQ6 18 4 M_A_BS1 147 BA1 A10/AP 148 M_A_A10 4
19 DQ7 VSS_9 20 M_A_DQ7 -M_A_CS0 149 VDD_13 VDD_14 150 M_A_BS0
M_A_DQ2 21 VSS_10 DQ2 22 4 -M_A_CS0 -M_A_WE 151 CS0_n BA0 152 -M_A_RAS M_A_BS0 4
23 DQ3 VSS_11 24 M_A_DQ9 4 -M_A_WE 153 A14/WE_n A16/RAS_n 154 -M_A_RAS 4
M_A_DQ13 25 VSS_12 DQ12 26 -M_A_ODT0 155 VDD_15 VDD_16 156 -M_A_CAS
27 DQ13 VSS_13 28 M_A_DQ8 4 -M_A_ODT0 -M_A_CS1 157 ODT0 A15/CAS_n 158 M_A_A13 -M_A_CAS 4
M_A_DQ12 29 VSS_14 DQ8 30 4 -M_A_CS1 159 CS1_n A13 160 M_A_A13 4
e
31 DQ9 VSS_15 32 -M_A_DQS1 -M_A_ODT1 161 VDD_17 VDD_18 162 TP_DIMM0_CHA_S2_N 1 @ TP31 Test_Point_40MIL
33 VSS_16 DQS1_c 34 M_A_DQS1 4 -M_A_ODT1 163 ODT1 C0/CS2_n/NC 164 DDR4_VREF_CA
35 DM1_n/DBl1_n DQS1_t 36 1 TP_DIMM0_CHA_S3_N 165 VDD_19 VREFCA 166 SA2
M_A_DQ15 37 VSS_17 VSS_18 38 M_A_DQ10 Test_Point_40MIL TP32 @ 167 C1/CS3_n/NC SA2 168
39 DQ15 DQ14 40 M_A_DQ30 169 VSS_53 VSS_54 170 M_A_DQ31 VCC1R2A_DIMN
M_A_DQ14 VSS_19 VSS_20 M_A_DQ11 DQ37 DQ36
c
41 42 171 172
43 DQ10 DQ11 44 M_A_DQ26 173 VSS_55 VSS_56 174 M_A_DQ25
M_A_DQ35 45 VSS_21 VSS_22 46 M_A_DQ32 175 DQ33 DQ32 176
47 DQ21 DQ20 48 -M_A_DQS3 177 VSS_57 VSS_58 178
M_A_DQ37 49 VSS_23 VSS_24 50 M_A_DQ36 M_A_DQS3 179 DQS4_c DM4_n/DBl4_n 180
51 DQ17 DQ16 52 181 DQS4_t VSS_59 182 M_A_DQ28
-M_A_DQS4 53 VSS_25 VSS_26 54 M_A_DQ27 183 VSS_60 DQ39 184
B M_A_DQS4 DQS2_c DM2_n/DBl2_n DQ38 VSS_61 M_A_DQ24 1 2 B
55 56 185 186 CD27 CD28
57 DQS2_t VSS_27 58 M_A_DQ39 M_A_DQ29 187 VSS_62 DQ35 188 2.2U_0402_6.3V6-M 0.1U_0201_6.3V6K
M_A_DQ38 VSS_28 DQ22 DQ34 VSS_63 M_A_DQ20
y
59 60 189 190 @
61 DQ23 VSS_29 62 M_A_DQ33 M_A_DQ21 191 VSS_64 DQ45 192 2 1
M_A_DQ34 63 VSS_30 DQ18 64 193 DQ44 VSS_65 194 M_A_DQ16
65 DQ19 VSS_31 66 M_A_DQ40 M_A_DQ17 195 VSS_66 DQ41 196
t
M_A_DQ44 67 VSS_32 DQ28 68 197 DQ40 VSS_67 198 -M_A_DQS2
69 DQ29 VSS_33 70 M_A_DQ41 199 VSS_68 DQS5_c 200 M_A_DQS2
M_A_DQ45 71 VSS_34 DQ24 72 201 DM5_n/DBl5_n DQS5_t 202
73 DQ25 VSS_35 74 -M_A_DQS5 M_A_DQ19 203 VSS_69 VSS_70 204 M_A_DQ18
f
75 VSS_36 DQS3_c 76 M_A_DQS5 205 DQ46 DQ47 206 PLACE THE CAP CLOSE TO SODIMM
77 DM3_n/DBl3_n DQS3_t 78 M_A_DQ22 207 VSS_71 VSS_72 208 M_A_DQ23
81 DQ30 DQ31 82 M_A_DQ48 211 VSS_73 VSS_74 212 M_A_DQ53 VCC1R2A_DIMN
DQ26 DQ27 VSS_75 VSS_76
a
85 86 M_A_DQ49 215 216 M_A_DQ52
87 VSS_41 VSS_42 88 217 DQ49 DQ48 218
89 CB5/NC CB4/NC 90 -M_A_DQS6 219 VSS_77 VSS_78 220
91 VSS_43 VSS_44 92 M_A_DQS6 221 DQS6_c DM6_n/DBl6_n 222
93 CB1/NC CB0/NC 94 223 DQS6_t VSS_79 224 M_A_DQ54
s
1 -M_A_DQS8 95 VSS_45 VSS_46 96 M_A_DQ50 225 VSS_80 DQ54 226
Test_Point_40MIL TP30 @ 1 M_A_DQS8 97 DQS8_c DM8_n/DBl8_n/NC 98 227 DQS5 VSS_81 228 M_A_DQ55
Test_Point_40MIL TP29 @ 99 DQS8_t VSS_47 100 M_A_DQ51 229 VSS_82 DQ50 230
101 VSS_48 CB6/NC 102 231 DQ51 VSS_83 232 M_A_DQ61
103 CB2/NC VSS_49 104 M_A_DQ56 233 VSS_84 DQ60 234
105 VSS_50 CB7/NC 106 235 DQ61 VSS_85 236 M_A_DQ60
107 CB3/NC VSS_51 108 -DRAMRST M_A_DQ57 237 VSS_86 DQ57 238
r
M_A_CKE0 109 VSS_52 RESET_n 110 M_A_CKE1 -DRAMRST 5 239 DQ56 VSS_87 240 -M_A_DQS7
4 M_A_CKE0 111 CKE0 CKE1 112 M_A_CKE1 4 241 VSS_88 DQS7_c 242 M_A_DQS7
M_A_BG1 113 VDD_1 VDD_2 114 M_A_ACT_N 243 DM7_n/DBl7_n DQS7_t 244
4 M_A_BG1 M_A_BG0 115 BG1 ACT_n 116 M_A_ALERT_N M_A_ACT_N 4 M_A_DQ63 245 VSS_89 VSS_90 246 M_A_DQ58
4 M_A_BG0 117 BG0 ALERT_n 118 M_A_ALERT_N 4 247 DQ62 DQ63 248
M_A_A12 119 VDD_3 VDD_4 120 M_A_A11 M_A_DQ62 249 VSS_91 VSS_92 250 M_A_DQ59
o
4 M_A_A12 M_A_A9 121 A12 A11 122 M_A_A7 M_A_A11 4 IN hynix spec ,vdd spd is 2.25V to 2.75V 251 DQ58 DQ59 252
123 A9 A7 124 SMB_CLK_3B 253 VSS_93 VSS_94 254 SMB_DATA_3B
M_A_A8 125 VDD_5 VDD_6 126 M_A_A5 65,70 SMB_CLK_3B 255 SCL SDA 256 SMB_DATA_3B 65,70
VDDSPD SA0
M_A_A6 127 A8 A5 128 M_A_A4 VCC3B 257 VDDSPD SA0 258
129 A6 A4 130 259 VPP_1 VTT 260 SA1
VDD_7 VDD_8 VPP_2 SA1
A 1 2 A
1 2 261 262
F
2 GND_1 GND_2
CD29 RD12 0_0201_5%
FOX_AS0A826-H4RB-7H 0.1U_0201_6.3V6K CD30 CD31 FOX_AS0A826-H4RB-7H
2.2U_0402_6.3V6-M 2 1 0.1U_0201_6.3V6K
1
@
place the cap within 200 mils from the sodimn
Issued Date 2014/08/10 Deciphered Date 2015/08/10 DDR4 SO DIMM

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom
WOLVERINE3 UMA 0.1

5 4 3 2 1
5 4 3 2 1
n ly D
n o
t io
a
C C
i c
r
BLANK
t if
B
ce B
f t y
s a
A
o r A
5
F 4 3
2
Title
Custom
Date:
BLANK

WOLVERINE3 UMA
1
Sheet 23 of 100
Rev
0.1
5 4 3 2 1
n ly D
n o
t io
C
i c a C
BLANK
r t if
ce
y
B B
a f t
r s
A
Title
BLANK
A
WOLVERINE3 UMA
5 4 3 2 1
5 4 3 2 1
n ly D
n o
t io
a
C C
i c
r
BLANK
t if
B
ce B
f t y
s a
A
o r A
5
F 4 3
2
Title
Custom
Date:
BLANK

WOLVERINE3 UMA
1
Sheet 25 of 100
Rev
0.1
5 4 3 2 1
n ly D
n o
t io
C
BLANK i c a C
r t if
ce
y
B B
a f t
r s
A
Title
BLANK

A
WOLVERINE3 UMA
5 4 3 2 1
5 4 3 2 1
n ly D
n o
t io
C
i c a C
BLANK
r t if
ce
y
B B
a f t
r s
A
Title
BLANK

A
WOLVERINE3 UMA
5 4 3 2 1
5 4 3 2 1
VCC3B VCC3B_PS8338B VCC3B_PS8338B Change power rail name to VCC3B_PS8338B www.xinxunwei.com 400-800-9990
0.01U_0201_10V7K
0.01U_0201_10V7K
RX55 1 2 0_0603_5%
0.1U_0201_6.3V6K
0.1U_0201_6.3V6K
0.1U_0201_6.3V6K
UX1
2 2 2 2 2
Reserved 0 ohm for power consumption test
y
CX18
CX2
CX4
CX17
C16
5 50
21 VDD33_1 OUT1_D0p 49 DOCK_DDIP2_0P 60
1 1 1 1 1 VDD33_2 OUT1_D0n DOCK_DDIP2_0N 60
l
30 47
51 VDD33_3 OUT1_D1p 46 DOCK_DDIP2_1P 60
57 VDD33_4 OUT1_D1n 45 DOCK_DDIP2_1N 60
D VDD33_5 OUT1_D2p 44 DOCK_DDIP2_2P 60 D
VCC3B OUT1_D2n 42 DOCK_DDIP2_2N 60
OUT1_D3p DOCK_DDIP2_3P 60
n
3 41
3 DDIP2_HPD 4 IN_HPD OUT1_D3n DOCK_DDIP2_3N 60
IN_CA_DET
CX5 1 2 0.1U_0201_6.3V6K DDIP2_0P_C 6 40
3 DDIP2_0P 1 2 DDIP2_0N_C 7 IN_D0p OUT2_D0p 39 DMUX_DDIP2_0P 29
CX6 0.1U_0201_6.3V6K
3 DDIP2_0N IN_D0n OUT2_D0n DMUX_DDIP2_0N 29
2
o
CX7 1 2 0.1U_0201_6.3V6K DDIP2_1P_C 9 37
3 DDIP2_1P 1 2 DDIP2_1N_C 10 IN_D1p OUT2_D1p 36 DMUX_DDIP2_1P 29
RX30 RX31 CX8 0.1U_0201_6.3V6K
3 DDIP2_1N 1 2 DDIP2_2P_C 12 IN_D1n OUT2_D1n 35 DMUX_DDIP2_1N 29
4.7K_0402_5% 4.7K_0402_5%3 CX9 0.1U_0201_6.3V6K
DDIP2_2P 1 2 DDIP2_2N_C 13 IN_D2P OUT2_D2p 34 DMUX_DDIP2_2P 29
CX10 0.1U_0201_6.3V6K
3 DDIP2_2N 1 2 DDIP2_3P_C 15 IN_D2n OUT2_D2n 32 DMUX_DDIP2_2N 29
CX11 0.1U_0201_6.3V6K
3 DDIP2_3P DMUX_DDIP2_3P 29
1
CX12 1 2 0.1U_0201_6.3V6K DDIP2_3N_C 16 IN_D3p OUT2_D3p 31
3 DDIP2_3N IN_D3n OUT2_D3n DMUX_DDIP2_3N 29
27
n
DDIP2_AUXP DDIP2_AUXP_C OUT1_AUXn_SDA DOCK_DDIP2_AUXN 60
CX14 1 2 0.1U_0201_6.3V6K 24 26
3 DDIP2_AUXP DDIP2_AUXN DDIP2_AUXN_C IN_AUXp OUT1_AUXp_SCL DOCK_DDIP2_AUXP 60
CX13 1 2 0.1U_0201_6.3V6K 25 29
3 DDIP2_AUXN IN_AUXn OUT2_AUXn_SDA 28 DMUX_DDIP2_AUXN 29
22 OUT2_AUXp_SCL DMUX_DDIP2_AUXP 29
3 DDIP2_CTRLCLK IN_DDC_SCL
o
23
3 DDIP2_CTRLDATA IN_DDC_SDA 48
OUT1_HPD 38 DOCK_DDIP2_HPD 60
OUT2_HPD DMUX_DDIP2_HPD 29
i
2
I2C_CTL_EN 43
Test_Point_40MIL TP34 @ 1 PS8338_PI1 1 OUT1_CA_DET 33
t
1 PS8338_PI0 60 PI1/SCL_CTL OUT2_CA_DET DMUX_DDIP2_CADET 29
PI0/SDA_CTL
56 PS8338_PC10
17 PC10 55 PS8338_PC11
CEXT PC11
a
20 54 PS8338_PC20
REXT PC20 53 PS8338_PC21
1 PC21
1
1 2 59 8 PS8338_PEQ
C VCC3B CFG0 PEQ C
RX2 RX32 4.7K_0402_5% 58
CX15 4.99K_0201_1% CFG1 11
if c
2.2U_0402_6.3V6-M 2 GND1 19
VCC3B 14 GND2 52
2
18 PD GND3 61
SW EPAD
1
Follow thorpe priority setting
RX26
PRIORITY : DOCKING>HDMI>WIGIG
1
4.7K_0402_5%
1
PS8338BQFN60GTR-A1_QFN60_5X9
1M_0402_5%
i
2
RX21 1M_0402_5%
RX54
rt
2
TABLE : Automatic Switching Mode (CFG0 = H) 9 DDI_PRIORITY2
SW (DDI_PRIORITY2)
e
Port 1 has higher priority when both ports are plugged
VCC3B
Port 2 has higher priority when both ports are plugged
y c RX9
RX11
1
1
@
@
2 4.7K_0402_5%
2 4.7K_0402_5%
PS8338_PEQ
PS8338_PC10
RX10
RX12
1
1
@
@
24.7K_0402_5%
2 4.7K_0402_5% B
t
@ @
RX13 1 2 4.7K_0402_5% PS8338_PC11 RX14 1 2 4.7K_0402_5%
f
@ @
RX15 1 2 4.7K_0402_5% PS8338_PC20 RX16 1 2 4.7K_0402_5%
a
@ @
RX17 1 2 4.7K_0402_5% PS8338_PC21 RX18 1 2 4.7K_0402_5%
s
@
RX37 1 2 4.7K_0402_5% PS8338_PI0
o r
F
A A

Issued Date 2014/08/10 Deciphered Date 2015/08/10 DP SWITCH
WOLVERINE3 UMA
5 4 3 2 1
5 4 3 2 1
VCC3B_PS8337B
VCC3B VCC3B_PS8337B
RX53 1 2 0_0603_5%
y
VCC3B_PS8337B
UX2
2 2 2 2
CX28 CX29 CX30 CX31
l
14 8 PS8337_PEQ
0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 0.1U_0201_6.3V6K 0.1U_0201_6.3V6K VDD33_1 PEQ
1 1 1 1 28
41 VDD33_2 5
D D
56 VDD33_3 IN_HPD 11 DMUX_DDIP2_HPD 28
VDD33_4 IN_CA_DET DMUX_DDIP2_CADET 28
Place 0.1uF caps near each VDD33 pin of PS8337 CX19 1 2 0.1U_0201_6.3V6K DMUX_DDIP2_0P_C 3 40
n
28 DMUX_DDIP2_0P DMUX_DDIP2_0N_C IN_D0p DP_D0p WIGIG_DP0P 50
CX20 1 2 0.1U_0201_6.3V6K 4 39
28 DMUX_DDIP2_0N DMUX_DDIP2_1P_C IN_D0n DP_D0n WIGIG_DP0N 50
VCC3B CX21 1 2 0.1U_0201_6.3V6K 6 37
CX22 1 2 0.1U_0201_6.3V6K 7 36
28 DMUX_DDIP2_1N DMUX_DDIP2_2P_C IN_D1n DP_D1n WIGIG_DP1N 50
CX23 1 2 0.1U_0201_6.3V6K 9 34
28 DMUX_DDIP2_2P DMUX_DDIP2_2N_C IN_D2P DP_D2p WIGIG_DP2P 50
CX24 1 2 0.1U_0201_6.3V6K 10 33
28 DMUX_DDIP2_2N IN_D2n DP_D2n WIGIG_DP2N 50
2
CX25 1 2 0.1U_0201_6.3V6K DMUX_DDIP2_3P_C 12 31
o
RX49 CX26 1 2 0.1U_0201_6.3V6K 13 30
28 DMUX_DDIP2_3N IN_D3n DP_D3n WIGIG_DP3N 50
4.7K_0402_5% WIGIG_AUXP
50 55
28 DMUX_DDIP2_AUXP 49 IN_DDC_SCL DP_AUXp_SCL 54 WIGIG_AUXN WIGIG_AUXP 50
1
28 DMUX_DDIP2_AUXN IN_DDC_SDA DP_AUXn_SDA WIGIG_AUXN 50
DDI_PRIORITY1 45 16 HDMI_CLKP
9 DDI_PRIORITY1 SW/SDA_CTL TMDS_CLKp HDMI_CLKN HDMI_CLKP 40
46 15
PD TMDS_CLKn HDMI_CLKN 40
52 19 HDMI_DATA0P
n
IN_AUXp TMDS_CH0p HDMI_DATA0N HDMI_DATA0P 40
51 18
IN_AUXn TMDS_CH0n HDMI_DATA1P HDMI_DATA0N 40
22
TMDS_CH1p HDMI_DATA1N HDMI_DATA1P 40
38 21 HDMI_DATA1N 40
I2C_CTL_EN TMDS_CH1n 25 HDMI_DATA2P
PS8337_MODE TMDS_CH2p HDMI_DATA2N HDMI_DATA2P 40
53 24
MODE TMDS_CH2n HDMI_DATA2N 40
o
1 48 HDMI_DDC_CLK
CEXT TMDS_SCL HDMI_DDC_DATA HDMI_DDC_CLK 40
27 47
REXT TMDS_SDA HDMI_DDC_DATA 40
PS8337_TMDS_PRE
i
32 20
50 WIGIG_HPD 42 DP_HPD TMDS_PRE
DP_CA_DET 23 PS8337_TMDS_RT
2 TMDS_RT
t
17 TMDS_DDCBUF 26
40 HDMI_HPD_CONN TMDS_HPD GND1 35
PS8337_DP_CFG0 44 GND2 43
Test_Point_40MIL TP36 @ 1PS8337_DP_CFG1 29 DP_CFG0/SCL_CTL GND3 57
DP_CFG1 EPAD
a
1
1
C C
RX52 RX50 PS8337BQFN56GTR2-A1_QFN56_7X7
27K_0201_5% CX27 1M_0402_5%
4.99K_0402_1%
2 RX51
c
2.2U_0402_6.3V6-M
2
Follow thorpe priority setting
PRIORITY : DOCKING>HDMI>WIGIG
if i VCC3B
t
@
RX48 1 2 4.7K_0402_5% PS8337_PEQ RX47 1 @ 24.7K_0402_5%
r
1 2 4.7K_0402_5% PS8337_TMDS_PRE 1 2 4.7K_0402_5%
Improve HDMI SI, change RX38, RX43 to ASM RX38 RX43
e
RX39 1 2 4.7K_0402_5% PS8337_MODE RX44 1 2 4.7K_0402_5%
@
RX40 1 2 4.7K_0402_5% PS8337_TMDS_RT
c
@
RX41 1 2 4.7K_0402_5% PS8337_DP_CFG0
B B
f t y
s a
A
o r A
5
F 4 3
2
Title
Custom
Date:
DP DEMUX

WOLVERINE3 UMA
1
Sheet 29 of 100
Rev
0.1
5 4 3 2 1
n ly D
n o
t io
C
BLANK i c a C
r t if
ce
y
B B
a f t
r s
A
Title
BLANK

A
Custom WOLVERINE3 UMA 0.1

5 4 3 2 1
5 4 3 2 1
n ly D
n o
t io
C
BLANK i c a C
r t if
ce
y
B B
a f t
r s
A
Title
BLANK

A
Custom WOLVERINE3 UMA 0.1

5 4 3 2 1
5 4 3 2 1
n ly D
n o
t io
C
i c a C
BLANK
r t if
ce
y
B B
a f t
r s
A
Title
BLANK

A
WOLVERINE3 UMA
5 4 3 2 1
5 4 3 2 1
n ly D
n o
t io
C
BLANK i c a C
r t if
ce
y
B B
a f t
r s
A
Title
BLANK

A
Custom
WOLVERINE3 UMA 0.1

5 4 3 2 1
5 4 3 2 1
n ly D
n o
t io
C
i c a C
BLANK
r t if
ce
y
B B
a f t
r s
A
Title
BLANK
A
WOLVERINE3 UMA
5 4 3 2 1
5 4 3 2 1
n ly D
n o
t io
C
i c a C
BLANK
r t if
ce
y
B B
a f t
r s
A
Title
BLANK
A
WOLVERINE3 UMA
5 4 3 2 1
5 4 3 2 1
n ly D
n o
t io
C
i c a C
BLANK
r t if
ce
y
B B
a f t
r s
A
Title
BLANK
A
WOLVERINE3 UMA
5 4 3 2 1
5 4 3 2 1
SIT RF
y
VCC5M VCC1V2B VCC1R2A_DIMN
RF_NS@
C306
0.1U_0201_6.3V6-K
1
2
2
1
RF_NS@
C307
68P_0201_25V8-J
RF@
C308
0.1U_0201_6.3V6-K
1
2
2
1
RF@
C309
RF@
C310
68P_0201_25V8-J 0.1U_0201_6.3V6-K
1
2
2
1
RF@
C311
68P_0201_25V8-J
n l D
Follow RF suggested, add by pass capacitance to GND
n o
t io
C
i c a C
r t if
ce
y
B B
a f t
r s
A
Title
RF Component
A
WOLVERINE3 UMA
5 4 3 2 1
5 4 3 2 1
VCC3P
Q1
1 8
y
2 7
VCC3M
2
3 6
R1 VINT20 VBL20
l
4 5 47_0201_5%
D D
1
TPCF8002_2-3U1A F1
1 2
n
1 3A_32V_ERBRD3R00X
2
C1
R2 0.01U_0402_25V7K
2
100_0201_5% 2
o
1 D1
1
VCC3P_DRV
72 VCC3P_DRV
2
2
R3
C2 47K_0201_5% VCC3P
0.1U_0201_6.3V6K
RF
n
1 F2 0.9A
1
VCC3LCD 1 2
3A_32V_ERBRD3R00X
2 2 2 1 2
o
RF_NS@ RF_NS@ 1.2A VCC3B
C3 C4 C5 C265 C266
100P_0201_25V8J
47P_0201_25V8J
1U_0402_10V6K 0.1u_0201_10V6K
1 1 1 2 1
i
0.01U_0201_10V7K
VBL20
2
t
F5
2A_32V_ERBRD2R00X
VCC3P
RF
LCD CONNECTOR
1
C VCC3SW VCC3SW VCC3B VCC3B VCC3M C
2 1 2
2
2
RF_NS@ RF_NS@
if c
R4 C6 C7 C8 C268 C267
47K_0201_5%
100P_0201_25V8J
0.01U_0402_25V7K 0.1U_0402_25 1UF_25V_0603
47P_0201_25V8J
1
1
1 2 1
2
2
1
100K_0201_5%
100K_0201_5%
F3 F4 C298
2
0.1u_0201_10V6K
1
0.5A_32V_ERBRD0R50X
0.5A_32V_ERBRD0R50X
J10
I-PEX_20374-030E-31
30
1
29 30 32
R5 1
R6 1
28 29 G2 31
27 28 G1
i
8/19 SVT change R7 to 220 ohm from 510 J11
26 27 I-PEX_20374-030E-31
25 26 30
PANEL_BKLT_CTRL 24 25 29 30 32
rt
3 PANEL_BKLT_CTRL BACKLIGHT_ON 23 24 -LED_PWR 1 2 220_0201_5% 28 29 G2 31
R7
61 BACKLIGHT_ON 22 23 61 -LED_PWR 27 28 G1
-PWRSWITCH
21 22 17,71 -PWRSWITCH 26 27
20 21 25 26
19 20 24 25
18 19 23 24
3 EDP_HPD 17 18 -LID_CLOSE D2 1 2 RB521CS-30GT2RA_VMN2-2 22 23
16 17 21 22
15 16 USBP9- R8 1 2 0_0201_5% USBP9-_CONN 20 21
e
14 15 10 USBP9- 1 2 USBP9+_CONN 19 20
USBP9+
13 14 10 USBP9+ 18 19
R9 0_0201_5%
12 13 17 18
11 12 Cut in R-short 16 17
C9 1 2 0.1u_0201_10V6K EDP_AUXN_CONN 10 11 15 16
3 EDP_AUXN EDP_AUXP_CONN 9 10 14 15
c
C10 1 2 0.1u_0201_10V6K
3 EDP_AUXP 8 9 -LED_LOGO 1 2 3.9K_0201_5% 13 14
R10
1 2 0.1u_0201_10V6K EDP_TXP0_CONN 7 8 61 -LED_LOGO 12 13
C11
3 EDP_TXP0 1 2 0.1u_0201_10V6K EDP_TXN0_CONN 6 7 TOUCH_EN Cut in R-short 11 12
C12
3 EDP_TXN0 5 6 TOUCH_EN 10 11
C13 1 2 0.1u_0201_10V6K EDP_TXP1_CONN 4 5 Add Touch_EN for touch function USBP7- R11 1 2 0_0201_5% USBP7-_CONN 9 10
3 EDP_TXP1 1 2 0.1u_0201_10V6K EDP_TXN1_CONN 3 4 10 USBP7- R12 1 2 0_0201_5% USBP7+_CONN 8 9
C14 USBP7+
B 3 EDP_TXN1 2 3 10 USBP7+ 7 8 B
1 2 -INT_MIC_DTCT 6 7
1 8 -INT_MIC_DTCT DMIC_DATA 5 6
y
54 DMIC_DATA DMIC_CLK 4 5
54 DMIC_CLK 3 4
-LID_CLOSE 2 3
t
62 -LID_CLOSE 1 2
1
RF
f
1000P_0201_25V7K
1000P_0201_25V7K
2 2 2 2200PF_0201_25V
1000P_0201_25V7K
C269
C20
C21
2
a
RF@
1 1 1
C19
@ @
1
@
r s For Touch Function

Add Pin24,25 to VCC3B, Pin14,15 to GND
Change F5 to 2A
Deciphered Date
2012/06/21
Title
LCD/LID/MIC/CAMERA/PWR SW

Custom
WOLVERINE3 UMA
Rev
0.1
A

5 4 3 2 1
5 4 3 2 1
n ly D
n o
t io
C
i c a C
BLANK
r t if
ce
y
B B
a f t
r s
A
Title
BANK

A
WOLVERINE3 UMA
5 4 3 2 1
5 4 3 2 1
VCC5B_HDMI
1/5 change for ESD request
1
y
R340 R341
1.5K_0201_1% 1.5K_0201_1%
l
EXC24CH900U_4P
HDMI_CLKN 4 3 HDMI_CLKN_CONN
29 HDMI_CLKN
2
4 3 J43
D HDMI_HPD_CONN 19 D
HDMI_CLKP 1 2 HDMI_CLKP_CONN 29 HDMI_HPD_CONN 18 HP_DET
29 HDMI_CLKP 1 2 +5V
n
17
L7 HDMI_DDC_DATA 16 DDC/CEC_GND
29 HDMI_DDC_DATA HDMI_DDC_CLK 15 SDA
29 HDMI_DDC_CLK 14 SCL
L8
HDMI_DATA1P 1 2 HDMI_DATA1P_CONN 13 Reserved
29 HDMI_DATA1P 1 2 CEC
o
HDMI_CLKN_CONN 12 20
11 CK- GND1 21
HDMI_DATA1N 4 3 HDMI_DATA1N_CONN HDMI_CLKP_CONN 10 CK_shield GND2 22
29 HDMI_DATA1N 4 3 HDMI_DATA0N_CONN 9 CK+ GND3 23
EXC24CH900U_4P 8 D0- GND4
HDMI_DATA0P_CONN 7 D0_shield
L9 HDMI_DATA1N_CONN 6 D0+
HDMI_DATA0P 1 2 HDMI_DATA0P_CONN 5 D1-
n
29 HDMI_DATA0P 1 2 HDMI_DATA1P_CONN 4 D1_shield
HDMI_DATA2N_CONN 3 D1+
HDMI_DATA0N 4 3 HDMI_DATA0N_CONN 2 D2-
29 HDMI_DATA0N 4 3 HDMI_DATA2P_CONN 1 D2_shield
D2+
DF2S6P8UFS_1-1L1A2
DF2S6P8UFS_1-1L1A2
DF2S6P8UFS_1-1L1A2
EXC24CH900U_4P
FOX_QJ111A1-R000H1-7H
EXC24CH900U_4P
ME@
i
HDMI_DATA2N 4 3 HDMI_DATA2N_CONN
1
29 HDMI_DATA2N 4 3 FOX_QJ111A1-R000H1-7H_19P-TXX
D55 D56 D57
t
HDMI_DATA2P 1 2 HDMI_DATA2P_CONN
29 HDMI_DATA2P 1 2 VCC5B_HDMI
2
L10
2
For EMC VCC5B R313
C C
0.01_1206_1%
if c
1
U23
1 6
IN OUT
4 5
FAULT ILIM
1
3 2
Close to JHDMI1 EN GND
i
1/14 swap pin 1/14 swap pin R314
61.9K_0201_1% 1
1
D52 D51 C238
rt
HDMI_DATA1N_CONN1 1 HDMI_DATA1N_CONN HDMI_CLKN_CONN HDMI_CLKN_CONN TPS2553DBVR_SOT23-6
10 9 1 1 10 9 C229 4.7U_0402_6.3V6M
2
0.1U_0402_10V6-K
2
HDMI_DATA1P_CONN 2 2 9 8 HDMI_DATA1P_CONN HDMI_CLKP_CONN 2 2 9 8 HDMI_CLKP_CONN 2
Change R314 from 59.1K to 61.9K for HDMI current limit (500mA)
HDMI_DATA2N_CONN4 4 7 7 HDMI_DATA2N_CONN HDMI_DATA0N_CONN4 4 7 7 HDMI_DATA0N_CONN
HDMI_DATA2P_CONN 5 6 6 HDMI_DATA2P_CONN HDMI_DATA0P_CONN 5 6 6 HDMI_DATA0P_CONN

5 5
e
3 3 3 3
8 8
c
ESD7004MUTAG For EMC ESD7004MUTAG
EMC@ EMC@
Follow EMC suggest , change D51, D52 to ASM
y
B B
a f t
r s
A
Deciphered Date
2013/08/05
Title
HDMI CONNECTOR
A
WOLVERINE3 UMA
5 4 3 2 1
5 4 3 2 1
www.xinxunwei.com 400-800-9990 VCC5B FOR SYSTEM DP NEAR DP CONN
VCC3B
2
C22
2
0.1U_0201_6.3V6K
2
1
R13 R14
y
2.2K_0201_5% 2.2K_0201_5%
@
1
U2
1
16
l
Vcc 4
DDIP1_AUXP C23 1 2 0.1U_0201_6.3V6K DDIP1_AUXP_C 2 1A 7
3 DDIP1_AUXP DDIP1_CTRLCLK 3 1B1 2A 9
D D
3 DDIP1_CTRLCLK DDIP1_AUXN 1 2 0.1U_0201_6.3V6K DDIP1_AUXN_C 5 1B2 3A 12
C24
3 DDIP1_AUXN DDIP1_CTRLDATA 6 2B1 4A
3 DDIP1_CTRLDATA 11 2B2 15
n
10 3B1 OE 1 DVI_DONGLE_DTCT
DDIP1_HPD 14 3B2 S
3 DDIP1_HPD 13 4B1 8
4B2 GND 17
T-PAD
2
CBT3257ABQ_DHVQFN16_2P5X3P5
o
R15
100K_0201_5%
1
Vender P/N
NXP CBT3257ABQ
n
On-semi 74FST3257MNTWG
t io
a
C C
i
3
3
if c
DDIP1_3N
DDIP1_3P
DDIP1_2N
C25
C26
C27
1
1
1
1
2 0.1U_0201_6.3V6K
2 0.1U_0201_6.3V6K
2 0.1U_0201_6.3V6K
2 0.1U_0201_6.3V6K
DP_DP3N_CONN
DP_DP3P_CONN
DP_DP2N_CONN
DP_DP2P_CONN
rt
C28
3 DDIP1_2P
C29 1 2 0.1U_0201_6.3V6K DP_DP1N_CONN
3 DDIP1_1N 1 2 0.1U_0201_6.3V6K DP_DP1P_CONN
C30
3 DDIP1_1P
C31 1 2 0.1U_0201_6.3V6K DP_DP0N_CONN
3 DDIP1_0N 1 2 0.1U_0201_6.3V6K DP_DP0P_CONN
C32
3 DDIP1_0P
VCC3B
e
DVI_DONGLE_DTCT
D3
2
DP_DP0N_CONN DP_DP0N_CONN
c
1 1 10 9
R16
DP_DP0P_CONN
DP_DP3N_CONN
2 2 9 8
DP_DP0P_CONN
DP_DP3N_CONN
100K_0201_5% DP CONN
J6
VCC3VIDEO_DP
1
4 4 7 7
DP_HPD_CONN 2 20
DP_DP3P_CONN 5 5 DP_DP3P_CONN HOT_PLUG DP_PWR
6 6 19
B DP_AUXP_CONN GND1 B
16 14
3 3 DP_AUXN_CONN 18 AUX_CH_P GND2 6
y
AUX_CH_N CONFIG2 4
CONFIG1
2
8 DP_DP3P_CONN 10 13
LANE3_P GND3 2
1
1
@ @ DP_DP3N_CONN 12 8
RCLAMP0524PATCT_SLP2510P8-10-9 LANE3_N GND4
t
R17 D4 D5 D6 7 C33
100K_0201_5% DP_DP2P_CONN 15 GND5 1
DF2S6P8UFS_1-1L1A2 DF2S6P8UFS_1-1L1A2 DF2S6P8UFS_1-1L1A2 DP_DP2N_CONN LANE2_P GND6 0.1U_0201_6.3V6K
1
NEAR DP CONN 17
1
LANE2_N 21
2
2
DP_DP1P_CONN 9 GND7 22
f
DP_DP1N_CONN 11 LANE1_P GND8 23
LANE1_N GND9 24
DP_DP0N_CONN 5 GND10
LANE0_N
5.1M_0201_5%
DP_DP0P_CONN
0.1U_0201_6.3V6K
3
LANE0_P
NEAR DP CONN
a
D7
DP_DP2P_CONN 1 1 DP_DP2P_CONN
10 9
DP_DP2N_CONN 2 2 9 8
DP_DP2N_CONN Typ. 500mA FOX_3V112M3-R05A13-7H
1
Max 1.5A VCC3VIDEO_DP
s
DP_DP1N_CONN 4 4 7 7
DP_DP1N_CONN
VCC3M R19
DP_DP1P_CONN DP_DP1P_CONN 2 1M_0201_5%
5 5 6 6
2
2
2
R18
3 3
@ 1
6 1 C34
C35
8 2 1
r
2
0.01U_0201_6.3V7K
2
C36 C37 C38 C39 5 2 1

RCLAMP0524PATCT_SLP2510P8-10-9 10U_0603_6.3V6M 0.1U_0201_6.3V6K 4.7U_0402_6.3V6M 10U_0603_6.3V6M
@ @ U3
1
1 D66
1
5 1 2
NEAR DP CONN IN OUT 2
SP3003-02UTG_UDFN-6L6_1P6X1P0
GND
3
4 3
o
EN OC#
TPS2530DBVR SOT23 5P POWER SWITCH
Modify Manufacturer PN
A A
VCC3B
F
Vender P/N
R20 1 @ 2 0_0201_5%
TI TPS2530
R21 1 2 0_0201_5%
On-semi NCP380HSN05AAT1G
72 BPWRG

Cut in R-short
Issued Date 2014/08/10 Deciphered Date 2015/08/10 DISPLAY PORT CONNECTOR
Custom
WOLVERINE3 UMA 0.1

5 4 3 2 1
5 4 3 2 1
n ly D
n o
t io
C
i c a C
BLANK
r t if
ce
y
B B
a f t
r s
A
Title
BLANK
A
WOLVERINE3 UMA
5 4 3 2 1
5 4 3 2 1
OE=L , DISCONNECT
OE=H, A PORT = B PORT
VCC5B VCC5B
7/10 Add for WD HDD can't power on when pcie cable plug into SATA hdd www.xinxunwei.com 400-800-9990
U27
1 5
13 -PLTRST_FAR A Vcc
IFDET
2
-PLTRST_FAR_HDD
2 F7
SATA Device GND
@ B
3A_32V_ERBRD3R00X PCIe Device 5K PU to Vsource
R435 1 2 0_0201_5% -PE_DTCT
CLKREQ_SLECTE -PE_DTCT 10
y
3 4
GND OE 1.to meet sata express .IFDET is 1.8v ,
1
2.to meet sata express defination for clkdet
1
TC7SB385FU_SSOP5 C
l
J1 IFDET 2 Q4
I-PEX_20374-030E-31 B
30
30 E9 CLKDET MMBT3904_SOT23-3
D CLKDET E D
29 E8 REFCLKN
3
29 30
1
-PCIE4_CLK_100M 32
12 -PCIE4_CLK_100M PCIE4_CLK_100M 28 29 G2 31 28 E7 REFCLKP VCC3B
R51
12 PCIE4_CLK_100M 27 28 G1
27 S1 GND
n
20K_0201_5%
PCIE4_L0_SATA1_TXP_CONN 26 27
PCIE4_L0_SATA1_TXN_CONN 25 26 26 S2 PETP0/A+
2
24 25 25 S3 PETN0/A-
2
PCIE4_L0_SATA1_RXN_CONN 23 24 R426 0_0201_5%
24 S4 GND 1 2 R52
PCIE4_L0_SATA1_RXP_CONN 22 23
21 22
23 S5 PERN0/B- 10K_0201_5%
o
20 21 22 S6 PERP0/B+
PCIE4_L1_TXP_CONN 19 20 Q38 @
21 S7 GND
1
Q5
PCIE4_L1_TXN_CONN 18 19 20 S8 GND LSK3541G1ET2L 1N VMT3 LSK3541G1ET2L 1N VMT3
17 18 -CLKREQ_DEVSLP 3 1 3 1
19 S9 PETP1 -CLKREQ_PCIE4 12
PCIE4_L1_RXN_CONN 16 17
D
PCIE4_L1_RXP_CONN 15 16 18 S10 PETN1
14 15 17 S11 GND VCC3B VCC3B
-PLTRST_FAR_HDD 13 14
-CLKREQ_DEVSLP 12 13 16 S12 PERN1
G
R433 1 2 0_0201_5%
2
IFDET 11 12 15 S13 PERP1 R410 @ R412 @
10 11
2
-HDD_DTCT CLKREQ_SLECTE
63 -HDD_DTCT 14 S14 GND 100K_0201_5% 100K_0201_5%
Add 1K ohm to avoid HDD issue 9 10
8 9 13 P2 PERST#
7 8 12 P3 CLKREQ#/DEVSLP
6 7 11 P4 IFDET
1
Follow EMC suggestion, add 0.1uf on -HDD_DTCT 5 6 CLKDET (DEVICE)
4 5
10 P5 GND Q37 @
3 4 9 P6 GND Requires the common RefClk -->GND
1
R411 @ D
2 3 Supports SRIS --> not GND
i
2 CLKDET 2 1 2
EMC@ 1 2 J1 PIN5/9 change to NC for assembly issue G LSK3541G1ET2L 1N VMT3
1 0_0201_5%
C302
10U_0603_6.3V6M
7/10 delete J1pin2 for follow SATA/ SATA EXPRESS spec VCCRE VCC5B
t
1 2 1 S
0.1U_0402_25V6-K
3
2
EMC@ C76 RF@ RF@
C75 C271 C301
VCC1V2B VCC3B VCCRE
RF
0.1U_0201_6.3V6-K
68P_0201_25V8-J
1
1 2
0.1U_0402_25V6-K
2
U7
VCCRE
a
1 1 5
RF_NS@ A Vcc
C R354 1 @ 2 0_0603_5%
2 2 2
C272
2
OE=L , DISCONNECT C
C77 C78 C79
100P_0201_25V8J
R355 1 2 0_0603_5%
1
0.01U_0201_10V7K 0.01U_0201_10V7K 1U_0402_10V6K
1 1
2 10 SATA1_DEVSLP B OE=H, A PORT = B PORT
c
3 4 -PE_DTCT
Follow RF suggestion GND OE
Follow EMC suggestion
C271 100p --> 68p
i
Change C75 to 0.1uf TC7SB385FU_SSOP5
15
C301 68p --> 0.1u U24
6
reserve 0_0201-R for test.
VDD1
VDD2
if
R421 0_0201_5%
PCIE4_L0_SATA1_TXP C83 1 2 0.01U_0201_10V7-K PCIE4_L0_SATA1_TXP_C 1 14 PCIE4_L0_SATA1_TXP_CONN_R 1 2 PCIE4_L0_SATA1_TXP_CONN
10 PCIE4_L0_SATA1_TXP AI+ AO+
R422 0_0201_5%
PCIE4_L0_SATA1_TXN C85 1 2 0.01U_0201_10V7-K
0_0201_5% PCIE4_L0_SATA1_TXN_C 2 13 PCIE4_L0_SATA1_TXN_CONN_R 1 2 PCIE4_L0_SATA1_TXN_CONN
10 PCIE4_L0_SATA1_TXN AI- AO-
VCC3B
close
R419 to U1
PCIE4_L0_SATA1_RXP_CONN 1 2 PCIE4_L0_SATA1_RXP_CONN_R 10 5 PCIE4_L0_SATA1_RXP_C C84 1 2 0.01U_0201_10V7-K PCIE4_L0_SATA1_RXP
t
PCIE4_L0_SATA1_RXP 10
BI+ BO+
R420 0_0201_5%
2
PCIE4_L0_SATA1_RXN_CONN 1 2 PCIE4_L0_SATA1_RXN_CONN_R 11 4 PCIE4_L0_SATA1_RXN_C C86 1 2 0.01U_0201_10V7-K PCIE4_L0_SATA1_RXN

BI- BO- PCIE4_L0_SATA1_RXN 10
r
R409
4.7K_0201_5% PI2EQX862XUAEX_TQFN18_2X2
reserve 0_0201-R for test. 17 U24_DE_A close to J1
1
CLKREQ_SLECTE DE_A
8 U24_DE_B
DE_B
1
D 2 1 U24_EN# 7
e
2 R352 4.7K_0201_5% EN# 16 U24_EQ_A
G LSK3541G1ET2L 1N VMT3 EQ_A
Q36 SATA_PCIE_SELECT 18 9 U24_EQ_B
GND_PAD
S MODE EQ_B
3
GND1
GND2 VCCRE
c
1.to meet sata express .IFDET is 1.8v ,
2.to meet sata express defination for clkdet
3
12
19
Improve SATA eye diagram, change R348, R349 to ASM
VCCRE VCCRE
2 @ 1 U24_DE_A 2 @ 1
R342 4.7K_0201_5% R346 4.7K_0201_5%
B 2 @ 1 U24_DE_B 2 @ 1 B
1
R343 4.7K_0201_5% R347 4.7K_0201_5%

U24_EQ_A
y
R383 R351 2 @ 1 2 1
4.7K_0201_5% 4.7K_0201_5% R344 4.7K_0201_5% R348 4.7K_0201_5%
2 @ 1 U24_EQ_B 2 1
R377 change to NI , because double pull low R345 4.7K_0201_5% R349 4.7K_0201_5%
t
2
SATA_PCIE_SELECT IFDET PCIE REDR _EN VCCRE

VCCRE
1
C
RF
1
D 2 Q28
f
-PE_DTCT 2 R377 B
LSK3541G1ET2L 1N VMT3 MMBT3904_SOT23-3
G 20K_0201_5% E
3
Q29 @
S 1
3
2 2 2 RF_NS@
a
C273
100P_0201_25V8J
C90 C91 C92
15
U25
6
reserve 0_0201-R for test. 2

1 0.01U_0201_10V7K1 0.01U_0201_10V7K1 1U_0402_10V6K
VDD1
VDD2
close to U1
s
R417 0_0201_5%
PCIE4_L1_TXP C241 1 2 0.01U_0201_10V7-K PCIE4_L1_TXP_C 1 14 PCIE4_L1_TXP_CONN_R 1 2 PCIE4_L1_TXP_CONN
10 PCIE4_L1_TXP AI+ AO+
R418 0_0201_5%
PCIE4_L1_TXN C242 1 2 0.01U_0201_10V7-K PCIE4_L1_TXN_C 2 13 PCIE4_L1_TXN_CONN_R 1 2 PCIE4_L1_TXN_CONN
10 PCIE4_L1_TXN AI- AO-
R415 0_0201_5%
PCIE4_L1_RXP_CONN 1 2 PCIE4_L1_RXP_CONN_R 10 5 PCIE4_L1_RXP_C C243 1 2 0.01U_0201_10V7-K PCIE4_L1_RXP
r
BI+ BO+ PCIE4_L1_RXP 10
R416 0_0201_5%
PCIE4_L1_RXN_CONN 1 2 PCIE4_L1_RXN_CONN_R 11 4 PCIE4_L1_RXN_C C244 1 2 0.01U_0201_10V7-K PCIE4_L1_RXN
BI- BO- PCIE4_L1_RXN 10
VCCRE
reserve 0_0201-R for test. PI2EQX862XUAEX_TQFN18_2X2
17 U25_DE_A close to J1
o
DE_A
8 U25_DE_B
PCIE REDR _EN 7 DE_B
EN# 16 U25_EQ_A
EQ_A
2 1 U25_MODE 18 9 U25_EQ_B
GND_PAD
A MODE EQ_B A
R365 4.7K_0201_5%
F
GND1
GND2
VCCRE
3
12
19
2 @ 1 U25_DE_A 2 @ 1
R356 4.7K_0201_5% R360 4.7K_0201_5%
2 @ 1 U25_DE_B 2 @ 1
R357 4.7K_0201_5% R361 4.7K_0201_5% Title
2 @ 1 U25_EQ_A 2 @ 1 Security Classification LC Future Center Secret Data
R358 4.7K_0201_5% R362 4.7K_0201_5% SATA HDD CONNNECTOR
2 @ 1 U25_EQ_B 2 @ 1
Issued Date 2014/08/10 Deciphered Date 2015/08/10
R359 4.7K_0201_5% R363 4.7K_0201_5% THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Custom
WOLVERINE3 UMA 0.1

5 4 3 2 1
5 4 3 2 1
USB_PWR_S1
J34
1
VBUS 2
D- 3 E_L2
E_L1 D+ 4 2 1
USBP0-_AOU 1 2 GND_1 5 USB3P0_RXN_CONN 2 1 USB3P0_RXN 10
1 2 USBP0-_CONN 10 StdA_SSRX- 6 USB3P0_RXP_CONN
USBP0+_CONN 11 GND_2 StdA_SSRX+ 7 3 4
USBP0+_AOU GND_3 GND_DRAIN USB3P0_TXN_CONN 3 4 USB3P0_RXP 10
y
4 3 12 8
4 3 13 GND_4 StdA_SSTX- 9 USB3P0_TXP_CONN EXC24CH900U_4P
1 GND_5 StdA_SSTX+
EXC24CH900U_4P 2 2
+ SINGA_2UB3908-000101F
l
C99 C100 C101 @
0.1u_0201_10V6K 0.1u_0201_10V6K 150U_B2_6.3VM_R35M
1 1 2
D D
D13
WIDE PATTERN(MIN 500mA) 1 6
PLACE NEAR USB CONN
n
E_L3
2 5 2 1 USB3P0_TXN_C C97 1 2 0.1u_0201_10V6K
2 1 USB3P0_TXN 10
3 4 USB3P0_TXP_C C98 1 2 0.1u_0201_10V6K

3 4 USB3P0_TXP 10
o
USB_PWR_S2 3 4
EXC24CH900U_4P
IP4223CZ6 SO-6 ESD
EXC24CH900U_4P
USBP1- 4 3
10 USBP1- 4 3 USBP1-_CONN
USBP1+_CONN E_L5
USB3P1_RXN_CONN
n
USBP1+ 1 2 J33 2 1
10 USBP1+ 1 2 2 1 USB3P1_RXN 10
1 1
E_L4 VBUS 2
2 2 D- USB3P1_RXP_CONN 3 4
+ 3
D+ 3 4 USB3P1_RXP 10
C104 C102 C103 4
150U_B2_6.3VM_R35M GND_1 5 EXC24CH900U_4P
0.1u_0201_10V6K 0.1u_0201_10V6K StdA_SSRX-
1 1 2 10 6
o
11 GND_2 StdA_SSRX+ 7
12 GND_3 GND_DRAIN 8
13 GND_4 StdA_SSTX- 9
GND_5 StdA_SSTX+
i
SINGA_2UB3908-000101F
@
t
PLACE NEAR USB CONNECTOR
WIDE PATTERN(MIN 500mA)
a
D14
1 6 E_L6
USB3P1_TXN_CONN 2 1 USB3P1_TXN_C C105 1 2 0.1u_0201_10V6K
2 1 USB3P1_TXN 10
C C
USB3P1_TXP_CONN 3 4 USB3P1_TXP_C C106 1 2 0.1u_0201_10V6K
2 5
c
3 4 USB3P1_TXP 10
EXC24CH900U_4P
i
3 4 D16 D15
SP3012-04UTG-1 MO-229 SP3012-04UTG-1 MO-229
IP4223CZ6 SO-6 ESD
if
USB3P1_RXN_CONN 1 9 USB3P1_RXN_CONN
USB3P0_TXP_CONN 1 9 USB3P0_TXP_CONN
USB3P1_RXP_CONN 2 8 USB3P1_RXP_CONN
USB3P0_TXN_CONN 2 8 USB3P0_TXN_CONN
USB3P1_TXN_CONN 4 7 USB3P1_TXN_CONN
USB3P0_RXP_CONN 4 7 USB3P0_RXP_CONN
USB3P1_TXP_CONN 5 6 USB3P1_TXP_CONN
USB3P0_RXN_CONN 5 6 USB3P0_RXN_CONN
t
1st:Infineon ESD3V3U4ULC
3
D229,D230
3
2nd:LittelFuse SP3012-04UTG
VCC5M
e r
c
RF
4.7U_0402_6.3V6M
0.1u_0201_10V6K
1 VCC5M
RF_NS@ 2 2
C274 @
100P_0201_25V8J
C107 C108 C275

2 RF_NS@
1 1 2 1
y
B B
100P_0201_25V8J
Current Limit Target: @
t
2.3A(2.1A - 2.45A) 1 2
C109 4.7U_0402_6.3V6M
USB_PWR_S1
f
U12 USB_PWR_S2
1 12
IN OUT 1 2
13 9 C110 0.1u_0201_10V6K
10 -USB_PORT0_OC0 FAULT# STATUS# -AOU_IFLG 62
U13
2 11 USBP0-_AOU 5 -USB_PORT1_OC1
a
10 USBP0- DM_OUT DM_IN USBP0+_AOU USB_ON1 OC# -USB_PORT1_OC1 10
3 10 4 6
10 USBP0+ DP_OUT DP_IN 62 USB_ON1 3 EN OUT#6 7
4 15 R89
N31995447 1 2 2.7M_0201_5% 2 IN#3 OUT#7 8
5 ILIM_SEL ILIM_LO 16 N30910915 1 2 22.1K_0201_1% 1 IN#2 OUT#8 9
62 USB_ON2 R90
EN ILIM_HI GND_1 GND_2
s
6 G517F1P81U_MSOP8
62 AOU_SEL1 CTL1
7 14
8 CTL2 GND 17
62 AOU_SEL2 CTL3 GPAD change U13 from SA00002Y20J to SA00007E300
TPS2546RTER_QFN16_3X3
r
TABLE of USB3.0 Single
Vendor P/N TI TPS2069DGN
o
TI TPS2546RTER 8/17 SVT modify source table
F
A A

Issued Date 2014/08/10 Deciphered Date 2015/08/10 USB POWER/CONNECTOR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom
WOLVERINE3 UMA 0.1

5 4 3 2 1
5 4 3 2 1
USB_PWR_S2
1/13 swap pin for layout request

EXC24CH900U_4P
y
USBP3-_SYS 4 3
0 USBP3-_SYS 4 3 USBP3-_SYS_CONN
USBP3+_SYS_CONN
l
E_L8
USBP3+_SYS 1 2 J42 USB3P3_RXN_SYS_CONN 2 1
0 USBP3+_SYS 1 2 1 2 1 USB3P3_RXN_SYS 10
1 VBUS
D E_L9 2 D
2 2 D- USB3P3_RXP_SYS_CONN
+ 3 3 4
D+ 3 4 USB3P3_RXP_SYS 10
n
C230 C232 C234 4
150U_B2_6.3VM_R35M GND_1 5 EXC24CH900U_4P
0.1u_0201_10V6K 0.1u_0201_10V6K StdA_SSRX-
1 1 2 10 6
11 GND_2 StdA_SSRX+ 7
12 GND_3 GND_DRAIN 8
GND_4 StdA_SSTX-
o
13 9
GND_5 StdA_SSTX+
SINGA_2UB3908-000101F
@
PLACE NEAR USB CONNECTOR

WIDE PATTERN(MIN 500mA)
2
D54
6
io
USB3P3_TXN_SYS_CONN 2
USB3P3_TXP_SYS_CONN 3
2
3
E_L7
1
4
n
1
4
USB3P3_TXN_SYS_C C236 1
USB3P3_TXP_SYS_C C235 1
2 0.1u_0201_10V6K
2 0.1u_0201_10V6K
USB3P3_TXN_SYS
USB3P3_TXP_SYS
10
10
t
EXC24CH900U_4P
3 4 D53
SP3012-04UTG-1 MO-229
a
IP4223CZ6 SO-6 ESD
C USB3P3_RXN_SYS_CONN 1 9 USB3P3_RXN_SYS_CONN C
USB3P3_RXP_SYS_CONN 2 8 USB3P3_RXP_SYS_CONN
c
USB3P3_TXN_SYS_CONN 4 7 USB3P3_TXN_SYS_CONN
USB3P3_TXP_SYS_CONN 5 6 USB3P3_TXP_SYS_CONN
if i
3
e r t
B
y c B
a f t
r s
A
Title

USB POWER/CONNECTOR
R ev
A
Custom 0.24
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. WOLVERINE3 UMA
5 4 3 2 1
5 4 3 2 1
VCC3GBE
VCC3B
PN: SA000073000; MPN:WGI219LM; For Vpro
2
y
2
PN: SA000072Z00; MPN: WGI219V; For non-Vpro
RL1 RL2
l
10K_0201_5% 10K_0201_5%
1
@
1
D D
12
12
13
-CLKREQ_PCIE3
-PLTRST_FAR
PCIE3_CLK_100M
-CLKREQ_PCIE3
-PLTRST_FAR
48
36
PCIE3_CLK_100M 44
-PCIE3_CLK_100M 45
UL1
CLK_REQ_N
PE_RST_N
PE_CLKP
MDI_PLUS[0]
MDI_MINUS[0]
MDI_PLUS[1]
13
14
17
18
MDI_0+
MDI_0-
MDI_1+
MDI_1-
MDI_0+
MDI_0-
MDI_1+
47
47
47
on
n
12 -PCIE3_CLK_100M PE_CLKN MDI_MINUS[1] MDI_1- 47
PCIE
MDI
PCIE3_RXP CL2 1 2 0.1U_0402_16V7-K PCIE3_RXP_C 38 20 MDI_2+
10 PCIE3_RXP PCIE3_RXN CL3 1 2 0.1U_0402_16V7-K PCIE3_RXN_C 39 PETp MDI_PLUS[2] 21 MDI_2- MDI_2+ 47 Cut in R-short
10 PCIE3_RXN PETn MDI_MINUS[2] MDI_2- 47
0_0201_5% 1 2 RL3
PCIE3_TXP PCIE3_TXP_C MDI_3+
o
CL4 1 2 0.1U_0402_16V7-K 41 23
10 PCIE3_TXP PCIE3_TXN 1 2 0.1U_0402_16V7-K PCIE3_TXN_C 42 PERp MDI_PLUS[3] 24 MDI_3- MDI_3+ 47
CL1
10 PCIE3_TXN PERn MDI_MINUS[3] MDI_3- 47 VCC3GBE
i
Follow Intel spec, change CAP from 0.01U to 0.1UF,
RL4 1 2 100_0201_1% 28 6
7 SML0_CLK 1 2 31 SMB_CLK SVR_EN_N
RL5 100_0201_1%
SMBUS
t
7 SML0_DATA SMB_DATA 1 1 2 4.7K_0201_5%
RL6
RSVD1_VCC3P3
-LANWAKE 2 5
13 -LANWAKE 3 LANWAKE_N VDD3P3_IN
LANPHYPC
13 LANPHYPC LAN_DISABLE_N
a
4
VDD3P3_4
15 CL5 1 2 1U_0402_6.3V6K
C -RJ45_LINKUP 26 VDD3P3_15 19 C
47,62 -RJ45_LINKUP -RJ45_ACTIVITY 27 LED0 VDD3P3_19 29
c
47 -RJ45_ACTIVITY 25 LED1 VDD3P3_29
LED
1 LED2
i
Test_Point_40MIL TP51 @ 47 VCC0R9GBE
1 VDD0P9_47 46
VCC3GBE
Test_Point_40MIL TP52 @ 32 VDD0P9_46 37
@ 34 JTAG_TDI VDD0P9_37
if
Cystal vendor suggestion 1 2 10K_0201_5% 33 JTAG_TDO 43
KEEP SHORT AND WIDE
RL7
JTAG
RL8 1 @ 2 10K_0201_5% 35 JTAG_TMS VDD0P9_43 PATTERN
JTAG_TCK 11
RL9 VDD0P9_11
1 2 9 40
t
10 XTAL_OUT VDD0P9_40 22
XTAL_IN VDD0P9_22 16
100_0201_1% VDD0P9_16 8
VDD0P9_8
r
30
TEST_EN
12 7 VCC0R9GBE_L FL6 1 2 4.7UH_FLF3215T-4R7M_20%
YL1 25MHZ_18PF_8Y25000004 RBIAS CTRL0P9
49
e
1 3 GND change FL6 from SHI0000FS0T to SHI0000FK00
1 3
GND1 GND2 WGI219LM-QREF-A0_QFN48_6X6 2 2
CL6 2
2
2
2 2 22U_0603_6.3V6M CL7 CL9
c
2 4 RL10 RL11 0.1U_0201_6.3V6K
0.1U_0201_6.3V6K
1 1
CL8 CL10 1K_0201_5% 3.01K_0201_1% 1 @
27P_0201_25V8J Change CL6 from 0805 to 0603
27P_0201_25V8J
1 1
1
y
B B
KDS 1ZZHAE25000CC0A
TXC 8Y25000004
EPSON Q22FA1280023800
a f t VCC3LAN
change R395
1
R395
from SD00001778T (0.001_0603_5% ) to SD000016Z0T (0.001_0603_5%)
2
VCC3GBE
r s 2
1
CL11
0.1U_0201_6.3V6K
2
1
CL12
0.1U_0201_6.3V6K
0.001_0603_5%
Change CL13
2
from 0805 to 0603

CL13
22U_0603_6.3V6M
2
1
CL14
0.1U_0201_6.3V6K
Deciphered Date
2015/08/10
Title
GBE CLARKVILLE

A
WOLVERINE3 UMA
Date: Friday, August 21, 2015 Sheet 46 of 100
5 4 3 2 1
5 4 3 2 1
D
VCC3GBE
n ly D
0.1U_0201_6.3V6K
0.1U_0201_6.3V6K
0.1U_0201_6.3V6K
0.1U_0201_6.3V6K
0.1U_0201_6.3V6K
o
VCC3GBE
2 2 2 2 2
n
2
1 1 1 1 1
C111
C112
C113
C114
C115
R91
4.7K_0201_5%
1
io
39
30
21
14
8
4
1
t
VDD7
VDD6
VDD5
VDD4
VDD3
VDD2
VDD1
38 DOCK_MDI_3-
B0+ 37 DOCK_MDI_3+ DOCK_MDI_3- 60
MDI_3- 2 B0- DOCK_MDI_3+ 60
46 MDI_3- A0+
a
34 DOCK_MDI_2-
MDI_3+ 3 B1+ 33 DOCK_MDI_2+ DOCK_MDI_2- 60
46 MDI_3+ A0- B1- DOCK_MDI_2+ 60
C 29 DOCK_MDI_1- C
MDI_2- 6 B2+ 28 DOCK_MDI_1+ DOCK_MDI_1- 60
if c
46 MDI_2- A1+ B2- DOCK_MDI_1+ 60
MDI_2+ 7 25 DOCK_MDI_0-
46 MDI_2+ A1- B3+ 24 DOCK_MDI_0+ DOCK_MDI_0- 60
B3- DOCK_MDI_0+ 60
MDI_1- 9 17
46 MDI_1- A2+ LEDB0 18
MDI_1+ 10 LEDB1 41
46 MDI_1+ A2- LEDB2
SYS_MDI_3-
i
36
MDI_0- 11 C0+ 35 SYS_MDI_3+ SYS_MDI_3- 48
46 MDI_0- A3+ C0- SYS_MDI_3+ 48
rt
MDI_0+ 12 32 SYS_MDI_2-
46 MDI_0+ A3- C1+ 31 SYS_MDI_2+ SYS_MDI_2- 48
C1- SYS_MDI_2+ 48
-DOCK_ATTACHED_AUX 13 27 SYS_MDI_1-
60 -DOCK_ATTACHED_AUX SEL C2+ 26 SYS_MDI_1+ SYS_MDI_1- 48
C2- SYS_MDI_1+ 48
R92 2 1 0_0201_5% 15 23 SYS_MDI_0-
46 -RJ45_ACTIVITY 2 1 16 LEDA0 C3+ 22 SYS_MDI_0+ SYS_MDI_0- 48
e
46 -RJ45_LINKUP R93 0_0201_5% LEDA1 C3- SYS_MDI_0+ 48
42
LEDA2 19 R94 1 2 0_0201_5% -RJ45_ACTIVITY_SYS 49
Cut in R-short 5 LEDC0 20 R95 1 2 0_0201_5% -RJ45_LINKUP_SYS 49
PD LEDC1 40
c
43 LEDC2
PAD_GND Cut in R-short
U14
PI3L720ZHE+CX_TQFN42_9X3P5
y
B B
t
Change LAN switch to SA00007E900
s a f U87
Vendor P/N
r
Pericom PI3L720ZHE
ST micro STMUX1800E
Onsemi NCN7201
Title
GBE LAN SWITCH

A
WOLVERINE3 UMA
5 4 3 2 1
5 4 3 2 1
47 SYS_MDI_3-
SYS_MDI_3-
1
T1
TD1+
1:1
T1/B 24 RJ45_TXD3N
TX1+ RJ45_TXD3N 49
SYS_MDI_3+ 2
47 SYS_MDI_3+ TD1-
23 RJ45_TXD3P
TX1- RJ45_TXD3P 49
y
T1_Pin3 3 22 T1_Pin22
TDCT1 T1/A TXCT1
l
4 21 T1_Pin21
SYS_MDI_2- TDCT2 1:1 TXCT2
5 T1/B
D 47 SYS_MDI_2- TD2+ 20 RJ45_TXD2N D
TX2+ RJ45_TXD2N 49
n
SYS_MDI_2+ 6
47 SYS_MDI_2+ TD2- 19 RJ45_TXD2P
TX2- RJ45_TXD2P 49
o
T1/A
SYS_MDI_1- 1:1
7
47 SYS_MDI_1- TD3+ T1/B
18 RJ45_TXD1N
TX3+ RJ45_TXD1N 49
SYS_MDI_1+ 8
n
47 SYS_MDI_1+ TD3-
17 RJ45_TXD1P
TX3- RJ45_TXD1P 49
9 16 T1_Pin16
TDCT3 TXCT3
o
T1/A
10 15 T1_Pin15
TDCT4 1:1 TXCT4
i
SYS_MDI_0- 11
47 SYS_MDI_0- TD4+ T1/B RJ45_TXD0N
14
TX4+ RJ45_TXD0N 49
75_0805_5%
75_0805_5%
75_0805_5%
75_0805_5%
SYS_MDI_0+ 12
47 SYS_MDI_0+ TD4- 13 RJ45_TXD0P
TX4- RJ45_TXD0P 49
a
T1/A
C C
2
TDK_TLA-7T231HF-T
if c
THE WIDTH OF THESE TRACE SHOULD
BE WIDER THAN 35MIL TO PREVENT
R96 1
R97 1
R98 1
R99 1
VOLTAGE DROP.
0.1U_0201_6.3V6K
0.1U_0201_6.3V6K
0.1U_0201_6.3V6K
0.1U_0201_6.3V6K
0.1U_0201_6.3V6K
0.1U_0201_6.3V6K
1U_0402_6.3V6K
PATTERN MUST BE
SHORT AND WIDE.
i
2
2
rt
C122
R100 100P_1808_2KV
2 2 2 2 2 2 2 1
1M_0805_5%
@ @
HIGH VOLTAGE
1
C303 1500PF CAP
SHOULD BE PLACED AS CLOSE 1 1 1 1 1 1 1 IS OPTIONAL
C116
C117
C118
C119
C120
C121
C123
TO MAGNETICS AS POSSIBLE.
e
12/29 add 2nd T2
SYS_MDI_3- 1 1:1
TD1+ T1/B RJ45_TXD3N
c
24
TX1+
SYS_MDI_3+ 2
TD1-
23 RJ45_TXD3P
ESD REASON TX1-
T1_Pin3 3 22 T1_Pin22
y
B B
TDCT1 T1/A TXCT1
T1_Pin21
t
4 21
Vendor P/N SYS_MDI_2- 5 TDCT2 1:1
T1/B
TXCT2
TD2+ 20 RJ45_TXD2N
TX2+
f
TDK TLA-7T231HF-T
SYS_MDI_2+ 6
Timag IH-115-F TD2- 19 RJ45_TXD2P
a
TX2-
Bothand NA69LF T1/A
s
SYS_MDI_1- 1:1
7
TD3+ T1/B RJ45_TXD1N
18
TX3+
SYS_MDI_1+ 8
TD3-
r
17 RJ45_TXD1P
TX3-
9 16 T1_Pin16
TDCT3 T1/A TXCT3
o
10 15 T1_Pin15
SYS_MDI_0- TDCT4 1:1 TXCT4
11 T1/B
TD4+ 14 RJ45_TXD0N
TX4+
F
A
SYS_MDI_0+ 12 A
TD4- 13 RJ45_TXD0P
TX4-
T1/A
IH_189-A

Issued Date 2014/08/10 Deciphered Date 2015/08/10 GBE MAGNETICS
WOLVERINE3 UMA
5 4 3 2 1
5 4 3 2 1
1. Follow EMC suggestion, change TVS Diode to SC300003N00.
n ly D
o
2. Change VCC3GBE/GND to NC
4
DL1
SRV05-4HTG SOT23-6 ESD
3
48
48
48
48
RJ45_TXD1P
RJ45_TXD1N
RJ45_TXD3P
RJ45_TXD3N
RJ45_TXD1P
RJ45_TXD1N
RJ45_TXD3P
RJ45_TXD3N
VCC3GBE
t io
a
1U_0402_10V6K
330_0402_5%
330_0402_5%
C C
4
DL2
2
if c
SRV05-4HTG SOT23-6 ESD 2
RL12
RL13
CL15
1
1
J3
10
Green_LED-
3
GREEN_LED 9
Green_LED+
i
47 -RJ45_LINKUP_SYS 1 16
RJ45_TXD0P PR1+ G4
48 RJ45_TXD0P RJ45_TXD0N 2 15
rt
48 RJ45_TXD0N PR1- G3
RJ45_TXD2P 3
48 RJ45_TXD2P RJ45_TXD2N PR2+
48 RJ45_TXD2N 4
PR3+
5
PR3-
6
47 -RJ45_ACTIVITY_SYS PR2-
e
7 14
PR4+ G2
0.1u_0201_10V6K
0.1u_0201_10V6K
8 13
PR4- G1
12
Yellow_LED-
c
YELLOW_LED 11
Yellow_LED+
2 2
SINGA_2RJ3047-108411F
RL14
RL15
1 1
B B
f t y
s a
A
o r A
5
F 4 3
Deciphered Date
2
2015/08/10
Title
Custom
Date:
RJ45 CONNECTOR

WOLVERINE3 UMA
1
Sheet 49 of 100
Rev
0.1
5 4 3 2 1
TYPE-B NGFF CCARD FOR WWAN
VCC3WAN
3.2H CONNECTOR
VCC3WAN
2
R101
CONN@ 47K_0201_5%
y
J22
1 2
1
8 WWAN_CFG3 3 CONFIG_3 3.3VAUX1 4
5 GND1 3.3VAUX2 6
2 1 0_0201_5% USBP2+_CONN 7 GND2 FULL_CARD_POWER_OFF# 8 -WWAN_DISABLE
R102
l
10 USBP2+ 2 1 0_0201_5% USBP2-_CONN 9 USB_D+ W_DISABLE#1 10 -WWAN_DISABLE 61
10 USBP2- R103
D 11 USBD- LED#1/DAS/DSS# D
GND3 NC 12
Cut in R-short 13 NC NC 14
15 NC NC 16
17 NC NC 18
19
20
NC GPIO_5
21 22
8 WWAN_CFG0 23 CONFIG_0 GPIO_6 24
WAKE_ON_WWAN# GPIO_7
n
25 26
27 DPR W_DISABLE#2 28
29 GND4 UIM-RFU 30 UIM_RESET
10 SSIC_RXN USB3.0-TX-(Device) UIM-RESET UIM_CLK
31 32 R104 1 2 200_0201_1%
10 SSIC_RXP 33 USB3.0-TX+(Device) UIM-CLK 34 UIM_DATA @ J25
35 GND5 UIM-DATA 36 UIM_PWR 1 9
10 SSIC_TXN 37 USB3.0-RX-(Device) UIM-PWR 38 2 VCC SWITCH
10 SSIC_TXP 39 USB3.0-RX+(Device) DEVSLP 40 3 RESET
41 GND6 GPIO_0 42 CLOCK
o
43 PERN0/SATA-B+ GPIO_1 44 4
@ D17 45 PERP0/SATA-B- GPIO_2 46 5 Reserved1 10
47 GND7 GPIO_3 48 6 GND1 GND2 11
VCC3WAN RCLAMP0502BPTCT_SC75-3 49 PETN0/SATA-A- GPIO_4 50 7 VPP_SWP GND3 12
51 PETP0/SATA-A+ PERST# 52 8 IO GND4 13
1
53 GND8 CLKREQ# 54 Reserved2 GND5
55 REFCLKN PEWAKE# 56
57 REFCLKP NC1 58 RF_NS@
GND9 NC2
2
1
2
3
5
2
59 60 R423 1 2 0_0201_5% COEX3 JAE_SF11V006S4C
G
@ 61 ANTCTL0 COEX3 62 R424 1 RF_NS@2 0_0201_5% COEX2 D18 C124

Q30 63 ANTCTL1 COEX2 64 R425 1 2 0_0201_5% COEX1 4.7U_0402_6.3V6M
1
65 ANTCTL2 COEX1 66 RF_NS@ FTZ6.8EGT148_SC-74A5
4
1 3 67 ANTCTL3 SIM_DETECT 68
D
n
63 EC_WWAN_RESET# 69 RESET# SUSCLK 70 @
8 WWAN_CFG1 CONFIG_1 3.3VAUX3
71 72
73 GND10 3.3VAUX4 74
LSK3541G1ET2L 1N VMT3 75 GND11 3.3VAUX5
8 WWAN_CFG2 CONFIG_2 VCC3WAN
76 77
R408 PEG1 PEG2 RF
2 1 8/20 SVT EMC cost down plan
o
TYCO_2199230-3
0_0201_5%
2
2 @
2
C126 C127 1 2
Change Q30 to NO-ASM for WWAN lose issue C125 1U_0402_6.3V6K RF_NS@ RF_NS@
1
i
0.1U_0201_6.3V6K 10U_0603_6.3V6M C278 C277
1
1
100P_0201_25V8J
47P_0201_25V8J
2 1
t
C TYPE-A NGFF CCARD FOR WLAN C
RF
3.2H CONNECTOR
a
VCC3WLAN
VCC3B
2
VCC3WLAN VCC3B VCC3B 2 2 1 2 @
2
R370 C129 1 2 1 1
c
10K_0201_5% C305 C304 C303 C128 C130 10U_0603_6.3V6M RF_NS@ RF_NS@ RF_NS@ RF_NS@
0.01U_0201_6.3V7K0.1U_0201_6.3V6K4.7U_0402_6.3V6M 0.1U_0201_6.3V6K C280 C279 C299 C300
1
1 1 2 1 1U_0402_6.3V6K
0.01U_0201_10V7-K
1
100P_0201_25V8J
0.01U_0201_10V7-K
47P_0201_25V8J
R368 2 1 2 2
2
Cut in R-short J32 CONN@ 100K_0201_5%
i
1 2 R108
USBP6+_CONN GND1 3.3VAUX1
10 USBP6+
USBP6+ R105 2 1 0_0201_5%
USBP6-_CONN
3 4 10K_0201_5%
USB_D+ 3.3VAUX2
10 USBP6-
USBP6- R106 2 1 0_0201_5% 5 6
7 USB_D- LED#1
8
1
9
GND2 NC
10
Add 3x Cap pad on VCC3WLAN line near M.2 Slot
NC NC
if
11 NC NC 12
13 NC NC 14
15
16
NC LED#2
17 18
WIGIG_DP3N C249 2 1 0.1U_0201_6.3V6K WIGIG_DP3N_C 19 MLDIR_SENSE GND16 20 WIGIG_AUXN
29 WIGIG_DP3N WIGIG_DP3P C250 0.1U_0201_6.3V6K WIGIG_DP3P_C DP_ML3N DP_AUXN WIGIG_AUXP WIGIG_AUXN 29
2 1 21 22
29 WIGIG_DP3P 23 DP_ML3P DP_AUXP 24 WIGIG_AUXP 29
WIGIG_DP2N C251 2 1 0.1U_0201_6.3V6K WIGIG_DP2N_C 25 GND3 GND13 26 WIGIG_DP1N_C C245 2 1 0.1U_0201_6.3V6K WIGIG_DP1N
29 WIGIG_DP2N WIGIG_DP2P C252 0.1U_0201_6.3V6K WIGIG_DP2P_C DP_ML2N DP_ML1N WIGIG_DP1P_C C246 0.1U_0201_6.3V6K WIGIG_DP1P WIGIG_DP1N 29
2 1 27 28 2 1
29 WIGIG_DP2P 29 DP_ML2P DP_ML1P 30 WIGIG_DP1P 29
WIGIG_HPD GND4 GND14 WIGIG_DP0N_C WIGIG_DP0N
t
31 32 C247 2 1 0.1U_0201_6.3V6K
29 WIGIG_HPD 33 DP_HPD DP_ML0N 34 WIGIG_DP0P_C C248 2 1 0.1U_0201_6.3V6K WIGIG_DP0P WIGIG_DP0N 29
PCIE2_TXP C253 2 1 0.1U_0201_6.3V6K PCIE2_TXP_C 35 GND5 DP_ML0P 36 WIGIG_DP0P 29
10 PCIE2_TXP PCIE2_TXN C254 0.1U_0201_6.3V6K PCIE2_TXN_C PETP0 GND15 -CL_RST_WLAN
2 1 37 38
10 PCIE2_TXN 39 PETN0 RESERVED1 40 CL_DATA_WLAN -CL_RST_WLAN 7
PCIE2_RXP GND6 RESERVED2 CL_CLK_WLAN CL_DATA_WLAN 7
41 42
r
10 PCIE2_RXP PCIE2_RXN 43 PERP0 RESERVED3 44 CL_CLK_WLAN 7
COEX3
10 PCIE2_RXN 45 PERN0 COEX3 46 COEX2
PCIE2_CLK_100M 47 GND7 COEX2 48 COEX1
12 PCIE2_CLK_100M -PCIE2_CLK_100M 49 REFCLKP0 COEX1 50 SUSCLK_32K
12 -PCIE2_CLK_100M REFCLKN0 SUSCLK -PLTRST_FAR SUSCLK_32K 12
51 52
-CLKREQ_PCIE2 53 GND8 PERST0# 54 -PLTRST_FAR 13
12 -CLKREQ_PCIE2 -PCIE_WAKE 55 CLKREQ0# RESERVED/W_DISABLE#2 56 -WiGig_RF_KILL BDC_ON 61
13,71 -PCIE_WAKE PEWAKE0# W_DISABLE#1 -WiGig_RF_KILL 61
57 58
e
PCIE1_TXP C220 2 1 0.1U_0201_6.3V6K PCIE1_TXP_C 59 GND9 I2C_DATA 60
Add Port/Device define table 10 PCIE1_TXP PCIE1_TXN PCIE1_TXN_C PETP1 I2C_CLK
C219 2 1 0.1U_0201_6.3V6K 61 62
10 PCIE1_TXN 63 PETN1 I2C_ALERT# 64
PCIE1_RXP 65 GND10 RESERVED4 66
B 10 PCIE1_RXP PCIE1_RXN PERP1 PERST1# -CLKREQ_PCIE1 B
67 68
10 PCIE1_RXN 69 PERN1 CLKREQ1# 70 -PCIE_WAKE -CLKREQ_PCIE1 12
PCIE1_CLK_100M 71 GND11 PEWAKE1# 72
12 PCIE1_CLK_100M -PCIE1_CLK_100M REFCLKP1 3.3VAUX4
c
73 74
12 -PCIE1_CLK_100M 75 REFCLKN1 3.3VAUX5
GND12
76 77 R369
PEG1 PEG2
2
100K_0201_5%
3
@ D19 TYCO_2199230-8
RCLAMP0502BPTCT_SC75-3
1
1
f t y
A
s a A
o r Security Classification
Title
PCIE MINI CARD SLOT
F
D
WOLVERINE3 UMA 0.1

5 4 3 2 1
5 4 3 2 1
10U_0603_6.3V6M
VCC3B
VCC3_MC VCC3B
VCC3B
ly
4.7U_0402_6.3V6M
10U_0603_6.3V6M
0.1U_0201_6.3V6K
0.1U_0201_6.3V6K
2
2 2
D D
C131 C132
2
10K_0201_5%
1
C133
R109
1 1
2 2
2
10K_0201_5%
o
R110
1 1
C134
C135
1
U15
n
11 30 -SD_MMC_CD
3V3_IN SD_CD# -SD_MMC_CD 52
C136 2 1 1U_0402_6.3V6K 18 31
DV33_18 MS_INS#
DAV12 10 32
AV12 WAKE#
o
14
DV12S
i
15 SD_MMC_D1
SP1 SD_MMC_D1 52
12 16 SD_MMC_D0
t
Card_3V3 SP2 SD_MMC_D0 52
17 SD_MMC_CLK R111 1 2 0_0201_5%
Follow vendor suggest, change to 0 ohm
SP3 SD_MMC_CLK_R 52
27
3V3aux 19 SD_MMC_CMD
SP4 SD_MMC_CMD 52
a
9 20 SD_MMC_D3
RREF SP5 SD_MMC_D3 52
21 SD_MMC_D2
SP6 SD_MMC_D2 52
C PCIE0_TXP CC74 1 2 0.1U_0201_6.3V6K PCIE0_TXP_C 3 29 SD_MMC_WP C
10 PCIE0_TXP HSIP SD_MMC_WP 52
if c
SP7
VCC3B PCIE0_TXN CC75 1 2 0.1U_0201_6.3V6K PCIE0_TXN_C 4
10 PCIE0_TXN HSIN C138
PCIE0_RXP C137 1 2 0.1U_0201_6.3V6K PCIE0_RXP_C 7 1 2
10 PCIE0_RXP HSOP
PCIE0_RXN C139 1 2 0.1U_0201_6.3V6K PCIE0_RXN_C 8 13
10 PCIE0_RXN HSON NC1 6P_0201_25V8-D
22
NC2
2
PCIE0_CLK_100M 5 23
12 PCIE0_CLK_100M REFCLKP NC3 C297
i
R112 -PCIE0_CLK_100M 6 24 1 2
12 -PCIE0_CLK_100M REFCLKN NC4
10K_0201_5%
25
rt
1
NC5 1U_0402_6.3V6K
-PLTRST_NEAR 1 26 @
13 -PLTRST_NEAR PERST# NC6
-CLKREQ_PCIE0 2
12 -CLKREQ_PCIE0 CLK_REQ#
0.1U_0201_6.3V6K
2 28 33
GPIO GND
e
6.19K_0201_1% R113
RTS5232S-GR_QFN32_4X4
1
4.7U_0402_6.3V6M
0.1U_0201_6.3V6K
2 2
c
2
C140 C141
1 1
1
C142
y
B B
a f t
r s
A
Title
MEDIA CARD CONTROLLER
A
WOLVERINE3 UMA
5 4 3 2 1
5 4 3 2 1
n ly D
VCC3_MC
2 2
n o
o
CW1 CW2
10U_0603_6.3V6M
1 0.1U_0201_6.3V6K
i
1
t
J23 CONN@
SD_MMC_D3
Cut in R-short
1 4
51 SD_MMC_D3 SD_MMC_CMD SD_MMC_CMD_R CD/DAT3 VDD
0_0201_5% 2 1 RW1 2
51 SD_MMC_CMD CMD
a
SD_MMC_CLK_R 5 3
51 SD_MMC_CLK_R SD_MMC_D0 7 CLK VSS1 6
51 SD_MMC_D0 SD_MMC_D1 8 DAT0 VSS2
C 51 SD_MMC_D1 SD_MMC_D2 9 DAT1 13 C
51 SD_MMC_D2 SD_MMC_WP 12 DAT2 GND1 14
c
51 SD_MMC_WP -SD_MMC_CD 10 WP GND2 15
51 -SD_MMC_CD 11 CD GND3 16
COM GND4
i
ALPS_SCDAAA0604
r t if
ce
y
B B
a f t
r s
A
Title
MEDIA CARD INTERFACE

A
WOLVERINE3 UMA
5 4 3 2 1
5 4 3 2 1
D
VCC5B
ly D
2
n
F8
0.5A_32V_ERBRD0R50X
1
9
10
10
USBP4-
USBP4+
-SC_DTCT
-SC_DTCT
2
2
4
6
8
10
12
2
4
6
8
10
GND2
ME@ J26
1
3
5
7
9
GND1
1
3
5
7
9
11
n o
o
HRS_DF12L3P010DP0P5V86
C143
0.1u_0201_10V6K
1
a t i C
i c
r t if
B
ce B
f t y
s a
A
o r A
5
F 4 3
2
Title
Custom
Date:
SMART CARD I/F

WOLVERINE3 UMA
1
Sheet 53 of 100
Rev
0.1
5 4 3 2 1
y
VCC3BA
l
D VCC5BA VCC5B
D
VCC3_SUS
1
1 RJA4
4.7U_0402_6.3V6-M
1
RF_NS@
1
n
CA60 JUMP_43X39
CA1
2
100P_0201_25V8J
2
2
RJA1
1
2
1
JUMP_43X39
4.7U_0402_6.3V6-M
0.1u_0201_10V6K
CA15 CA16
VCC1R8_SUSA 1
2
place close to PIN3 RF_NS@
2
VCC1R8_SUSA VCC3B 1
CA61
2
o
100P_0201_25V8J
2
4.7U_0402_6.3V6-K
4.7U_0402_6.3V6-K
0.1u_0201_10V6K
0.1u_0201_10V6K
2 2 2 2 CA62 1
RF_NS@
1 CA17 CA18 CA19 CA20
1
0.1U_0201_6.3V6K
RF_NS@
1
1
CA58 RF_NS@ 2 RJA2 1
100P_0201_25V8J
1 1 1
1
RJA3 2
1
CA57 JUMP_43X39
100P_0201_25V8J
2 CA2 JUMP_43X39
100P_0201_25V8J
2
2
change CA17 / CA18 / CA19@/ CA20 from ASM@ to NI for follow codec vendor suggestion
2
1 CA21 @ @
2
1 2
2.2U_0201_6.3V6-M
100K_0201_5%
8/20 SVT add 100K ohm for vendor suggestion
2
1
0.1u_0201_10V6K
0.1u_0201_10V6K
1U_0201_6.3V6-K
4.7U_0402_6.3V6-M
1 2 2 2 CA6
RF_NS@
CA59 CA3 CA4 CA5
1
100P_0201_25V8J
o
2 1 1 1
40
38
27
41
46
25
21
3
RA53
UA1
CA22
VREF
AVDD2
AVDD1
PVDD1
PVDD2
DVDD-IO
DVDD
CPVDD
LDO1-CAP
10U_0603_6.3V6M
1
change CA22 from 4.7U_0402 to 10U_0603 for follow codec vendor suggestion
i
I2S_CTRL 1 23
60 I2S_CTRL I2S-I/F-FLOAT LINE1-VREFO LINE1_VREFO 57
-HDA_RST 11 29
MIC_SLEEVE 55,57
t
9 -HDA_RST RESET# LINE1-R/SLEEVE 28 8/28 SVT Follow vendor suggestion, change RA7 and RA8 to 137 ohm.
change RA2/RA3 from SD00000LHPT (33_5% ) to SD00000LHYT (33_5%) LINE1-L/RING2 MIC_RING2 55,57
6 33 RA7 1 2 137_0201_1% HP_L_JACK 55
C
9 HDA_BCLK HDA_SYNC BCLK HP-OUT-L C
9 HDA_SYNC 10 32 RA8 1 2 137_0201_1% HP_R_JACK 55
HDA_SDIN0 EMC@ 2 1 HDA_SDIN0_R 8 SYNC HP-OUT-R
9 HDA_SDIN0 RA2 33_0201_5%
HDA_SDO 5 SDATA-IN 30 VCC3B
9 HDA_SDO SDATA-OUT MIC1-VREFO 100K_0201_5% change RA10/11 from SD0431003PT(100k_0201_5% ) to SD0431003YT(100k_0201_5%)
RA101 2
19
a
DMIC_CLK RA3 DMIC_CLK_R MIC1-L
38 DMIC_CLK EMC@ 2 1 33_0201_5% 2 20 RA111 100K_0201_5%
2
DMIC_DATA 4 GPIO0/DMIC-CLK MIC1-R I2S_OUT_JD 55
38 DMIC_DATA GPIO1/DMIC-DATA12 Cut in R-short
1 2 I2S_IN_JD 56
48 22 RA12 200K_0201_5%
63 -SPK_MUTE EAPD+PD JD3(AUX MODE/LINE1) 13 RA9 1 2 0_0201_5%
BEEP_MIX_ATT JD1(HP/MIC1) HP_JD 56
CA7 1 2 0.1U_0201_6.3V6K 12 ALC3245-GRT_MQFN48_6X6 14
59 BEEP_MIX_ATT PCBEEP JD2(I2S)
@
c
add -SPK MUTE signal from EC connector to codec 15 RA13 2 1 0_0201_5% DOCK_I2S_MCLK 60
31 I2S_MCLK 16 RA14 2 1 0_0201_5% DOCK_I2S_BCLK 60
delete RA4 to NI for follow codec vendor suggestion MIC-CAP I2S_SCLK 17 RA15 2 1 0_0201_5% DOCK_I2S_SD_O 60
7 I2S_DOUT 18 RA16 2 1 0_0201_5%
LDO3-CAP I2S_LRCK DOCK_I2S_LRCLK 60
24 RA17 2 1 0_0201_5% DOCK_I2S_SD_I 60
i
39 I2S_DIN
2 2
LDO2-CAP
33P_0201_25V8J
33P_0201_25V8J
45
33P_0201_25V8J
33P_0201_25V8J
SPK-OUT-R+
1
47 44
RF_NS@ CA23
CA24
GPIO2/DMIC-DATA34/SPDIF-OUT SPK-OUT-R- 1 1
1
RA44 42
10K_0201_5% SPK-OUT-L+ 43
Follow Realtek suggest, change RA14 to pull low RA18
2
if
36 SPK-OUT-L-
10K_0201_5%
RF_NS@
CBP CA27
GND-PAD
1 CA12 CA13 2 2
2
10U_0603_6.3V6M 10U_0603_6.3V6M 35 34 2 1
AVSS2
AVSS1
CA26
1
CA25
2
CA11 CBN CPVEE
@ @
22P_0201_25V8-J
33P_0201_50V8J
2 change CA12 /CA13 from 4.7U_0402 to 10U_0603 for follow codec vendor suggestion 1U_0201_6.3V6 1 1
2 EMC@
49
37
26
33P_0201_50V8J
CA8
2
47K_0201_5%
2
1 2
t
RA5
CA14
1
CA9 1 1U_0201_6.3V6
1
SP_OUTR+_L SP_OUTR+
2
@ EMC@ FLA1 1 2 BLM18SG260TN1D_2P

CA10 SP_OUTR-_L SP_OUTR- SP_OUTR+ 58
EMC@ FLA2 1 2 BLM18SG260TN1D_2P
r
10U_0603_6.3V6M SP_OUTL-_L SP_OUTL- SP_OUTR- 58
change AVSS2 DGND to AGND for meet spec EMC@ FLA3 1 2 BLM18SG260TN1D_2P
1
SP_OUTL+_L SP_OUTL+ SP_OUTL- 58

EMC@ FLA4 1 2 BLM18SG260TN1D_2P
SP_OUTL+ 58
change CA10 from 4.7U_0402 to 10U_0603 for follow codec vendor suggestion
CLOSE TO J4
B
VCC5B
1
RJA5
JUMP_43X39
2
2
VCC5BA Add CA71_0.1u / CA72_10U for follow codec vendor suggestion
ce 1
1
CA37
0.01U_0201_10V7K
CA38
2
2
@
EMC@ EMC@ EMC@ EMC@

B
0.1u_0201_10V6K
0.1u_0201_10V6K
0.1u_0201_10V6K
@ CA28 CA29 CA30 CA31

10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
2 2 2
1000P_0201_25V7K
2
100P_0201_25V8J
1000P_0201_25V7K
1000P_0201_25V7K
2 2 2 2
1000P_0201_25V7K
CA32 CA33 CA35 CA36 CA71 CA72
1
y
1 1 1
1 1 1 1
CA34 @
1 2 RA6
2 1
t
0.01U_0201_10V7K 0_0402_5%
PLACE UNDER CODEC
f
VCC3B VCC3BA
RJA6
1 2
1 2
JUMP_43X39
a
VCC5M
0.1u_0201_10V6K
0.1u_0201_10V6K
@
10U_0603_6.3V6M
10U_0603_6.3V6M
2 2
2
CA39 CA40 CA42 CA43

1
1 1
0.1U_0402_25V7K
s
CA41
2
CA68
1 2
VCC1R8_SUS
1
@ 0.01U_0201_10V7K VCC1R8_SUSA
1
UA2 @
VDD
A 3 4 A
r
D S
VCC1R8_SUS VCC1R8_SUSA
2 5
72 BPWRG ON CAP
RA45 1 2 0.01_1206_LE_1%
GND
0.1u_0201_10V6K
0.1u_0201_10V6K
SLG5NT1533VTR_STDFN8-6_1X1P6
6
o
10U_0603_6.3V6M
10U_0603_6.3V6M
2 2 1
2
CA69 1
CA66 CA65 CA67 CA64 10U_0603_6.3V6M
@
CA70
1
1 1 2
@ 220P_0201_25V7K
2
CA63 @
1 2 Title
Security Classification LC Future Center Secret Data
Follow THP1_SWG_SIT_EC026 @ 0.01U_0201_10V7K Issued Date 2012/05/02 Deciphered Date 2012/5/02 054_AUDIO ALC3245-GRT
F
Change ASM to NA (UA2,CA68, CA69 CA70)
Change ASM to NA (UA2,CA68, CA69 CA70) Change NA to ASM (RA45) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Change NA to ASM (RA45) Size Document Number Rev
WOLVERINE3 UMA
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 0.1
5 4 3 2 1
5 4 3 2 1
54 HP_L_JACK
HP_L_JACK
NEAR AUDIO CONN
1
FLA5
2
n ly D
54 HP_R_JACK
HP_R_JACK 1
FLA6
2
n o
1000P_0201_25V7K
1000P_0201_25V7K
2 2
2
RA19 RA20 CA44 CA45
@ @
220_0201_5% 220_0201_5%
1 1
o
0603_1/20w 0603_1/20w
1
C
WIDE AND SHORT PATTERN
a t i MIC_SLEEVE
MIC_RING2
54
54
C
i c
if
VCC3B
t
1
10K_0201_5% RA21
r
2
e
J19 ME@
4 MIC_SLEEVE
3 MIC_RING2 MIC_RING2
7 1 HP_L_JACK_conn
HP_R_JACK_conn
c
8 2
5
6 HP_JACK_OUT
HP_JACK_OUT 56
DA6
SINGA_2SJ3052-012111F DAN222MGT2L_VMD3
2
B 1 HP_JACK_IN B
3 HP_JACK_IN 61,63
y
RSB5.6SGTE61_SC-79-2-2
VCC3B
2
100K_0201_5%
2
RA25
t
EMC_NS@
VCC3B 470K_0201_1%
DA4 DA5
1
EMC@ EMC@
f
100K_0201_5%
RA22 1
1
2
CA46
1
RA24
DA1 DA2 1 2
I2S_OUT_JD 54
4.7K_0201_5%
2
2
2
EMC_NS@
a
1U_0402_10V6K
RA23
1
RA48
1
DA3 D
EMC@ HP_JACK_DOCK 2 1 2
1
RSB5.6SGTE61_SC-79-2-2 G
s
1
22K_0201_5% 2SK3541_VMT3 S
3
2 QA1 QA6
60 -DOCK_HP_DCT
DTC115EMGT2L_VMT3
3
A
o r Add RA48 / QA6 for docking HP issue
5
F 4 3
Deciphered Date
2
2012/5/02
Title
Date:
AUDIO CONNECTOR
Custom
C WOLVERINE3 UMA
1
Sheet 55 of 100
Rev
0.1
5 4 3 2 1
n ly D
o
@
RA26 add RA46_200K / RA47_100K for improve HP_JD driving by vendor suggestion
1 2
0_0201_5%
VCC3B
2
RA47
100K_0201_5%
1
o
RA27 @
1 2 RA46 1 2 200K_0201_5%
add RA49_22K for improve HP_JD driving by vendor suggestion HP_JD 54
i
0_0201_5%
RA49
1
QA2 D change QA2/3/4 from SB00000C80J to SB00000VY0J
t
2 1 2
55 HP_JACK_OUT G
2SK3541_VMT3
22K_0201_5% S
3
1
a
RA28
@ CA47 100K_0201_5%
4.7U_0402_6.3V6-M
2
C C
1
@
c
change RA28 from SD0431003PT(100k_0201_5% ) to SD0431003YT(100k_0201_5%)
change RA28 from ASM to NI
if i
Delete RA29 /RA30 / QA3 for Docking Mic detect issue
r t
Add RA51 / RA52 / QA8 / RA50 / QA7 /CA73 for Docking MIC detect issue
VCC3B
e
VCC3B
c
2
RA51
100K_0201_5%
I2S_IN_JD 54
1
B B
1
RA52
y
10K_0201_5%
1
D
DOCK_MIC_EN RA50 2 1 22K_0201_5% 2
2
t
1
2SK3541_VMT3 S
3
2 QA8 QA7
60 -DOCK_MIC_DCT
f
DTC115EMGT2L_VMT3
1
CA73
1000P_0201_25V7-K
2
a
@
r s
A
F o Delete RA31 / RA32 / QA4 for Docking HP detect issue
Title
AUDIO JACK SENSE

Custom C
WOLVERINE3 UMA
Rev
0.1
A

5 4 3 2 1
5 4 3 2 1
LINE1_VREFO
54 LINE1_VREFO
ly
1UF_0402_6.3V
2
2
D D
CA48
RA33
2.2K_0201_5%
1
n
1
FLA7
1 2
o
BK1005HS102-T_2P
1UF_0402_6.3V
2
2
CA49
RA34
n
2.2K_0201_5%
1
o
FLA8
1 2
i
BK1005HS102-T_2P
C
MIC_SLEEVE
2
a t MIC_SLEEVE 54
C
c
@
2
0_0201_5% CA50
RA35 1000P_0201_25V7K
i
1
1
MIC_RING2
r t if MIC_RING2 54
2
e
@
2
0_0201_5% CA51
RA36 1000P_0201_25V7K
1
1
y c NEAR EXT MIC CONN

RA37
1
@
2
0_0201_5%
B
a f t 2
CA52
0.01U_0201_10V7K
r s
A
Title
AUDIO EXT MIC I/F

Custom
STING UMA
Rev
0.1
A

5 4 3 2 1
5 4 3 2 1
n ly D
Cut in R-short
n o
o
J4
SP_OUTR- RA38 1 2 0_0201_5% SP_OUTR-_R 1
54 SP_OUTR- SP_OUTR+ SP_OUTR+_R 1
i
RA39 1 2 0_0201_5% 2
54 SP_OUTR+ SP_OUTL- 1 2 SP_OUTL-_R 3 2
RA40 0_0201_5%
54 SP_OUTL- SP_OUTL+ 1 2 SP_OUTL+_R 4 3
RA41 0_0201_5%
54 SP_OUTL+ 4
t
5
6 GND1
GND2
TYCO_2041180-4
a
1000P_0201_50V7-K
1000P_0201_50V7-K
1000P_0201_50V7-K
1000P_0201_50V7-K
C C
2
CA53 CA54 CA55 CA56
c
1
1
PLACE, NEAR SPEAKER CONNECTOR
if i
e r t
B
y c B
a f t
r s
A
Title
AUDIO SPEAKER
Custom
C WOLVERINE3 UMA
Rev
0.1
A

5 4 3 2 1
5 4 3 2 1
n ly D
n o
o
DA7
EC_SPKR 2 1
61 EC_SPKR
i
t
DA8
1
PCH_SPKR 2 1
9 PCH_SPKR
RA42
RB521CS-30GT2RA_VMN2-2 33K_0201_5%
2
C C
c
1
RA43
i
10K_0201_5%
2
if
BEEP_MIX_ATT
BEEP_MIX_ATT 54
r t
1
QA5 D
-BEEP_ENABLE 2
61 -BEEP_ENABLE G
LSK3541G1ET2L 1N VMT3
e
S
3
B
y c B
a f t
r s
A
Title
AUDIO BEEP

Custom
Date:
WOLVERINE3 UMA
Thursday, August 20, 2015 Sheet 59 of 100
Rev
0.1
A
5 4 3 2 1
5 4 3 2 1
12/9 Delete DDIP2 pull high resistor
VCC3SW
DOCK_DCIN20
n ly D
1
o
R116
33K_0201_5%
J17A
2
70 1 -DOCKED0
69 GND_1 DOCKED0# 2 DOCK_MDI_0+
68 RESERVE_7 DOCK_MDI_0P 3 DOCK_MDI_0- DOCK_MDI_0+ 47
67 VOID1 DOCK_MDI_0N 4 DOCK_MDI_0- 47
66 DOCK_DCIN20 GND_5 5 DOCK_MDI_1+
n
-PWRSWITCH 65 VOID2 DOCK_MDI_1P 6 DOCK_MDI_1- DOCK_MDI_1+ 47
17,71 -PWRSWITCH DOCK_I2S_MCLK 64 DOCK_PWR_SW# DOCK_MDI_1N 7 DOCK_MDI_1- 47
54 DOCK_I2S_MCLK DOCK_I2S_SD_I 63 DOCK_I2S_MCLK GND_6 8 DOCK_MDI_2+
54 DOCK_I2S_SD_I DOCK_I2S_SD_O 62 DOCK_I2S_SD_I DOCK_MDI_2P 9 DOCK_MDI_2- DOCK_MDI_2+ 47
54 DOCK_I2S_SD_O DOCK_I2S_BCLK 61 DOCK_I2S_SD_O DOCK_MDI_2N 10 DOCK_MDI_2- 47 VCC3B
54 DOCK_I2S_BCLK DOCK_I2S_LRCLK 60 DOCK_I2S_BCLK GND_7 11 DOCK_MDI_3+
o
54 DOCK_I2S_LRCLK -DOCK_HP_DCT 59 DOCK_I2S_LRCLK DOCK_MDI_3P 12 DOCK_MDI_3- DOCK_MDI_3+ 47
55 -DOCK_HP_DCT -DOCK_MIC_DCT 58 DOCK_MICIN_DCT# DOCK_MDI_3N 13 DOCK_MDI_3- 47
56 -DOCK_MIC_DCT 57 DOCK_HPOUT_DCT# GND_8 14
RESERVE_1 RESERVE_5
1
i
56 15
100K_0201_5%
55 #DOCK_PWRSHUTDOWN RESERVE_6 16 DOCK_DDIP2_HPD R117
54 DOCK_DISCHARGE DOCK_DP0_HPD 17 DOCK_DDIP2_HPD 28
53 #DOCK_PWRDCT DOCK_DP0_DGL_DCT 18
t
52 DOCK_PWRGOOD DOCK_DP0_DDC_DATA 19
2
71 -PWRON_DOCK 51 DOCK_PWRON# DOCK_DP0_DDC_CLK 20
DOCKID3
DOCKID2 50 DOCK_ID3 GND_9 21 DOCK_DDIP2_AUXN
7 DOCKID[3:0] 49 DOCK_ID2 DOCK_DP0_AUXN 22 DOCK_DDIP2_AUXP DOCK_DDIP2_AUXN 28
DOCKID1
48 DOCK_ID1 DOCK_DP0_AUXP 23 DOCK_DDIP2_AUXP 28
DOCKID0
a
ACDC_ID_DOCK 47 DOCK_ID0 GND_10 24 DOCK_DP3N
73 ACDC_ID_DOCK DOCK_ACDC_ID DOCK_DP0_LANE3N
1
DOCK_CONSUMP 46 25 DOCK_DP3P
100K_0201_5%
C 75 DOCK_CONSUMP 45 DOCK_CONSUMP DOCK_DP0_LANE3P 26 C
R118
USB3P3_TXP_DOCK 44 GND_2 GND_11 27 DOCK_DP2N
10 USB3P3_TXP_DOCK USB3P3_TXN_DOCK 43 DOCK_USB_SS_TXP DOCK_DP0_LANE2N 28 DOCK_DP2P
10 USB3P3_TXN_DOCK DOCK_USB_SS_TXN DOCK_DP0_LANE2P
c
42 29
2
USB3P3_RXP_DOCK 41 GND_3 GND_12 30 DOCK_DP1N
10 USB3P3_RXP_DOCK USB3P3_RXN_DOCK 40 DOCK_USB_SS_RXP DOCK_DP0_LANE1N 31 DOCK_DP1P
10 USB3P3_RXN_DOCK 39 DOCK_USB_SS_RXN DOCK_DP0_LANE1P 32
i
USBP3+_DOCK 38 GND_4 GND_13 33 DOCK_DP0N
10 USBP3+_DOCK USBP3-_DOCK 37 DOCK_USB_SS_DP DOCK_DP0_LANE0N 34 DOCK_DP0P
10 USBP3-_DOCK 36 DOCK_USB_SS_DN DOCK_DP0_LANE0P 35 -DOCKED0
DOCKED2# DOCKED1#
if
TE_2129525-2
t
D22
1 2 I2S_CTRL
I2S_CTRL 54
r
D23
1 2 -DOCK_ATTACHED_20
e
-DOCK_CAP_ID 7
1SS400CMT2R VMN2M
2
c
R119
Cut in R-short 0_0201_5% VCC3M
1
1 2
R120 100K_0201_5%
D25
B 3 -DOCK_ATTACHED_3M B
1 -DOCK_ATTACHED_3M 62,63
-DOCK_ATTACHED_AUX
y
2
-DOCK_ATTACHED_AUX 47
DAN222MGT2L_VMD3
DOCK_PWR20
a f
1
2
3 t Q6
DOCK_PWR20_IN
SI7121DN-T1-GE3_POWERPAK-8-5
DOCK_PWR20_IN
J17B
28
28
28
DOCK_DDIP2_3N
DOCK_DDIP2_3P
DOCK_DDIP2_2N
NEAR DOCK CONN
C144 1
C145 1
C146 1
C147 1
2 0.1u_0201_10V6K
2 0.1u_0201_10V6K
2 0.1u_0201_10V6K
2 0.1u_0201_10V6K
DOCK_DP3N
DOCK_DP3P
DOCK_DP2N
DOCK_DP2P
s
28 DOCK_DDIP2_2P
5 71 73
PWR20 SHELL_1 74 C148 1 2 0.1u_0201_10V6K DOCK_DP1N
SHELL_2 28 DOCK_DDIP2_1N DOCK_DP1P
75 C149 1 2 0.1u_0201_10V6K
28 DOCK_DDIP2_1P
4
SHELL_3
2
2 76
C151 SHELL_4 77 C150 1 2 0.1u_0201_10V6K DOCK_DP0N
SHELL_5 28 DOCK_DDIP2_0N
2
R121 78 C152 1 2 0.1u_0201_10V6K DOCK_DP0P

SHELL_6 28 DOCK_DDIP2_0P
200K_0201_5% 0.1U_0402_25V4Z 79
r
R122 1 SHELL_7 80
1
100_0201_5% SHELL_8 81
72 SHELL_9 82
1
GND_14 SHELL_10
-DOCK_ATTACHED_20 1 2
o
R123 100K_0201_5%
A
TE_2129525-2 A
5
F 4 3
Deciphered Date
2
2014/08/10
Title
Custom
Date:
DOCKING CONNECTOR

WOLVERINE3 UMA
1
Sheet 60 of 100
Rev
0.1
5 4 3 2 1
VCC3B
U16A
DRV[15:0] 64
-EC_RESET F1 L11 DRV0
71 -EC_RESET RESETI# KSO0 B7 -PAD_RESET R375 2 1 100K_0201_5%
DRV1
y
KSO1 E6 DRV2
SUSCLK_32K B3 KSO2 B6 DRV3
12 SUSCLK_32K 32KHZ_IN/GPIO165 KSO3
l
VCC3B H12 DRV4 VCC3M
-KBRC J5 KSO4 G10 DRV5
7 -KBRC KBRST KSO5 G9 DRV6
D KSO6 H13 DRV7 D
-EC_SCI K6 KSO7 C6 DRV8
8 -EC_SCI EC_SCI# KSO8
n
C7 DRV9
2 1 -KBRC -EC_WAKE N7 KSO9 B5 DRV10 -BEEP_ENABLE R1242 1 100K_0201_5%
8 -EC_WAKE SMI# KSO10 H10 DRV11
R126 10K_0201_5%
-SUS_STAT KSO11 -KBD_BL_DTCT
HOST I/F
H6 H11 DRV12 R1252 1 100K_0201_5%
7 -SUS_STAT LPCPD# KSO12 A5 DRV13
KSO13
o
-CLKRUN L5 L13 DRV14
7,70 -CLKRUN CLKRUN# KSO14 N12 DRV15 VCC3SW
IRQSER N5 KSO15 M11 DRV16
7,70 IRQSER SER_IRQ KSO16/GPIO152 D5 DRV17
4700P_0402_25V C260
VCC3M 1 2 KSO17/GPIO175
Keyboard/TrackPoint
-PLTRST_FAR M5
13 -PLTRST_FAR LRESET# SENSE[7:0] 64
-LPC_FRAME L6 N13 SENSE0 -HOTKEY R1271 2 20K_0201_5%
n
7 -LPC_FRAME LFRAME# KSI0 J6 SENSE1
LPCCLK_EC_24M N6 KSI1 N8 SENSE2
2 1 7
I2C_DATA_BT0 LPCCLK_EC_24M PCI_CLK KSI2 J11 SENSE3
C257
R128 4.7K_0201_5% 2 1 LPC_AD0 M6 KSI3 J12 SENSE4
LPC_AD1 LAD0 KSI4
o
M7 J13 SENSE5
2 1 I2C_CLK_BT0 33P_0201_25V8J LPC_AD2 L7 LAD1 KSI5 M12 SENSE6
R129 4.7K_0201_5% LPC_AD3 K7 LAD2 KSI6 M13 SENSE7
LAD3 KSI7
i
DRV16 R130 2 1 10K_0201_5%
2 1 -REAR_EJECT_LEVER 7,70 LPC_AD[3:0] DRV17 R132 2 1 10K_0201_5%
R131 10K_0201_5% C2 -HOTKEY
t
VCI_IN2#/GPIO161 -HOTKEY 64 KBD_BL_PWM R133 2 1 100K_0201_5%
2 1 -EC_RESET M_TEMP R135 1 2 1K_0201_5% K3 M9
74 M_TEMP ADC0/GPIO200 PWM0/GPIO053 KBD_BL_PWM 64 BYPASS_PAD R374 2 1 100K_0201_5%
R134 10K_0201_5%
I2C_DATA_BT0 E7 A6
74 I2C_DATA_BT0 SMB00_DATA GPIO036 -KBD_BL_DTCT 64
a
2 1 I2C_DATA_CHARGE I2C_CLK_BT0 A7
74 I2C_CLK_BT0 SMB00_CLK
R136 10K_0201_5%
IPDCLK_R
Battery
F11 R137 1 2 33_0201_5%
C 2 1 I2C_CLK_CHARGE EC_H7 H7 PS2_CLK0A/GPIO114 IPDCLK 65 C
R138 10K_0201_5% GPIO223 K13 IPDDATA_R R139 1 2 33_0201_5%
c
BAT_FET_HOT K1 PS2_DAT0A/GPIO115 IPDDATA 65
2 1 -LED_CAPSLOCK 75 BAT_FET_HOT ADC1/GPIO201
i
R404 10K_0201_5% J7
I2C_DATA_CHARGE GPIO052 -PAD_RESET 65
R140 1 2 100_0201_1% E8
2 1 EC_H7 75 I2C_DATA_CHARGE I2C_CLK_CHARGE SMB02_DATA
R142 1 2 100_0201_1% B8 A13
75 I2C_CLK_CHARGE SMB02_CLK GPIO133 TP4_RESET 64,65
R141 100K_0201_5%
if
C12
S_TEMP 1 2 L4 GPIO134 BYPASS_PAD 65
R143 1K_0201_5%
74 S_TEMP ADC4/GPIO204 Change -PAD_RESET and TP4_RESET for some cobain3 EC code
G7
GPIO224
t
C9
GPIO143/SMB04_DATA VGA_BLON 3
LCD
A8
GPIO144/SMB04_CLK BACKLIGHT_ON 38
r
-LED_LOGO A4
38 -LED_LOGO LED0/GPIO156
-LED_PWR F5
38,100 -LED_PWR LED1/GPIO157 C11
e
GPIO145/JTAG_TDI BDC_ON 50,63
Wireless
C3 A11
64 -LED_MICMUTE GPIO024 GPIO146/JTAG_TDO -WWAN_DISABLE 50,63
-REAR_EJECT_LEVER
D12 C10
c
64 -LED_MUTE GPIO035 GPIO147/JTAG_CLK -WiGig_RF_KILL 50,63
LED
F6
64 -LED_FNLOCK GPIO034
-LED_CAPSLOCK H2
GPIO221 J8
PWM2/GPIO055 EC_SPKR 59
C5 K5
100 DC_BAT_LED GPIO225 GPIO166 -BEEP_ENABLE 59,63
y
B B
Audio
H1 D10 R144 2 1 0_0201_5%
100 CHARGER_LED GPIO226 GPIO171/MSDATA -SPK_MUTE 63
t
E10 R145 2 1 0_0201_5%
GPIO170/MSCLK HP_JACK_IN 55
1
1
Cut in R-short
f
R403 R402 1 1 1 @
220P_0201_25V7K C155
220P_0201_25V7K C156
4700P_0402_25V C157
For co-lay ALPS switch 10K_0201_5% 10K_0201_5% MEC1653 D26
DF2S6P8UFS_1-1L1A2
2
0_0201_5% 2 2 2
2
a
@ @
R414 1 2
@
4
SPVT210101_4P
S2
r s
3
Deciphered Date
2015/08/10
Title
EC - MEC1653 (1/3)

A
WOLVERINE3 UMA
5 4 3 2 1
5 4 3 2 1
VCC3M
VCC3M
10K_0201_5%
100K_0201_5%
100K_0201_5%
2 10K_0201_5%
2 10K_0201_5%
2 100K_0201_5%
VCC3M
y
VCC3M
2
l
D D
2
R151
R152
R158
R153
R148
R155
R159 R160 R161
@ 100K_0201_5% 2.2K_0201_5% 2.2K_0201_5%
1
n
U16B
Sensor
-PWRSW D7 D8
71 -PWRSW GPIO127/A20M SMB01_DATA/GPIO005 I2C_DATA_GSENSE 68
-PWRSW_EC G2 C8
13 -PWRSW_EC GPIO106 SMB01_CLK/GPIO006 I2C_CLK_GSENSE 68
o
-EXTPWR D28 1 2 RB521CS-30GT2RA_VMN2-2 L9
75 -EXTPWR GPIO001/PWM4
ACDC_ID L2 M1 FAN_ID
73 ACDC_ID ADC2/GPIO202 ADC3/GPIO203 FAN_ID 67
-SHUTDOWN
E2 -SHUTDOWN 72
FAN
13 AC_PRESENT GPIO022 FAN_ON
N9 VCC3B
PWM1/GPIO054 FAN_ON 67
8/18 SVT add 0 ohm for Resemt glitch VCCST
-PCH_SLP_SUS K12 D6 FAN_FRQ
13 -PCH_SLP_SUS FAN_FRQ 67
1
GPIO140/SMB06_CLK FAN_TACH0/GPIO050
1 2 0_0201_5% -RSMRST_EC E3
-RSMRST R430
13,19 -RSMRST BGPO3/GPIO172 2
BPWRG Q8
n
B2
72 SUS_ON1 BGPO1/GPIO101 DTC115EMGT2L_VMT3
C4
83 SUS_ON2
3
BGPO2/GPIO102
Power Management
B11
VREF_VTT
G11 B12PECI_R R163 1 2 43_0201_5% PECI
13 -PCH_SLP_S3 PECI 6
2
GPIO110 PECI_DAT
o
G12
13,85 -PCH_SLP_S4 GPIO111 C159 @ 47P_0201_25V8J
R164
F3 2 1 4.7K_0201_5%
72 BPWRG VCC_PWRGD
2
1
D9 EC_SDA2
R165 1 2 100_0201_1% R166 2
SMB03_DATA/GPIO007 EC_SDA2 7
i
1K_0201_5%
-LID_CLOSE 1 2 0_0201_5% A1 F8 EC_SCL2
R393 R167 1 2 100_0201_1% R168
38 -LID_CLOSE VCI_IN3#/GPIO000 SMB03_CLK/GPIO010 EC_SCL2 7
0.1U_0201_6.3V6K
1
1
t
A12
13 -PCH_SLP_WLAN GPIO043
E12 R169 1 2 0_0201_5% -THRM
C M8 SYS_SHDN# C
72 VCC5_TP_ON GPIO222
Thermal
-RJ45_LINKUP G3
46 -RJ45_LINKUP GPIO033 DP1_DN4 Enable emergency thermal shutdown function
G13
a
DP1_DN4
-DOCK_ATTACHED_3M B10
60 -DOCK_ATTACHED_3M GPIO150/JTAG_TMS F13 DN1_DP4
2 2200PF_0201_25V 1 REMOTE
1 REMOTE 2SC5658GT2LR_VMT3
1.Schematic drawing issue (Q9.2) 7/7
1
DN1_DP4 DIODE 4 E DIODE 1 C
C160 C161 2 C255 2 Q25
2.Optimize readability for EC request 7/9
B
N1 E13 DP2_DN5 Q9 B
75 ISYS ADC5/GPIO205 DP2_DN5 22P_0201_25V8 22P_0201_25V8
1 2 C 2 E
3
if c
J4 2SC5658GT2LR_VMT3
75 -BOOST_MODE GPIO227 D13 DN2_DP5
PROCHOT_EC D3 DN2_DP5 PLACE NEAR MEC1619 PLACE NEAR DIODE 4 PLACE NEAR DIODE 1
LED2/GPIO153
C13 DP3_DN6
DP3_DN6 Update Thermal Sensor Table
B13 DN3_DP6
M10 DN3_DP6 REMOTE
TABLE
44 AOU_SEL1 2 2200PF_0201_25V 1 1
1
GPIO015/PWM7 DIODE 5 E C
L8 C162 C163 2 B
C164 2 Q11
44 AOU_SEL2 GPIO016 Q10 B
Sensor Device Placed on
22P_0201_25V8 22P_0201_25V8 2SC5658GT2LR_VMT3
1 2 2
USB/AOU
H9 C REMOTE E
3
44 -AOU_IFLG GPIO025/UART_CLK DIODE 2
D11 2SC5658GT2LR_VMT3
GPIO220/VIN
i
C161+Q9 CPU DC/DC(PU402) BOTTOM
B4
44 USB_ON1 BGPO4/GPIO173 E11
VSET
PLACE NEAR MEC1619 PLACE NEAR DIODE 5 PLACE NEAR DIODE 2
C164+Q11 DIMM (J21) BOTTOM
E4
44 USB_ON2 BGPO5/GPIO174
C167+Q13 WLAN (J32) BOTTOM
rt
REMOTE
2 1 1
1
DIODE 6 C
FAN module
E
C165 2 2
C255+Q25 TOP
C166 C167 Q13
B
Q12
1
2200PF_0201_25V
2
22P_0201_25V8 22P_0201_25V8 B 2SC5658GT2LR_VMT3 C163+Q10 Charger (PU101) BOTTOM
MEC1653 2SC5658GT2LR_VMT3 2 REMOTE E
C
3
DIODE 3
C166+Q12 WWAN(J22) BOTTOM
PLACE NEAR MEC1619 PLACE NEAR DIODE 6 PLACE NEAR DIODE 3
ce 4.53K_0201_1%
2
1
R170
10K_0201_5%
2
1
R171
B
f t y
VCC3SW
VCC3_SUS
a
R392 1 2 75_0201_1% 1 2 100K_0201_5% -RSMRST_EC
-RSMRST R146
-PROCHOT 6,75
1
SUS_ON1
1
R427 R147 2 1 100K_0201_5%
10K_0402_5% R429
2 1 100K_0201_5% SUS_ON2
Q7 @ 10K_0402_5% R149
place near Q7
s
2
LSK3541G1ET2L 1N VMT3 D VCC5_TP_ON

1
R157 2 1 100K_0201_5%
D67
2
PROCHOT_EC
1
2 2 Q40 D @
2 2 1 -RSMRST_EC 2 1 100K_0201_5% AOU_SEL2
G -RSMRST R154
2
C158 G
S 47P_0201_25V8J LSK3541G1ET2L_VMT3 1
3
R156 1 Q39 D S RB521CM_30

3
100K_0201_5% 2 CC98 @
72 MPWRG G 100P_0201_25V8J
1
LSK3541G1ET2L_VMT3 2
A S A
r
3
8/18 SVT Add circuit to avoid -RSMRST pulse 8/18 SVT Reserve Diode to avoid -RSMRST pulse Change R146 pin 2 net name to -RSMRST_EC
F o 4 3 2
Size
D
Title
Date:
1
EC - MEC1653 (2/3)
Document Number
WOLVERINE3 UMA
Rev
0.1
5 4 3 2 1
VCC3M
R172 1 2 10_0402_5%
y
2
VCC3M VCC3M_EC
C168
10U_0603_6.3V6M
1 VCC3M_EC
l
R173 1 2 0_0603_5%
D D
VCC3SW VCC3M_EC
0.1U_0201_6.3V6K
0.1U_0201_6.3V6K
0.1U_0201_6.3V6K
n
2
VCC3M VCC3SW
@
R174 R175
0_0402_5% 0_0402_5% 2 2 2
1
o
2
1 1 1
C169
C170
C171
VCC3M_EC C172
1M_0201_5%
4.7U_0402_6.3V6M
10K_0201_5%
10K_0201_5%
10K_0201_5%
2 100K_0201_5%
1
4.7K_0201_5%
4.7K_0201_5%
F12
1
G6
G8
H8
H3
H4
F4
J1
J3
U16C
VBAT
VTR_18
VTR_REG
VTR
VTR_LPC
VTR_FLASH
AVTR_ADC
VREF_ADC
VR_CAP
2
2
n
1
1
R188
R189
R176
R177
R178
R179
R180
change R188/R189 from 10K_0201_% to 4.7K_0201_5%
J10 L12 B_ON

GPIO130/SMB10_DATA GPIO012/SMB07_DATA B_ON 71
o
VCC3M K10 K11
GPIO131/SMB10_CLK GPIO013/SMB07_CLK
N11
GPIO014/PWM6
E9
74 I2C_DATA_BT1 GPIO141/SMB05_DATA
i
Change -PCH_SLP_LAN to GPIO135
2 10K_0201_5%
B9 E1
74 I2C_CLK_BT1 GPIO142/SMB05_CLK GPIO023
F10
GPIO135 -PCH_SLP_LAN
t
Disable EC JTAG function , Change R181 to @ / R182 to stuff. F9
GPIO104/UART_TX
A9 M3
C WWAN_RST from GPIO131 change to GPIO56 GPIO105/UART_RX ADC6/GPIO206 C
N3
ADC7/GPIO207
50 EC_WWAN_RESET# N10 J2
1
GPIO056/PWM3 ADC8/GPIO210
a
E5 K2 GSENSE_INT
R181
GPIO051/FAN_TACH1 ADC9/GPIO211 GSENSE_INT 68

L1
VIDEO_ID F2 ADC10/GPIO212
GPIO062 L3
-JTAG_RST A10 ADC11/GPIO213 change ADAPTER_ID_ON# function GPIO from GPIO130 to GPIO215
JTAG_RST# M2
ADC12/GPIO214
if c
2 10K_0201_5%
0.1U_0201_6.3V6K
N2 R371 2 1 0_0201_5%
ADC13/GPIO215 ADAPTER_ID_ON# 73
ECSPI_CLK J9 M4
71 ECSPI_CLK SPI_CLK ADC14/GPIO216
ECSPI_MOSI K9 N4 -EC_SLP_LAN
71 ECSPI_MOSI SPI_MOSI ADC15/GPIO217 -EC_SLP_LAN
SPI
ECSPI_MISO K8
71 ECSPI_MISO SPI_MISO change -pch_slp_lan to EC, use ec to control lan power
2 -ECSPI_SS L10
71 -ECSPI_SS SPI_CS#
1
1
C173
R182
-HDD_DTCT VBAT
i
D2
43 -HDD_DTCT VCI_IN0#/GPIO163
-INTRUDER_EC G1 D1 EC_PWRREQ
13 -INTRUDER_EC VCI_IN1#/GPIO162 VCI_OUT EC_PWRREQ 71
rt
B1
VCI_IN4#/GPIO234
A2 C1 -BATLOW
VCI_IN5#/GPIO235 BGPO0 -BATLOW 13
D4
VCI_IN6#/GPIO167
2 10K_0201_5%
VSS_ADC
VSS_RO
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
BGND
VSS0
VSS1
VSS2
e
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
100K_0201_5%
100K_0201_5%
100K_0201_5%
2
MEC1653
H5
G5
F7
G4
K4
A3
B @ To use common code with CB3 for EC B
1
1
2
c
R184
R185
R186
R187
R413
R183
@ @ @
change R183 from NI to install for WV3 have no GPU device
1
delete R184 for WWAN_RST change to GPIO56
R192
R193
R194
R195
R196
R197
R198
R199
R200
R201
R202
R203
R204
R205
R206
R207
Change R192 to ASM
change ADAPTER_ID_ON# function GPIO from GPIO130 to GPIO215 and set R194 to NI
y
For -PCH_SLP_LAN change to GPIO135, modify R201 to N0_ASM and R202 to ASM.
TP5
TESTPAD
TP6
TESTPAD TESTPAD
TP7
Disable EC JTAG interface
VCC3M
VCC3M
f t TP8
TESTPAD
TP9
TESTPAD TESTPAD
TP10
10K_0201_5%
10K_0201_5%
10K_0201_5%
49.9_0201_1%
1
TP11 TP12 TP13
a
TESTPAD TESTPAD TESTPAD
2
TP14 TP15
2
TESTPAD TESTPAD
1
@
@ @ @
s
1
1
R208
1
R209
R210
R211
BDC_ON
BDC_ON 61
-WWAN_DISABLE -BEEP_ENABLE
-WWAN_DISABLE 61 -BEEP_ENABLE 61
A -WiGig_RF_KILL -SPK_MUTE A
r
-WiGig_RF_KILL 61 -SPK_MUTE 54,61
-DOCK_ATTACHED_3M HP_JACK_IN
-DOCK_ATTACHED_3M 60 HP_JACK_IN 55
F o 4 3 2
Size
D
Title
Date:
1
EC - MEC16353 (3/3)
Document Number
WOLVERINE3 UMA
Rev
0.1
5 4 3 2 1
y
VCC5_TP VCC5_TP VCC5_TP VCC5B
4.7K_0201_5%
4.7K_0201_5%
D VCC3M D
10K_0201_5%
VCC3M
1A_32V_ERBRD1R00X
1A_32V_ERBRD1R00X
0.5A_32V_ERBRD0R50X
2
2
2
2
C174
F10
F11
0.01U_0201_10V7K
1
F9
2 15K_0201_5%
2 15K_0201_5%
2 15K_0201_5%
2 15K_0201_5%
2 15K_0201_5%
2 15K_0201_5%
2 15K_0201_5%
2 15K_0201_5%
1
1
JAE_FL10S012HA1_12P-T
R220
R221
R222
N19578386
N19578390 12 14
KBD_BL_PWM 11 12 GND2 13
61 KBD_BL_PWM
n
10 11 GND1
-KBD_BL_DTCT 9 10
2 61 -KBD_BL_DTCT 8 9
7 8
C217
7
R212 1
R213 1
R214 1
R215 1
R216 1
R217 1
R218 1
R219 1
0.1U_0201_6.3V6K TP4CLK 6
65 TP4CLK 5 6
1
5
o
4
3 4
TP4_RESET 2 3
JAE_FL10F032HA2R3000 61 TP4_RESET
TP4DATA 1 2
i
32 34 65 TP4DATA 1
31 32 GND2 33
30 31 GND1 J37
30 CONN@
-HOTKEY 29
t
61 -HOTKEY 29
R223 1 2 680_0402_5% 28
61 -LED_MICMUTE 28
R224 1 2 680_0402_5% 27
61 -LED_MUTE 27
R225 1 2 100_0402_5% 26
61 -LED_FNLOCK 25 26
N19578404 1 2 2
DRV11 24 25 C176 C177
a
61 DRV[15:0] 23 24 C175 22U_0603_6.3V6M 22U_0603_6.3V6M
DRV8
DRV10 22 23 220P_0201_25V7K
22 2 1 1
C DRV12 21 C
DRV9 20 21
DRV13 19 20
19
c
DRV15 18 Change C176/C177 from 0805 to 0603
DRV5 17 18
DRV7 16 17
DRV6 15 16
i
DRV3 14 15
61 SENSE[7:0] 13 14
DRV1
SENSE5 12 13
DRV2 11 12
if
DRV4 10 11
SENSE0 9 10
SENSE2 8 9
DRV0 7 8
SENSE1 6 7
SENSE4 5 6
4 5
t
DRV14
SENSE6 3 4
SENSE7 2 3
SENSE3 1 2
1
r
J38
ce B
f t y
s a
A
o r A
5
F 4 3
Deciphered Date
2
2015/08/10
Title
KEYBOARD/TRACK POINT

Custom
Date:
WOLVERINE3 UMA
1
Sheet 64 of 100
Rev
0.1
5 4 3 2 1
VCC3B
VCC3B VCC5B VCC3B
VCC3B VCC3FP
4.7K_0201_5%
4.7K_0201_5%
y
1
0.5A_32V_ERBRD0R50X
0.5A_32V_ERBRD0R50X
R394
0.5A_32V_ERBRD0R50X
0.5A_32V_ERBRD0R50X
l
10K_0201_5%
2
2
2
D D
F14
F15
F12
F13
1
@
1
R226
R227
1
1
J16
2 1
4 2 1 3 NFC_ON
6 4 3 5 -NFC_DTCT NFC_ON 8
FUSEVCC3FP
USBP8-_CONN 6 5 NFC_INT -NFC_DTCT 7
USBP8- R228 1 2 0_0201_5% 8 7
o
10 USBP8- USBP8+_CONN 8 7 NFC_INT 8
10 USBP8+
USBP8+ R229 1 2 0_0201_5% 10
10 9
9
SMB_CLK_3B
12 11
14 12 11 13 SMB_DATA_3B
14 13
Cut in R-short 16
16 15
15
18 17
20 18 17 19 BYPASS_PAD
22 20 19 21 TP4_RESET BYPASS_PAD 61
SMB_CLK_3B 24 22 21 23 TP4_RESET 61
IPDDATA
22,70 SMB_CLK_3B 26 24 23 25 IPDDATA 61
2 100K_0201_5%
TP4DATA IPDCLK
n
64 TP4DATA TP4CLK 28 26 25 27 -PAD_RESET IPDCLK 61
64 TP4CLK SMB_DATA_3B 30 28 27 29 -PAD_RESET 61
22,70 SMB_DATA_3B 32 30 29 31
GND2 GND1
HIGHS_BT5P0301-4001H
o
1
C178 +
i
2.2U_0402_6.3V6M
R230 1
2
a t C
c
VCC3M
i
@ Q14 VCC3FP
RW1E014SNT2R_WEMT6
if
D
4 5
2
1
G
3
@ R231
t
3FP_DRV 2 1 N36983374
72 3FP_DRV
100_0201_5%
2
r
@ C180
1000P_0201_25V7K
1
M_ON 1 2 3FP_ON
e
71,78 M_ON 3FP_ON 72
@ R232 47K_0201_5%
@ D31
2
1 2 1 2
@ R233 1K_0201_5% @ C181
c
1SS400CMT2R_VMN2-2 0.1U_0201_6.3V6K
1
B B
f t y
s a
A
o r A
5
F 4 3
2
Title
Custom
Date:
TOUCH PAD/NFC/FPR

WOLVERINE3 UMA
1
Sheet 65 of 100
Rev
0.1
5 4 3 2 1
n ly D
n o
C
BLANK
t io C
i c a
r t if
B
ce B
f t y
A
s a A
Issued Date
Deciphered Date
Title
BLANK
F
Custom 0.1
5 4 3 2 1
5 4 3 2 1
n ly D
VCC5B
FAN CURRENT
IS 0.5A MAX
n o
2
FUSE 2.0A
F16
o
2A_32V_ERBRD2R00X
1
RF
1
RF_NS@
C281
a t
100P_0201_25V8J
C 2 C
c
HIGHS_FC5AF071-3151H
9
GND2
i
8
7 GND1
6 7
5 6
if
62 FAN_ON 4 5
3 4
FAN_FRQ 2 3
62 FAN_FRQ FAN_ID 1 2
62 FAN_ID 1
t
J15
e r
B
y c B
a f t
r s
A
Title
FAN CONNECTOR

A
WOLVERINE3 UMA
5 4 3 2 1
5 4 3 2 1
D
TABLE
P/N Mode Selection
n ly D
o
TABLE H I2C Mode
P/N ADDR_SEL Address

VCC3M L SPI Mode
VCC3M
n
H 32h (W) & 33h (R)
LIS3DH
L 30h (W) & 31h (R)
2
o
H 3Eh (W) & 3Fh (R) VCC3M
i
KX023-1025 R234
L 3Ch (W) & 3Dh (R) @ 10K_0201_5% 2
2
C184 C185
t
0.1U_0201_6.3V6K 10U_0603_6.3V6M
1
1
2
a
R235
10K_0201_5%
C C
c
1
i
U17
14
1
LIS3DHTR_LGA16_3x3
if
Vdd_IO
Vdd
8
I2C_CLK_GSENSE 4 CS
62 I2C_CLK_GSENSE I2C_DATA_GSENSE 6 SCL/SPC
62 I2C_DATA_GSENSE ADDR_SEL 7 SDA/SDI/SDO
t
SDO/SA0 11 GSENSE_INT
16 INT1 9 1 GSENSE_INT 63
15 ADC1 INT2
ADC2
r
13 10 TESTPAD TP16
ADC3 RES
2
GND_1
GND_2
3 NC_1
NC_2
2
e
R236
10K_0201_5%
12
c
1
change U17 from SA000076M00 to SA00004VF0J
y
B B
a f t
r s
A
Deciphered Date
2015/08/10
Title
G-SENSOR

A
Custom
WOLVERINE3 UMA 0.1

5 4 3 2 1
5 4 3 2 1
n ly D
o
change TPM power rail from VCC3_SUS_SPI to VCC_SUS for TPM VDD SPEC
VCC3_SUS
n
2
R237
0_0603_5%
o
1
1
C261
10U_0603_6.3V6M 1
C264
10U_0603_6.3V6M
1
C263
0.1u_0201_10V6K
1
C262
C186
10U_0603_6.3V6M
1 1
C187
a t i
0.1u_0201_10V6K
@ @ 0.1u_0201_10V6K
C 2 2 2 2 2 2 C
i c
if
Follow THP1_SWG_SIT_EC005, update TPM table
change R238 / R397 pull high power rail from VCC3_SUS_SPI to VCC3_SUS VCC3_SUS
t
VCC3B VCC3_SUS
1
R238 R397
r
10K_0201_5% 10K_0201_5%
@ @
1
R376
2
10K_0201_5%
e
22
14
U26 8
1
Follow Thorpe schematic
R397 to Non-ASM
VDD3
VDD2
VDD1
VSB
@
R396 to ASM
2
c
15 4
-TPM_IRQ R396 1 2 0_0201_5% -TPM_IRQ_R 18 LAD3 PP 3 1 3
S
D
10 -TPM_IRQ SPI_MOSI_IO0 R242 LAD2/SPI_IRQ GPX/GPIO2
7,21 SPI_MOSI_IO0
1 2 33_0201_5% SPI_MOSI_IO0_2_R 21 30
SPI_MISO_IO1 R243 1 2 33_0201_5% SPI_MISO_IO1_2_R 24 LAD1/MOSI SCL/GPIO1 Q41
7,21 SPI_MISO_IO1 -SPI_CS2 LAD0/MISO
7 -SPI_CS2 R240 1 2 33_0201_5% -SPI_CS2_R 20 RTM002P02GT2L_VMT3
LFRAME/SCS
1
27 R428
G
SPI_CLK SPI_CLK_2_R SERIRQ
2
R241 1 2 33_0201_5% 19 29 10K_0201_5%
7 SPI_CLK LCLK/SCLK XOR_OUT/SDA/GPIO0 @ -SPI_CS2
y
B 6 @ B
R434 1 2 100_0201_1%
13 GPIO3/BADD 5
-PLTRST_FAR 17 CLKRUN/GPIO04/SINT TEST
13 -PLTRST_FAR
t 2
LRESET/SPI_RST/SRESET
28 2
LPCPD NC1
f
7
NC2 10
NC3
1
R239 11
10K_0201_5% 12 NC4 25
Reserved NC5 Reserve circuit for use NPCT650LA0 to improve power consumption in S0
26
a
NC6 31
NC7
2
GND1
GND2
GND3
GND4
33
EX-PAD
s
S IC NPCT650LB0YX QFN 32P DISCRETE TPM
9
16
23
32
8/20 SVT Change TPM to SA00007H110
o r
F
A A

Issued Date 2042/08/10 Deciphered Date 2015/08/10 TPM
WOLVERINE3 UMA
5 4 3 2 1
5 4 3 2 1
D
LPC Debug port
J5
Planner Only
ASM
BOX
NO_ASM
n ly TABLE
o
RC29 ASM ASM
J5
LPCCLK_DEBUG_24M 1 2 -PWRSWITCH
n
7 LPCCLK_DEBUG_24M 3 1 2 4 LPC_AD_DBG0 2 1 LPC_AD0 -PWRSWITCH 17,71
R244 0_0201_5%
-LPC_FRAME 5 3 4 6 LPC_AD_DBG1 R245 2 1 0_0201_5% LPC_AD1
7 -LPC_FRAME -CLKRUN 7 5 6 8 LPC_AD_DBG2 2 1 0_0201_5% LPC_AD2
1 R246
7,61 -CLKRUN 9 7 8 10 LPC_AD_DBG3 R247 2 1 0_0201_5% LPC_AD3
IRQSER
7,61 IRQSER -PLTRST_NEAR 9 10
o
C258 11 12
13 -PLTRST_NEAR B_ON 13 11 12 14 -SUS_STAT LPC_AD[3:0] 7,61
33P_0201_25V8J 71 B_ON 13 14 -SUS_STAT 7
2
i
15 16
GND1 GND2
HRS_DF12L3P014DP0P5V86A
C
VCC3B
a t C
10K_0201_5%
10K_0201_5%
i c
if
2
2
R248 VCC5M VCC3_SUS
R249
t
U19
1
1
SMB_CLK_3B 1 5
22,65 SMB_CLK_3B SMB_DATA_3B A Vcc
r
22,65 SMB_DATA_3B
2
R251 R252
2
B
10K_0201_5% 10K_0201_5%
e
3 4
1
GND OE
TC7SB385FU_SSOP5
c
SMB_CLK
SMB_DATA SMB_CLK 7
SMB_DATA 7
BPWRG
72 BPWRG
U20
1 5
A Vcc
y
B B
t
B
2
C188
3 4
GND OE
f
0.01U_0201_10V7K
1
TC7SB385FU_SSOP5
s a
o r
F
A A

Issued Date 2014/08/10 Deciphered Date 2015/08/10 SMBUS SW/LPC DEBUG PORT
WOLVERINE3 UMA
5 4 3 2 1
5 4 3 2 1
VCC3SW
VCC3SW
www.xinxunwei.com 400-800-9990 VCC3B
VCC3SW
2
R382
R254 1 2 47K_0201_5% -EXTPWR_ASIC
0.01U_0201_10V7K
0.01U_0201_10V7K
0.01U_0201_10V7K
10K_0201_5%
VL5
1
D59
CPUCORE_ON_ASIC 1 2 CPUCORE_ON
CPUCORE_ON 13,79
R255 1 2 10K_0201_5%
2
R256 100K_0201_5%
R257 100K_0201_5%
100K_0201_5%
R259 100K_0201_5%
RB521CM_30 2 2 2
1
y
Q16 D
2 1 2 D60
-PCH_SLP_S3 1 1 1
C189
C191
C192
C190 1000P_0201_25V7K G 1 2
l
1
1
S U21A
3
RB521CM_30
R258
D LSK3541G1ET2L 1N VMT3 D
-EXTPWR 1
75 -EXTPWR
-EXTPWR_ASIC F5 E7 R260 1 2 0_0201_5% M_ON
n
EXTPWR# MON M_ON 65
D9 VCCLAN_ON
-PCH_SLP_S3 H7 LANON VCCLAN_ON 72
13 -PCH_SLP_S3 SLP_S3# E8 1 Test_Point_40MIL TP40 @ 1
-PCH_SLP_S4 J7 MEON Test_Point_40MIL TP38 @
13,85 -PCH_SLP_S4 SLP_S4# F9 A_ON
o
-PCH_SLP_S5 J8 AON A_ON 85,94
13 -PCH_SLP_S5 SLP_S5# E9 B_ON
-EC_SLP_LAN G6 BON B_ON 63,70,72,94
-EC_SLP_LAN SLP_LAN# E6 CPUCORE_ON_ASIC
-PCH_SLP_M F6 CPUON
13 -PCH_SLP_M change -pch_slp_lan to EC, use ec to control lan power SLP_M#
H6
SUS_PWR_ACK
n
-PLTRST_FAR A7 B8 -PWRON_DOCK
13 -PLTRST_FAR PLTRST# PWRON_DOCK# -PWRON_DOCK 60
-PWRSW_ASIC F8 ThinkEngine_2
PWRSW#
1/2
o
-PCIE_WAKE F7 B6 -EC_RESET
50 -PCIE_WAKE PME# EC_RST# -EC_RESET 61
i
C6
PGPIO0
C7 H3 M_TRCL
t
63 EC_PWRREQ PGPIO1 MTRCL M_TRCL 76
C8 G3 S_TRCL
PGPIO2 STRCL S_TRCL 76
C9 B7 BAT_CRG
PGPIO3 BATCRG BAT_CRG 76
a
DISCHARGE E4 Delete TP53/54/55 for power
73 DISCHARGE PGPIO4
C A8 C
PGPIO5 H9 ECSPI_CLK_R R261 1 2 33_0201_5% ECSPI_CLK
SPICLK ECSPI_CLK 63
ECSPI_MOSI_R ECSPI_MOSI
c
H8 R262 1 2 33_0201_5%
A1 SPIMOSI ECSPI_MOSI 63
A9 NC1 G8 -ECSPI_SS_R R263 1 2 33_0201_5% -ECSPI_SS
J1 NC2 SPISS# -ECSPI_SS 63
i
J9 NC3 G7 ECSPI_MISO_R 1 2 0_0201_5% ECSPI_MISO
100K_0201_5%
100K_0201_5%
R264
NC4 SPIMISO ECSPI_MISO 63
TEST
if
100K_0201_5%
100K_0201_5%
100K_0201_5%
G5
1
1
R265
R266
2
t
1
C259
33P_0201_25V8J
2
R436
R268
R269
r
1
ce VCC3M
2
VCC3SW 8/17 SVT phase add pull low resistor for charger function
2
R270 R271
10K_0201_5% 4.7K_0201_5%
B B
1
D34
y
1 2 -PWRSW
-PWRSW 62
t
D35
f
-PWRSWITCH 1 2 -PWRSW_ASIC
38,60,70 -PWRSWITCH
1SS400CMT2R_VMN2-2
1
a
C193
0.22U_0201_6.3V6K
2
r s
A
Deciphered Date
2015/08/10
Title
THINK ENGINE(1/2)

Custom
WOLVERINE3 UMA
Rev
0.1
A

5 4 3 2 1
5 4 3 2 1
VREGIN20 VINT20
y
VCC3M VCC5M VDD10
20_0603_5%_ESR03EZPJ200
20_0603_5%_ESR03EZPJ200
2
R273 VCC3SW
0.1u_0201_10V6K
0.1u_0201_10V6K
10_0603_5%
0.1UF_25V
2
2
D D
1
R274
R275
n
2 2
2
VCC5B
1
2
C194
C195
C196
1
2
C197 1 1
0.1U_0402_25V
1
o
2
R276 2
1.78M_0402_1% R277 C198
100_0402_5% 1U_0402_10V6K
R278 2 1 0_0402_5% 1
1
VREGIN20
VCC5M
Cut in R-short VDD10 VCC5M
2
2
n
2
R279 C199
1.24M_0402_1% 470P_0201_25V7K C200
D36 D37
2.2UF_0603_25V
1
1 1 2 1 2
100K_0201_5%
1
o
2 2 2 RB521CS-30GT2RA_VMN2-2
C201 C202
i
1U_0603_25V7K 1U_0603_25V7K
1 1
1
R280
SKRPABE010_4P
t
3
G1
H1
C5
R281
A5
A2
J4
S3 20_0603_5%_ESR03EZPJ200 U21B
1 2
VREGIN20
VINT20
VCC5B
VDD10
VCC5M
VCC3SW
a
C C
2
C203
0.1U_0402_25V7K G2 A4
4
BAT_VOLT CP10OUT
if c
VCC3M
1 H2
exchange VCC5_TP_ON / 3FP_ON port define SW_OFF#
2
B4 B3
62 VCC5_TP_ON RD0_ON/5MUBAY RD0_DRV/UBAY_DRV VCC5_TP_DRV 92
R405 G4 C3
71 VCCLAN_ON RD1_ON RD1_DRV VCC3LAN_DRV 93
10K_0201_5%
1
D64 H4 D4
1 2 62,86 SUS_ON1 RD2_ON RD2_DRV SUS_DRV 92
71 B_ON J5 D3
65 3FP_ON RD3_ON RD3_DRV 3FP_DRV 65
i
RB521CM_30 H5 D2
exchange VCC5_TP_ON / 3FP_ON port define RD4_ON RD4_DRV VCCCPUIO_DRV 92
D65 D1
rt
ThinkEngine_2
1 2 RD5_DRV VCC3WLAN_DRV 96
13 -PCH_SLP_S3 2/2 E3
RD6_DRV VCC3WAN_DRV 96
RB521CM_30 F3 B_DRV_R R437 1 2 0_0201_5%
RD7_DRV B_DRV 92,95
8/20 SVT add 0hm for reserve BDRV issue
F4 B5
3 PANEL_POWER_ON 3P_ON 3P_DRV VCC3P_DRV 38
VINT20 A6
e
3B_DRV C4 VCC3B_DRV 95
VCC3SW VCC3B VCC3M
5B_DRV VCC5B_DRV 95
E2
M1_DRV M1_DRV 74
C204 1 2 1U_0603_25V7K E1 C1
CP25OUT M2_DRV M2_DRV 74
2
33K_0201_5%
2K_0201_5%
10K_0201_5%
c
2 1 2 1 B1 F1
VCPIN25 S1_DRV S1_DRV 74
R283
R284
R285
D39 RB521CS-30GT2RA_VMN2-2 C2
S2_DRV S2_DRV 74
D38 RB521CS-30GT2RA_VMN2-2
J6 F2
1
73 DISCHARGE DISCHARGE BAT_DRV B2 BAT_DRV 75
2 DCIN_DRV DCIN_DRV 73
2
C205 C206 D7 D6 R286 1 2 0_0201_5%
B SHUTDWNIN# M_PGS D5 MPWRG 13,62 B
0.01U_0402_25V7K 0.22U_0603_50V7K
1 B_PGS BPWRG 13,41,54,62,70
1 TH_DET
y
J3 D8
TH_DTCT PWRSHUTDWN# -PWRSHUTDOWN 73,75
VCC3SW
t
DGND1
PGND1
PGND2
AGND1
5M_3M_PWRG 1 2
78 5M_3M_PWRG
R287 0_0201_5%
2
f
G9
A3
B9
J2
R288
33K_0201_5%
1
2@
540_0402NEW_30%_PRF15BB541NB6RC
540_0402NEW_30%_PRF15BB541NB6RC
540_0402NEW_30%_PRF15BB541NB6RC
C207
a
470P_0201_25V7K
540_0402NEW_30%_PRF15BB541NB6RC
s
TABLE
1
1
62 -SHUTDOWN
RT1
RT3
RT5
RT7
ID Target
@
-PWRSHUTDOWN 1 2 RT1 S_BAT_PWR to S_BAT_PWR_A FET(PQ12/PQ13)
R289 0_0201_5% RT2 VCC3M Switching VR Dual FET(PQ202/PQ204)
2
2
540_0402NEW_30%_PRF15BB541NB6RC
540_0402NEW_30%_PRF15BB541NB6RC
540_0402NEW_30%_PRF15BB541NB6RC
r
RT3 VCC5M Switching VR Dual FET(PQ201/PQ203)
540_0402NEW_30%_PRF15BB541NB6RC
RT2_R
RT6_R
RT4_R
RT4 M_BAT_PWR to M_BAT_PWR_A FET(PQ9/PQ10)

RT5_R
RT7_R
RT3_R
RT1_R
RT5 DOCK_PWR20_IN to DOCK_PWR20 FET(Q6)

RT6 DCIN_PWR20_F to CV20 FET(PQ301)
o
1
1
1
C208 2 RT7 CV20 to VINT20 FET(PQ20)

RT4
RT6
RT8
RT2
0.1u_0201_10V6K
RT8 Battery Chager Dual FET(PQ101/PQ102)
1
2
A A
2
5
F 4 3
Issued Date
2014/08/10
2
Title
Custom
Date:
THINK ENGINE(2/2)

WOLVERINE3 UMA
1
Sheet 72 of 100
Rev
0.1
5 4 3 2 1
confirm with EE
VCC3M
y
1
DCIN_PWR20_F
l
PR12
750_0201_1%
1
D D
@ PD1
RB751V-40_SOD323-2 PR15
1M_0201_5%
n
ACDC_ID_DOCK 60
2
PQ23A
6
D NTJD5121NT1G 2N SC88-6
2 ADAPTER_ID_ON
@ PR13 G
0_0201_5%
S PQ23B
1
o
1
3
PR14 D NTJD5121NT1G 2N SC88-6
10K_0402_1% 5
RF_NS@ RF_NS@ 1 2 PR16 G
ADAPTER_ID_ON# 63
ACDC_ID 62 1M_0201_5%
1
S
4
47P_0402_50V8-J
1
PC25
100P_0402_50V8-J
1
1
PC8 PC1 PC24 PD2

680P_0402_50V7-K 0.1U_0402_6.3V7-K AZ5425-01F_DFN1006P2E2
n
2
2
2
DCIN DOCK_PWR20 PLACE NEAR CONNECTOR

DCIN_PWR20_F
PQ1
AON7409 1P DFN-8
t io
a
PJ1
PF1 1
5
5
4
7A_24V_0429007.WRMLHF
1 2
2
3
VINT20
C 4 3 5 PQ20 C
3 2 AON7466 1N DFN 3X3 EP
2 1 3 PR1
c
0.47U_0402_25V6-K
4
1 CV20 2 0.01_1206_LE_1%
1000P_0201_25V7K
2 RF_NS@ RF_NS@
1 5 1 2
200K_0201_5%
0.01U_0402_25V
0.01U_0402_25V
MOLEX_78048-0543
2
2
PC5
i
@ PR2
PC3
PC4
PR3
470K_0201_5% 1 PR4 PQ3
PC2
0.01U_0402_25V7K
1
4
100_0201_5% 2 PD6 DTC015EMT2L_VMT3
100P_0402_50V8-J
100P_0402_50V8-J
@ @ 2
1
1 2 3 1
PC26
PC27
1
2
PC6
PC7
if
2
1SS400CMT2R PR48 PR49
1M_0201_5%
100_0201_5%
0.01U_0402_25V7K
2
1 1
0_0201_5% 0_0201_5%
PR5
PR6
2
1
1
1
PR7
270_0201_5%
t
Total MLCC capacitance at DCIN connector is PQ4
2
smaller than 1000pF to avoid LC resonance DTA014EMT2L_VMT3
3 1
r
PR8
100K_0201_5%
2
1 2
2
72 DCIN_DRV
PR9
e
100K_0201_5%
1
1
2
G PQ5
LSK3541G1ET2L
c
S
3
PQ6
1
DTC015EMT2L_VMT3
2
2
@ PR10
B 0_0201_5% B
y
3
t
1
D
2
71,72 DISCHARGE G PQ7
f
LSK3541G1ET2L
75 DCIN_CURRENT_P
S
3
@ PR11
1
D 0_0201_5%
a
2
72 -PWRSHUTDOWN G PQ8
1
LSK3541G1ET2L
S
3
75 DCIN_CURRENT_N
r s
o
TABLE
PEAK SHIFT YES NO
PR10 NO-ASM ASM
F
A A
PR2 ASM NO-ASM
PQ7 ASM NO-ASM
PQ6 ASM NO-ASM

LOGIC Issued Date Deciphered Date DC-IN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 0.1
5 4 3 2 1
5 4 3 2 1
VCC3M
M-BAT-PWR BAT-PWR12
2
20150602@Change 20150617@Change
PR43
MAIN BAT CONN
y
6.19K_0201_1% PQ9
PF2 AON7466 1N DFN 3X3 EP
10A_32V_0501010.WRS 3 PQ10
1
@ PJ4 2 AON7409 1P DFN-8
WIDE PATTERN
l
6 1 M_BAT_IN 1 2 1 5 M_BAT_PWR_A 1
7 NC1 1 2 PR44 2
D NC2 2 3 100_0201_5% 3 5 RF@ RF@ RF@ D
8 3 4 1 2 I2C_CLK_BT0
I2C_CLK_BT0 61
4
9 VCC 4 5 PR45
68P_0402_50V8J
0.1U_0402_25V6
0.1U_0402_25V6
GND 5 100_0201_5%
2 4
n
1
1 2 I2C_DATA_BT0
PC19
PC20
PC21
I2C_DATA_BT0 61
2
JST_SM05BLBTAKSTDN2T-HF
PR46 PR47
2
510K_0201_5% 100_0201_5%
M_TEMP 61
RF_NS@ RF_NS@
1
390P_0201_25V7-K
2200P_0201_25V7K
390P_0201_25V7-K
o
2200P_0201_25V7K
2 2 2 2
PC23
PC11
PC12
PR19
PC13
100K_0201_5%
1 2
1 1 1 1 72 M1_DRV
n
PR20
150K_0201_5%
1 2
72 M2_DRV
VCC3M
t io
a
C C
S-BAT-PWR
2
c
confirm with ME 20150602@Change
PR22
6.19K_0201_1%
PF3 PQ12
i
@ PJ5 10A_32V_0501010.WRS AON7466 1N DFN 3X3 EP PQ13
1
1 3 AON7409 1P DFN-8
1 2 S_BAT_IN 1 2 2 1
2 3 PR23 1 5 S_BAT_PWR_A 2
if
3 4 100_0201_5% 3 5
4 5 1 2
5 6 I2C_CLK_BT1 63
8
4
9 GND1 6 7 PR24
4
GND2 7 100_0201_5%
FOX_BBP27BY-B4801-7H 1 2
I2C_DATA_BT1 63
2
PR25 PR26
RF_NS@ RF_NS@ S_TEMP 61
510K_0201_5% 100_0201_5%
RF@ 20150617@Change
r
390P_0201_25V7-K
2200P_0201_25V7K
390P_0201_25V7-K
2200P_0201_25V7K
0.1U_0402_25V6
2 2 2 2
1
1
PR27
1 2
PC15
PC16
PC17
PC18
PC22
72 S1_DRV
2
1 1 1 1 100K_0201_5%
ce 72 S2_DRV
1
PR28
2
150K_0201_5% B
y
DOCK_DCIN20 VREGIN20
t
DOCK_DCIN20_F
PD3
DAN222MGT2L_VMD3
PF4 2
f
1 2 1
3
0.5A_32V_ERBRD0R50X
a
DCIN_PWR20_F
PD4
DAN222MGT2L_VMD3
PF5 2
s
1 2 1
3
0.5A_32V_ERBRD0R50X
M-BAT-PWR
M-BAT-TRCL PD5
DAN222MGT2L_VMD3
r
PF6 2
1 2 1
3
0.5A_32V_ERBRD0R50X
o
A
S-BAT-PWR A
S-BAT-TRCL PD16
DAN222MGT2L_VMD3
PF7 2
1 2 1
3
F
0.5A_32V_ERBRD0R50X
Issued Date 2014/07/01 Deciphered Date BATTERY INPUT

Custom 0.1
5 4 3 2 1
5 4 3 2 1
www.xinxunwei.com 400-800-9990 DCIN_CURRENT_P 73
EMC@ RF_NS@
VINT20
2200P_0402_25V7-K
DCIN_CURRENT_N 73
10U_0805_25V6-K
10U_0805_25V6-K
47P_0402_50V8-J
68P_0402_50V8-J
20150602@Change
1 1
1
PC106
PC107
PC108
PC109
PC110
PD101 PR101
RB530SM-30T2R_EMD2-2 20_0603_5%
2
2 1 1 2 2 2
y
DCIN_PWR20_F
PR102 2 PC102
20_0603_5% 0.1U_0402_25V6
l
2 1 1 2 PC101 20150707@Change
D VINT20
1U_0603_25V6-K 1 2 RF_NS@ D
PD102 1
2
RB530SM-30T2R_EMD2-2 BAT-PWR12
PC104
0.1U_0402_25V6
VINT20
1
n
2 1
DOCK_DCIN20_F
@ PD103
RB530SM-30T2R_EMD2-2 PQ11 20150617@Change
AON7466 1N DFN 3X3 EP
3
o
2
1 5 RF@RF@
1
1
1
PC105 PR125 20150602@Change
0.1U_0402_25V6
1U_0603_25V6-K PR124 10_0201_1%
2 4
47P_0402_50V8-J
10_0201_1% 1
PC28
PC29
2
PR103 PR50
2
1K_0201_1% 100_0201_5%
2
1 2 2
n
DOCK_CONSUMP 60
1
2
1 2
PC123 PC10
1
100P_0402_50V8-J 1
0.01U_0402_25V7K
o
@ PR17 PR18 PC9
DCIN_PWR20_F 27K_0201_5% 750K_0201_5% 1500P_0402_50V7-K
2
ACN
ACP
5
i
1
D
1
2
PR106 PQ101
t
432K_0201_1% PC111 AON7410 1N DFN PD15
ACP
ACN
C C
4.7U_0603_10V6-M 4 1SS400CST2RA
1
28 24 1 2 G
2
VCC REGN
S3
S2
S1
6 @ PR108 PC112
ACDET
a
0_0402_5% 0.047U_0402_25V7K BAT_DRV 72
CHARGER_OUT12
3
2
1
25 BST_CHG 1 2 1 2
BTST
1
PL101 PR110
2
PR107 4.7UH_PCMB063T-4R7MS_5.5A_20% 0.01_1206_LE_1%

68K_0402_1% PC126 3 26 DH_CHG 1 2 1 2
CMSRC HIDRV
c
0.1U_0402_25V6
1
10U_0805_25V-6K
10U_0805_25V-6K
10U_0805_25V6-K
4
EMC@
2
ACDRV PQ102
2
27 LX_CHG AON7410 1N DFN PR126
i
PHASE
PC114
PC115
PC116
D
BQ24780_ACOK 5 4.7_0603_5%
1
ACOK
PR109 1 2 0_0201_5% 11
61 I2C_DATA_CHARGE EMC@
1 1
SDA DL_CHG
if
0.1U_0402_25V6
0.1U_0402_25V6
PU101 23 4
LODRV G PC127 @
1
PC119
PC120
PR111 1 2 0_0201_5% 12 BQ24780SRUYR 22 680P_0402_50V7K
S3
S2
S1
61 I2C_CLK_CHARGE SCL GND
2
3
2
1
2
PR127 1 2 0_0201_5% 7 29
62 ISYS IADP PAD
t
PR128 1 2 0_0201_5% 8 18
IDCHG BATDRV
PR129 1 2 0_0201_5% 9
79 PSYS PMON 17 PR112 1 2 10_0201_1%
BATSRC
r
100P_0201_50V7-K
100P_0201_50V7-K
100P_0402_50V8J
20 PR113 1 2 10_0201_1%
SRP
2
2
PC128
6,62,79 -PROCHOT PR130 1 2 0_0201_5% 10

PROCHOT#
2
PC121
PC122
PR114 1 2 10K_0201_5% 13 PC118

VCC3B
1
CMPIN PR115
e
0.1U_0402_25V6
1
BATPRES#
TB_STAT#
@ PR116 2 1 10K_0201_5% 14 10_0201_1%
B VCC3M CMPOUT 19 1 2
B
PR117 1 2 178K_0201_1% 21 SRN

VCC3M ILIM
c 16
15
2
PR21
PR118 4.7K_0201_5%
10K_0201_5%
0.1U_0201_6.3V6-K
2 1
1
PR131
1
PC14
@ PR123 0_0201_5%
BAT_FET_HOT 61
y
2 1 1 2
VCC3SW -BOOST_MODE 62
2
10K_0201_5%
t
VCC3SW
1
0.793V=>3.96A PRT1
540_0402NEW_30%_PRF15BB541NB6RC
Discharge=>15.86A
2
f
2
PR119 NEAR TO PQ11
2
PR120 PR121 1M_0201_5%
100K_0201_5% 100K_0201_5%
1
D
1
a
2 PQ105
G LSK3541G1ET2L
1
62,71 -EXTPWR
S PR122
3
100K_0201_1%
1
s
D D
1
PC124 2 BQ24780_ACOK 2 PQ103

2
G 72 -PWRSHUTDOWN G LSK3541G1ET2L
47P_0201_25V8-J
A A
2
S S
3
PQ104
LSK3541G1ET2L
Issued Date
Deciphered Date
Title
BATTERY CHARGER

Custom

WOLVERINE3 UMA
Rev
0.1
F
Date: Sheet 75 of 100
5 4 3 2 1
5 4 3 2 1
BAT-PWR12
CHARGER_OUT12
D
5
PQ14
AON7409 1P DFN-8
1
2
3
n ly D
2
N37033365 2
PC30
2
PR29 0.1U_0402_25V7K
o
PR30 470K_0201_5%
220K_0201_5% PR31 1
1
100_0201_5%
1
2
PR32
n
100K_0201_5%
1 1
D
o
2
PR33 G PQ15
200K_0201_5% LSK3541G1ET2L
1 2
i
S
71 BAT_CRG
3
2
0.033U_0201_10V6-K
PD7 PR34
t
1SS400CMT2R 1K_0201_5%
1 2 1 2 1
PC32
a
M-BAT-TRCL
C C
PQ16
c
SSM6J402TU_UF6
6 PD8
5 DAN222MGT2L_VMD3
i
4 2 2
1 M-BAT-TRCL_A 1
3
if
2 3
2
2
PC33 2
0.01U_0402_25V7K PR35 1
470K_0201_5% PR39 3
1 100_0201_5%
1
PD9
1
t
DAN222MGT2L_VMD3
r
2
PR36
4.7K_0201_5%
e
1
1
c
2 PQ17
71 M_TRCL
DTC015EMT2L_VMT3
y
B B
S-BAT-TRCL
t
PQ18
SSM6J402TU_UF6
6 PD10
5 DAN222MGT2L_VMD3
f
4 2 2
1 S-BAT-TRCL_A 1
23 3
2
a
2
PC31 PR37 PR40 1
0.01U_0402_25V7K 470K_0201_5% 100_0201_5% 3
1
1
s
PD11
DAN222MGT2L_VMD3
N37033408
2
r
PR38
4.7K_0201_5%
1
o
1
2 PQ19
71 S_TRCL
DTC015EMT2L_VMT3
F
3
A A
Issued Date Deciphered Date CHARGER SELECTOR

C 0.1
5 4 3 2 1
5 4 3 2 1
n ly D
n o
t io
C
i c a C
BLANK
r t if
ce
y
B B
a f t
r s
A
Issued Date
Deciphered Date
Title
BLANK
A
C 0.1
5 4 3 2 1
5 4 3 2 1
y
All the input MLCCs on 20V must be placed
symmetrically on Top and Bottom.
All the input MLCCs on 20V must be placed 20150617@Change
l
D D
symmetrically on Top and Bottom. 20150617@Change
@ PJ202
@ PJ201 JUMP_43X79
JUMP_43X79 EMC@ RF@ RF@ EMC@ 3V_VIN 2 1
2 15V_VIN EMC@ RF@ RF@ EMC@ 2 1
VINT20
VINT20
n
2 1
2200P_0402_25V7-K
10U_0805_25V6K
10U_0805_25V6K
68P_0402_50V8J
2200P_0402_25V7-K
10U_0805_25V6K
10U_0805_25V6K
68P_0402_50V8J
47P_0402_50V8-J
0.1U_0402_25V6-K
1 1 1
1
VINT20 VL5
PC221
PC208
PC209
47P_0402_50V8-J
0.1U_0402_25V6-K
1 1 1
PC206
1
2
PC226
PC117
VCC3M
PC205
PC203
PC204
PC219
PC113
PC207
VCC5M
2
2 2 2
1
2 2 2
o
TDC= 8A TDC= 8A
OCP =12A OCP =12A
PR221
4.7U_0402_6.3V
4.7U_0402_6.3V
0_0201_5%
1 2 1 1
D
65 M_ON
PC212
5
PC213
PQ201 PC211
n
AON7410 1N DFN 0.01U_0402_25V
D
2
4 2 2
G PQ202
AON7410 1N DFN
S1
S2
S3
4 VCC3MP
12
13
G
3
VCC5MP
1
2
3
o
S3
S2
S1
VREG5
VREG3
VIN
20 6
3
2
1
EN1 EN2
i
VCC5M_DH 16 10 VCC3M_DH
@ PR209 DRVH1 DRVH2 @ PR208
t
C 0_0402_5% 0_0402_5% C
5
1 2 1 2VCC5M_BST
17 9 VCC3M_BST 1 2 1 2
PL201 VBST1 PU201 VBST2 PL202
D
2.2UH_PCMB063T-2R2MS_8A_20% PC214 TPS51285BRUKR_WQFN20_3X3 PC215 2.2UH_PCMB063T-2R2MS_8A_20%
EMC@ EMC@ 1 2 0.1U_0402_25V7-K VCC5M_LX
18 8 VCC3M_LX 0.1U_0402_25V7-K 1 2 EMC@ EMC@
SW1 SW2
5
PQ204
2
2200P_0402_25V7-K
2200P_0402_25V7-K
PQ203 4 AON7534 1N DFN
D
G
1
VCC5M_DL 15 VCC3M_DL
0.1U_0402_25V6-K
0.1U_0402_25V6-K
PR212 AON7534 1N DFN 11
DRVL1 DRVL2
1
2
4.7_0603_5% VCC5MP PR213 PR211
S1
S2
S3
1
PC210
PC227
PC125
PC129
PR210 4.7_0603_5% 130K_0201_1%
EMC_NS@ VCC3M_VFB2 1
+
0.01U_0201_6.3V7-K
150K_0201_1% 14 4 4 PC218 PC220
c
EMC_NS@
2
1 1
1
2
3
1
VO1 VFB2 G
220U_B2_6.3VM_R35M
220U_B2_6.3VM_R35M
PGOOD
1 0.01U_0201_6.3V7-K 220U_B2_6.3VM_R35M
2
VCC5M_FB12
PC224
VCLK
PC216
S3
S2
S1
1 1
GND
2
CS1
CS2
680P_0402_50V7K VFB1 2 2
2
1
PC222
PC223
+ + PC225 PC217
EMC_NS@
2
3
2
1
1
2 0.1U_0201_6.3V6K 680P_0402_50V7K PR214
19
21
7
PR215
EMC_NS@ 0_0201_5%
2
2 2 1
0_0201_5%
if
2
2
11.8K_0201_1%
1
1
PR216
PR217
200_0201_1% PR218 PR222
1
11.8K_0201_1% 0_0201_5%
1 2 PR219
t
2
5M_3M_PWRG 72
200K_0201_1%
2
2
r
PR220
100K_0201_1% 20150602@Change
1
e
B B
PJ203
c
2 1
VCC3MP 2 1
VCC3M
@ JUMP_43X118
PJ204
2 1
VCC5MP 2 1
VCC5M
@ JUMP_43X118
f t y
A
s a A
Issued Date
Deciphered Date
Title
DC/DC VCC5M/VCC3M(TPS51285B)

Custom
WOLVERINE3 UMA
Rev
0.1
F
Date: Sheet 78 of 100
5 4 3 2 1
5 4 3 2 1
VINT20 VCC5M
y
20150602@Change
VCCST VCC3B
1
VCCST VCC5M
1
PR402 PR403 PC403
l
PC402 1K_0402_5% 2_0603_5% 1U_0402_6.3V6-K
D 0.01U_0402_25V D
2
2
2
1
1
1
PR401 PR404 PC401
1
100_0201_5% 47_0201_5% 0.1U_0201_6.3V6-K GND_81208 GND_81208
12
13
2
2
n
@ PR405
2
PR474 10K_0201_5%
VCC
VRMP
0_0201_5%
2
1
PR477
0_0201_5%
CPUCORE_ON CPUCORE_PWRGD_R
71 CPUCORE_ON PR406 1 2 0_0201_5% 37 38 1 2 CPUCORE_PWRGD 13,19
EN VR_RDY PR410
o
75_0201_5%
-SVID_ALERT
14 -SVID_ALERT PR409 1 2 0_0201_5% 33 31 1 2 -PROCHOT -PROCHOT 6,75
PR407 ALERT# VR_HOT# PR475
51_0201_5% 0_0201_5%
SVID_CLK 1 2 34 35 1 2
14 SVID_CLK DRVON DRVON 80,81,82
PR408 SCLK DRVON
10_0201_5%
SVID_DATA 1 2 32 22 PWM_1A
14 SVID_DATA SDIO PWM_1A PWM_1A 80
46 29 1 2 3K_0402_1% SW_1A
75 PSYS PSYS PR411 SW_1A 80
PSYS CSP_1A
PR412
20150330@Change 1 2 PR413
n
20K_0402_1% 10K_0201_1%
PC404 1 2
1000P_0201_25V7-K PR452
VCC_SENSE 1 2 1 2
14 VCC_SENSE
1
2.21K_0201_1%
GND_81208 PU401 1 PRT401
1
PR414 PC433 MURAT_NCP15WF104F03RC
1 2 24 NCP81208MNTXG_QFN48_6X6 PC405 0.015U_0402_25V7-K
VSP_1A
o
0.047U_0402_25V7-K
2
2.21K_0201_1% 2 PLACE CLOSE TO
1
PC406
1000P_0201_25V7-K
VCCCPUCORE PL401
28 CSN_1A
CSN_1A 80
2
CSN_1A
i
PR415 PR416
1K_0201_1% 0_0201_5%
1 2 25 23 1 2
VSN_1A TSENSE_1PH
PC407
t
2200P_0201_25V7-K
VSS_SENSE
1
14 VSS_SENSE 1 2
1
PC408 PRT402
C 0.1U_0201_25V6-K PR417 MURAT_NCP15WF104F03RC C
PC409 1 2 15P_0201_25V8-J 26 61.9K_0201_1%
2
COMP_1A
2
PLACE CLOSE TO
2
1 PR418 2 1 2 VCCCPUCORE PU402
a
2.49K_0201_1%
PR419 PC410
GND_8120820150602@Change 33.2K_0201_1% 1500P_0201_25V7-K
1 2 27 GND_81208
ILIM_1A
PC412 1 2 1000P_0201_25V7-K 16 PWM1_2PH
PWM1_2PH PWM1_2PH 81
if c
GND_81208 PR420 1 2 71.5K_0201_1% 30
IOUT_1A 17 PR450
PC411 1 2 270P_0201_25V7-M PWM2_2PH
20150608@Change 0_0201_5%
1 2
VCC5M
PR421
7.5K_0201_1%
GND_81208 10 1 2 CSP1 CSP1 81
VCCGT_SENSE 47 CSP1_2PH
15 VCCGT_SENSE VSP_2PH 9
CSP2_2PH
1
2
PC414
PC413 PR424 0.022U_0201_16V6-K
2
1000P_0201_25V7-K 1K_0201_1% 20150608@Change PR423
1
i
1 2 48 10_0201_1%
VSN_2PH 8 2 1 CSN1
CSREF_2PH CSN1 81
PC416 PR425
3300P_0201_25V7-K 23.7K_0201_1%
VSSGT_SENSE 1 2 1 2 1
15 VSSGT_SENSE IOUT_2PH
rt
PC417
1
470P_0201_25V7-K PC418
20150608@Change 1 2 0.01U_0201_6.3V7-K
2
PR427
GND_81208 68K_0402_1%
2 7 20150608@Change GND_81208 1 2 CSP1
DIFFOUT_2PH CSSUM_2PH
20150608@Change 3 1
2
FB_2PH @ PC419
1000P_0201_25V7-K PC420
PR428 PR432 PC421 820P_0201_25V7-K
e
1
562_0201_1% 4.75K_0201_1% 2200P_0201_25V7-K 2 PR429 PR430
1 2 1 2 1 2 4 73.2K_0201_1% 165K_0201_1%
PR434 PC422 PC423 COMP_2PH 6 1 2 1 2
49.9_0201_1% 470P_0201_25V7-K 15P_0201_25V8-J CSCOMP_2PH PR433
B 1 2 1 2 1 2 12.4K_0201_1% B
5 1 2
PC424
1000P_0201_25V7-K
PR473
2.8K_0201_1% ILIM_2PH PRT403 PLACE CLOSE TO
VCCGT PL402
c
1 2 1 2 1 2
MURAT_NCP15WM224J03RC
15 VCCSA_SENSE VCCSA_SENSE 1 2 45
VSP_1B PR436
2.8K_0201_1% PRT404
0_0201_5%
PR435 11 1 2 1 2
TSENSE_2PH
2
1
PC426
1
1000P_0201_25V7-K PC425 PR437
0.1U_0201_25V6-K 61.9K_0201_1% PLACEMURAT_NCP15WF104F03RC
CLOSE TO
1
PR438
VCCGT PU403
2
1K_0201_1%
2
15 VSSSA_SENSE VSSSA_SENSE 1 2 44
y
VSN_1B
36 GND_81208 PWM_1B
PC428
1 2 1000P_0201_25V7-K PWM_1B PWM_1B 82
15P_0201_25V8-J PC427
1 2 43 40 1 2 3K_0402_1% SW_1B
PR439 SW_1B 82
COMP_1B CSP_1B PRT405
t
PR440 1 2 10K_0201_1% 1 2
1 2 PC429 1 2 15N_0201_10V6-K
2
ROSC_COREGT
PR441 PC434 @
1.5K_0201_1% PR442 1 2 31.6K_0201_1% 42
ADDR_VBOOT
PC430 1000P_0201_25V7-K PLACE MURAT_NCP15WF104F03RC
CLOSE TO
ICCMAX_2PH
ROSC_SAUS
ILIM_1B
ICCMAX_1A
ICCMAX_1B
GND_81208 0.047U_0402_25V7-K
VCCSA PL404
1
1 2 1000P_0201_25V7-K
f
PC432
1 2 110K_0201_1% 39 41 CSN_1B
PR443 TAB
CSN_1B 82
IOUT_1B CSN_1B
GND_81208
PC431 1 2 220P_0201_25V7K
14
15
18
19
20
21
49
20150608@Change
88.7K_0201_1%
15.8K_0201_1%
a
24K_0201_5%
10K_0201_1%
49.9K_0201_1%
@ PR462
0_0402_5% GND_81208
1 2
2
s
PR444
24K_0201_5%
1
2
PR445
PR446
PR447
PR448
PR449
GND_81208
A A
20150608@Change
r
GND_81208 GND_81208 GND_81208
F o 4 3 2
Issued Date
Deciphered Date
Size
D
Title
Date:
DC/DC IMVP8(NCP81208)
Document Number
1
WOLVERINE3 UMA
Rev
0.1
5 4 3 2 1
y
EMC@ All the input MLCCs must be placed
PL406
BLM18KG300TN1D
l
1 2
D D
EMC@
1 2 EMC@ EMC@ RF_NS@
VINT20
n
33U_D2_25VM_R40M
PL405
BLM18KG300TN1D
VCCCPUCORE
33U_D2_25VM_R40M
33U_D2_25VM_R40M
33U_D2_25VM_R40M
1 1 1 1
47P_0402_50V8-J
10U_0603_25V6-M
10U_0603_25V6-M
10U_0603_25V6-M
10U_0603_25V6-M
0.1U_0402_25V6
2200P_0402_25V7-K
16pcs 22uF for VCCCPUCORE
PC439
1
+VCC_CORE
1
o
+ + + +
PC500
PC501
PC502
PC503
PC498
PC499
PC435
PC436
PC437
PC438
2
2
2 2 2 2 2
@ @ @ @
TDC= 21A
VCC5M IccMAX=28A
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
2 2 2 2 2 2 2 2 2 2
OCP min = 38A
PC440
PC441
PC442
PC443
PC452
PC444
PC445
PC446
PC447
PC448
PR453
3.9_0402_1%
1 2 1 1 1 1 1 1 1 1 1 1
o
1
1
PC449
20
21
22
23
24
25
28
30
1
20150602@Change PR451 0.22U_0402_16V6-M
i
2_0603_5%
BOOT
THWN
GH
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
2
6
VCCCPUCORE
2
VCC
t
7 29
VCCD PHASED 27
PHASEF
1
PC451 PC450 PL401

1U_0402_6.3V6-K 1U_0402_6.3V6-K 0.15UH_PCME063T-R15MS0R907_37A_20%
C PU402 12 1 2 C
2
VSW1
a
13
VSW2
NCP81382MNTXG_QFN39-31_6X4 VSW3
14
15
VCCCPUCORE
VSW4 16
VSW5
2
5 17
if c
PWM_1A 4 CGND1 VSW6 18 PR455
79 PWM_1A PWM VSW7
79 DRVON DRVON 2 4.7_0603_5%
DISB#
1
31
VCC5M
3 ZCD_EN EMC@ PR463 PR464
PGND1
PGND2
1
SMOD#
0_0201_5% 0_0201_5%
GL1
GL2
GL3
GL4
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
2 2 2 2 2 2
PC454
PC455
PC456
PC457
PC458
PC459
8
9
10
11
19
26
1
i
PC453
1500P_0402_50V7-K CSN_1A 1 1 1 1 1 1
CSN_1A 79
2
EMC@
rt
SW_1A
SW_1A 79
VCCCPUCORE
ce 1
B
22U_0603_6.3V6M
22U_0603_6.3V6M
330U_D2_2V_R9M
2 2
+
PC460
PC461
PC462
y
2 1 1
@ @
a f t
A
r s A
F o 4 3
Issued Date
Deciphered Date
2
Title

Custom
Date:
DC/DC CPUCORE(NCP81382)

WOLVERINE3 UMA
1
Sheet 80 of 100
Rev
0.1
5 4 3 2 1
EMC@
PL408
BLM18KG300TN1D
1 2
y
EMC@
1 2 EMC@ EMC@ RF_NS@ VCCGFXCORE_I
VINT20
l
PL407
D BLM18KG300TN1D D
2200P_0402_25V7-K
10U_0603_25V6-M
10U_0603_25V6-M
10U_0603_25V6-M
10U_0603_25V6-M
47P_0402_50V8-J
0.1U_0402_25V6
PC469
1
1
PC463
PC464
PC465
PC466
PC467
PC468
2
2
n
2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
2 2 2 2 2 2 2 2 2 2 2 2 2
PC472
PC473
PC474
PC475
PC476
PC477
PC478
PC479
PC481
PC482
PC483
PC484
PC485
VCCGFXCORE_I
1 1 1 1 1 1 1 1 1 1 1 1 1
TDC= 18A
o
VCC5M IccMAX=31A
OCP min = 41A
PR456
3.9_0402_1%
1 2
1
20150602@Change PR457 PC470
20
21
22
23
24
25
28
30
1
n
2_0603_5% 0.22U_0402_16V6-M
BOOT
THWN
GH
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
2
2
6
VCC
VCCGFXCORE_I
7 29
VCCD PHASED
1
1
PC471 PC480 27
1U_0402_6.3V6-K 1U_0402_6.3V6-K PHASEF PL402
o
0.15UH_PCME063T-R15MS0R907_37A_20%
2
2
12 1 2
PU403 VSW1 13
VSW2 14
i
NCP81381MNTXG_QFN39-31_6X4
VSW3 15
VSW4 16 VCCGFXCORE_I 34pcs 22uF for VCCGFXCORE_I
VSW5
2
5 17
PWM1_2PH CGND1 VSW6
t
79 PWM1_2PH 4 18 PR461
DRVON 2 PWM VSW7 4.7_0603_5%
79 DRVON DISB#
C 31 C
VCC5M ZCD_EN EMC_NS@
1
3
PGND1
PGND2
1
SMOD# PR465 PR466
GL1
GL2
GL3
GL4
0_0201_5% 0_0201_5%
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
330U_D2_2V_R9M
1
8
9
10
11
19
26
2
1
PC486 CSN1 CSN1 79 2 2 2 2 2 2 2 2 2 2
PC487
PC488
PC489
PC490
PC491
PC492
PC493
PC494
PC495
PC496
PC497
680P_0402_50V7K +
EMC_NS@
2
c
2 1 1 1 1 1 1 1 1 1 1
CSP1 CSP1 79
if i
B
e r t VCCGFXCORE_I
c
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
2 2 2 2 2 2 2 2 2 2 2
PC506
PC510
PC511
PC512
PC513
PC514
PC515
PC516
PC507
PC517
PC508
1 1 1 1 1 1 1 1 1 1 1
f t y
A
s a A
Issued Date
Deciphered Date
Title
DC/DC VCCGFXCORE_I(NCP81382)
F
Custom 0.1
5 4 3 2 1
5 4 3 2 1
All the input MLCCs must be placed

n ly D
VINT20
1
EMC@
PL410
BLM18KG300TN1D
2 EMC@ EMC@ RF_NS@
n o
47P_0402_50V8-J
10U_0603_25V6-M
10U_0603_25V6-M
2200P_0402_25V7-K
0.1U_0402_25V6
PC526
1
1
PC522
PC523
PC524
PC525
o
+VCCSA 6pcs 22uF for VCCSA
2
2
VCC5M
i
TDC= 4A VCCSA
IccMAX=5A
t
PR470
3.9_0402_1%
OCP min = 9A
1
C 1 2 C
a
20150602@Change PR469
2_0603_5%
12
13
14
15
23
1
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
PC527 2 2 2 2 2 2
BOOT
THWN
VIN1
VIN2
VIN3
VIN4
2
0.22U_0402_16V6-M
PC530
PC531
PC532
PC533
PC534
PC535
c
6
VCCSA
2
7 VCC 22
VCCD GH 21 1 1 1 1 1 1
i
PHASE
1
PC528 PC529 PU405 PL404

1U_0402_6.3V6-K 1U_0402_6.3V6-K NCP81380MNTXG_QFN30-24_4X4 0.47UH_PCMB063T-R47MS3R675_18A_20%
17 1 2
2
VSW1
if
18
5 VSW2 19
PWM_1B 4 CGND VSW3 20
79 PWM_1B PWM VSW4
79 DRVON DRVON 2
DISB#
2
24
PGND1
VCC5M ZCD_EN
3 PR476
SMOD# GL1
GL2
GL3
GL4
t
4.7_0603_5%
EMC_NS@ VCCSA VCCSA
8
9
10
11
16
1
r
PR467 PR468
0_0201_5% 0_0201_5%
1
PC536
2
680P_0402_50V7K
e
CSN_1B
EMC_NS@ CSN_1B 79
22U_0603_6.3V6M
22U_0603_6.3V6M
2 2 2 2
c
PC537 PC538
PC540
PC539
B 22U_0603_6.3V6M 22U_0603_6.3V6M B
1 1 1@ 1@
SW_1B
SW_1B 79
f t y
s a
A
o r Security Classification LC Future Center Secret Data Title

A
F
Issued Date Deciphered Date DC/DC VCCSA(NCP81380)
Custom 0.1
5 4 3 2 1
5 4 3 2 1
y
PR755
l
D 0_0201_5% D
62 SUS_ON2 1 2
1
PC717
0.1U_0402_16V7-K
n
2
0.1U_0402_6.3V7-K
2
2
PR765
PC792
o
210K_0402_1%
1
VCC3M
1
2
1
PR766 PR738
+VCC1R0_SUS
24
25
26
27
28
29
210K_0402_1% 100K_0201_5%
REFIN2
GND2
REFIN
EN
VREF
RA
PR749
TP56 TDC= 10A
2
0_0201_5%
VCC5M 23
GSNS PGOOD
1 VDDPALW_PWRGD 1 2 1
OCP = 16A
22 2 @ PR761
VSNS LP# TESTPAD
o
PC776 0_0201_5%
@ PR708 2 1 21 3 2 1
0_0201_5% SLEW MODE
i
2 1 0.01U_0402_25V7-K 20 4 @ PR709 PC789
TRIP NC
PC716 19 PU702 5
0_0402_5%
1 2
0.1U_0603_25V7K
1 2 PL702
VCC1R0_SUS
C 2.2U_0603_10V6-K GND1 BST 1.0UH_PCMC063T-1R0MN_11A_20% PJ702 C
t
1 2 18 TPS51367RVER SW1 6 1 2 EMC@ 2 1
PJ701 V5 2 1
1 2 EMC@ EMC@ RF_NS@ RF_NS@ 17 7 @ JUMP_43X118
VINT20
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
2200P_0402_25V7-K
0.1U_0201_10V6-K
1 2 VIN3 SW2
2
2 2 2 2 2
1
16 8 PR760 PJ703
PC718
PC719
PC720
PC721
PC722
PC723
PC724
10U_0603_25V6-M
10U_0603_25V6-M
68P_0402_50V8J
0.1U_0402_25V6
47P_0402_50V8-J
2200P_0402_25V7-K
a
JUMP_43X79 VIN2 SW3 4.7_0603_5% 2 1
PC790
1 2 1
1
1
@ 15 9
PC713
PC714
PC712
PC715
PC788
EMC_NS@
2
VIN1 SW4 1 1 1 1 1@ @ JUMP_43X118
PGND5
PGND4
PGND3
PGND2
PGND1
1
2
2
2
c
14
13
12
11
10
1
PC787
i
680P_0402_50V7K
EMC_NS@
2
B
r t Mode
GND
Frequency
400KHz
if B
e
Float 800KHz
y c
A
a f t A
r s Security Classification
Issued Date
Deciphered Date
Title
DC/DC VCC1R0_SUS(TPS62134C)
o
Custom 0.1
5 4 3 2 1
F
5 4 3 2 1
n ly D
n o
t io
C
BLANK i c a C
r t if
ce
y
B B
a f t
r s
A
Title
BLANK

A
Custom
WOLVERINE3 UMA 0.1

5 4 3 2 1
5 4 3 2 1
2
@ PC302
0.1U_0402_10V6-K
PR301
20150617@Change
@ PJ301
12/10 change netname
n ly D
o
0_0201_5% JUMP_43X79
2 1 DDR_VTT_PG_CTRL 4
RF@ RF@ EMC@ EMC@ 1.2V_B+ 2 1
2 1 VINT20
PR306
1.2V_GND 0_0201_5%
2200P_0402_25V7-K
68P_0402_50V8J
10U_0805_25V6-K
10U_0805_25V6-K
0.1U_0402_25V6
2 1
47P_0402_50V8-J
2R5A_PWRGD 88 1
1
1.2V_GND
PC320
PC321
PC308
PC309
PC310
VCC3M
PC319
PD301
2
2 1 2
20150602@Change A_ON 71,88
1
@ PR302
S3_1.2V
@ PR305 0_0201_5%
61.9K_0201_1%
2
1
o
100K_0201_1% 2 1 -PCH_SLP_S4 13,17,62,71
PR303
PR304
1K_0201_5%
S5_1.2V
2
i
1 2
VDDQ_PGOOD
2
@ PC301
t
0.1U_0402_10V6-K
+VCC1R2A
5
C C
20
19
18
17
16
D
S3
S5
PGOOD
MODE
TRIP
12/23 @ modify 21 @ PR309 PC311 PQ301
TDC= 9.2A
a
PAD 0_0402_5% 0.1U_0603_25V7-M AON7410 1N DFN
1
VTTSNS VBST
15 1R2A_BST
1 2 1 2 4
G OCP =12A
1.2A
S3
S2
S1
1R2A_SW 2 14 1R2A_UG
c
VLDOIN DRVH PL301
3
2
1
1UH_PCMC063T-1R0MN_11A_20% PJ302
VCC0R6BP 3 PU301 13 1R2A_LX 1 2 1R2A_SW EMC@ EMC@ 2 1
i
VTT SW 2 1
VCC1R2A
1
PC304 PC303 TPS51716RUKR_WQFN20_3X3

10U_0603_6.3V6M 0.1U_0402_6.3V7-K PQ302 @ JUMP_43X118
330U_D2_2V_R9M
1
4 12 AON7534 1N DFN
2200P_0402_25V7-K
0.1U_0402_25V6
VCC5M
2
VTTGND V5IN
5
+
PC314
PJ303
1 if
2
1
PC316
PC317
PC312 2 1
D
+VTT_REFP VDDQSNS 2 1
5 11 1U_0603_25V6-K PR311
VTTREF DRVL 4.7_0603_5% 2 @ JUMP_43X118
2
1
REFIN
PGND
VREF
PC305
EMC_NS@
GND
1U_0402_6.3V6-K 1R2A_LG 4
1
G
t
2
S3
S2
S1
6
10
1
PC313
DDR_VREF 680P_0402_50V7K
3
2
1
1.2V_GND
EMC_NS@
r
2
1
REFIN
13K_0201_1%
1
PR307
PC306
0.1U_0402_25V6-K
PJ304
2 1 2
e
2
B
VCC0R6BP 2 1
VCC0R6B 1.2V_GND
B
@ JUMP_43X39
1.2V_GND
1
c
1
PR308
PC307 25.5K_0201_1%
0.01U_0402_25V
2
1.2V_GND 1.2V_GND
f t 2
@
PR312
0_0402_5%
1
y
a
1.2V_GND
r s Security Classification LC Future Center Secret Data Title

A
o
Issued Date Deciphered Date DC/DC VCC1R35A(TPS51716)
Custom 0.1
WOLVERINE3 UMA
F
5 4 3 2 1
5 4 3 2 1
n ly D
n o VCC1R8_SUS
TDC= 1A
C
PL703
t io 20150623@Change
C
4
PJ712 1UH_PH041H-1R0MS_3.8A_20% PJ711
2 1 EMC@ EMC@ 10 1 1 2 EMC@ EMC@ 2 1
VCC5M VCC1R8_SUS
PG
2 1 PVIN2 LX1 2 1
2200P_0402_25V7-K
a
9 2
10U_0603_10V
@ JUMP_43X79 @ JUMP_43X79
PVIN1 LX2
22P_0402_50V
PC795
PC738
2200P_0402_25V7-K
22U_0603_6.3V6-M
22U_0603_6.3V6-M
PC737
0.1U_0402_25V6
0.1U_0402_25V6-K 8 3 PR722
SVIN1 LX3
1
PC741
PC740
PC743
PC746
PC739
4.7_0603_5%
c
2
1
PU706 EMC_NS@
RT8068AZQW PR723
2
5 6
i
20K_0201_1%
GND
EN FB
NC
2
PC745
2
PR718 680P_0402_50V
11
7
if
0_0201_5%
EMC_NS@
1
2 1 EN_+1.8VS
72 SUS_ON1
1
@ PD701
t
RB751V-40 @ PR762 @ PC794
1 2 1M_0201_1% 0.1U_0402_10V
1
2
r
PR721
2
10K_0201_1%
2
e
B B
y c
a f t
s
A A
r
Issued Date Deciphered Date DC/DC VCC1R8_SUS(RT8068A)
o
Custom 0.1
5 4 3 2 1
F
5 4 3 2 1
n ly D
n o
t io
C
BLANK i c a C
r t if
ce
y
B B
a f t
r s
A
Title
BLANK

A
Custom
WOLVERINE3 UMA 0.1

5 4 3 2 1
5 4 3 2 1
n ly D
VCC3M
20150617@Change
n o +VCC2R5A
2
PR751
100K_0201_5% TDC= 2A
OCP=3A
1
i
2R5A_PWRGD 85
t
C C
PL704
4
PJ715 1UH_PH041H-1R0MS_3.8A_20% PJ716
2 1 EMC@ EMC@ 10 1 1 2 EMC@ EMC@ 2 1
VCC5M VCC2R5A
PG
2 1 PVIN2 LX1 2 1
2200P_0402_25V7-K
a
2
9 2
10U_0603_10V
10U_0603_10V
@ JUMP_43X79 @ JUMP_43X79
PVIN1 LX2
22P_0402_50V
PC783
PC784
PC791
2200P_0402_25V7-K
22U_0603_6.3V6-M
22U_0603_6.3V6-M
PC801 PR803
0.1U_0402_25V6
0.1U_0402_25V6-K 8 3 4.7_0603_5% PR724
SVIN1 LX3
1
PC803
PC785
PC793
PC756
PC786
31.6K_0201_1%
EMC_NS@
2
c
2
PU701
2 1
RT8068AZQW
2
5 6
i
PC802
GND
EN FB 680P_0402_50V
NC
EMC_NS@
1
PR750
if
11
7
0_0201_5%
2 1
85,94 A_ON
1
@ PD702
t 1
1
RB751V-40 @ PR801 @ PR802
1 2 1M_0201_1% 0.1U_0402_10V PR753
10K_0201_1%
2
r 2
2
e
B B
y c
a f t
s
A A
r
Issued Date Deciphered Date DC/DC VCC2R5A(RT8068A)
o
Custom 0.1
5 4 3 2 1
F
5 4 3 2 1
Adapter
DCBATOUT
TI
TPS51285B
PWM
+5VLP/ 100mA
+5VALW/8A
n ly D
o
5VALW_ON EN PGOOD ALW_PWRGD
FOR SYSTEM
RICHTEK
+3VLP/ 100mA RT8068A
DCBATOUT
1.8V/1A
n
+3VALW/10A EN FOR V1.8A PGOOD
o
3VALW_ON EN PGOOD ALW_PWRGD
C
TI
DCBATOUT
SYSON
SUSP#
S5
S3
TI
TPS51716RUKR
FOR DDR
+1.35V/13A
+0.675VS/1.8A
a t i EN
RICHTEK
RT8068A
FOR DDR4
PGOOD
2.5V/2A
c
PGOOD SUS_PWRGD
BQ24780SRUYR
Battery Charger
Switch Mode
TI
TPS51367
if i
t
1V/10A
Onsemi
SMBus PSYS FOR V1R0A NCP81382
r
EN PGOOD
CPU Core
TDC 21A / IccMAX 28A
FOR VCCCPU
e
EN PGOOD
Battery Onsemi
c
DCBATOUT
Li-ion NCP81208 Onsemi
NCP81381
VCCGT
VR_ON
FOR IMVP8 TDC 18A / IccMAX 31A
EN PGOOD
y
B PGOOD_NB FOR VCCGFX B
EN PGOOD
a f t Onsemi
NCP81380 VCCSA
TDC 4A / IccMAX 5A
r s EN
FOR VCCSA
PGOOD
F o Security Classification LC Future Center Secret Data Title

BLOCK DIAGRAM
A
Issued Date Deciphered Date

Custom 0.1
5 4 3 2 1
5 4 3 2 1
n ly D
n o
t io
C
BLANK i c a C
r t if
ce
y
B B
a f t
r s
A
Title
BLANK

A
WOLVERINE3 UMA
5 4 3 2 1
5 4 3 2 1
n ly D
n o
t io
C
BLANK i c a C
r t if
ce
y
B B
a f t
r s
A
Title
BLANK

A
Custom
WOLVERINE3 UMA 0.1

5 4 3 2 1
5 4 3 2 1
0.3A
VCC3M VCC3_SUS VCC5B VCC5_TP
ly
1
D D
RJ4
1
n
JUMP_43X79
Q17 @ Q18
2
RW1E014SNT2R_WEMT6 RW1E014SNT2R_WEMT6
2
6 6
5 5
o
2 4 2 4
1 1
3
3
2
2
100_0201_5%
100_0201_5%
1
1
R291
R290
2
2
R292 R293 VCCCPUIO
t
33_0201_5% 33_0201_5%
1
1
a
C286 C287 C288 C289 C290
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
0.1U_0402_25V7K
2 2 2 2
2
C C
2
2
1
c
D41 D40 RJ3
1
RB521CS-30GT2RA_VMN2-2 RB521CS-30GT2RA_VMN2-2
1
1 1 1 1
1
JUMP_43X79
1
i
VCC1R0_SUS @
2
Change C286/C287/C288/C289 from 0805 to 0603
2
if
72 SUS_DRV 72 VCC5_TP_DRV
5
0.1U_0402_25V7K
0.1U_0402_25V7K
Q33
r
TPCF8002_2-3U1A
2
2
C210
C209
1
1
ce
4
y
B N37033767 B
2
t
R390
270_0201_5%
100_0201_5%
0.1U_0402_25V7K
f
2
C285
R389
a
1
1
2
D61
@
1
@
r
R406 1 2 0_0201_5%
72 B_DRV
R407 1 2 0_0201_5%
72 VCCCPUIO_DRV
o
0.1U_0402_25V7K
2
C282
1
F
A A

Issued Date 2014/08/10 Deciphered Date 2015/08/10 LOAD SW PCH SUS
Custom
WOLVERINE3 UMA 0.1

5 4 3 2 1
5 4 3 2 1
D
0.5A
VCC3LAN
n ly D
1
VCC3M
RJ5
1
JUMP_43X79
@
2
o
2
n
8
5
Q19
TPCF8002_2-3U1A
io
1
4
t
2
R294
a
2
100_0201_5%
33_0201_5%
C C
1
1
c
R295
2
i
D42
1
if
72 VCC3LAN_DRV
e r t 1 2
C211
0.1U_0402_25V7K
y c B
a f t
r s
A
Title
LOAD SW LAN

Custom
WOLVERINE3 UMA
Rev
0.1
A

5 4 3 2 1
5 4 3 2 1
n ly D
"change Q34 from SA000073C00 to SA000073D00 ,

and change power rail from 3M to 5M
C293 from 2200PF to 220PF"
VCC5M
VCC5M
n o
o
VCC3M
0.1U_0402_25V7K
i
0.1U_0402_25V7K
2
C291
t
2
C295
VCC1R0_SUS
1
VCCST VCC1R0_SUS
1
VCCSTG
2
Q34
1
R398 Q35
VDD
C C
10K_0201_5%
VDD
3 4
if c
D S 3 4
1
D S
2 5 D62
71,88 A_ON ON CAP 1 2 2 5
71 B_ON ON CAP
GND
GND
RB521CM_30
SLG5NT1533VTR_STDFN8-6_1X1P6
D63
6
i
1 SLG5NT1533VTR_STDFN8-6_1X1P6
6
C292 1 1 2 1
13,17 -PCH_SLP_S0
10U_0603_6.3V6M C296 1
rt
Q34
C293 10U_0603_6.3V6M
2 RB521CM_30 Q35
220P_0201_25V7K C294
2 change D63 from NI to install for power off sequence 2
220P_0201_25V7K
2
ce
y
B B
a f t
r s
A
Title

LOAD SW CPU
R ev
A
Custom
WOLVERINE3 UMA 0.1

5 4 3 2 1
5 4 3 2 1
3A
VCC3B
4A VCC5B
8/17 change PN for GCM
n ly D
o
VCC5M
1
VCC3M 8/17 change PN for GCM R387 VCC1R2A_DIMN VCC1V2B
0.01_0805_1%
2
1
n
R386
0.01_0805_1%
o
1
2
5
1 5 3
i
2 Q21
5 3 TPCF8002_2-3U1A
Q26
4
SIS402DNT1GE_POWERPAK1212-8-5
4
1
Q20
SIS402DNT1GE_POWERPAK1212-8-5 Footprint common design R372
2
1
a
47_0201_5%
2
100_0201_5%
R296 R297
2
100_0201_5%
0.1U_0402_25V7K
270_0201_5% 100_0201_5%
2
C C
0.1U_0402_25V7K
2
C283
if c
1
2
2
C284
1
R373
1
1
2
2
100_0201_5%
R299
1
2
2
D58
D44 D43 RB521CS-30GT2RA_VMN2-2
1
RB521CS-30GT2RA_VMN2-2 @
1
1
@
1
R301
B_DRV
i
72 VCC3B_DRV 72 VCC5B_DRV 72 B_DRV
rt
0.022U_0402_25V7K
0.1U_0402_25V7K
2
2
C212
C256
0.047U_0402_25V7K
2
C213
1
1
e
1
y c B
a f t
r s
A
Title

LOAD SW B
R ev
A
Custom
WOLVERINE3 UMA 0.1

5 4 3 2 1
5 4 3 2 1
VCC3WLAN
8/17 change PN for GCM VCC3WAN
y
8/17 change PN for GCM
l
2.7A
1
R384 2.7A
D 0.01_0805_1% R385 VCC3B D
VCC3M VCC3M 0.01_0805_1%
n
2
2
10A
R302
o
1 2
0.001_0603_5%
@
8
5
Q23 Q24
TPCF8002_2-3U1A TPCF8002_2-3U1A
io n
1
4
C
N37033752
a t C
2
2
c
R303 R304
33_0201_5% 33_0201_5%
i
100_0201_5%
100_0201_5%
2
2
1
1
R305
R306
if
1
1
2
2
D46 D47
RB521CS-30GT2RA_VMN2-2 RB521CS-30GT2RA_VMN2-2
t
1
1
72 VCC3WLAN_DRV 72 VCC3WAN_DRV
r
0.1U_0402_25V7K
e
2
C215
0.1U_0402_25V7K
c
1
2
C216
1
y
B B
t
TABLE
s a f AOAC
R1055
Q94
R8924
C8283
YES
NO-ASM
ASM
ASM
ASM
NO
ASM
NO-ASM
NO-ASM
NO-ASM
o r D238 ASM NO-ASM
F
A A
LOGIC

Issued Date 2014/08/10 Deciphered Date 2015/08/10 LOAD SW WWAN & WLAN
Custom
WOLVERINE3 UMA 0.1

5 4 3 2 1
5 4 3 2 1
n ly D
n o
t io
C
BLANK i c a C
r t if
ce
y
B B
a f t
r s
A
Title
BLANK

A
Custom
WOLVERINE3 UMA 0.1

5 4 3 2 1
5 4 3 2 1
n ly D
o
ST1 ST2 ST3 ST4 ST5
HOLEA HOLEA HOLEA HOLEA HOLEA
1
FD1 FD2 FD3 FD4 FD5 FD6
PAD_C6P5D2P8 PAD_C6P5D2P8 PAD_C5P6D3P4 PAD_CB6P6D3P4
io
pad_ct6p5b7p5d3p4
n
t
H1 H2 H3 H4
1
1
HOLEA HOLEA HOLEA HOLEA
a
1
1
C C
pad_c6p5d3p5 pad_c6p5d3p5 pad_c6p5d3p5 pad_c6p5d3p5
i c
if
H9 H10 H11 H12
HOLEA HOLEA HOLEA HOLEA
t
1
1
r
pad_ct6p0b5p0d2p5 PAD_C6P5D2P5 PAD_C6P5D2P5 PAD_C6P5D2P5
ce H5
HOLEA
1
H6
HOLEA
H7
HOLEA
H8
HOLEA
1
PAD_C6P5D2P8 PAD_C6P6D2P5 PAD_C6P6D2P5 PAD_C7P0D2P8
y
B B
t
Add H15 for ME request
f
H13 H14 H15
HOLEA HOLEA PAD_C4P0D1P7
a
1
1
PAD_O1P8X2P6D1P8X2P6N pad_ct6p5b8p0d2p5 PAD_C4P0D1P7
r s
A
Title
PTH FOR SCREW HOLES

A
Custom
WOLVERINE3 UMA 0.1

5 4 3 2 1
5 4 3 2 1
n ly D
n o
t io
a
C C
BLANK i c
r t if
B
ce B
f t y
s a
A
o r A
5
F 4 3
2
Title
Custom
Date:
BLANK

WOLVERINE3 UMA
1
Sheet 99 of 100
Rev
0.1
5 4 3 2 1
change Power rail for NEC LED color only green and amber
VCC3B VCC3M VCC3M
n ly D
2
o
F19 F18 F17
0.5A_32V_ERBRD0R50X 0.5A_32V_ERBRD0R50X 0.5A_32V_ERBRD0R50X
J45 ME@
1
1 2
R380 1 2 150_0201_5% 3 1 2 4 R381 1 2 150_0201_5%
10 SATALED# 3 4 -LED_PWR 61
R378 1 2 0_0201_5% R399 1 2 150_0201_5% 5 6 R400 1 2 150_0201_5% R379 1 2 0_0201_5%
61 DC_BAT_LED 5 6 CHARGER_LED 61
7 8
n
9 7 8 10
9 10
11 12
GND1 GND2
1
D HRS_DF12L3P010DP0P5V86 D
o
2 @ @ 2
G Q31 Q32 G
LSK3541G1ET2L 1N VMT3 LSK3541G1ET2L 1N VMT3
i
S S
3
3
8/17 SVT Change Limited resistor to 150 ohm
C C
a t
i c
B
r t if B
ce
f t y
A
s a A
r
Issued Date 2014/08/10 Deciphered Date 2015/08/10 NEC LED BOARD

o
WOLVERINE3 UMA
5 4 3 2 1

.ThinkPad X260 - NM-A531 Schematic

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5 4 3 2 1

014.CPU(12/16) : CPU POWER

070.SMBUS SW/LPC DEBUG PORT Issued Date 2014/08/10

Size Document Number

Date: Thursday, August 20, 2015 Sheet 1 of 100

Size Document Number

Size Document Number R ev

Security Classification LC Future Center Secret Data Title

Place near to CPU

Size Document Number R ev

For DCI debug

Size Document Number R ev

AW13 AW9 LPCCLK_EC_24M_R RC30 1 2 22_0201_5%

Size Document Number R ev

Size Document Number R ev

RC36 1 2 1K_0201_5% RC37 1 @ 2 0_0603_5%

RC39 1 2 33_0201_5% HDA_SYNC_R BA22

Size Document Number R ev

1 2 PCIE_RCOMPN F5 USB2_ID AG4 USB2_VBUSSENSE

Security Classification LC Future Center Secret Data Title

B31 CSI2_DN6 AP2 PLANARID1 RC51 1 2 0_0201_5%

Size Document Number R ev

RC56 1 2 0_0201_5% XTAL24_OUT_R1 3

Size Document Number R ev

VCCCPUCORE VCCCPUCORE RC74 1 2 0.001_0603_5%

CPU(12/16) : CPU POWER

VCCGFXCORE_I K20 A22 K21 AM40 AL23

N63 AM58 AM23

VCCGT_N69 VCCGTX_BB66 VCCSA_SENSE

SKYLAKE-U_BGA1356 100_0201_1% 100_0201_1%

Security Classification LC Future Center Secret Data Title

Date: Thursday, August 20, 2015 Sheet 15 of 100

CC39 CC40 CC41 N17 VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3

Size Document Number

Security Classification LC Future Center Secret Data Title

CFG4 : eDP Enable RESERVED SIGNALS-1 SPARE

1 : Disabled E68 BB68 AW69 F6

Size Document Number

REF DES Planar only BOX

e r t TABLE: PCH ITP DEBUG port

B TRST# RC113 ASM ASM TDI RC115 ASM ASM B

Size Document Number

VCC3SW VCC3SW RTCVCC

Size Document Number

SF100 PIN HEADER INTERFACE (TOP VIEW)

vPro/non-vPro Model (16MB)

Size Document Number R ev

CD26 2 RF@ 2 1 100P_0201_25V8J 47P_0201_25V8J

RD4 RD5 RD6

PLACE THE CAP CLOSE TO SODIMM

Security Classification LC Future Center Secret Data Title

Issued Date 2014/08/10 Deciphered Date 2015/08/10 DDR4 SO DIMM

Date: Thursday, August 20, 2015 Sheet 22 of 100

Size Document Number

Size Document Number