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Digital Logic Design: Assignment# 3

This document contains the solutions to 5 questions on digital logic design. It includes Verilog code for an 4-bit adder/subtractor, 4-bit multiplexer, 8-bit decoder, and 4-bit decoder. It also lists the name, registration number, and class of the student submitting the assignment.

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Zojaan Aheer
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101 views8 pages

Digital Logic Design: Assignment# 3

This document contains the solutions to 5 questions on digital logic design. It includes Verilog code for an 4-bit adder/subtractor, 4-bit multiplexer, 8-bit decoder, and 4-bit decoder. It also lists the name, registration number, and class of the student submitting the assignment.

Uploaded by

Zojaan Aheer
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Digital Logic Design

Assignment# 3

Name Muhammad Farhan

Registration Number SP20-BSE-049

Class Section 2A

Teacher’s Name Pro. Sikander Gul


Question 1
module Adder_sub(a,b1,cin,out_sum_diff, carry,borrow);
input[3:0] a,b1;
input cin;
output [3:0] out_sum_diff;
output [3:0] borrow;
output [3:0] carry;
wire [3:0] sums;
wire [3:0] diff;

// following code is for subtractor

wire [3:0] w;
not n1(w[0],b1[0]);
FullAdder h1(diff[0],borrow[0],a[0],w[0],1'b1);
not n2(w[1],b1[1]);
FullAdder h2(diff[1],borrow[1],a[1],w[1],borrow[0]);
not n3(w[2],b1[2]);
FullAdder h3(diff[2],borrow[2],a[2],w[2],borrow[1]);
not n4(w[3],b1[3]);
FullAdder h4(diff[3],borrow[3],a[3],w[3],borrow[2]);

// following code is for adder

FullAdder g1(sums[0],carry[0],a[0],b1[0],1'b0);
FullAdder g2(sums[1],carry[1],a[1],b1[1],carry[0]);
FullAdder g3(sums[2],carry[2],a[2],b1[2],carry[1]);
FullAdder g4(sums[3],carry[3],a[3],b1[3],carry[2]);

mux_4bit fu(sums,diff,cin,out_sum_diff);

endmodule

module FullAdder (s,cout,a, b, c);


input a, b,c;
output s, cout;
assign s= a ^ b^c;
assign cout= (a & b) | (c&(a^b));
endmodule

module Full_Subtractor(D,B,X,Y,Z);
output D, B;
input X, Y, Z;
assign D = X ^ Y ^ Z;
assign B = ~X & (Y^Z) | Y & Z;
endmodule

module mux_4bit ( a ,b , sel, dout );

output [3:0]dout;

input [3:0]a ;
input [3:0]b ;
input sel ;

assign dout = sel ? b : a;

endmodule

output of the code:

Question 3
module multiplex(Out,s,inp);
input [7:0]inp;
input[2:0]s;
output Out;
wire w1,w2,w3,w4,w5;
mux g1 ({s[1:0]},{ inp[3:0]},w1);
mux g2({s[1:0]},{ inp[7:4]},w2);
not g3(w3,s[2]);
and g4(w4,w1,w3);
and g5(w5,w2,s[2]);
nor g6(out,w4,w5);
endmodule

module mux( sel, inp, out );


input[1:0] sel;
input[3:0] inp;
output out;
reg out;
always @( sel or inp )
begin
if( sel == 0)
out = inp[0];
else if( sel == 1)
out = inp[1];
else if( sel == 2)
out = inp[2];
else if( sel == 3)
out = inp[3];

end
endmodule
output of the above code:

Question 4
module decoder(x,y,z,w,e,d);
input w,x,y,z,e;
output [15:0]d;
assign d[0]= (~x) & (~y) &(~z) & (~w) & (e) ;
assign d[1]= (~x) & (~y) &(~z) & (w) & (e) ;
assign d[2]= (~x) & (~y) &(z) & (~w) & (e) ;
assign d[3]= (~x) & (~y) &(z) & (w) & (e) ;
assign d[4]= (~x) & (y) &(~z) & (~w) & (e) ;
assign d[5]= (~x) & (y) &(~z) & (w) & (e) ;
assign d[6]= (~x) & (y) &(z) & (~w) & (e) ;
assign d[7]= (~x) & (y) &(z) & (w) & (e) ;
assign d[8]= (x) & (~y) &(~z) & (~w) & (e) ;
assign d[9]= (x) & (~y) &(~z) & (w) & (e) ;
assign d[10]= (x) & (~y) &(z) & (~w) & (e) ;
assign d[11]= (x) & (~y) &(z) & (w) & (e) ;
assign d[12]= (x) & (y) &(~z) & (~w) & (e) ;
assign d[13]= (x) & (y) &(~z) & (w) & (e) ;
assign d[14]= (x) & (y) &(z) & (~w) & (e) ;
assign d[15]= (x) & (y) &(z) & (w) & (e) ;

endmodule
output of the above code is:
Question 5:
module decoder(Data_out, inp);
input [2:0] inp;
output [7:0] Data_out;
reg [7:0] Data_out;
always @(inp)
case (inp)
3'b000 : Data_out = 8'b00000001;
3'b001 : Data_out = 8'b00000010;
3'b010 : Data_out = 8'b00000100;
3'b011 : Data_out = 8'b00001000;
3'b100 : Data_out = 8'b00010000;
3'b101 : Data_out = 8'b00100000;
3'b110 : Data_out = 8'b01000000;
3'b111 : Data_out = 8'b10000000;

default : Data_out = 8'b00000000;


endcase

endmodule

output of the above code is:

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