6/24/2020 How Does the PrimeTime SI si_xtalk_delay_analysis_mode all_path_edges Alignment Mode Work?

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Dec 11, 2019 • Knowledge

Title
How Does the PrimeTime SI si_xtalk_delay_analysis_mode all_path_edges Alignment Mode Work?

Description
Question:

pre { padding-left: 15pt; } p.image { text-align: center; } p.caption { font-style:italic; text-align: center; }

A PrimeTime SI delta delay analysis mode can be set with with the si_xtalk_delay_analysis_mode variable. The default setting is all_paths. An alternative setting, all_path_edges,
changes the aggressor-victim window alignment mode. How do the default and optional alignment modes work?

Answer:

The all_paths Alignment Mode

By default, PrimeTime SI uses the all_paths mode and computes the delta delays using the entire arrival window of the victim net.

Consider the logic shown in Figure 1:

Figure 1: Coupled Net Example

In the all_paths alignment mode, the victim arrival window is created using the earliest minimum-delay arrival and the latest maximum-delay arrival. The resulting victim arrival window
is used for both minimum-delay and maximum-delay delta delay calculations.

Figure 2 shows how a victim window might be computed for the coupled logic in all_paths mode. Since the victim window overlaps the aggressor window, the delta delays are nonzero
for both minimum-delay and maximum-delay analyses.

Figure 2: Victim Window in all_paths Alignment Mode

The all_paths alignment mode is fast and efficient, but it is also conservative. Because only the early side of the victim window overlaps the aggressor window, it might be possible that
the delta is zero for maximum-delay analysis because no maximum-delay edges arrive early enough to overlap with the aggressor.

The all_path_edges Alignment Mode

To reduce pessimism, use the all_path_edges alignment mode by setting the following application variable:

set_app_var si_xtalk_delay_analysis_mode all_path_edges

In this mode, PrimeTime SI considers all possible edge arrivals from the upstream logic, using minimum-delay edges for the minimum delta calculation and using maximum-delay edges
for the maximum delta calculation. In the example, the arrivals might be as shown in Figure 3:

Figure 3: Victim Arrival Edges

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The arriving edges are

1. Maximum-delay arrival through top path

2. Minimum-delay arrival through top path
3. Maximum-delay arrival through middle path
4. Minimum-delay arrival through middle path
5. Maximum-delay arrival through bottom path
6. Minimum-delay arrival through bottom path

In the example, the maximum-delay delta calculation is shown in Figure 4.

Figure 4: Maximum-Delay Calculation in all_path_edges Mode

The three late arrival edges are used to compute the maximum-delay delta. Since no arriving maximum-delay edges overlap with the aggressor window, PrimeTime SI computes a zero
maximum-delay delta.

The minimum-delay delta calculation is shown in Figure 5.

Figure 5: Minimum-Delay Calculation in all_path_edges Mode

The three early arrival edges are used to compute the minimum-delay delta. Since at least one minimum-delay edge overlaps with the aggressor window, PrimeTime SI computes a
nonzero minimum-delay delta.

A significant advantage of this mode over the all_paths mode is that on-chip variation effects no longer cause SI pessimism by widening the min/max victim windows. Figure 6 shows
that as on-chip variation increases, the early and late victim edges will move apart, but there is no longer a min/max victim arrival window that widens.

Figure 6: The all_path_edges Mode and Alignment and On-Chip Variation

Using an edge-based approach provides additional benefits. In some cases, an aggressor window might exist between multiple victim edges without any overlap. Such a situation is
shown in Figure 7.

Figure 7: Setup Calculation With Separated Arrival Edges

In this case, a window-based approach would result in a victim window that overlaps the aggressor window. However, the all_path_edges edge-based approach correctly detects that
no individual arriving edge overlaps with an aggressor arrival event.

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When multiple victim edges overlap with aggressor windows, as shown in Figure 8, PrimeTime SI keeps the worst delta delay across all overlapping victim edge configurations, and uses
it for all paths through the net.

Figure 8: Multiple Overlapping Victim Edges

In real designs, the logic is significantly more complex than what exists in this example. The number of possible edge arrivals at a net is typically very large due to effects like signal
convergence, signal reconvergence, and nonunate logic. PrimeTime SI uses proprietary algorithms to achieve the pessimism reduction in all_path_edges mode while keeping memory
and runtime reasonable.

To summarize, the all_path_edges alignment mode provides the following benefits:

The all_path_edges mode does not use minimum-delay victim arrivals to compute maximum-delay deltas, and vice versa.
The all_path_edges mode does not incur aggressions for non-overlapping aggressor windows that exist between separated victim edges.
The all_path_edges mode provides a timing graph whose edge-based delta delay calculation is closer to the path-based delta delay calculation.

Ensuring a Conservative Analysis

Take the following example where a victim net is attacked by a very strong aggressor net:

Figure 9: Critical and Subcritical Victim Arrival Edges

The edge of the most critical timing path is the latest-arriving edge V. In all_path_edges mode, the arrival time for this edge does not overlap the arrival window span for the aggressor.
Is it possible that the slightly earlier edge V' could incur such a large delta delay, that the overall resulting timing would actually be worse?

The answer is no. PrimeTime SI accounts for the "tail effect", where a victim can be partially attacked by an aggressor if there is partial overlap. You can see from the waveforms that the
transition for V partially overlaps the latest aggressor transition, so a partial delta delay would be computed. It is true that a larger delta delay would probably be computed for V'.
However, this larger delta delay will never be larger by an amount exceeding the difference in arrival times between V and V'.

Consider the following two edges feeding some arbitrary CMOS logic:

Figure 10: Bounding Property of CMOS Logic

CMOS logic works by using current to accumulate voltage levels within the gates. At every point in time, the voltage for input waveform (a) is equal to or greater than the voltage for input
waveform (b). This means at every point in time, a greater amount of current will have flowed at all points in the circuit, and the voltage at any downstream point will also be equal to or
greater than the voltage response from edge (b).

Stated more succinctly:

If the voltage of waveform (b) completely bounds waveform (a), any downstream response from (b) will also bound the response from (a).

Our example in Figure 4 is even more simple than this. In Figure 4, the waveform shapes V and V' are identical, and they are only displaced in time:

Figure 11: Varying Victim Arrivals (Shown Undisturbed) in the Presence of Crosstalk

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Let's say that aggressor net A is strong enough to cause a fairly sizeable delta delay on our victim edge V':

Figure 12: Disturbed Victim Waveforms for V and V', Attacked by Strong Aggressor

We can see that our disturbed victim edge V' has a large delta delay, but our later victim edge V remains undisturbed. If we look at our downstream response, we can see that the
disturbed response Z' has been pushed rightward, but not enough to reach edge Z.

What happens if our aggressor is so strong, it pushes the disturbed V' waveform past our later victim edge V? Let's make the aggressor even stronger:

Figure 13: Disturbed Victim Waveforms for V and V', Attacked by Even Stronger Aggressor

Now our aggressor is so strong, our disturbed victim edge V' has pushed past our original victim edge V. However, if the aggressor is this strong, the tail effect would attack edge V as
well, resulting in the disturbed victim edge V as shown. The arrival times and slews for our downstream responses Z and Z' have also changed. We can see that the change in delay for Z'
is larger than Z, but the response at Z still represents a later bound than the response at Z'.

Here is another common-sense way to think of the property:

It is not possible to move an input stimulus edge earlier in time, such that the response at any downstream point is pushed later in time.

In conclusion, the all_path_edges is conservative because both of the following conditions are true:

For each individual edge, the CMOS bounding property ensures that the overall coupled delay behavior for that edge is conservative.
For the overall analysis, all arriving victim edges are considered, and the worst delta delay across all edges is kept and used.

Comparison to Legacy Alignment Modes

Earlier releases of PrimeTime provided the all_violating_paths and worst_path enhanced alignment modes, as described in SolvNet article 015943, "Frequently asked questions
about the PrimeTime SI enhanced alignment modes" ().

The all_path_edges alignment mode solves the optimism and usability issues associated with these legacy alignment modes. The all_path_edges mode provides the following
advantages over the legacy enhanced alignment modes:

Unlike the all_violating_paths mode, positive slack paths can be reported without optimism.
Unlike the worst_path modes, subcritical paths to an endpoint can be reported without optimism.
Unlike the worst_path mode, no additional performance overhead for timing exception management is required.
Unlike the all_violating_paths and worst_path modes, the delta delay calculations are not affected by slack, and therefore are not affected by changes to timing exceptions.

Workaround

Product L1
PrimeTime-SI (/s/detail/01t1U000003IY0KQAW)

Additional Product(s)

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Article Number
000006197

Last Published Date

12/11/2019, 10:40 PM

Article Record Type

How To

URL Name
How-Does-the-PrimeTime-SI-si-xtalk-delay-analysis-mode-all-path-edges-Alignment-Mode-Work-1576012076304

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