ELEC 335

Digital Logic Design

by

Dr. Mohammad Shakeel Laghari

Course Coordinator

ELEC 335, Digital Logic Design, UAE University

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 Chapter 6

Sequential Systems

ELEC 335, Digital Logic Design, UAE University

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 Outline
• Sequential Circuits
• NOR and NAND Gates Latch
• SR Flip Flop
• D Flip Flop
• Edge Trigger Flip Flops
• JK Flip Flop
• T Flip Flop

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 Sequential Circuits
• Sequential circuits contain memory elements
• Most digital systems contain sequential elements
• Basic building blocks of sequential circuits are
flip-flops or latches
• We will study synchronous sequential circuits in
detail
• We will look at asynchronous counter design

ELEC 335, Digital Logic Design, UAE University

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 Sequential System

ELEC 335, Digital Logic Design, UAE University

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 P = (S + Q)¢
Q = (R + P)¢
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 P = (S + Q)¢
Q = (R + P)¢
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 NOR Gate Latch
٠-١ ‫ او‬١-٠ ‫ضع اي نواج‬

nor gates

Inputs Output
R (reset) Q S R Q Q’
0 0 No change
0 1 0 1
S (set) Q
1 0 1 0
S=1 …….Q=1
R=0…….Q:=0 1 1 Not allowed

ELEC 335, Digital Logic Design, UAE University

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 NAND Gate (S’-R’) Latch
Q should be !=Q'

NAND GATERS

Inputs Output
S Q S R Q Q’
1 1 No change
1 0 0 1
Q 0 1 1 0
R
0 0 Not allowed

‫ﺗﺗﺑﻊ اﻟﺻﻔر ﻓﻲ اﻟﻧور اﻣﺎ اﻟﺑﺎﻗﯾﺎت ﺗﺗﺑﻊ اﻟواﺣد‬

R ‫تتبع الواحد في الناند تتبع ناتج‬

ELEC 335, Digital Logic Design, UAE University

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 NAND Gate (S’-R’) Latch

Inputs Output
S Q S R Q Q’
1 1 No change
1 0 0 1
Q 0 1 1 0
R
0 0 Not allowed

‫ﺗﺗﺑﻊ اﻟﺻﻔر ﻓﻲ اﻟﻧور اﻣﺎ اﻟﺑﺎﻗﯾﺎت ﺗﺗﺑﻊ اﻟواﺣد‬

‫اﻟﻧﺗﺎﺋﺞ راح ﺗﻛون ﻋﻛس رﺳﻣﮫ اﻟﻧور ﺑﺎﻟﺿﺑط‬

ELEC 335, Digital Logic Design, UAE University

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 S S
Q
١ ‫د ا ي م ا تكون‬

R Q
R

Inputs Output
S R Cp Q Q’
1 1 1 Not allowed
S - R Flip Flop 1 0 1 1 0
0 1 1 0 1
0 0 1 No change
x x 0
ELEC 335, Digital Logic Design, UAE University
No change
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 S S
Q Save 1 pit of infor..

R Q
R

00 No change
01 the Q will be 0
Inputs Output
10 the Q will be 1
11 Not allowed because Q=Q, S R Cp Q Q’
1 1 1 Not allowed
S - R Flip Flop 1 0 1 1 0
0 1 1 0 1
0 0 1 No change
x x 0
ELEC 335, Digital Logic Design, UAE University
No change
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 S - R Flip Flop

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 S - R Flip Flop

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 D – Flip Flop
S
D S
Q
1
C

R Q
R
d=q with c=1

Inputs Output
D C Q Q’
0 1 0 1
1 1 1 0
X 0 No change
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D – Flip Flop

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 D – Flip Flop

dont know

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 D - Flip Flop

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 without D

D – Flip Flop

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 D – Flip Flop

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 J
Q

Q
K

Inputs Outputs
J K Q Q’
0 0 No change
JK - Flip Flop 0 1 0 1
1 0 1 0

ELEC 335, Digital Logic Design, UAE University 1 1 Invert

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 JK - Flip Flop

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 JK - Flip Flop

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 T - Flip Flop

T
Q

Input Outputs
T Q Q’
0 No change
1 Invert

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 T - Flip Flop

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 Edge Triggered Flip Flops

• A positive-edge-triggered D flip-flop (FF)

combines a pair of D latches, to create a circuit
that:
– Samples its D input and changes Q and Q only at the
falling or rising edge of a controlling CLK signal
• The first latch is called the master
• The second latch is called the slave

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 Negative-Edge-Triggered Flip Flop

D d q d q Q
Master Slave
CLK c c Q

Inputs Output
D CLK Q Q’
D 1 ¯ 1 0
CLK 0 ¯ 0 1
X 0 No change
Q X 1 No change
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 Positive-Edge-Triggered Flip Flop

D d q d q Q
Master Slave
c c Q

CLK

Inputs Outputs
D D Cp Q Q’
CLK 1 ­ 1 0
0 ­ 0 1
Q X 0 No change
X 1 No change
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 The Master Slave SR Flip-Flop
Falling edge triggered

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 Negative-Edge-Triggered D Flip Flop

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 The Master Slave JK Flip-Flop
Rising edge triggered

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 The Master Slave JK Flip-Flop
Falling edge triggered

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