ROM and its Design Methods: An Overview

Jaspreet Kaur, Srishti Sabharwal, Shabnam Khan, Karan Chauhan

Department of Electronics and Communication Engineering
Chandigarh University, Mohali

ABSTRACT
Read Only Memory is one of the prominent components that provide the required instructions
for efficient communication among hardware components. It plays crucial role in storage of
BIOS, data management and in reading and writing to the peripheral devices. This
semiconductor memory can be deployed in various applications like mobile sensing,
automobiles, home appliances etc. In order to meet the requirements of its application system
ROM designs need to be efficient enough to deal with the challenges like reduced supply
voltage, power dissipation etc. In this paper we have overviewed ROM as section of
semiconductor memories, discussed its different types and different design methods.

KEYWORDS: ROM, Semiconductor Memories, Bit lines, Word lines, CMOS.

INTRODUCTION
CMOS memories are one of the classifications of semiconductor memories; these are referred to
as CMOS memories as they are fabricated using Complementary-metal-oxide-semiconductor
technology. These memories are designed to perform the basic operation modes like read and
write and also capable of working in storage mode, data access mode and organization mode.

Read Only Memories (ROM) are used in storing constants, program instructions etc in digital
systems. ROM, a non-volatile memory can also be described as combinational Boolean network
that delivers fixed specific binary output for each input combination or we can say for each
address.

The Read only memory is hard wired and cannot be changed electronically. However, it exists in
form of erasable and electrically erasable ROMs which can be re-programmed and erased. But
this process of erasing and reprogramming usually occurs at slow speed and can be implemented
only limited number of times. The disadvantage of leakage power demands update in the ROM
technology, this leakage power comprises of 36% of the total ROM power [1].

In addition to the ROM, CMOS memories also consist of Random Access memories. RAM is
mainly a kind of Volatile memory which stores the data temporarily. The RAM deploys
transistors to store the information and when the electric current is stopped the data vanishes.
The essential difference between RAM and ROM is that data in the RAM can be updated,
changed and expanded as needed but in ROM this is not possible. In comparison to other
embedded memories, ROM has smaller size as its contents cannot be changed [2].

1. TYPES OF ROM
The types of ROM vary according to the ease of erasing and re programming the data onto
the ROM. Some of the eminent types of ROM are as follows:

a) Masked ROM
Masked ROM (MROM) in which the data is programmed into an integrated circuit and it
acts as static memory. It consists of grid of address inputs called word lines and data
output called bit lines. This grid is attached to transistor switches and this layout emerges
as look up table. Mask ROM also called solid state ROM is programmed during
fabrication and cannot be altered therefore leads to disadvantages which are addressed by
the subsequent developments like PROM, EEPROM etc.

b) Programmable Read Only Memory

This type of Memory can be altered and modified by user only once. A blank PROM is
written with desired data with the aid of PROM program. There are fuses inside the
PROM chip which are burnt open during the programming. All the possible pathways in
blank PROM have current running through it [3]; the pathways are chosen by the
programmer by sending high voltage to burn out the unwanted fuses. The PROM is more
vulnerable to damage than conventional ROM as static electricity can replicate the effect
of high voltage accidently and thus may burn the fuses which are required.

c) Erasable Programmable ROM

EPROM can be reused as it can be erased and programmed again. The data written on
EPROM with high voltage can be erased by exposing it to Ultraviolet light rays of
specific frequency. The quartz window in the chip allows UV light to burn out tiny
charges and open the circuits of the chip. The Ultraviolet light needs to be in effect for 10
minutes or longer. Due to this feature the EPROM can be retrieved as blank ROM and
can be programmed with new data. It also has grid of rows and columns, at each
intersection, there are two transistors: Floating gate and control gate [4]. The floating gate
is connected to row with the aid of control gate and this link gives cell the value 1. The
charge applied to the floating gate transform it to electron gun and these electrons form
barrier between floating gate and control gate and the logic value changes. To erase it, the
energy applied should be enough to break through the blocking electrons, therefore UV
light is used. The EPROM cannot be used and erased forever, they have lifetime of about
1000 erasers.
 d) Electrically Erasable Programmable Read Only Memory
Like EPROM, EEPROM can also be programmed again by erasing the data on it.
However, it differs on the method being employed to erase the data. Instead of ultraviolet
light, electrical fields are used to erase the data. There is no need of specific instrument to
rewrite the EEPROM. One of the unique features of EEPROM is that whole data does not
need to be erased for single edit, the data can be selectively erased and it possible to erase
one byte at a time, therefore preventing the wash out of entire information on the chip.
The time to erase and program EEPROM is also very small i.e. about few milliseconds.
There is no need of quartz window and it does not need to be separated from the
hardware to get updated. In the EEPROM the storage transistors have trapped electrons in
the floating gate. The another difference between EPROM and EEPROM is that in
EEPROM cell is erased when the floating gate gets electron trapped in it while in
EPROM the cell is erased when the electrons are exterminated from the floating gate.

2. IMPLEMENTATION METHODS OF ROM

The ROM comprises of array of MOSFETs, the gates of which are linked to the rows (word
lines), drains are connected to columns(bit lines) and the sources are grounded. The data path can
be present or absent from word line(selected row) and bit line(selected column) and this can be
used to store the binary information at particular address as this presence and absence is
analogous to device’s presence and absence at particular location. The ROM referred to as 2 n x m
bit ROM means it can store 2n words. Each word of m bit and n here denotes number of address
inputs and m denotes data bits [5].

In pseudo NMOS logic, PMOS load transistor is used to connect each bit line to the power
supply. If the NMOS is present in any cell, it indicates the cell value is 0, the cell which has 1
value indicates that there is no MOSFET. Let us consider we have (4 word x 4 bit) MOS ROM.
The row decoder would choose one of the 4 words by raising the corresponding word line
voltage. The transistor in this cell, which is connected to this word line will conduct and will
bring down the voltage of the connected bit line, close to the ground. This will lead to logic value
0 and the bit lines which are not connected to transistors will remain at logic 1.

In this paper, we have discussed two different types of methods of implementations of ROM:

(a) NOR – based ROM array:

To illustrate the functioning of NOR-based ROM array, Figure 3.1 is used. The Figure
shows memory array of 4 bit x 4 bit memory. The Truth table for the figure is
demonstrated in Table 1. The word line i.e. row signals drive pseudo nMOS NOR gate in
each column. By raising the voltage to VDD, one of the word line is activated and the
remaining rows are at low voltage level. Now, if an active transistor is present at
intersection of selected row and column then the transistor pulls down the voltage of the
 respective column to low level. The absence of transistor at the intersection drives the
column voltage to high level with the aid of pMOS load device. This demonstrates that
logic ‘1’ is stores at cell where there is no active transistor while at the cross point where
transistor is present, logic ‘0’ is stored.

Figure 3.1: NOR based ROM Array [4]

According to the functioning illustrated, the Truth table of the ROM array can be
obtained as follows:

Table 1: Truth Table for Figure 3.1

R1 R2 R3 R4 C1 C2 C3 C4
1 0 0 0 0 1 0 1
0 1 0 0 0 0 1 1
0 0 1 0 1 0 0 1
0 0 0 1 0 1 1 0

The nMOS transistors can be installed at cross point of two metal lines and two polysilicon word
lines as shown in Figure 3.3. When the drain or source connection is omitted, ‘1’ bit is realised
and to store the ‘0’ bit, metal bit line is connected to drain diffusion of the corresponding
transistor. When fast speed is needed, Core of NOR type is deployed [6].
 Figure 3.3: Metal column line to load devices [4]

The layout of ROM with programming using the active layer only is shown in Figure 3.4

Figure 3.4: Programming using active layer [6]

There is alternate method of implementation using NOR ROM, where, the threshold voltage of
nMOS transistor is raised through channel implants. By raising this threshold voltage the nMOS
transistor corresponding to the HIGH bit can be deactivated [7].

(b) NAND - Based ROM Array:

In NAND based ROM Array, depletion – load NAND gate is present at each bit line and
is driven by word lines. Except the line which is selected, all the other row signals are
kept at Logic ‘1’ voltage level and the selected one is pulled down to LOW logic level. If
at the cross point of selected row, transistor is present then it is turned off and the load
device pulls the column voltage to HIGH level[8]. In the absence of transistor at
intersection, the nMOS transistors in the multi-input NAND structure pull down the
column voltage. As a result, in presence of transistor which can be deactivated, logic ‘1’
is stored and logic ‘0’ is stored in case of shorted transistor at the cross point. Figure 3.5
shows the NAND- based ROM array.
 Figure 3.5: NAND – Based ROM [4]

According to the operation we get the Truth Table represented in Table 2.

Table 2: Truth Table for Figure 3.6

R1 R2 R3 R4 C1 C2 C3 C4
0 1 1 1 0 1 0 1
1 0 1 1 0 0 1 1
1 1 0 1 1 0 0 1
1 1 1 0 0 1 1 0

Similar to NOR ROM, NAND ROM can be initialized with presence of transistor at every
intersection of word line and bit line. The threshold voltage of transistor can be lowered to to
store the ‘0’ bit. As a result, the ON state of transistor is preserved independent of gate voltage.
In another type of implementation of NAND ROM consisting of Implant masks, there is
interaction at regular intervals between vertical columns and horizontal rows of polysilicon [9].
The threshold voltage implant in transistor allows it to operate as ON depletion device,
irrespective of gate voltage level and thus provide continuous current path [10].

3. CONCLUSION
Read only memory is an important component deployed in microprocessors, DSPs and other
special purpose accelerators. Its design allows it to store the information for the basic purpose of
reading. The updates in the ROM technology allow the erasing and reprogramming of data but to
a specific limit. In this paper we illustrated how the various types of ROM differ and the main
implementation methods to design the Read only memory using the MOS technology.
REFERENCES
[1] Kim, Y. E., Jung, K. S., Hong, S. A., Cho, S. I., & Chung, J. G. (2007). Efficient Design
Method of ROM.  ISOCC, 564-565.

[2] Nowrin, S., Nazneen, P., & Jamal, L. (2015). Design of a Compact Reversible Read-Only-
Memory with MOS Transistors. arXiv preprint arXiv:1610.06088.

[3] A 9GHz 320×80bit Low Leakage Microcode Read Only Memory in 65nm CMOS," 2006
Proceedings of the 32nd European Solid-State Circuits Conference

[4] Semiconductor Memories, [Online] available at

https://nptel.ac.in/content/storage2/courses/117101058/downloads/Lec-31.pdf, accessed on
07.12.2020

[5]Etinne Sicard, Sonia Delemas Bendhia(2003).Deep submicron CMOS Design. Tata McGraw-
Hill Education.

[6] Memory Design III: ROMs and Non Volatile memories, [Online] available at
http://aboutme.samexent.com/classes/spring09/ee5324/lecture/Lect_05_Memory_2up.pdf,
accessed on 07.12.2020

[7] Cho, Y. H., & Mangione-Smith, W. H. (2004, April). Deep packet filter with dedicated logic
and read only memories. In 12th Annual IEEE Symposium on Field-Programmable Custom
Computing Machines (pp. 125-134). IEEE.

[8] Maxfield, C. (2008). Bebop to the Boolean boogie: An unconventional guide to electronics.

Newnes.

[9] Yang, B. D., & Kim, L. S. (2003). A low-power charge-recycling ROM architecture. IEEE
transactions on very large scale integration (VLSI) systems, 11(4), 590-600.

[10] Bertagnolli, E., Hofmann, F., Willer, J., Mary, R., Lau, F., von Basse, P. W., ... & Hain, M.
(1996, June). ROS: An extremely high density mask ROM technology based on vertical
transistor cells. In 1996 Symposium on VLSI Technology. Digest of Technical Papers (pp. 58-
59). IEEE.