LCL Filter Design
LCL Filter Design
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1226 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 50, NO. 2, MARCH/APRIL 2014
C. Delta-Connected Capacitors ⎡ ⎤ ⎡ ⎤
O3×3
Vc
Vi
An LCL filter with delta-connected capacitors can be ana- B = ⎣ L11 I3×3 ⎦ u= X = ⎣ Ii ⎦ .
lyzed in the abc stationary frame with the circuit in Fig. 3. The Vg 9×1,
− L1 I3×3 9×3,
2
Ig 9×1
voltages and currents can be formulated as given by equations
1
HLCL (s) = (9)
L1 C f L2 s3 + (L1 + L2 )s
Cf R f s + 1
HdLCL (s) = .
L1 Cf L2 s3 + Cf (L1 + L2 )Rf s2 +(L1 + L2 )s
(10)
The Bode plots of the LCL filter without and with damping Fig. 5. LCL filter design algorithm.
are shown in Fig. 4. The insertion of a series resistance with
the capacitor eliminates the gain spike, smoothing the overall The base impedance and the base capacitance are defined by
response and rolling-off to −180◦ for high frequency, instead (11) and (12). Thus, the filter values will be referred to in a
of −270◦ . It is possible to observe in this Bode diagram that the percentage of the base values, i.e.,
closed loop bandwidth must be within 1000 Hz when the phase
shift is around −90◦ . En2
Zb = (11)
Pn
1
III. F ILTER D ESIGN P ROCEDURE Cb = . (12)
ωg Z b
A. Systematic Filter Design
For the design of the filter capacitance, it is considered that
Several characteristics must be considered in designing an the maximum power factor variation seen by the grid is 5%,
LCL filter, such as current ripple, filter size, and switching indicating that the base impedance of the system is adjusted
ripple attenuation. The reactive power requirements may cause as follows: Cf = 0.05Cb . A design factor higher than 5% can
a resonance of the capacitor interacting with the grid. There- be used, when it is necessary to compensate the inductive
fore, passive or active damping must be added by including a reactance of the filter. The maximum current ripple at the output
resistor in series with the capacitor. In this paper, the passive of dc/ac inverter is given by [8]
damping solution has been adopted, but active solutions can be
2VDC
also applied [1]. ΔILmax = (1 − m)mTsw (13)
The algorithm for designing the LCL filter is indicated 3L1
in Fig. 5. In the example below, the filter design steps are where m is the inverter modulation factor (for a typical SPWM
described in detail. inverter).
The following parameters are needed for the filter design: It can be observed that the maximum peak-to-peak current
VLL , line-to-line RMS voltage (inverter output); Vph , phase ripple happens at m = 0.5, then
voltage (inverter output); Pn , rated active power; VDC , dc-link
voltage; fg , grid frequency; fsw , switching frequency; and fres , VDC
ΔILmax = (14)
resonance frequency. 6fsw L1
1228 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 50, NO. 2, MARCH/APRIL 2014
where
√
Pn 2
Imax = (16)
3Vph
VDC
L1 = . (17)
6fsw ΔILmax
TABLE II
The LCL filter should reduce the expected current ripple to I NDUCTORS PARAMETERS
20%, resulting in a ripple value of 2% of the output current [2],
[5]. In order to calculate the ripple reduction, the LCL filter
equivalent circuit is initially analyzed considering the inverter
as a current source for each harmonic frequency in accordance
with Fig. 1.
Equations (18) and (19) relate the harmonic current gener-
ated by the inverter with the one injected in the grid, i.e.,
rated active power; VDC = 400 V, dc-link voltage; ωg = 2π60,
ig (h) 1 grid angular frequency; ωsw = 15 kHz, switching frequency;
= = ka (18)
ii (h) |1 + r [1 − L1 Cb ωsw
2 x] |
x = 0.05, maximum power factor variation seen by the grid;
or and ka = 0.2 (20%), attenuation factor. Therefore, the base
impedance and the base capacitance are Zs = 8.64Ω and Cs =
1
ka2 +1 307 μF, respectively (parameters are shown in Table I).
L2 = 2
(19) 1) Using 10% allowed ripple, (15) gives an inductance L1 =
Cf wsw
2.23 mH.
where ka is the desired attenuation. Cf = 0.01 ÷ 0.05 Cb . 2) The maximum capacitor value is 16.63 μF in order to be
The constant r is the ratio between the inductance at the within the limit of 5% of the base value of CB . After
inverter side and the one at the grid side. Thus, rounding to the closest commercial value, Cf = 15 μF
for the wye configuration or 5 μF for the delta connection.
L2 = rL1 . (20)
3) One can set the desired attenuation ka = 20%, and then,
Plotting the results for several values of r helps in evaluat- using (19), L2 is found to be 0.045 mH.
ing the transfer function of the filter at a particular resonant 4) Putting all calculated parameters of L1 , Cf , and L2
frequency, depending on the nominal grid impedance [4]. A into (21) gives fres = 6450 kHz, which meets condition
resistor in series (Rf ) with the capacitor attenuates part of from (22).
the ripple on the switching frequency in order to avoid the 5) Equation (23) gives the damping resistance Rf = 0.55Ω
resonance. The value of this resistor should be one third of the for wye configuration or 1.65 Ω for delta connection.
impedance of the filter capacitor at the resonant frequency [9], 6) The construction of the inductors was defined using the
and the resistor in series with the filter capacitance is given by software available on the website of Magnetics [10] and
(23). Thus, presented in Table II
7) The inductor parameters were validated during the ex-
L1 + L2 perimental setup by taking note of the inductors values
ωres = (21)
L1 L2 C f when measuring voltage and current with an oscilloscope
and multipled in a spreadsheet in order to compute L =
10fg < fres < 0.5fsw . (22) (Δt/Δi)/V .
The resonant frequency range must be considered to satisfy
(22), i.e., V. S IMULATION R ESULTS AND A NALYSIS
1 A. System Modeling
Rf = . (23)
3ωres Cf
Two models for LCL filter evaluation have been analyzed
using MATLAB and Simulink Power System ToolBox sim-
ulation environment, as shown in Figs. 6 and 7; the same
IV. LCL F ILTER D ESIGN E XAMPLE
simulation structure has been implemented in the hardware.
This section shows a step-by-step procedure used to de- The sampling time and simulation step size is 0.5 μs, whereas
sign a wye√ capacitor configuration. The specifications are the sampling time for the control system is 100 μs. Such a
En = 120 3V , line-to-line RMS voltage; Ps = Pn = 5 kW, choice of multisampling is done in order to allow the hardware
REZNIK et al.: LCL FILTER DESIGN AND PERFORMANCE ANALYSIS FOR GRID-INTERCONNECTED SYSTEMS 1229
implementation using a hardware-in-the-loop dSPACE 1104 of magnetic cores from Magnetics (www.mag-inc.com) and
system [11]. Both voltage and current control systems for stand- software [12] were used in the assembly of the inductors.
alone and grid-connected modes are developed using Park and The Inductor Design software assisted in selecting the op-
Clarke transformations with proportional–integral control in the timum core for inductor applications. This software uses an
dq frame. algorithm intended to specify the smallest design package
size for the given input parameters (current, inductance value,
frequency).
VI. E XPERIMENTAL DATA AND P ERFORMANCE A NALYSIS
The LCL filter was then verified by experimental results.
The proposed LCL filter has been validated using a grid- Figs. 10–12 show important system variables, which were
connected three-phase 5-kW inverter prototype with the ability captured with an Agilent MSO-X 3104A oscilloscope. The
to operate in a stand-alone mode. The LCL filter shown in first set of experimental results obtained is shown in Figs. 10
Figs. 8 and 9, which is based on parameter values listed in and 11, during which the proposed installation is supplying
Tables I–III, has been designed and built. The control algorithm 100% nominal load power in open-loop voltage control mode.
was executed in a dSPACE 1104 real-time platform. Two types A sinusoidal PWM (SPWM) strategy is used in the inverter,
1230 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 50, NO. 2, MARCH/APRIL 2014
TABLE III
ACTUAL F ILTER PARAMETERS
ACKNOWLEDGMENT
The authors would like to thank Dr. R. Ammerman of the
Colorado School of Mines for his comments and review.
Fig. 13. THD analysis and experimental data for stand-alone mode. R EFERENCES
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Fig. 15. THD analysis and experimental data for grid-connected mode
(PF = 0.94 lag).