B.

TECH,ECE
VLSI Design LAB: PART-A
LIST OF EXPERIMENTS

S.No. Name of the experiment

1. CMOS Inverter
2. CMOS - NAND and NOR Gates
3. CMOS – AND and OR Gates
4. CMOS - Ex-OR Gate and Ex-NOR Gate
5. CMOS AOI Gate

OBJECTIVE:
Objective of this lab is to learn the Virtuoso tool as well learn the first step in flow of
the Full Custom IC design cycle. In this process you will design the circuit and verify its
functionality using simulation. You will create a new cell with schematic view and hence
build the schematic by instantiating various components. Once schematic is done, this circuit
is verified by doing various simulations using spectre. In the process, you will learn to use
spectre,waveformwindowoptions,waveformcalculator

1
 PROCEDURE

Procedure to enter in to the virtuoso Environment

 Right click on the desktop and click on the open terminal.
 A new window opens. Give the commands:
mount –t nfs cadence: /root/cadenceDB/ /root/cadenceDB/
cd database

csh

source cshrc1
cd cadence_ms_labs_613
virtuoso
 A command interpreter window will open.
Procedure to create Schematic
 Go to file -> library -> Create Library and cell view.
 A virtuoso schematic window opens, then create your own schematic.
 To create schematic, go to create -> instance (I). Add instance window opens, then
browse Library -> gpdk180/analog lib ->pmos /nmos/Vdd/Vdc/gnd -> symbol and then
close.
 To connect the terminals, go to create -> wire narrow (W).
 For input, output or input-output pins, go to create -> pin (P).
 To change the properties of any component, select the component and press „Q‟.
 Using the above steps required schematic can be created.
 Go to file -> check & save.
Procedure for the Transient Analysis:
 Go to launch -> ADEL. Virtuoso Analog Design Environment window will open.
 Click on setup->select stimuli to apply inputs.
 Click on analyses -> choose. For transient response, enable „trans‟ and enter some value
for stop time. Enable „moderate‟ and then click apply & OK.
 Go to outputs -> to be plotted -> select on schematic. Select the input and output wires in
the schematic and return to ADE window. Go to simulation ->netlist& run.
 After few seconds, the transient response will be displayed. In that, click on „strip chart
mode‟, to split the plotted waveforms

2
 B.TECH,ECE
VLSI Design LAB: PART-B
LIST OF EXPERIMENTS

S.No. Name of the experiment

6. Logic Gates
7. Full Adder
8. Full Subtractor
9. 2to 8 DECODER
10. 8X1 MULTIPLEXER
11. Flip Flop’s
12. Binary counter

3
PROCEDURE TO WORK WITH XILINX TOOL
After installing Xilinx software go to start menu, Programs →Xilinx→ Project
navigator

1. Select file →New project

2. A window given below will be appearing. Write the project name like “and
gate” then click next.

3. The below window will be displayed. In the project device options select the
following options shown in the fig. and then click on Next.

4
4. The following window will be displayed. Click on new source.

5. Then the following window will be displayed. Select VHDL Module and
write the file name as same as project name. And click Next button.

5
6. Then the following window will be displayed. Provide inputs and outputs.
And click next

7. Click finish button. Then the following window will be displayed.

6
8. Click Next two times and Finish once for upcoming windows. A dummy
program will be created as shown in the following window.

9. Make the changes in the program according to your requirements and save
the program.

7
10.Perform check syntax if the check syntax is completed successfully.
Synthesize the program. You will get the synthesis report, schematic and
Technology Schematic.

CREATING TEST BENCH FOR THE VHDL MODEL

1. Create a test bench by Right clicking on the project name and Select new
source. As shown in the fig.
2.

2. Select VHDL Test bench and give the file name as “tb_Program name” and
click next. A dummy test bench will be created. Provide the test bench and save
the test bench.

3. Perform Check syntax and simulate test bench. SIMULATION RESULTS

will be displayed

8
SCHEMATIC DIAGRAM:

9
EXP.NO:01 CMOS INVERTER

AIM:-
To design a CMOS Inverter and verify its functionality using transient response.

TOOLS USED:

 Cadence Virtuoso
 Gpdk 180nm Technology

THEORY:
The inverter is universally accepted as the most basic logic gate doing a Boolean operation on
a single input variable and CMOS is sometimes referred to as complementary-symmetry metal–
oxide–semiconductor. The words "complementary-symmetry" refer to the fact that the typical digital
design style with CMOS uses complementary and symmetrical pairs of p-type and n-type metal oxide
semiconductor field effect transistors (MOSFETs) for logic functions. Two important characteristics
of CMOS devices are high noise immunity and low static power consumption. Significant power is
only drawn while the transistors in the CMOS device are switching between on and off states.
Consequently, CMOS devices do not produce as much waste heat as other forms of logic, for
example transistor-transistor logic (TTL) or NMOS logic, which uses all n-channel devices without p-
channel devices.
The CMOS inverter, a logic gate which converts high input to low and low to high. When the input is
high, the n-MOSFET on the bottom switches on, pulling the output to ground. The p-MOSFET on top
switches OFF. When the input is low, the gate-source voltage on the n-MOSFET is below its
threshold, so it switches off, the p-MOSFET switches on to pull the output high. It consists of only
two transistors, a pair of one N-type and one P-type transistor. If the input voltage is „1‟ (VCC) the P-
type transistor on top is non-conducting and provides a path from GND to the output Y. The output
level therefore is „0‟. On the other hand, if the I/P level is „0‟, the P-transistor is conducting and
provides a path from VCC to the output Y, so that the output level is „1‟ while N-type transistor is
blocked.

10
SYMBOL:

Vdd Vout=(Vin)‟
Vi Vout

gnd

TRUTH TABLE:

Vin Vout (Theoritical) Vout ( Practical)

0(0v) 1(1.8v) 1(1.8v)

1(1.8v) 0(0v) 857.95pv

TRANSIENT ANALYSIS:

11
THE SWITCHING LEVEL OPERATION (ON/OFF) OF THE CMOS INVERTER :
Vin PMOS NMOS Conduction Path of Y
T1 T2 Transistors
0(0v) ON OFF T1 1(1.8v)
1(1.8v) OFF ON T2 0(0V)

RESULT: CMOS Inverter is designed and verified its functionality using transient response.

12
 MODEL VIVA QUESTIONS

1) What is the latch up problem that arises in bulk CMOS technology? How is it overcome?
2) Explain the operation of CMOS Inverter using transfer characteristic curves.
3) Distinguish between the bulk CMOS technology with the SoI technology fabrications?
4) In CMOS inverter, PMOS is preferably in pull up stage and NMOS in pull down stage. Why?
5) How CMOS inverter will acts if we interchange NMOS and PMOS positions?
6) Draw the ideal characteristics of a CMOS inverter and compare it with the actual
characteristics?
7) What is noise margin? Find out the noise margin from the actual characteristics the inverter.
8) What is the lower limit of supply voltage of a CMOS inverter? What happens if the supply
voltage is further reduced?
9) What are the various ways to reduce the delay time of a CMOS inverter?
10) Explain the commonly used technique to estimate the delay time of a CMOS inverter?
11) Define nMOS and pMOS transistors.
12) Differentiate enhancement and depletion mode transistors.
13) Compare nMOS and CMOS.
14) What is the abbreviation of ECAD.
15) What is meant by Gpdk 180nm Technology.

13
NAND GATE:
BLOCK DIAGRAM WITH ITS BEHAVIOUR:

SCHEMATIC DIAGRAM:

14
EXP.NO:02 NAND and NOR GATES

AIM:-
To design a two-input CMOS NAND and NOR gates and verify their functionalities using
transient response.

TOOLS USED:

 Cadence Virtuoso
 Gpdk 180nm Technology

THEORY:
NAND GATE:
NAND gate is actually a combination of two logic gates: AND gate followed by NOT gate.
The first part is an AND gate and second part is a dot after it represents a NOT gate. So it is clear
that during the operation of NAND gate, the inputs are first going through AND gate and after that
the output is reversed and we get the final output.So its output is complement of the output of an
AND gate.
The NAND gate and the NOR gate can be said to be universal gates since combinations of
them can be used to accomplish any of the basic operations and can thus produce an Inverter, an OR
gate or an AND gate. The non-inverting gates do not have this versatility since they can‟t produce an
invert.
The output of NAND gate is high if any of the inputs are low. In the NAND gate the P-type
transistors are connected in parallel between VCC and the output Y, while the N-type transistors are
connected in series from GND to the output Y. If any of the input is LOW, one of two PMOS
transistor will ON and path is established between Output and VDD, hence Output is HIGH. If both
the two inputs are LOW, then both the PMOS transistors are ON and both the NMOS transistors are
OFF. Therefore, path is established between output and VDD and no path is existed between GND
and Output. Hence, Output is HIGH. If the both inputs are HIGH, then both the NMOS transistors
are ON and both the PMOS transistors are OFF. Therefore, path is established between output and
GND and no path is existed between VDD and Output. Hence, the Output is LOW.

15
NOR GATE:
BLOCK DIAGRAM WITH ITS BEHAVIOUR:

SCHEMATIC DIAGRAM:

16
NOR GATE:
THEORY:
NOR gate is actually a combination of two logic gates: OR gate followed by NOT gate. The
first part is an OR gate and second part is a dot after it represents a NOT gate. So it is clear that
during the operation of NOR gate, the inputs are first going through OR gate and after that the output
is reversed and we get the final output.So its output is complement of the output of an OR gate.
The NAND gate and the NOR gate can be said to be universal gates since combinations of
them can be used to accomplish any of the basic operations and can thus produce an Inverter, an OR
gate or an AND gate. The non-inverting gates do not have this versatility since they can‟t produce an
invert.
.The output of NOR gate isLOW if any of the inputs are HIGH. In the NOR gate the N-type
transistors are connected in parallel between GND and the output Y, while the P-type transistors are
connected in series fromVDD to the output Y. If any of the input is HIGH, one of two NMOS
transistor will ON and path is established between Output and GND, hence Output is LOW. If both
the two inputs are HIGH, then both the PMOS transistors are OFF and both the NMOS transistors
are ON. Therefore, path is established between output and GND and no path is existed between
VDD and Output. Hence, Output is LOW. If the both inputs are LOW, then both the PMOS
transistors are ON and both the NMOS transistors are OFF. Therefore, path is established between
output and VDD and no path is existed between GND and Output. Hence, the Output is HIGH.

17
NAND GATE:

TRUTH TABLE:

a b Therical Y Practical Y
0(0v) 0(0v) 1(1.8v) 1.8v
0(0v) 1(1.8v) 1(1.8v) 1.8v
1(1.8v) 0(0v) 1(1.8v) 1.8v

1(1.8v) 1(1.8v) 0(0v) 9.0149nv

SYMBOL:

Y = (a.b)’

TRANSIENT ANALYSIS:

18
NOR GATE:
TRUTH TABLE:
Vin1 Vin2 Theoretical Practical
Vout Vout
0(0v) 0(0v) 1(1.8v) 1.8v
0(0v) 1(1.8v) 0(0v) 255.23nv
1(1.8v) 0(0v) 0(0v) 363.91uv
1(1.8v) 1(1.8v) 0(0v) 2.3665uv

SYMBOL:

Vout = ( a+b)’

TRANSIENT ANALYSIS:

19
THE SWITCHING LEVEL OPRERATION (ON/OFF) OF THE CMOS NAND GATE:
A B PMOS PMOS NMOS NMOS Conduction Path of Y
T1 T2 T3 T4 Transistors
0(0v) 0(0v) ON ON OFF OFF T1/T2 1(1.8v)
0(0v) 1(1.8v) ON OFF OFF ON T1 1(1.8v)
1(1.8v) 0(0v) OFF ON ON OFF T2 1(1.8v)
1(1.8v) 1(1.8v) OFF OFF ON ON T3&T4 0(0v)

THE SWITCHING LEVEL OPERATION (ON/OFF) OF THE CMOS NOR GATE:

Vin1 Vin2 PMOS PMOS NMOS NMOS Conduction Path of Y
T1 T2 T3 T4 Transistors
0(0v) 0(0v) ON ON OFF OFF T1&T2 1(1.8v)
0(0v) 1(1.8v) ON OFF ON OFF T3 0(0v)
1(1.8v) 0(0v) OFF ON OFF ON T4 0(0v)
1(1.8v) 1(1.8v) OFF OFF ON ON T3/T4 0(0v)

RESULT:

Two-input NAND & NOR gates are designed and its functionality is verified using transient response.

20
 MODEL VIVA QUESTIONS

1. How the transfer characteristic of a CMOS NAND gate is affected with increase in fan-in?
2. How the transfer characteristic of a CMOS NOR gate is affectedwith increase in fan-in?
3. How switching characteristic of a CMOS NAND gate is affectedwith increase in fan-in?
4. How switching characteristic of a CMOS NOR gate is affectedwith increase in fan-in?
5. How noise margin of a CMOS NAND/NOR gate is affected withincrease in fan-in?
6. What are universal gates? Why called so.
7. Draw the pull up section of NAND gate and NOR gates?
8. Draw the pull down section of NAND gate and NOR gates?
9. Explain the logical operation of NAND gate with the help of a truth table?
10. Explain the logical operation of NOR gate with the help of truth table.
11.Draw the 3 input CMOS NAND gate.
12. Draw the 3 input CMOS NOR gate.

21
AND GATE:
BLOCK DIAGRAM WITH ITS BEHAVIOUR:

SCHEMATIC DIAGRAM:

22
 EXP.NO: 03 AND and OR GATES

AIM:-To design a two-input CMOS AND and OR gates and verify their functionalities using transient
response.
TOOLS USED:
 Cadence Virtuoso
 Gpdk 180nm Technology

AND GATE:
THEORY:
The AND gate is a basic digital logic gate that implements logical conjunction. A HIGH
output (1) results only if both the inputs to the AND gate are HIGH (1). If neither or only one input to
the AND gate is HIGH, a LOW output results. In another sense, the function of AND effectively finds
the minimum between two binary digits. Therefore, the output is always 0 except when all the inputs
are 1s.Commonly available Digital Logic AND Gate IC‟s include:
TTL Logic AND GatesCMOS Logic AND Gates

 CD4081 Quad 2-inpu 74LS08 Quad 2-input

 74LS11 Triple 3-input CD4073 Triple 3-input
 74LS21 Dual 4-input CD4082 Dual 4-input

If no specific AND gates are available, one can be made from NAND or NOR gates, because NAND
and NOR gates are considered the "universal gates," meaning that they can be used to make all the
others. XOR Gates can also be used to simulate AND functions, but are rarely used to do so.

Desired gate
NAND construction for
AND NOR construction for AND

23
OR GATE:
BLOCK DIAGRAM WITH ITS BEHAVIOUR:

SCHEMATIC DIAGRAM:

24
 OR GATE:
THEORY:

The OR gate is a digital logic gate that implements logical disjunction. A HIGH output (1)
results if one or both the inputs to the gate are HIGH (1). If neither input is high, a LOW output (0)
results. In other sense, the function of OR effectively finds the maximum between two library digits.
Commonly available Digital Logic OR Gate IC‟s include:
TTL Logic OR GatesCMOS Logic OR Gates

 74LS32 Quad 2-input CD4071 Quad 2-input

CD4075 Triple 3-input CD4072 Dual 4-input

If no specific OR gates are available, one can be made from NAND or NOR gates in the configuration
shown in the image below. Any logic gate can be made from a combination ofNAND or NOR gates.

NAND Construction for OR

NOR construction for OR

25
AND GATE:
TRUTH TABLE:
X Y Z Z
Theoretical Practical
0(0v) 0(0v) 0(0v) -56.291nv
0(0v) 1(1.8v) 0(0v) 1.2298nv
1(1.8v) 0(0v) 0(0v) 5.8028uv
1(1.8v) 1(1.8v) 1(1.8v) 1.8v

SYMBOL:

Z = ( X.Y)

TRANSIENT ANALYSIS:

26
THE SWITCHING LEVEL OPERATION (ON/OFF) OF THE CMOS AND GATE:

A B PMOS PMOS NMOS NMOS PMOS NMOS Conduction Y

T1 T2 T3 T4 T5 T6 Path of
Transistors
0(0v) 0(0v) ON ON OFF OFF OFF ON T1/T2&T6 0(0v)
0(0v) 1(1.8v) ON OFF OFF ON OFF ON T1&T6 0(0v)
1(1.8v) 0(0v) OFF ON ON OFF OFF ON T2&T6 0(0v)
1(1.8v) 1(1.8v) OFF OFF ON ON ON OFF T3&T4&T5 1(1.8v)

THE SWITCHING LEVEL OPRERATION (ON/OFF) OF THE CMOS OR GATE:

A B PMOS PMOS NMOS NMOS PMOS NMOS Conduction Y

T1 T2 T3 T4 T5 T6 Path of
Transistors
0(0v) 0(0v) ON ON OFF OFF OFF ON T1&T2&T6 0(0v)
0(0v) 1(1.8v) ON OFF OFF ON ON OFF T4&T5 1(1.8v)
1(1.8v) 0(0v) OFF ON ON OFF ON OFF T3&T5 1(1.8v)
1(1.8v) 1(1.8v) OFF OFF ON ON ON OFF T3/T4&T5 1(1.8v)

RESULT: Two-input AND & OR gates are designed and its functionality using transient response is
verified practically.

27
OR GATE:
SYMBOL:

Vout = (Vin1 +Vin2)

TRUTH TABLE:
Vin1 Vin2 Theoretical Practical
Vout Vout
0(0v) 0(0v) 0(0v) 2.583nv
0(0v) 1(1.8v) 1(1.8v) 1.8v
1(1.8v) 0(0v) 1(1.8v) 1.8v
1(1.8v) 1(1.8v) 1(1.8v) 1.8v

TRANSIENT ANALYSIS:

28
 MODEL VIVA QUESTIONS
1. How the transfer characteristic of a CMOS AND gate is affected with increase in fan-in?
2. How the transfer characteristic of a CMOS OR gate is affected with increase in fan-in?
3. How switching characteristic of a CMOS AND gate is affected with increase in fan-in?
4. How switching characteristic of a CMOS OR gate is affected with increase in fan-in?
5. How noise margin of a CMOS AND/OR gate is affected with increase in fan-in?
6. What are basic gates? Why called so.
7. Draw the pull up section of AND gate and OR gates?
8. Draw the pull down section of AND gate and OR gates?
9. Explain the logical operation of AND gate with the help of a truth table?
10. Explain the logical operation of OR gate with the help of a truth table?
11.Draw the 3 input CMOS NAND gate.
12. Draw the 3 input CMOS NOR gate.

29
Ex-OR GATE:
BLOCK DIAGRAM WITH ITS BEHAVIOUR:

SCHEMATIC DIAGRAM:

30
 EXP.NO:04 EX-OR and EX-NOR GATES

AIM :-To design a two-input CMOS EX-OR and EX-NOR gates verify their functionalities using
transient response.
TOOLS USED:
 Cadence Virtuoso
 Gpdk 180nm Technology

EX-OR GATE:
THEORY:
The X in the EXOR gate stands for “exclusive.” This means that the output from this gate will
be a 1 only when one or the other of the inputs is a 1. If an XOR gate has more than two inputs, then
its behaviour depends on implementation. In the vast majority of cases, an XOR gate will output true
if and odd number of its inputs is true. However, it‟s important to note that this behaviour differs from
the strict definition or exclusive OR, which insists that exactly one input must be true for the output to
be true.
Exclusive-OR Gates are used mainly to build circuits that perform arithmetic operations and
calculations especially Adders and Half-Adders as they can provide a “carry-bit” function or as a
controlled inverter, where one input passes the binary data and the other input is supplied with a
control signal.
Commonly available Digital Logic Exclusive-OR Gate IC‟s include:

TTL Logic Ex-OR GatesCMOS Logic Ex-OR Gates

 74LS86 Quad 2-input CD4030 Quad 2-input

31
Ex-NOR GATE:
BLOCK DIAGRAM WITH ITS BEHAVIOUR:

SCHEMATIC DIAGRAM:

32
EX-NOR GATE:
THEORY:

An XNOR gate is a digital logic gate with two or more inputs and one output that performs
logical equality. The output of an XNOR gate is true when all of its inputs are true or when all of its
inputs are false. If some of its inputs are true and others are false, then the output of XNOR gate is
false. XNOR gates are represented in most TTL and CMOS IC families. The standard 4000 series
CMOS IC is the 4077 and the TTL IC is the 74266. Both include four independent, two-input, XNOR
gates. OUTPUT is high only if all its inputs are the same.
Ex-NOR gates are used mainly in electronic circuits that perform arithmetic operations and
data checking such as Adders, Subtractors or Parity Checkers, etc. As the Ex-NOR gate gives an
output of logic level “1” whenever its two inputs are equal it can be used to compare the magnitude of
two binary digits or numbers and so Ex-NOR gates are used in Digital Comparator circuits.
Commonly available Digital Logic Exclusive-NOR Gate IC‟s include:
TTL Logic Ex-NOR Gates CMOS Logic Ex-NOR Gates

74LS266 Quad 2-input CD4077 Quad 2-input

33
Ex-OR GATE:
TRUTH TABLE:

A B Y (Theoretical) Y( Practical)
0(0v) 0(0v) 0(0v) 9.039nv
0(0v) 1(1.8v) 1(1.8v) 1.8
1(1.8v) 0(0v) 1(1.8v) 1.8
1(1.8v) 1(1.8v) 0(0v) 8.815nv

SYMBOL:

Y = a‟ b + a b‟

TRANSIENT ANALYSIS:

34
THE SWITCHING LEVEL OPRERATION (ON/OFF) OF THE Ex-OR GATE:

A B PM0 PM1 PM2 PM3 NM0 NM1 NM2 NM3 Conduction Path of Y
T1 T2 T3 T4 T5 T6 T7 T8 Transistors
0v 0v ON ON OFF OFF OFF OFF ON ON T2&T8 0v

0v 1.8v ON OFF OFF ON OFF ON ON OFF T1&T4 1.8v

1.8v 0v OFF ON ON OFF ON OFF OFF ON T2&T3 1.8v

1.8v 1v OFF OFF ON ON ON ON OFF OFF T5&T6 0v

THE SWITCHING LEVEL OPRERATION (ON/OFF) OF THE Ex-NOR GATE:

A B PM0 PM1 PM2 PM3 NM0 NM1 NM2 NM3 Conduction Path of Y
T1 T2 T3 T4 T5 T6 T7 T8 Transistors
0v 0v OFF OFF ON ON ON OFF OFF ON T2&T3 1.8v

0v 1.8v OFF ON ON OFF ON ON OFF OFF T5&T6 0v

1.8v 0v ON OFF OFF ON OFF OFF ON ON T7&T8 0v

1.8v 1v ON ON OFF OFF OFF ON ON OFF T1&T4 1.8v

RESULT: Two-input EX-OR & EX-NOR gates are designed and its functionality is verified using
transient response.

35
Ex-NOR GATE:
TRUTH TABLE:
A B Y Y
(Theoretical) (Practical)
0(0v) 0(0v) 1(1.8v) 1.8v

0(0v) 1(1.8v) 0(0v) 8.826nv

1(1.8v) 0(0v) 0(0v) 5.808nv

1(1.8v) 1(1.8v) 1(1.8v) 1.8v

SYMBOL:

Y = (a‟ b + a b‟)‟

TRANSIENT ANALYSIS:

RESULT: Two-input EX-OR & EX-NOR gates are designed and its functionality is verified using
transient response.

36
 MODEL VIVA QUESTIONS

1. How the transfer characteristic of a CMOS Ex-OR gate is affected with increase in fan-in?
2. How the transfer characteristic of a EX-NOR gate is affected with increase in fan-in?
3. How switching characteristic of a CMOS Ex-OR gate is affected with increase in fan-in?
4. How switching characteristic of a CMOS Ex-NOR gate is affected with increase in fan-in?
5. How noise margin of a CMOS Ex-OR/ Ex-NOR gate is affected with increase in fan-in?
6. What are arithmetic gates? Why called so.
7. Draw the pull up section of Ex-OR gate and Ex-NOR gates?
8. Draw the pull down section of Ex-OR gate and Ex-NOR gates?
9. Explain the logical operation of Ex-OR gate with the help of a truth table?
10. Explain the logical operation of Ex-NOR gate with the help of a truth table?
11. What is equivalence gate.

37
AOI GATE:
BLOCK DIAGRAM WITH ITS BEHAVIOUR:

SCHEMATIC DIAGRAM:

38
 5.AOI GATE
AIM:-To design an AOI gate and verify their functionalities using transient response.

TOOLS USED:

 Cadence Virtuoso
 Gpdk 180nm Technology

THEORY:

The AOI gate, as its name suggests, enables the sum-of-products realization of a
BooleanFunction in one logic stage. The pull-down net of the AOI gate consistsofparallel branches of
series-connected N-MOS driver transistors. The corresponding p-typepull-up network can simply be
found using the dual-graph concept.

A function is a good example of AND-OR-INVERT (AOI) because it

performs the NOR of apair of two input ANDs.
AOI gates are particularly advantaged in that the total number of transistors (or gates) is less
than if the AND, NOT, and OR functions were implemented separately. This results in increased
speed, reduced power, smaller area, and potentially lower fabrication cost.
The OAI gate, on the other hand, enables the product-of-sums realization of aBoolean function in one
logic stage. The pull-down net of the OAI gateconsists of series branches of parallel-connected nMOS
driver transistors, while thecorresponding p-type pull-up network can be found using the dual-graph
concept.

39
TRUTH TABLE:

A B C D Theoretical Practical
Y Y
0(0v) 0(0v) 0(0v) 0(0v) 1(1.8v) 1(1.8v)
0(0v) 0(0v) 0(0v) 1(1.8v) 1(1.8v) 1(1.8v)
0(0v) 0(0v) 1(1.8v) 0(0v) 1(1.8v) 1(1.8v)
0(0v) 0(0v) 1(1.8v) 1(1.8v) 0(0v) 0(0 v)
0(0v) 1(1.8v) 0(0v) 0(0v) 1(1.8v) 1(1.8v)
0(0v) 1(1.8v) 0(0v) 1(1.8v) 1(1.8v) (1.8v)
0(0v) 1(1.8v) 1(1.8v) 0(0v) 1(1.8v) (1.8v)
0(0v) 1(1.8v) 1(1.8v) 1(1.8v) 0(0v) 0(0 v)
1(1.8v) 0(0v) 0(0v) 0(0v) 1(1.8v) 1(1.8v)
1(1.8v) 0(0v) 0(0v) 1(1.8v) 1(1.8v) 1(1.8v)
1(1.8v) 0(0v) 1(1.8v) 0(0v) 1(1.8v) 1(1.8v)
1(1.8v) 0(0v) 1(1.8v) 1(1.8v) 0(0v) 0(0 v)
1(1.8v) 1(1.8v) 0(0v) 0(0v) 0(0v) 0(0 v)
1(1.8v) 1(1.8v) 0(0v) 1(1.8v) 0(0v) 0(0 v)
1(1.8v) 1(1.8v) 1(1.8v) 0(0v) 0(0v) 0(0 v)
1(1.8v) 1(1.8v) 1(1.8v) 1(1.8v) 0(0v) 0(0 v)

LOGIC DIAGRAM:

TRANSIENT ANALYSIS:

RESULT: AOI gate is designed and its functionality is verified using transient response.

40
 MODEL VIVA QUESTIONS

1)For a complex/compound CMOS logic gate, how do you realize the pull-up and the pull-
down networks?
2)Give the two possible topologies AND-OR-INVERT AND-ORINVERT (AOI) and OR-
AND-INVERT (OAI) to realize CMOS logic gate. Explain with an example.
3)Give the AOI and OAI realizations for the sum and carry functions of a full adder.
what are Compound Gate? Explain why.
4)Explain the operation of AOI gate with the help of truth table?
5)Draw all possible ways to implement AOI Gates?
6)Draw all possible ways to implement OAI Gates?
7)Draw the Digital implementation of AOI gates with help of universal gates?
8)Draw the Digital implementation of OAI gates with help of universal gates?
9)Compare the PULL DOWN sections of XOR GATES AND AOI gates?

41
 6. Logic Gates

Aim: Design of all Basic gates, Universal gates and simulates it on Xilinx Software.

Software Used: Xilinx ISE

Theory:

A logic gate is an elementary building block of a digital circuit. Most of the logic gates have two
inputs and one output. At any given moment, every terminal is in one of the two binary conditions low
(0) or high (1), represented by different voltage levels. The logic state of a terminal can, and generally
does, change often, as the circuit processes data. In most logic gates, the low state is approximately
zero volts (0 V), while the high state is approximately five volts positive (+5 V).There are seven basic
logic gates: AND, OR, XOR, NOT, NAND, NOR, and XNOR.

Algorithm:

 Make sure that Logic Diagram/Symbol and truth table should be known for all the logic gates.
 For all logic gates input have to instantiated in the entity declarations.i.e., A,B is declared as
inputs and Z is declared as output is of signal type std_logic
 Inside the Architecture body, all the logic gates inputs have to assigned to the output by using
signal assignment statement ( Z<=A and B).

42
Logic Symbol for AND Gate:

Truth Table for AND Gate

Model graph for AND Gate

Logic Symbol for OR Gate:

Truth Table for OR Gate

Model graph for OR Gate

43
VHDL Code for Logic Gates:(AND Gate)

Data flow:
library ieee;
use ieee.std_logic_1164.all;
entity and_gate is
Port ( x1,y1 : in STD_LOGIC;
z1 : out STD_LOGIC);
end and_gate;

architecture dataflow of and_gate is

begin
z1 <= x1 and y1;
end dataflow;

Behavioral:
library ieee;
use ieee.std_logic_1164.all;

entity and_gate is
Port ( x,y : in STD_LOGIC;
z : out STD_LOGIC);
end and_gate;
architecture Behavioral of and_gate is
begin
process(x,y)
begin
if(x='0' and y='0') then z<='0';
elsif(x='0' and y='1') then z<='0';
elsif(x='1' and y='0') then z<='0';
elsif(x='1' and y='1') then z<='1';
end if;
end process;
end Behavioral;
Structural:
library ieee;
use ieee.std_logic_1164.all;

entity andstr is
Port ( x,y : in STD_LOGIC;
c : out STD_LOGIC);
end andstr;
architecture structural of and_gate is
component and gate
port(x,y: in STD_LOGIC;
z:out STD_LOGIC);
end component;
begin
g1:andgate portmap(x,y,z=>c);
end structural;

44
 VHDL Code for Logic Gates:(OR GATE)

Data flow:
library ieee;
use ieee.std_logic_1164.all;

entity orgate is
Port ( x1,y1 : in STD_LOGIC;
z1 : out STD_LOGIC);
end orgate;

architecture dataflow of orgate is

begin
z1 <= x1 or y1;
end dataflow;

Behavioral:
library ieee;
use ieee.std_logic_1164.all;

entity or_gate is
Port ( x,y : in STD_LOGIC;
z : out STD_LOGIC);
end and_gate;
architecture Behavioral of orgate is
begin
process(x,y)
begin
if(x='0' or y='0') then z<='0';
elsif(x='0' or y='1') then z<='1';
elsif(x='1' or y='0') then z<='1';
elsif(x='1' or y='1') then z<='1';
end if;
end process;
end Behavioral;
Structural:
library ieee;
use ieee.std_logic_1164.all;
entity orstr is
Port ( x,y : in STD_LOGIC;
c : out STD_LOGIC);
end orstr;
architecture structural of and_gate is
component orgate
port(x,y: in STD_LOGIC;
z:out STD_LOGIC);
end component;
begin
g1:orgate portmap(x,y,z=>c);
end structural;
45
Logic Symbol for NOT Gate:

Truth Table for NOT Gate

Model graph for NOT Gate

Logic Symbol for NAND Gate:

Truth Table for NAND Gate

Model graph for NAND Gate

46
VHDL Code for Logic Gates:(NAND gate)
Data flow:
library ieee;
use ieee.std_logic_1164.all;

entity nandgate is
Port ( x1,y1 : in STD_LOGIC;
z1 : out STD_LOGIC);
end nandgate;
architecture dataflow of nandgate is
begin
z1<= x nand y;
end dataflow;
Behavioral:
library ieee;
use ieee.std_logic_1164.all;

entity nand_gate is
Port ( x,y : in STD_LOGIC;
z : out STD_LOGIC);
end nand_gate;
architecture Behavioral of nand_gate is
begin
process(x,y)
begin
if(x='0' and y='0') then z<='1';
elsif(x='0' and y='1') then z<='1';
elsif(x='1' and y='0') then z<='1';
elsif(x='1' and y='1') then z<='0';
end if;
end process;
end Behavioral;

Structural:
library ieee;
use ieee.std_logic_1164.all;

entity nandstr is
Port ( x,y : in STD_LOGIC;
c : out STD_LOGIC);
end nandstr;
architecture structural of nand_gate is
component nandgate
port(x,y: in STD_LOGIC;
z:out STD_LOGIC);
end component;
begin
g1:nandgate portmap(x,y,z=>c);
end structural;
47
Logic Symbol forNOR Gate:

Truth Table for NOR Gate

Model graph for NOR Gate

Logic Symbo l forEx-OR Gate:

Truth Table for Ex-OR Gate

Model Graph forEx-OR Gate

48
 VHDL Code for Logic gates:(NOR gate)

Data flow:
library ieee;
use ieee.std_logic_1164.all;
entity norgate is
Port ( x1,y1 : in STD_LOGIC;
z1 : out STD_LOGIC);
end norgate;
architecture dataflow of norgate is
begin
z1<= x nor y;
end dataflow;
Behavioral:
library ieee;
use ieee.std_logic_1164.all;

entity nor_gate is
Port ( x,y : in STD_LOGIC;
z : out STD_LOGIC);
end nor_gate;
architecture Behavioral of nor_gate is
begin
process(x,y)
begin
if(x='0' and y='0') then z<='1';
elsif(x='0' and y='1') then z<='0';
elsif(x='1' and y='0') then z<='0';
elsif(x='1' and y='1') then z<='0';
end if;
end process;
end Behavioral;

Structural:
library ieee;
use ieee.std_logic_1164.all;
entity norstr is
Port ( x,y : in STD_LOGIC;
c : out STD_LOGIC);
end norstr;
architecture structural of nor_gate is
component norgate
port(x,y: in STD_LOGIC;
z:out STD_LOGIC);
end component;
begin
g1:norgate portmap(x,y,z=>c);
end structural;

49
 VHDL Code for Logic gates:(EX-OR gate)

Data flow:
library ieee;
use ieee.std_logic_1164.all;

entity xorgate is
Port ( x1,y1 : in STD_LOGIC;
z1 : out STD_LOGIC);
end xorgate;
architecture dataflow of xorgate is
begin
z1<= x xor y;
end dataflow;
Behavioral:
library ieee;
use ieee.std_logic_1164.all;

entity xor_gate is
Port ( x,y : in STD_LOGIC;
z : out STD_LOGIC);
end xor_gate;
architecture Behavioral of xor_gate is
begin
process(x,y)
begin
if(x='0' and y='0') then z<='0';
elsif(x='1' and y='1') then z<='0';
else z<='1':
end if;
end process;
end Behavioral;

Structural:
library ieee;
use ieee.std_logic_1164.all;

entity xorstr is
Port ( x,y : in STD_LOGIC;
c : out STD_LOGIC);
end xorstr;
architecture structural of xor_gate is
component xorgate
port(x,y: in STD_LOGIC;
z:out STD_LOGIC);
end component;
begin

50
 g1:xorgate portmap(x,y,z=>c);
end structural;
VHDL Code for Logic gates:(EX-NOR gate)

Data flow:
library ieee;
use ieee.std_logic_1164.all;

entity xnorgate is
Port ( x1,y1 : in STD_LOGIC;
z1 : out STD_LOGIC);
end xnorgate;
architecture dataflow of xnorgate is
begin
z1<= x xnor y;
end dataflow;
Behavioral:
library ieee;
use ieee.std_logic_1164.all;
entity xnor_gate is
Port ( x,y : in STD_LOGIC;
z : out STD_LOGIC);
end xnor_gate;
architecture Behavioral of xnor_gate is
begin
process(x,y)
begin
if(x='0' and y='0') then z<='1';
elsif(x='1' and y='1') then z<='1';
else z<='0':
end if;
end process;
end Behavioral;
Structural:
library ieee;
use ieee.std_logic_1164.all;
entity xnorstr is
Port ( x,y : in STD_LOGIC;
c : out STD_LOGIC);
end xnorstr;
architecture structural of xnor_gate is
component xnorgate
port(x,y: in STD_LOGIC;
z:out STD_LOGIC);
end component;
begin
g1:xorgate portmap(x,y,z=>c);
end structural;
RESULT: Output response of each logic gate is observed.

51
Symbol forEx-NOR Gate

Truth Table for Ex-NOR Gate

Model graph for Ex-Nor Gate

52
Model Viva Questions:
1. Define logic gate?
2. Difference between universal gates and basic gates?
3. Implement inverter using nand gates?
4. Implement inverter using NOR gates?

5. Implement OR gate using multiplexer?

6. Implement the following function using VHDL coding. (Try to minimize if you can).
F(A,B,C,D)=(A′+B+C) . (A+B′+D′). (B+C′+D′) . (A+B+C+D)
7. What will be the no. of rows in the truth table of N variables?
8. What are the advantages of VHDL?
9. Design Ex-OR gate using behavioral model?
10. Implement the following function using VHDL codef=AB+CD.

53
 7. Full Adder
Aim: Design of a full adder using 3 modeling styles and simulate it on Xilinx Software.

Software Used:
Xilinx ISE

Theory:

Half Adder:

A combinational circuit that performs an addition of two bits is called half adder. For this the circuit
needs two binary inputs and two binary outputs. The input variables designate the augend and addend
bits; the output variable produces the sum and carry.

Algorithm 2:

1. Make sure that Logic Diagram and truth table should be known for the Full Adder .
2. For all Full Adder inputs have to instantiated in the entity declarations i.e., A,B,C in is declared
as inputs and sum,carry is declared as outputs and is of signal type std_logic
3. Full adder can be implemented either in dataflow,structural and behavioral style of modeling.

54
Logic Diagram for Full Adder:

Truth Table for the Full Adder:

Model graphs for the Full Adder:

55
VHDL Code for Full Adder

Data flow:(Half-Adder)
library ieee;
use ieee.std_logic_1164.all;

entity halfadder is
Port ( a,b: in STD_LOGIC;
sum,carry : out STD_LOGIC);
end halfadder;
architecture dataflow of halfadder is
begin
sum<= a xor b;
carry<=a and b;
end dataflow;
Data flow:(Full-Adder)
library ieee;
use ieee.std_logic_1164.all;

entity fulladder is
Port ( a,b,c : in STD_LOGIC;
sum,carry : out STD_LOGIC);
end fulladder;
architecture dataflow of fulladder is
begin
sum<= a xor b xor c;
carry<=( (a xor b)and c)or (a and b);
end dataflow;
Behavioral:
library ieee;
use ieee.std_logic_1164.all;

entity fulladder beh is

Port ( a,b,c: in STD_LOGIC;
x,y: out STD_LOGIC);
end fulladder _gate;
architecture Behavioral of fulladder beh is
begin
process(a,b,c)
begin
if a='0' and b='0' and c='0' then x<='0';y<='0';
elsif a='1' and b='1' and c='1' then x<='1';y<='1';
elsif a='0' and b='0' and c='1' then x<='1';y<='0';
elsif a='0' and b='1' and c='0' then x<='1';y<='0';
elsif a='1' and b='0' and c='0' then x<='1';y<='0';
else x<='0';
y<='1';
56
 end if;
end process;
end Behavioral;

Structural:
library ieee;
use ieee.std_logic_1164.all;

entity fulladderstr is
Port ( a,b,c : in STD_LOGIC;
sum,carry : out STD_LOGIC);
end fulladder str;
architecture structural of fulladderstr is
signal s1,c1,c2: in STD_LOGIC;
component halfadder
port(a,b,c: in STD_LOGIC;
sum,carry:out STD_LOGIC);
end component;
begin
g1:halfadder portmap(a,b,sum=>s1,carry<=c1);
g2:halfadder portmap(a=>s1,b=>c,sum,carry=>c2);
carry1<=c1 or c2;
endstructural;

RESULT: Full adder is designed using 3modelling styles and simulation is done.

57
Model Viva Questions:
1. What are the differences between half adder and full adder?
2. What are the advantages of minimizing the logical expressions?
3. What does a combinational circuit mean?
4. Implement the half adder using VHDL code?
5. Implement the full adder using two half adders and write VHDL program in structural model?
6.Give expression for difference and borrow in Half adder.
7.Give expression for difference and borrow in Full adder.
8.Implement Full adder using Half adders.
9.How many NAND are needed to implement Half adder?
10.How many NAND are needed to implement Full adder?
11.How many NOR are needed to implement Half adder?
12.How many NOR are needed to implement Full adder?

58
 8. Full Subtractor
Aim: Design of full subtractor using 3 modeling styles and simulate it on Xilinx Software.

Software Used:Xilinx ISE

Theory:

Full Subtractor:

A full subtractor is a combinational circuit that performs a difference of three input bits. For this the
circuit needs three binary inputs and two binary outputs. Two of the input variables represent two
significant bits to be subtracted. The third input represents a borrow from the previous lower
significant position. A two-output variable represents the difference and borrow.

Algorithm 1:

1. Make sure that Logic Diagram and truth table should be known for the Full Subtarctor .
2. For all Full Subtractor inputs have to instantiated in the entity declarations i.e., A,B,Bin is
declared as inputs and Difference, Borrow is declared as outputs and are of signal type
std_logic
3. Full Subtractor can be implemented in dataflow, structural and behavioral style of modeling.

59
Logic Diagram for Full Subtractor:

Truth Table for the Full Subtractor:

Model graphs for the Full Subractor:

60
VHDL Code for VHDL Code for Full Subtractor

Data flow:(Half-Subtractor)

library ieee;
use ieee.std_logic_1164.all;
entity halfsub is
Port ( a,b: in STD_LOGIC;
diff,borrow: out STD_LOGIC);
end halfsub;
architecture dataflow of halfsub is
begin
sum<= a xor b;
carry<= (not a) and b;
end dataflow;
Data flow: :(Full-Subtractor)

library ieee;
use ieee.std_logic_1164.all;
entity fullsub is
Port ( a,b,c : in STD_LOGIC;
diff,bor : out STD_LOGIC);
end fullsub;
architecture dataflow of fullsub is
begin
diff<= a xor b xor c;
bor<=( (not a ) and b)or( (not( a xor b)) and c);
end dataflow;
Behavioral:
library ieee;
use ieee.std_logic_1164.all;
entity fullsub beh is
Port ( a,b,c: in STD_LOGIC;
diff,bor: out STD_LOGIC);
end fullsub beh;
architecture Behavioral of fullsub beh is
begin
process(a,b,c)
begin
if a='0' and b='1' and c='1' then diff<='0';bor<='1';
elsif a='1' and b='0' and c='0' then diff<='1';bor<='0';
elsif a='0' and b='0' and c='0' then diff<='0';bor<='0';
elsif a='1' and b='0' and c='1' then diff<='0';bor<='0';
elsif a='1' and b='1' and c='0' then diff<='0';bor<='0';
else diff<='1';
bor<='1';

61
 end if;
end process;
end Behavioral;
Structural:
library ieee;
use ieee.std_logic_1164.all;

entity fullsubstr is
Port ( a,b,c : in STD_LOGIC;
diff,bor : out STD_LOGIC);
end fullsub str;
architecture structural of fullsubstr is
signal d1,b1,b2: in STD_LOGIC;
component halfsub

port(a,b,c: in STD_LOGIC;
diff,bor:out STD_LOGIC);
end component;
begin
g1:halfsub portmap(a,b,diff=>d1,bor<=b1);
g2:halfsub portmap(a=>d1,b=>c,diff=>diff,bor=>b2);
bor1<=b1 or b2;
end structural;

RESULTS: Full subtractor is designed using 3modelling styles and simulation is done.

62
Model Viva Questions:
1. Give expression for difference and borrow in Half Subtractor
2. Give expression for difference and borrow in Full Subtractor
3. Implement Full Subtractor using Half Subtractors
4. How many NAND are needed to implement Half Subtractor?
5. How many NAND are needed to implement Full Subtractor?
6. How many NOR are needed to implement Half Subtractor?
7. How many NOR are needed to implement Full Subtractor?
8. Implement Half Subtractor using VHDL code.
9. Implement Full Subtractor using Half Subtractor and write VHDL program in structural style.
10. Difference in expressions of Half Adder and Half Subtractor
11. Difference in expressions of Full Adder and Full Subtractor

63
 9. 3to 8 DECODER
Aim:
Design & Write a VHDL code for 3-8 Decoder and verify its functionality .

Software Used:
Xilinx ISE

Theory:

A decoder is a multiple-input, multiple-output logic circuit that converts coded inputs into
coded outputs, where the input and output codes are different.
The input code generally has fewer bits than the output code, and there is a one-to-one
mapping from input code words into output code words.
In a one-to-one mapping, each input code word produces a different output code word.

Fig.Decoder circuit structure.

The general structure of a decoder circuit is shown in above Figure. The enable inputs, if
present, must be asserted for the decoder to perform its normal mapping function.
The most commonly used input code is an n-bit binary code, where an n-bit word represents one of 2n
different coded values, normally the integers from 0 through 2 n-1.

Decoder
This Decoder has one enable input which is active high and 4 outputs which are active high.
The binary decoder‟s truth table introduces a “don‟t-care” notation for input combinations. If
one or more input values do not affect the output values for some combination of the remaining inputs,
they are marked with an “x” for that input combination. This convention can greatly reduce the
number of rows in the truth table, as well as make the functions of the inputs more clear.

64
Logic Symbol:

Truth Table:
Inputs outputs
EN I1 I0 Y3 Y2 Y1 Y0
0 X X 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0

Logic Diagram:

Model Output Waveforms:

65
Logic Diagram:

Truth Table:

66
VHDL Code: (2 to 4 Decoder)
Dataflow:
library ieee;
use ieee.std_logic_1164.all;
entity decoder_1 is
port(a:in STD_LOGIC;
b:in STD_LOGIC;
en:in STD_LOGIC;
d0,d1,d2,d3:all STD_LOGIC);
end decoder_1;
architecture of decoder is
begin
do<=?(not a)and(not b) and en;
do<=(not a)an b and en;
do<= (a)and(not b) and en;
do<=( a)and( b) and en;
end decoder;
3 to 8 Decoder:
Dataflow:
library ieee;
use ieee.std_logic_1164.all;
entity decoderdf is
port(a,b,c,en:in STD_LOGIC;
d0,d1,d2,d3,d4,d5,d6,d7:out STD_LOGIC);
end decoderdf;
architecture of decoder dfis
begin
do<=(not a)and(not b) and (not c) en;
d1<=(not a)and(not b) and c and en;
d2<=(not a)and b and (not c) en;
d3<=(not a)and b and c and en;
d4<=( a)and(not b) and (not c)and en;
d5<=( a)and(not b) and (c) and en;
d6<=( a)and b) and (not c) and en;
d7<=(a)and(b) and ( c) and en;
end decoderdf;
Behavioral:
library ieee;
use ieee.std_logic_1164.all;
entity decoderbeh is
port(a2,a1,a0,en:in STD_LOGIC;
d0,d1,d2,d3,d4,d5,d6,d7:out STD_LOGIC);
end decoderdf;
architecture of decoder beh is
begin
Process(a2,a1,a0,en)
begin
67
if a2='0'and a1='0'and a0='0'and en='1' then
do<='1';d1<='0'; d2<='0'; d3<='0'; d4<='0'; d5<='0'; d6<='0'; d7<='0';
elsif a2='0'and a1='0'and a0='1'and en='1' then
do<='0';d1<='1'; d2<='0'; d3<='0'; d4<='0'; d5<='0'; d6<='0'; d7<='0';
elsif a2='0'and a1='1'and a0='0'and en='1' then
do<='0';d1<='0'; d2<='1'; d3<='0'; d4<='0'; d5<='0'; d6<='0'; d7<='0';
elsif a2='0'and a1='1'and a0='1'and en='1' then
do<='0';d1<='0'; d2<='0'; d3<='1'; d4<='0'; d5<='0'; d6<='0'; d7<='0';
elsif a2='1'and a1='0'and a0='0'and en='1' then
do<='0';d1<='0'; d2<='0'; d3<='0'; d4<='1'; d5<='0'; d6<='0'; d7<='0';
elsif a2='1'and a1='0'and a0='1'and en='1' then
do<='0';d1<='0'; d2<='0'; d3<='0'; d4<='0'; d5<='1'; d6<='0'; d7<='0';
elsif a2='1'and a1='1'and a0='0'and en='1' then
do<='0';d1<='1'; d2<='0'; d3<='0'; d4<='0'; d5<='0'; d6<='1'; d7<='0';
else
do<='0';d1<='1'; d2<='0'; d3<='0'; d4<='0'; d5<='0'; d6<='0'; d7<='1';
end if;
end process;
end behavioral;
Structural:
library ieee;
use ieee.std_logic_1164.all;
entity decoderstr is
port(a,b,c,en:in STD_LOGIC;
d0,d1,d2,d3,d4,d5,d6,d7:out STD_LOGIC);
end decoderstr;
architecture of decoderstr is
signal a2:STD_LOGIC;
component decoder1
port(a,b,en:in STD_LOGIC;
d0,d1,d2,d3:out STD_LOGIC);
end component;
begin
a2<=nota1;
g1:decoder1 portmap(a=>c,b=>b,en=>a2,do=>do,d1=>d1, d2=>d2, d3=>d3);
g2:decoder1 portmap(a=>c,b=>b,en=>a1,do=>d4,d1=>d5, d2=>d6, d3=>d7);
end structural;

RESULT: 3 to 8 decoder is designed and its functionality is verified.

68
MODEL VIVA QUESTIONS:

1. Define functionality of decoder.

2. Write the syntax of CASE statement.
3. What are the applications of decoders
4. A device which converts BCD to Seven Segment is called -----
5. What is difference between demultiplexer and a decoder.
6. What does priority encoder mean?
7. How many 2-4 decoders are needed to construct 4X16 decoder?
8. What is the difference between decoder and encoder?
9. Write the syntax for exit statement?
10. Explain briefly about next statement?
11. How to specify the delay in VHDL program?
12. Write the syntax for component declaration.

69
 10. 8x1 MULTIPLEXER
AIM: Design & Write a VHDL code for 8X1 Multiplexer and verify its functionality .
Software Used: Xilinx ISE

Theory:

Multiplexer is a digital switch or Many into One and also called Data Selector. Multiplexer allows
digital information from several sources routed on to single data out put.

Fig. Multiplexer structure with inputs and outputs

The selection of particular input line is controlled by a set of select lines. Normally there are 2 n input
lines and n select lines. Select lines determine whose input is selected.
The 74x151 is 8-input 1-bit Multiplexer, The 74x151, selects among eight 1-bit inputs. The
select inputs are named C, B, and A, where C is most significant numerically. The enable input EN_L
is active low; both active-high (Y) and active-low (Y_L) versions of the output are provided.
Algorithm:
 8-to-1 Multiplexer has 8 data inputs (D0 to D7), Y is the output and Y_L is the negated output.
 3 select inputs (A, B and C), all three are the active high.
 One Enable input EN_L : Enable Low : Enables when 0,
Disables when 1.
 EN_L is active low then based on selection inputs output selects the data input otherwise the
output is the “null”.
 C is the Most Significant select input Bit
 A is the Least Significant select input Bit
 Declare the data inputs, Enable input and outputs (active high and low) in Entity declaration
part.Declare the required components and signals in Architecture definition part.
 Declare the component label, name and port map with required component instantiation
statement for structural style. Otherwise based on VHDL styles define Architecture body.

70
Logic Symbol:

Truth Table:

71
VHDL Code:

library ieee;
use ieee.std_logic_1164.all;
entity mux8 is
port(d0,d1,d2,d3,d4,d5,d6,d7:in STD_LOGIC;
s2,s1,s0:in STD_LOGIC;
y:out STD_LOGIC);
end mux8;
architecture mux8_arch of mux8 is
begin
y <= ((not s2) and (not s1) and (not s0) and d0) or
((not s2) and (not s1) and s0 and d1) or
((not s2) and s1 and (not s0) and d2) or
((not s2) and s1 and s0 and d3) or
(s2 and (not s1) and (not s0) and d4) or
(s2 and (not s1) and s0 and d5) or
(s2 and s1 and (not s0) and d6) or
(s2 and s1 and s0 and d7)
end mux8_arch;

Behavioral
entity mux8_b is
port(d0,d1,d2,d3,d4,d5,d6,d7:in STD_LOGIC;
s2,s1,s0:in STD_LOGIC;
y:out STD_LOGIC);
end mux8_b;
architecture mux8_b of mux_b is
begin
process(d0,d1,d2,d3,d4,d5,d6,d7,s2,s1,s0)
begin
if s2='0' and s1='0' and s0='0' then y <= d0;
elsif s2='0' and s1='0' and s0='1' then y <= d1;
elsif s2='0' and s1='1' and s0='0' then y <= d2;
elsif s2='0' and s1='1' and s0='1' then y <= d3;
elsif s2='1' and s1='0' and s0='0' then y <= d4;
elsif s2='1' and s1='0' and s0='1' then y <= d5;
elsif s2='1' and s1='1' and s0='0' then y <= d6;
else y <= d7;
end if;
end process;
end mux8_b;

72
 Structural
entity mux8_struct is
port(d0,d1,d2,d3,d4,d5,d6,d7:in STD_LOGIC;
s2,s1,s0:in STD_LOGIC;
y:out STD_LOGIC);
end mux8_struct;
architecture mux8_arch of mux8_struct is
signal y1,y2:STD_LOGIC;
component mux2 is
port(d0,d1:in STD_LOGIC;
s :in STD_LOGIC;
y:out STD_LOGIC);
end component;
component mux4 is
port(d0,d1,d2,d3:in STD_LOGIC;
s1,s0:in STD_LOGIC;
y:out STD_LOGIC);
end component;
begin
g1:mux4 portmap(d0,d1,d2,d3,s1,s0,y=>y1);
g2:mux4 portmap(d0=>d4,d1=>d5,d2=>d6,d3=>d7,s1=>s1,s1=>s0,y1=>y2);
g3:mux2 portmap(d0=>y1,d1=>y2,s=>s2,y=>y);
end mux8_arch;

RESULT: 8X1 multiplexer is designed and its functionality is verified.

73
Logic Diagram:

Model Output Waveforms:

74
MODEL VIVA QUESTIONS:

1. What is meant by multiplexer.

2. Write the syntax of IF statement.
3. What is the difference between CASE & WITH statements.
4. How many select lines required for 64:1 mux.
5. What does demultiplexer mean?
6. How many 8X1 multiplexers are needed to construct 16X1 multiplexer?
7. Compare decoder with demultiplexer?
8. Design a full adder using 8X1 multiplexer?
9. What are the two kinds of subprograms?
10. What are the difference between function and procedure?
11. Explain briefly about subprogram overloading

75
 11. Flip Flops

AIM: Design & Write a VHDL code for Flip-Flop‟s and verify its functionality by using any two
VHDL Styles.

Software Used: Xilinx ISE

Theory:

Flip-flops can be divided into common types: the SR ("set-reset"), D ("data" or

"delay"[11]), T ("toggle"), and JK types are the common ones. The behavior of a particular type can be
described by what is termed the characteristic equation, which derives the "next" (i.e., after the next
clock pulse) output, Qnext in terms of the input signal(s) and/or the current output, .
D flip-flop:

The D flip-flop is widely used. It is also known as a "data" or "delay" flip-flop.The D flip-flop captures
the value of the D-input at a definite portion of the clock cycle (such as the rising edge of the clock).
That captured value becomes the Q output. At other times, the output Q does not change.[21][22] The D
flip-flop can be viewed as a memory cell, a zero-order hold, or adelay line.

SR Flip Flop:

The simplest way to make any basic single bit set-reset SR flip-flop is to connect together a pair of
cross-coupled 2-input NAND gates as shown, to form a Set-Reset Bistable also known as an active
LOW SR NAND Gate Latch, so that there is feedback from each output to one of the other NANDgate
inputs. This device consists of two inputs, one called the Set, S and the other called the Reset,R with
two corresponding outputs Q and its inverse or complement Q (not-Q) as shown logic diagram

The Set State

Consider the circuit shown above. If the input R is at logic level “0” (R = 0) and input S is at logic
level “1” (S = 1), the NAND gate Y has at least one of its inputs at logic “0” therefore, its
output Q must be at a logic level “1” (NAND Gate principles). Output Q is also fed back to input “A”
and so both inputs to NAND gate X are at logic level “1”, and therefore its output Q must be at logic
level “0”.

76
Logic Symbol:
SR Flip Flop:

JK Flip Flop:

T Flip Flop:

D-Flip Flop:
PIN DIAGRAM:

77
 Again NAND gate principals. If the reset input R changes state, and goes HIGH to logic “1”
with Sremaining HIGH also at logic level “1”, NAND gate Y inputs are now R = “1” and B = “0”.
Since one of its inputs is still at logic level “0” the output at Q still remains HIGH at logic level “1”
and there is no change of state. Therefore, the flip-flop circuit is said to be “Latched” or “Set”
with Q = “1” and Q = “0”.

Reset State

In this second stable state, Q is at logic level “0”, (not Q = “0”) its inverse output at Q is at logic level
“1”, (Q = “1”), and is given by R = “1” and S = “0”. As gate X has one of its inputs at logic “0” its
outputQ must equal logic level “1” (again NAND gate principles). Output Q is fed back to input “B”,
so both inputs to NAND gate Y are at logic “1”, therefore, Q = “0”.

If the set input, S now changes state to logic “1” with input R remaining at logic “1”, output Q still
remains LOW at logic level “0” and there is no change of state. Therefore, the flip-flop circuits
“Reset” state has also been latched and we can define this “set/reset” action in the following truth
table.

.JK flip-flop:

The JK flip-flop augments the behavior of the SR flip-flop (J=Set, K=Reset) by interpreting the S = R
= 1 condition as a "flip" or toggle command. Specifically, the combination J = 1, K = 0 is a command
to set the flip-flop; the combination J = 0, K = 1 is a command to reset the flip-flop; and the
combination J = K = 1 is a command to toggle the flip-flop, i.e., change its output to the logical
complement of its current value. Setting J = K = 0 does NOT result in a D flip-flop, but rather, will
hold the current state. To synthesize a D flip-flop, simply set K equal to the complement of J.
Similarly, to synthesize a T flip-flop, set K equal to J. The JK flip-flop is therefore a universal flip-
flop, because it can be configured to work as an SR flip-flop, a D flip-flop, or a T flip-flop.

The characteristic equation of the JK flip-flop is:

T flip-flop

If the T input is high, the T flip-flop changes state ("toggles") whenever the clock input is strobed. If
the T input is low, the flip-flop holds the previous value. This behavior is described by the
characteristic equation:

78
CIRCUIT DIAGRAM:

Truth Table:
D Flip Flop:

JK Flip Flop:

T-Flip Flop:

(expanding the XOR operator)

79
Algorithm:
D-Flip Flop: (74X74)
 Identify the how many inputs and outputs are required for developing of Dflipflop& Next write
the entity declaration.
 In between of the architecture develop the function of Dflipflop 7474 with help of truth table.
 For simulation to develop the test bench.
 Give the sufficient time dimensions.(observe the model graphs).
SR Flip Flop:
 Identify the how many inputs and outputs are required for developing of SR flipflop&Next
write the entity declaration.
 Declare the required components and signals in Architecture definition part.

 Declare the component label, name and port map with required component instantiation
statement for structural style. Otherwise based on VHDL styles define Architecture body.

 For simulation to develop the test bench.

 Give the sufficient time dimensions.(observe the model graphs).
Remaing Flip Flop also follows the same way.(Choose any design style in VHDL)

80
VHDL Code:

SR Flip-Flop:

entity srff is
Port(clk,s,r: in STD_LOGIC;
q,qo:out STD_LOGIC);
end srff;
architecture behavioral of srff is
begin
process(s,r,clk)
variable x:STD_LOGIC;
begin
if(clk='1' and clk'event)then
if(s='0' and r='0') then x='r';
elsif(s='1' and r='0') then x='1';
elsif(s='0' and r='1') then x='0';
else x='1';(undefined)
end if;
end if;
q<=x;
qo<=not x;
end process;
end behavioral;
D Flip-Flop:

entity dff is
Port(clk,d: in STD_LOGIC;
q,qo:out STD_LOGIC);
end dff;
architecture behavioral of dff is
begin
process(d,clk)
variable x:STD_LOGIC;
begin
if(clk='1' and clk'event)then
if d='0' then x='r0;
else x='1';
end if;
end if;
q<=x;
qo<=not x;
end process;
end behavioral;

81
Model Output Waveforms:

JK Flip Flop:

D Flip Flop:

SR Flip Flop:

T-Flip Flop:

82
VHDL Code:
T Flip-Flop:

entity tff is
Port(clk,t: in STD_LOGIC;
q,qo:out STD_LOGIC);
end tff;
architecture behavioral of tff is
begin
process(t,clk)
variable x: in STD_LOGIC;
begin
if(clk='1' and clk'event)then
if t='0' then x='x';
else x='not x';
end if;
end if;
q<=x;
qo<=not x;
end process;
end behavioral;
JK Flip-Flop:

entity jkff is
Port(clk,j,k: in STD_LOGIC;
q,qo:out STD_LOGIC);
end jkff;
architecture behavioral of jkff is
begin
process(j,k,clk)
variable temp:STD_LOGIC;
begin
if(clk='1' and clk'event)then
if j='0' and k='0',and clk='1' then temp=temp;
elsif j='0' and k='1',and clk='1' then temp='0';
elsif j='1' and k='0',and clk='1' then temp='1';
else
temp<=not temp;
end if;
q<=temp;
qo<=not temp;
end process;
end behavioral;

RESULT: Flipflops are designed and its functionality is verified.

83
MODEL VIVA QUESTIONS:

1. Write the behavioral code for the IC 74x74.

2. Write the dataflow code for the IC 74x74.
3. What is the difference between sequential and combinational circuit?
4. What is a flip-flop?
5. Explain the functions of preset and clear inputs in flip-flop?
6. What is meant by a clocked flip-flop?
7. What is meant by excitation table?
8. What is the difference between flip-flop and latch?
9. What are the various methods used for triggering flip-flops?
10. Explain level triggered flip-flop?
11. Write the behavioral code for IC 74X74.
12. Write the syntax of IF statement?

84
 12. Binary Counter
AIM:
Design & Write a VHDL code for Binary Counter and verify its functionality .
Software Used:
Xilinx ISE

Theory:
The modulus of a counter is the number of states in the cycle. A counter with m states is called a
modulo-m counter or, sometimes, a divide-by-m counter. A counter with a nonpower- of-2 modulus
has extra states that are not used in normal operation.
An n-bit binary counter can be constructed with just n flip-flops and no other components, for any
value of n.
T flip-flop changes state (toggles) on every rising edge of its clock input. Thus, each bit of the counter
toggles if and only if the immediately preceding bit changes from 1 to 0. This corresponds to a normal
binary counting sequence—when a particular bit changes from 1 to 0, it generates a carry to the
next most significant bit. The counter is called a ripple counter because the carry information ripples
from the less significant bits to the more significant bits, one bit at a time.

Algorithm:
 First write the entity for T FF by describing T, CLK, CLR as inputs and Q as INOUT.
 Initialize Q as „0‟
 Write the architecture body declaration
 Declare process statement with clk, clr as sensitivity list
 Use the IF statement to declare conditions for clk, clr
 Create a test bench for T FF for functional verification.
 Now write the program for decade counter using T FF using following instructions.
 Write the entity for decade counter with clock as input and Q(3)Q(2)Q(1)Q(0) as inout.
 Write the architecture body for decade counter by its syntax.
 Create 4 T FF instances using component instantiation statements or port map statements.
 Create a test bench for the above decade counter program.
 Give the clock stimuli and check the functional behavior of the Binary counter.

85
Logic Diagram:

Truth Table:
Present state Next state
Clock( Negative Edge Transition) Q(3)Q(2)Q(1)Q(0) Q(3)Q(2)Q(1)Q(0)
1-0 0000 0001
1-0 0001 0010
1-0 0010 0011
1-0 0011 0100
1-0 0100 0101
1-0 0101 0110
1-0 0110 0111
1-0 0111 1000
1-0 1000 1001
1-0 1001 1010
1-0 1010 1011
1-0 1011 1100
1-0 1100 1101
1-0 1101 1110
1-0 1110 1111
1-0 1111 0000

Model Output Waveforms:

86
VHDL Code:
Up/down counter:

entity updcounter is
Port(clk,clr,upd: in STD_LOGIC;
y:out STD_LOGIC_Vector(3 down to 0);
end updcounter ;
architecture behavioral of updcounter is
signal x:std_logic_vector(3 down to 0);
begin
process(clr,clk,upd)
variable temp:STD_LOGIC;
begin
if(clr='0' then x<='0000';
elsif (clk'event='0' and k='1',and clk='1' then temp='0';
elsif j='1' and k='0',and clk='1' then temp='1';
else
temp<=not temp;
end if;
q<=temp;
qo<=not temp;
end process;
end behavioral;

RESULT: Flipflops are designed and its functionality is verified

87
88
 1.FULL ADDER
AIM:
 To design full adder and to determine the transient response and observe the propagation
delay.
 To design a Full Adder in XILINX vivado.

TOOLS USED:

 Cadence virtuoso
 Gpdk 180nm Technology
 XILINX vivado

THEORY:

The difference between a half-adder and a full-adder is that the full-adder has three inputs and
two outputs, whereas half adder has only two inputs and two outputs. The first two inputs are A
and B and the third input is an input carry as C-IN. When a full-adder logic is designed, you
string eight of them together to create a byte-wide adder and cascade the carry bit from one adder
to the next.

With the truth-table, the full adder logic can be implemented. You can see that the output S is an
XOR between the input A and the half-adder, SUM output with B and C-IN inputs. We take C-
OUT will only be true if any of the two inputs out of the three are HIGH.

So, we can implement a full adder circuit with the help of two half adder circuits. At first, half
adder will be used to add A and B to produce a partial Sum and a second half adder logic can be
used to add C-IN to the Sum produced by the first half adder to get the final S output. If any of
the half adder logic produces a carry, there will be an output carry. So, COUT will be an OR
function of the half-adder Carry outputs. Take a look at the implementation of the full adder
circuit shown below.

LOGIC CIRCUIT:

89
SYMBOL:

PROCEDURE:

CREATING SCHEMATIC:

 Right click on desktop and click on open terminal.

 A new window opens, give the commands:
csh
virtuoso
 Click enter. A command interpreter window will open.
90
  Go to file -> library- > create library -> and cell view(inverter).
 A virtuoso schematic window opens, then create your own schematic.
 To create schematic, go to create -> instance. Instance window opens, then browse
Library -> gpdk180/analog lib -> pmos/nmos/Vdd/Vdc/gnd > symbol and then close.
 To connect the terminals, go to create- > wire narrow (W).
 For input, output or input-output pins. Go to create -> pin (P).
 To change the properties of any component, select the component and give its respective
values.
 Using the above steps required schematic can be created.
 Go to file -> check and save.
 Go to launch -> ADE-L. Virtuoso Analog Design Environment window will open.

TRANSIENT ANALYSIS:

 Click on analysis > choose. For transient response, enable ‘trans’ and enter some value
for stop time. Enable ‘moderate’ and then click apply and OK.
 Go to outputs -> to be plotted -> select on schematic -> net list and run.
 After few seconds, the transient response will be displayed. In that, click on ‘strip chart’
mode, to get individual waveforms.
 From the transient response we calculate propagation delay (tp) for the output from low
to high and high to low.
 CALCULATING PROPAGATION DELAY:

 Mark the points Tphl and T plh

Tphl=output-input(from high to low transition)
Tplh= output-input(from low to high transition)

Tpd=(Tphl+Tplh)/2

91
TRUTH TABLE:

A B CIN SUM CARRY SUM CARRY

(theoretical) (theoretical) (practical (practical)
)
0 0 0 0 0 -5.74uV -2.048uV

0 0 1.8V 1.8V 0 1.8V -2.161uV

0 1.8V 0 1.8V 0 1.8V -1.61uV

0 1.8V 1.8V 0 1.8V 2.85uV 1.8V

1.8V 0 0 1.8V 0 1.8V 2.0022uV

1.8V 0 1.8V 0 1.8V 2.88uV 1.8V

1.8V 1.8V 0 0 1.8V 225.9nV 1.8V

1.8V 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V

SCHEMATIC DIAGRAM OF FULL ADDER:

92
OUTPUT:

TRANSIENT RESPONSE:

RESULT: Designed the full adder using cadence and vivado and observed the transient response
and propagation delay.

93
 2.PSEUDO LOGIC GATES

AIM:

 To design pseudo logic gates and observe the transient response, dc response and
propagation delay of pseudo inverter using cadence.
 To design pseudo logic gates using Xilinx vivado.
TOOLS USED:

 Cadence virtuoso
 Gpdk 180nm Technology
 Xilinx vivado
THEORY:

The CMOS logic style described in the previous section is highly robust and scalabe with
technology, but requires 2N transistors to implement a N-input logic gate. Also, the load
capacitance is significant since each gate drives two devices (a PMOS and an NMOS) per fan-out.
Ratioed logic is an attempt to reduce the number of transistors required to implement a given logic
function, at the cost of reduced robustness and extra power dissipation. The purpose of the PUN in
complementary CMOS is to provide a conditional path between VDD and the output when the
PDN is turned off. In ratioed logic, the entire PUN is replaced with a single load device that pulls
up the output when the PDN is turned off. Figure 6.24 shows an example of ratioed logic which
uses a grounded PMOS load and referred to as a pseudo-NMOS style. Instead of a combination of
active pull-down and pull-up networks, such a gate consists of an NMOS pull-down network that
realizes the logic function, and a simple load device.

The clear advantage of pseudo-NMOS is the reduced number of transistors (N+1 vs. 2N for
complementary CMOS). The nominal high output voltage (VOH) for this gate is VDD since the
pull-down devices is turned off when the output is pulled high (assuming that VOL is below VTn).
On the other hand, the nominal low output voltage is not 0V since there is a fight between the
devices in the PDN and the load grounded PMOS device. This results in reduced noise margins
and more importantly static power dissipation. The sizing of the load device relative to the pull-
down devices can be used to trade-off parameters such a noise margin, propagation delay and
power dissipation. Since the voltage swing on the output and overall functionality of the gate is
dependent on the device size, the circuit is called ratioed. This is in contrast to the ratioless logic
styles, such as complementary CMOS, where the low and high levels do not depend upon
transistor sizes. Computing the dc transfer characteristic of the pseudo-NMOS proceeds along
paths similar to those used for its complementary CMOS counterpart. The value of VOL is
obtained by equating the currents through the driver and load devices for Vin = VDD
At this operation point, it is reasonable to assume that the NMOS device resides in linear mode (since
the output should ideally be close to 0V), while the PMOS load is saturated

94
SCHEMATIC DIAGRAM OF PSEUDO AND LOGIC GATE:

TRANSIENT RESPONSE OF PSEUDO AND LOGIC GATE:

95
In order to make VOL as small as possible, the PMOS device should be sized much smaller than
the NMOS pull-down devices. Unfortunately, this has a negative impact on the propagation delay
for charging up the output node since the current provided by the PMOS device is limited. An
important disadvantage of pseudo-NMOS gates is static power that happens when the output is
low, because a direct current path exists between VDD and GND through the load and driver
devices
PROCEDURE:

CREATING SCHEMATIC:

 Right click on desktop and click on open terminal.

 A new window opens, give the commands: csh
virtuoso
 Click enter. A command interpreter window will open.
 Go to file -> library- > create library -> and cell view(barrel shifter).
 A virtuoso schematic window opens, then create your own schematic.
 To create schematic, go to create -> instance. Instance window opens, then browse Library
-> gpdk180/analog lib -> pmos/nmos/Vdd/Vdc/gnd > symbol and then close.
 To connect the terminals, go to create- > wire narrow (W).
 For input, output or input-output pins. Go to create -> pin (P).
 To change the properties of any component, select the component and give its respective
values.
 Using the above steps required schematic can be created.
 Go to file -> check and save.
 Go to launch -> ADE-L. Virtuoso Analog Design Environment window will open.

TRANSIENT ANALYSIS:

 Click on analysis > choose. For transient response, enable ‘trans’ and enter some value for
stop time. Enable ‘moderate’ and then click apply and OK.
 Go to outputs -> to be plotted -> select on schematic -> net list and run.
 After few seconds, the transient response will be displayed. In that, click on ‘strip chart’
mode, to get individual waveforms.

DC ANALYSIS:

 For Dc response, enable ‘dc’ and ‘save operating dc point’. In sweep variable, select
‘component parameter’ and then click on ‘select component’. Select the required
component (Vpulse) in the inverter schematic you have created.
 Select component parameter window opens, in which Vdc DC voltage must be selected and
click ok.
 In ‘sweep range’, enter ‘start’ and ‘stop’ (voltage 0v > 1.8v) values. Apply -> ok.

96
SCHEMATIC DIAGRAM OF PSEUDO NAND LOGIC GATE:

TRANSIENT RESPONSE OF PSEUDO NAND LOGIC GATE:

97
 Go to outputs -> to be plotted -> select on schematic and return to ADE window. Go to
simulation - > net list and run.
CALCULATING PROPAGATION DELAY OF INVERTER:

 Mark the points Tphl and T plh

Tphl=output-input(from high to low transition) Tplh=
output-input(from low to high transition)
Tpd=(Tphl+Tplh)/2

98
SCHEMATIC DIAGRAM OF PSEUDO OR LOGIC GATE:

TRANSIENT RESPONSE OF PSEUDO OR LOGIC GATE:

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SCHEMATIC DIAGRAM OF PSEUDO NOR LOGIC GATE:

TRANSIENT RESPONSE OF PSEUDO NOR LOGIC GATE:

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SCHEMATIC DIAGRAM OF PSEUDO XOR LOGIC GATE:

TRANSIENT RESPONSE OF PSEUDO XOR LOGIC GATE:

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SCHEMATIC DIAGRAM OF PSEUDO XNOR LOGIC GATE:

TRANSIENT RESPONSE OF PSEUDO XNOR LOGIC GATE:

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 RESULT:
Designed pseudo logic gates in cadence and vivado and observed the transient response, DC
response and propagation delay

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