Scribd
Upload
20 views19 pages

Unit 4 Testing

This document discusses design for testability in integrated circuits. It notes that testing is a major cost, accounting for over 50% of the design effort for many chips. Without design for testability, test costs can increase 5-10x. The document outlines various testing considerations like controllability, observability, and generating test patterns to detect stuck-at faults. It discusses challenges in testing sequential logic, where the order of test patterns is important. Overall, the document advocates designing circuits to make internal nodes and states more easily tested.

Uploaded by

Mmk Reddy
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
20 views19 pages

Unit 4 Testing

This document discusses design for testability in integrated circuits. It notes that testing is a major cost, accounting for over 50% of the design effort for many chips. Without design for testability, test costs can increase 5-10x. The document outlines various testing considerations like controllability, observability, and generating test patterns to detect stuck-at faults. It discusses challenges in testing sequential logic, where the order of test patterns is important. Overall, the document advocates designing circuits to make internal nodes and states more easily tested.

Uploaded by

Mmk Reddy
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 19

Design for Testability

A Anitha, Sr. Assistant Professor


Electronics & Communication Engineering

1
Testing Considerations
 the test costs could rise by a factor of five to ten, compared with the
same system designed for testability
 Controllability
 Observability

2
A Anitha, Sr. Assistant Professor
Testing
 Testing is one of the most expensive parts of chips
 Logic verification accounts for > 50% of design effort for many chips
 Debug time after fabrication has enormous opportunity cost
 Shipping defective parts can sink a company

 Example: Intel FDIV bug (1994)


 Logic error not caught until > 1M units shipped
 Recall cost $450M (!!!)

3
A Anitha, Sr. Assistant Professor
Logic Verification
 Does the chip simulate correctly?
 Usually done at HDL level
 Verification engineers write test bench for HDL
 Can’t test all cases
 Look for corner cases
 Try to break logic design

 Ex: 32-bit adder


 Test all combinations of corner cases as inputs:
 0, 1, 2, 231-1, -1, -231, a few random numbers

 Good tests require ingenuity

4
A Anitha, Sr. Assistant Professor
Silicon Debug
 Test the first chips back from fabrication
 If you are lucky, they work the first time
 If not…
 Logic bugs vs. electrical failures
 Most chip failures are logic bugs from inadequate simulation
 Some are electrical failures
 Crosstalk
 Dynamic nodes: leakage, charge sharing
 Ratio failures
 A few are tool or methodology failures (e.g. DRC)
 Fix the bugs and fabricate a corrected chip

5
A Anitha, Sr. Assistant Professor
Manufacturing Test
 A speck of dust on a wafer is sufficient to kill chip
 Yield of any chip is < 100%
 Must test chips after manufacturing before delivery to customers to only
ship good parts
 Manufacturing testers are
very expensive
 Minimize time on tester
 Careful selection of
test vectors

6
A Anitha, Sr. Assistant Professor
Manufacturing Failures

SEM images courtesy Intel Corporation

7
A Anitha, Sr. Assistant Professor
Stuck-At Faults
 How does a chip fail?
 Usually failures are shorts between two conductors or opens in a
conductor
 This can cause very complicated behavior
 A simpler model: Stuck-At
 Assume all failures cause nodes to be “stuck-at” 0 or 1, i.e. shorted to
GND or VDD
 Not quite true, but works well in practice

8
A Anitha, Sr. Assistant Professor
Examples

9
A Anitha, Sr. Assistant Professor
Observability & Controllability
 Observability: ease of observing a node by watching external output
pins of the chip
 Controllability: ease of forcing a node to 0 or 1 by driving input pins of
the chip

 Combinational logic is usually easy to observe and control


 Finite state machines can be very difficult, requiring many cycles to
enter desired state
 Especially if state transition diagram is not known to the test engineer

10
A Anitha, Sr. Assistant Professor
Test Pattern Generation
 Manufacturing test ideally would check every node in the circuit to
prove it is not stuck.
 Apply the smallest sequence of test vectors necessary to prove each
node is not stuck.

 Good observability and controllability reduces number of test vectors


required for manufacturing test.
 Reduces the cost of testing
 Motivates design-for-test

11
A Anitha, Sr. Assistant Professor
Test Example
SA1 SA0
 A3 {0110} {1110}
A3 n1
 A2 {1010} {1110} A2
Y

 A1 {0100} {0110} A1
n2 n3

 A0 {0110} {0111} A0

 n1 {1110} {0110}
 n2 {0110} {0100}
 n3 {0101} {0110}
 Y {0110} {1110}

 Minimum set: {0100, 0101, 0110, 0111, 1010, 1110}

12 12: Design for Testability


A Anitha, Sr. Assistant Professor
Sensitized path-based testing
 1. Manifestation: Gate inputs at the site of an assumed fault, say a 'stuck
at' (SA) fault, are specified to generate the opposite value to the
assumed SA value (0 for SAl, 1 for SA0).
 2. Propagation: Inputs of other gates are determined so as to propagate
the fault signal along the selected path to the primary output of the
circuit. This is done by setting And/Nand inputs to '1' and Or/Nor
inputs to '0'.
 3. Consistency (or justification): This final step finds the primary input
patterns to realize all the necessary values. This is done by tracing
backward from the gate inputs to the primary input of the logic. ·

13
A Anitha, Sr. Assistant Professor
14
A Anitha, Sr. Assistant Professor
15
A Anitha, Sr. Assistant Professor
Testing Sequential Logic
 Sequential circuits, which may be generally represented as finite state
machines, may be modeled as combinational logic with a set of delays
and feedback from output to input.

16
A Anitha, Sr. Assistant Professor
 The 'm' feedback variables constitute the state vector and determine
the maximum number of finite states which may be assumed by the
circuit.
 The next state and the output are both functions of the present state
and the independent inputs.
 The test generation for a sequential circuit is a very complicated task
since the test signals must not only be logically correct but must also
occur at the correct time relative to other signals.

17
A Anitha, Sr. Assistant Professor
The effect of memory
 It is not only the test pattern but also the order or sequence in which
it is applied is significant.

 the state of output Q


 a 'good machine' (GM)
 a 'faulty machine' (FM) for a SA1 fault on each of the four input lines (1 , 2, 3,
4).

18
A Anitha, Sr. Assistant Professor
The Iterative test generation method
 the testing of sequential logic is done by 'converting' the logic into
combinational logic by cutting the feedback lines, thus creating pseudo
inputs and outputs as well as the original primary input and output lines.
 For an N-state machine, this arrangement is then replicated N times so that
an N-state sequential machine is converted into an N-time frame combinational
machine.
 The main problem of this technique is that a simple fault in the sequential
machine is manifest as N multiple faults during test.This is time-consuming for
circuits of any complexity.
 It is also necessary to describe all the initial states of the circuit, which is
also time-consuming.
 For these reasons the iterative test generation (ITG) methods are best
suited to logic with few feedback loops as in control logic for example.

19
A Anitha, Sr. Assistant Professor

You might also like