Lecture 7:

CMOS DC & Transient Response

Mark McDermott
Electrical and Computer Engineering
The University of Texas at Austin

9/20/18 VLSI-1 Class Notes

 Agenda

§ DC Response
§ Logic Levels and Noise Margins
§ Transient Response
§ Delay Estimation

9/20/18 VLSI-1 Class Notes Page 2

 DC Response

§ DC Response: Vout vs. Vin for a gate

§ Ex: Inverter
– When Vin = 0 -> Vout = VDD
– When Vin = VDD -> Vout = 0
– In between, Vout depends on
transistor size and current
– By KCL, we know that VDD

Idsn = |Idsp| Idsp

Vin Vout
Idsn
– We could solve equations
– But graphical solution gives more insight

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 Transistor Operation Review

§ Current depends on region

of transistor behavior 60 Linear Region Saturation Region
§ For what Vin and Vout are VGS = +5V

nMOS and pMOS in 50

Drain Current, IDS (µa)

– Cutoff? VGS = +4V
– Linear? 40
– Saturation?
30 VGS = +3V

20
VGS = +2V

10 VGS = +1V

0
0 1 2 3 4 5 6
Drain-Source Voltage, VDS
(volts)

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 nMOS Operation

Cutoff Linear Saturated

Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn
Vin < Vtn Vin > Vtn Vin > Vtn
Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn
Vout < Vin - Vtn Vout > Vin - Vtn

VDD

Vgsn = Vin Idsp

Vin Vout
Vdsn = Vout Idsn

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 pMOS Operation

Cutoff Linear Saturated

Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp
Vin > VDD + Vtp Vin < VDD + Vtp Vin < VDD + Vtp
Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp
Vout > Vin - Vtp Vout < Vin - Vtp

VDD

Idsp
Vgsp = Vin - VDD Vin Vout
Vtp < 0
Vdsp = Vout - VDD Idsn

9/20/18 VLSI-1 Class Notes Page 6

 I-V Characteristics

§ Make pMOS wider than nMOS such that βn = βp

Vgsn5

Vgsn4
Idsn

Vgsn3
-Vdsp
-VDD Vgsn2
Vgsp1 Vgsn1
Vgsp2 0 VDD
Vgsp3 Vdsn

Vgsp4 -Idsp

Vgsp5

9/20/18 VLSI-1 Class Notes Page 7

 Current vs. Vout, Vin

Vin0 Vin5

Vin1 Vin4
Idsn, |Idsp|

Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
VDD
Vout

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 Load Line Analysis

§ For a given Vin:

– Plot Idsn, Idsp vs. Vout
– Vout must be where |currents| are equal

Vin0 Vin5

Vin1 Vin4
Idsn, |Idsp|
VDD
Vin2 Vin3
Idsp
Vin Vout
Vin3 Vin2 Idsn
Vin4 Vin1
VDD
Vout

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 Load Line Analysis

§ Vin = 0

Vin0

Idsn, |Idsp|

Vin0
VDD
Vout

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 Load Line Analysis

§ Vin = 0.2VDD

Vin1
Idsn, |Idsp|

Vin1
VDD
Vout

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 Load Line Analysis

§ Vin = 0.4VDD

Idsn, |Idsp|

Vin2
Vin2

VDD
Vout

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 Load Line Analysis

§ Vin = 0.6VDD

Idsn, |Idsp|

Vin3
Vin3

VDD
Vout

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 Load Line Analysis

§ Vin = 0.8VDD

Vin4
Idsn, |Idsp|

Vin4
VDD
Vout

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 Load Line Analysis

§ Vin = VDD

Vin0 Vin5

Vin1
Idsn, |Idsp|

Vin2
Vin3
Vin4
VDD
Vout

9/20/18 VLSI-1 Class Notes Page 15

 Load Line Summary

Vin0 Vin5

Vin1 Vin4
Idsn, |Idsp|

Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
VDD
Vout

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 DC Transfer Curve

§ Transcribe points onto Vin vs. Vout plot

Vin0 Vin5 VDD

A B

Vin1 Vin4 Vout

C

Vin2 Vin3

Vin3 Vin2 D
E
Vin4 Vin1 0 Vtn VDD/2 VDD+Vtp
VDD VDD
Vout Vin

9/20/18 VLSI-1 Class Notes Page 17

 Operating Regions

§ Revisit transistor operating regions

Region nMOS pMOS

A Cutoff Linear VDD

B Saturation Linear A B

Vout
C Saturation Saturation C

D Linear Saturation
D
E Linear Cutoff 0 Vtn VDD/2
E
VDD+Vtp
VDD
Vin

9/20/18 VLSI-1 Class Notes Page 18

 Beta Ratio

§ If bp / bn ¹ 1, switch point will move from VDD/2

§ Called a skewed gate
§ Other gates: decompose into an equivalent inverter

VDD
bp
= 10
bn
Vout 2
1
0.5
bp
= 0.1
bn

0
VDD
Vin

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 Noise Margins

§ How much noise can a gate input see before it does not recognize
the input?

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 Logic Levels

§ To maximize noise margins, select logic levels at the unity gain

point of DC transfer characteristic
Vout

Unity Gain Points

VDD
Slope = -1
VOH

b p/b n > 1

Vin Vout

VOL
Vin
0
Vtn VIL VIH VDD- VDD
|Vtp|

9/20/18 VLSI-1 Class Notes Page 21

 Transient Response

§ DC analysis tells us Vout if Vin is constant

§ Transient analysis tells us Vout(t) if Vin(t) changes

– Requires solving differential equations

§ Input is usually considered to be a step or ramp

– From 0 to VDD or vice versa

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 Inverter Step Response

§ Ex: find step response of inverter driving load cap

Vin (t ) = u(t - t0 )VDD

Vin(t)
Vout (t < t0 ) = VDD Vout(t)
Cload
dVout (t ) I dsn (t )
=- Idsn(t)
dt Cload
ì Vin(t)
ï 0 t £ t0
ï
( )
b 2
I dsn (t ) = í 2 V DD - V Vout > VDD - Vt
ï Vout(t)
V (t )
ï b æçVDD - Vt - out 2 ö÷Vout (t ) Vout < VDD - Vt t
î è ø t0

9/20/18 VLSI-1 Class Notes Page 23

 Delay Definitions

§ tpdr: rising propagation delay

– Max time from input to rising
output crossing VDD/2
§ tpdf: falling propagation delay
– Max time from input to falling
output crossing VDD/2
§ tpd: average propagation delay
– tpd = (tpdr + tpdf)/2
§ tr: rise time
– From output crossing 0.2 VDD to 0.8 VDD
§ tf: fall time
– From output crossing 0.8 VDD to 0.2 VDD

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 Delay Definitions

§ tcdr: rising contamination delay

– Minimum time from input to rising output
crossing VDD/2
§ tcdf: falling contamination delay
– Minimum time from input to falling output
crossing VDD/2
§ tcd: average contamination delay
– tpd = (tcdr + tcdf)/2

NOTE:
Contamination delay is not the same thing as minimum delay. It is the minimum
amount of time from an input signal change to an output signal change

Minimum delay - is the minimum amount of time from an input signal change (to
its correct value) to an output signal taking on its correct value (tpd)

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 Simulated Inverter Delay

§ Solving differential equations by hand too hard

§ SPICE simulator solves equations numerically
– Uses more accurate I-V models too!
– But simulations can take a long time to run
2.0

1.5

1.0
(V)
tpdf = 66ps tpdr = 83ps
Vin
Vout
0.5

0.0

0.0 200p 400p 600p 800p 1n

t(s)

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 Delay Estimation

§ We would like to be able to easily estimate delay

– Not as accurate as simulation
– But easier to ask
What if?
§ The step response usually looks like a 1st order RC response with
a decaying exponential.
§ Use RC delay models to estimate delay
– C = total capacitance on output node
– Use effective resistance R
– So that tpd = ReffC

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 Effective Resistance

§ Shockley models have limited value

– Not accurate enough for modern transistors
– Too complicated for much hand analysis
§ Simplification: treat transistor as resistor
– Replace Ids(Vds, Vgs) with effective resistance R
• Ids = Vds/R
– R averaged across switching of digital gate
§ Too inaccurate to predict current at any given time
– But good enough to predict RC delay

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 RC Delay Models

§ Use equivalent circuits for MOS transistors

– Ideal switch + capacitance and ON resistance
– Unit nMOS has resistance R, capacitance C
– Unit pMOS has resistance 2R, capacitance C
§ Capacitance proportional to width
§ Resistance inversely proportional to width

d
s
kC
kC
R/k
d 2R/k
d
g k g kC
g k g
s kC kC
kC s
s
d

9/20/18 VLSI-1 Class Notes Page 29

 RC Values

§ Capacitance
– C = Cg = Cs = Cd = 2 fF/μm of gate width for technology scaled devices

§ Resistance
– R » 10 KΩ•μm in 0.6 μm process
– Improves with shorter channel lengths
– 1.25 KΩ•μm in 65 nm process

§ Unit transistors
– May refer to minimum contacted device (4/2 λ)
– Or maybe 1 μm wide device
– Doesn’t matter as long as you are consistent

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 Inverter Delay Estimate

§ Estimate the delay of a fanout-of-1 inverter

2C

2C 2C
2C 2C
2 Y 2
A Y
1 1 R C
C
R C C

d = Reff * 6C
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 Delay Model Comparison

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 Example: 3-input NAND

§ Sketch a 3-input NAND with transistor widths chosen to achieve

effective rise and fall resistances equal to a unit inverter (R).
– Assume βp = ½βn

2 2 2

3
3

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 3-input NAND Caps
§ Annotate the 3-input NAND gate with gate and diffusion
capacitance.

2C 2C 2C
2C 2C 2C
2 22 22
2C 2C 2C
9C
33 3C
5C 3C
3C
3C
33
5C 3C
3C
3C
33
5C 3C
3C

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 Elmore Delay

§ ON transistors look like resistors

§ Pullup or pulldown network modeled as RC ladder
§ Elmore delay of RC ladder

t pd » å
nodes i
Ri -to - sourceCi

= R1C1 + ( R1 + R2 ) C2 + ... + ( R1 + R2 + ... + RN ) C N

R1 R2 R3 RN

C1 C2 C3 CN

9/20/18 VLSI-1 Class Notes Page 35

 Fanout Example: 3-input NAND
§ Estimate worst-case rising and falling delay of 3-input NAND
driving h identical gates.
2 2 2 Y
3 9C 5hC
n2
3 n1 3C
h copies 3 3C

t pdr = ( 9 + 5h ) RC t pdf = ( 3C ) ( R3 ) + ( 3C ) ( R3 + R3 ) + éë( 9 + 5h ) C ùû ( R3 + R3 + R3 )

= (12 + 5h ) RC
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 Delay Components

§ Delay has two parts

– Parasitic delay
• 9 or 12 RC
• Independent of load
– Effort delay
• 5h RC
• Proportional to load capacitance

t pdr = ( 9 + 5h ) RC t pdf = ( 3C ) ( R3 ) + ( 3C ) ( R3 + R3 ) + éë( 9 + 5h ) C ùû ( R3 + R3 + R3 )

= (12 + 5h ) RC
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 Contamination Delay

§ Best-case (contamination) delay can be substantially less

than propagation delay.
§ Ex: If all three inputs fall simultaneously

2 2 2 Y
3 9C 5hC
n2
3 n1 3C

3 3C

æRö æ 5 ö
tcdr = éë( 9 + 5h ) C ùû ç ÷ = ç 3 + h ÷ RC
è3ø è 3 ø

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 Diffusion Capacitance

§ We assumed contacted diffusion on every source / drain.

§ Good layout minimizes diffusion area
§ Ex: NAND3 layout shares one diffusion contact
– Reduces output capacitance by 2C
– Merged uncontacted diffusion might help too

2C 2C
Shared
Contacted
Diffusion Isolated
Contacted 2 2 2
Merged Diffusion
Uncontacted 3 7C
Diffusion 3 3C

3C 3C 3C 3 3C

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 Layout Comparison

§ Which layout is better?

VDD VDD
A B A B

Y Y

GND GND

9/20/18 VLSI-1 Class Notes Page 40