Lecture 4:

Implementing Logic in CMOS

Mark McDermott
Electrical and Computer Engineering
The University of Texas at Austin

9/11/18 VLSI-1 Class Notes

 Review of DeMorgan’s Theorem

Recall that:
(AB)’ = A’+B’ and AB = (A’ + B’)’
(A+B)
= A’B
and A+B = (A’B’)’

A A’
(AB)’ A’+B’
B B’
A A’
AB (A’+B’)’
B B’

A A’
(A+B)’ A’B’
B B’
A A’
A+B (AB)’
B B’

9/11/18 VLSI-1 Class Notes Page 2

 Bubble Pushing

§ Start with network of AND / OR gates

§ Convert to NAND / NOR + inverters
§ Push bubbles around to simplify logic

Y Y

(a) (b)

Y Y

D
(c) (d)

9/11/18 VLSI-1 Class Notes Page 3

 Static CMOS Circuits

§ N and P channel networks implement logic functions

– Each network connected between Output and VDD or VSS

Parallel network:
"OR" function

Series network:
"AND" function

9/11/18 VLSI-1 Class Notes Page 4

 Duality in CMOS Circuits

§ N and P networks must implement complementary functions

§ Duality is sufficient for correct operation
What are the values of A, B
and C which will produce a
P connection between P and Q

A+B*C
B
A
C

9/11/18 VLSI-1 Class Notes Page 5

 Constructing Complex Gates

§ Example: F = (A * B) + (C * D)
– Take un-inverted function F = (AB + CD) and derive N-network
– Identify AND, OR components; F is OR of AB,CD
– Make connections of transistors
• AND , Series connection, OR , Parallel

A C

B D

9/11/18 VLSI-1 Class Notes Page 6

 Construction of Complex Gates, Cont
d

§ Construct P-network by taking complement of N-expression (AB

+CD), which gives the expression, (A + B) * (C + D)
§ Combine P and N circuits
V DD

A B

A B
C D

C D A C

B D

9/11/18 VLSI-1 Class Notes Page 7

 Layout of Complex Gate
V DD
AND-OR-INVERT (AOI) gate
A B
Metal 2
Vdd

C D B A
C D

F Metal 1

A C

GND

B D
Layout

9/11/18 VLSI-1 Class Notes Page 8

 Example of Compound Gate
V DD

C
F = (A + B + C) * D

B D

A
F

A B C

9/11/18 VLSI-1 Class Notes Page 9

 Example of More Complex Gate
+V

A C F

B D G H
OUT
A B

OUT = (A+B)*(C+D)*(E+F+GH)
C D

E F

9/11/18 VLSI-1 Class Notes Page 10

 Exclusive-NOR Gate in CMOS

IN1
IN2 OUTPUT

VDD

P B
P
OUTPUT = AB + AB
N N
OUT P A
N

N
IN1 IN2 B
(A) (B)

9/11/18 VLSI-1 Class Notes Page 11

 Pseudo nMOS Logic

VDD

Generally a
weak device

A C

B D E

9/11/18 VLSI-1 Class Notes Page 12

 Duality is not Necessary

§ Functions realized by N and P networks must be complementary,

and one of them must conduct for every input combination
VDD

a c
F = ab + a
b
+ a’c’ + cd + c
d

b d

a b c d

The N and P networks are NOT

duals, but the switching functions
a b c d

F
they implement are complementary
"Hybrid"
a b CMOS Circuit

a b

a c

c d

c d
GND

9/11/18 VLSI-1 Class Notes Page 13

 Example of
Dual Rail Complex CMOS Gate
VDD

F=
G F
z z

G=

x x

x x

y y

9/11/18 VLSI-1 Class Notes Page 14

 Signal Strength

§ Strength of signal
– How close it approximates ideal voltage source

§ VDD and GND rails are strongest 1 and 0

§ nMOS pass strong 0

– But degraded or weak 1

§ pMOS pass strong 1

– But degraded or weak 0

§ Thus nMOS are best for pull-down network

9/11/18 VLSI-1 Class Notes Page 15

 Pass Transistors

§ Transistors can be used as switches

g g=0 Input g = 1 Output

s d 0 strong 0
s d
g=1 g=1
s d 1 degraded 1

g g=0 Input Output

g=0
s d 0 degraded 0
s d
g=1
g=0
s d strong 1

9/11/18 VLSI-1 Class Notes Page 16

 Transmission Gates

§ Pass transistors produce degraded outputs

§ Transmission gates pass both 0 and 1 well

Input Output
g = 0, gb = 1 g = 1, gb = 0
g
a b 0 strong 0
a b g = 1, gb = 0 g = 1, gb = 0
a b 1 strong 1
gb

g g g
a b a b a b
gb gb gb

9/11/18 VLSI-1 Class Notes Page 17

 Pass Transistor Logic

§ What is the difference between the two circuits?

A A B B A A B B

P1

C, C P
2
F(A,B,C) F(A,B)
P
3

P
4

9/11/18 VLSI-1 Class Notes Page 18

 Pass Transistor Logic -- Better Layout

§ Group similar transistors, so they can be in the same well

A A B B

F(A,B)
P4

P
3

P
2

P1

9/11/18 VLSI-1 Class Notes Page 19

 Pass Transistor Logic Pull-Up Version

§ How do voltage levels at the output of this gate differ from that
of the pass-transistor multiplexer in the previous foil?

A A B B

F(A,B)

9/11/18 VLSI-1 Class Notes Page 20

 Tristates

§ Tristate buffer produces Z when not enabled

EN
EN A Y
A Y
0 0
0 1
EN
1 0
A Y
1 1
EN

9/11/18 VLSI-1 Class Notes Page 21

 Non-restoring Tri-state®

§ Transmission gate acts as Tri-state® buffer

– Only two transistors
– But nonrestoring
• Noise on A is passed on to Y

EN

A Y

EN

9/11/18 VLSI-1 Class Notes Page 22

 Tri-state® Inverter

§ Tri-state® inverter produces restored output

– Violates conduction complement rule
– Because we want a Z output

A A
A
EN
Y Y Y
EN

EN = 0 EN = 1
Y = 'Z' Y=A

9/11/18 VLSI-1 Class Notes Page 23

 Multiplexers (mux)

§ 2:1 multiplexer chooses between two inputs

S
S D1 D0 Y
D0 0
0 X 0 0 Y
0 X 1 1 D1 1
1 0 X 0
1 1 X 1

9/11/18 VLSI-1 Class Notes Page 24

 Gate-Level Mux Design

§ How many transistors are needed?

Y = SD1 + SD0 (too many transistors) 20

D1
S Y
D0

D1 4 2
S 4 2 Y
D0 4 2
2

9/11/18 VLSI-1 Class Notes Page 25

 Transmission Gate Mux

§ Nonrestoring mux uses two transmission gates

– Only 4 transistors if both of the select signals are available
– If not then it takes 6 transistors…

D0
S Y
D1

9/11/18 VLSI-1 Class Notes Page 26

 Inverting Mux

§ Inverting multiplexer
– Use compound AOI22
– Or pair of tristate inverters
– Essentially the same thing
§ Non-inverting multiplexer requires adding an inverter

D0 S D0 D1 S
S D1 S S
Y Y D0 0
S S S S Y
D1 1

9/11/18 VLSI-1 Class Notes Page 27

 4:1 Multiplexer

§ 4:1 mux chooses one of 4 inputs using two selects

– Two levels of 2:1 muxes
– Or four tristates
Requires pre-decoded signals

S1S0 S1S0 S1S0 S1S0

D0
S0 S1

D0 0
D1
D1 1
0
Y Y
1
D2 0 D2
D3 1

D3

9/11/18 VLSI-1 Class Notes Page 28

 D Latch**

§ When CLK = 1, latch is transparent

– D flows through to Q like a buffer
§ When CLK = 0, the latch is opaque
– Q holds its old value independent of D

CLK CLK

D
Latch

D Q
Q

** transparent latch or level-sensitive latch

9/11/18 VLSI-1 Class Notes Page 29

 D Latch Design

§ Multiplexer chooses D or old Q

CLK
CLK
D Q Q
1
Q D Q
0
CLK CLK

CLK

9/11/18 VLSI-1 Class Notes Page 30

 D Flip-flop Design

§ Built from master and slave D latches

CLK CLK
CLK QM
D Q
CLK CLK CLK CLK
CLK
Latch

Latch

QM
D Q
CLK CLK

9/11/18 VLSI-1 Class Notes Page 31

 Questions?

9/11/18 VLSI-1 Class Notes Page 32