NumDer

Digtal Logke & COA (MU-Sem 3-Comp) (14) S Digtal Logic & COA (M-Sem. 3-Comp)
NumDer
= number decimal or radix poin odale
where N
INTRODUCTION b number system
Thus, the value of cach digit in a oumber can be delermined (Hexadecimal number syate
1.1 D
fdirits in fractional pat
The Hexadecimal aumber system i5 used in micropre
basc
"

number of digits in integer pat systems. The bexadecimaa uiber y

ot the digit
d Least Signi hicant Digie osition 16 (sirieen)
3, 4, 3, 6, 7, 8, 9, A, B,
Ans. d Most Significant Digit (MSD) n the dugits 0, 1, 2,

ODeinNtion
. .
The mumber system is used
: A number system is a method to

-- tor
*************
representing a quatngy or
nd
4, or d.p)sb-
The, digits in the integer part will have weights that
are
pO6iave powErs ol basC (b) and the digits in the iractional part
wll have weighis ihat are
H 1.2

digits used in
TYPES OF NUMBER SYSTEMS

Ihe buse or radix ot the number system is the total number

inat number
sten
of
W 1.3 DECIMAL NUMBER SYSTEM
Decimal oumber system is the number system
ourday-to-day life.
that we use in

0, ,2 3, 4, D, 0. 1, 0
egle eg Decinal numbers have ten digits
:

hematical representation rby pu 2.

ne umbers by a set of digits or symbols. Every number is 0 Definition: The base or radix (6) of the
rpresenied by the posibonal notadon ot uhie dugils.
uMDEr s4stem is the total number of digits;
epending on the basis, the different types of mumber 3. Base: The bae of te decimal nunber
nu
ye hown in
ner systenm can be classified as

() Decimal number system

4 The decimal number dgs

(u) Binary number systcm Table 1.3.1 : Decimal number diglts and thelr values
of its posiion and weight, eg. Roman number systems. Non-Examplc, Decimal digit Value Radis or base
(i) Octal number system
() Posdtional number system : ln a pošin nnoe
i) lfa mumber system represents digits 0 and I then the base of
v)HexaCclml n 0 L 0
that system is 4.
significance
Occia)
or
weight
t be atached to that digit: ) f oumber system represents digits 0, 1, 2, 3, 4, 5, 6, 7, 8,9
Dumoe 5ystem.

cieroaics systems are posiuonal number systems. a nDer syse, ne lgSt vae a gu s ne ess
comues, nucroproceEssoTs, data than the base.
Decimal Binary Octal Hexadecimi
g KADAK, Dgaion dc. v) The value of a number is the sum of products of the digits of
thait murnber with their corEsponding
imber stem Sysem
poSiional weights.
1.1.1 Representing a Number
In any number aystrm, every syrnbol Im ne nunDer ix
digit. has a weight of b' and the tird digit to the left has a weight
The leltmost dugit or he number has die grealcst posiaona b and so on. 1 he fint dgit lo ne ngnt or
e uecnaon 9
E tispositioaal
(nine).
enning dgils in that number, lt is called ( cach digit can be determined by its
0E Signifcant Digit (MSD). Point has weught so on. Thus, each digit of the
band
number represents a differeat multiple of the base. a.i
i
13pes Dumber ystems sition or place in the given uumber. This posibon
weight among the digits in that umber value of the digits is called as wesgh
ier g. 1.1,1
0 Decimal number sysienm us dhe decimal nunber ysten p
tem ie. he posio
AnnDer is Tormed by the collection of digits. nificant git Sianifcant Digit he decimul number system has l0 symbols or digits :0, 1,2, he of thalt di git
(LSD)) 3,4, 5,6, 7, 8 and 9. AS it compnes ot len gis it sCueu
er can be epresented by tbe sum of the weighicd
as decimal nuinber system.
|(a) Integer part (b) Fractional part (o to }, 5o
ne numoer Syetn represenls ten igis
ecim Fig .3. sows Ow e ags And her welgs
he buse oecimal Durnber 3ysem as
a power of 10.
part is separuted from the integer part with a epresseu ln ie
ruonal
decimal point or aai" Binary number system ecimal raumo
(e) pNnt
Eaa)
The dgits a8 the lelt side of the radix poine ronn hgpa Fracuo
uc integer radx p
and digits on the righi side of the radix The modem computers use binary number sysicm
oneumber erfoorming operai ons.
*

pAt Or thc number,

A Dinary number syslem
uses two symbols 0 and L. Ius, une
Thus, a number e

Integer Part
raon (1A1Flg. 1.1.1 :
O: base or radix mal
Positional wedghts of a number Octal number system
(I) radapon
he value of the number shown 1,2,3,4.5, 6 and 7.
in Fig 1.1.1 can be computied as, octal number system has 8 digits:0,
he
MSD LSD
N
4,xb)*(d, xb)+ (d, xb') +4,x5) is bsc
IC Octal
is cignlo
nurnber 5ystem was used in
mini-computers ce'llE3
Dectnl orn polnt d. *b )+d*b)+ d., xb5)+(d.,xb) wegnis for decimal number system
(AP g. 13,liPosidonal SACREN SHAH Yantare
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 Digital Logic & COA (MU-Sem &.Comp) & Number SyS
Digtlal Logie cOA (MU-Sem.3.
wit
E number
nd is s
Thetbost digi has the grestes poitiona N
i Definition
(radis) two called as binary
is ruimber
base
system, Uses of binary number system
B(elght).
rightmost digit has the lowest positional weight and is called
as the Leest Sgnifhcant Digit (LSD). MSES wo synbois or augits o and 1 called as "
s ue binary umbers
devices like diodes, transistors operate as
nE anumber system is a positional
welghted syslem.
an octa

EL 1.3.1
binary digne switches and have two stabie slates, 0 and 1, 1Lc. a switch can we Deea uEE Dnaiy dgis lo reprtsent
an octal
A binary number is a sequcnce of bits 0 and 1. The
radi shows the weights for different posidons in
g.S.
Represent tbe decimal oumber 728.14 in powers of 10.
or nay pount seplainies e meger pat rrom the OPEN switch and binaryI can be used to represet a
numoer 5yem.
pont

. sa
Ans.:(Reler Fig. Ex. 1.3.1) a. cal Nuhro
2 n can be easily maintained in digital systems that
uy number Sysiem is 2.
Most Significt Dig Least Significant Diglt
(LSD)
"***
postional wesphted system Le every dugit position is
aperate on binary data
(MSD)
aSs4gned a weignt in tes Or powe
PDISOVantage o1 Dinary number syslem
e wegnts diierent positions in a
fr For epresenting a binary mumber we require a kong sinng or

7. As shown in ig. 14.1, the first bit to the left of binary point sas. Eg. humber (0}j ts cquivalent in
coet
s
. ie o se
binary
as weghi 2he second bit to the et of the binay point wegns
Posibonal value of diog w
the fourth bit
third Dit to the ert has a weight 2 and
to the left has a weight 2. 1e. he weignt or
of 0's and 1's will be needed. Hence, the binary numbers are
Convertcd to any other DUmber system like decimal, octal or
Positional

(AEFg. 1.S.l: weghts For dinferent positons is an octa

e ne power of 2 greater than the
E 131: Kepresentation of decimal number
8. The first bit to the right of the binary point has a weight 2. 14.1 Binary Number Formats
t s weighe 8.
ig. E 1.3.I shows e Diny pount has a
represeuuadon or oEma
te n ore
the
1. A binary digit is called as a bit e.g 0, 1. The seconl dgt to
.The
tleftmost he third bit to the ngt has a weignt 2
bit has the greatest posidonal weigh ano ts be thiurd gt *

Ditt mition to the left is ooe power of

itional valut=Namber= sum of al c ust ugnihicant Bit and tne nghtmost
(S5) 3 a
Byte: In a binary number system, group of 8 bits called is than the weight of the digit to its successi've nga
greater

Significant Bit (LSB). as a byte. A by1e is a group of 2 nibbles. eg. 1000 0. The eftmost digt has greaest poitomal weight ana B
te
OS .700+20 +B+0.1 4Word i a binary hurier 5ysem, a go
ln Cale as ue D0St S
2 bytes or 4 nibbies is Calca a wou od
g 8. The radix or octal point sepundes une nieg pa
d
1000 fractional part
pesent ne Dinary number 1.in powers of 2
Doube weight8
100.1 x0.1 =0.1 Ans. Refer Fig. Ex. 14.1) 4 brtes or 8 nibbles is c 9 he st eal oint has weigh

L4110"0.01| 4x001 =0.04 SB double word. eg. 0110 0111 1010 1011 1000 1111 0011 and so on. The righrmost digit has the lowest positiona
Sinary INumoe O10. wEight and is called as the Least Snincant DpLsD,
14 BINARY NUMBER SYSTEM Table 1.4.1: Data formats wed in binary number syste
Example
13.1
Moderm computers, micropro Dat press Ue octal number a6.12 m powErs or B.
decimal numbers. They use the binary Dumber format
s operalons. Bit 1 bit Ans.: (Refer Fig. ExL 13.1)

ry numbeT sysiem uses 2 digits : 0 and 1. It allows rosvonal vaue o1 DIS Nibbie
4
bils
s,diOdes, 1 Leasi s nt Dg
clc with two stales HIGH or IOWrON Ex 1A.I: Repreentation of binary number 1001.11 Byic 5DiS ioDICS = 1101 10 Nost >
Word 16 bits 2 bytes 4 1000 0110 1101 1010
MSB n powers o 2 Octal Number
inary Ne
gn nal alueNumber sum or w hsR nibbles
1011 1000 111o iil
0110 1101 10
1001

eghted digits
Radx
*U+0+I+ 0.5 1.5 OCTAL NUMBER SYSTEM
= 9.75
0 *0. that
che number system ue -Positional vate of dgt
O Definition: The that uses
Positional weights
9 Kepresenladon ot octal umber
tionscalled as octal; t
ESk. 1S.1
1XI APg.
(1A4Fig. 14.li Weights for different pesitions in a binary I 2=0.5 Ix0.5 0.5 number system
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 Digial Logic & COA (MU-Som. 3-Como) 18) yslems
Ka Diojital Logic & COA (MU-Sem. 3-Comp) Number SYstems
nio o or oaxe ot ue neka0cmal number syste
Welaht
UmberUm is 16 (sheteen).
k Hexadeclmal ModulJe
The hexadecimal number system is an alphanumerk
The eflmast digit has
egrealepositional
Called as the Mont Significant Digit (MSD
weIgt au s
|DEin
OctalE
Dunber umber (base 16) 1
number system as it uses bodh numeric dignts and alphabet. The fist digit to the right of hex point has weight 16 The base 10) base

3064 The minmum value dignt is zero) and the maumum value seconddg to tne nntonee p1nt has weight
so on. 1The nghmost digit has the lowest positional weig
and 6 0101
dgit is Hdecimal 19).
ea Dipt (LSD).
0123 1x O.125 = 0.125 The heradkecimal number system is a postional welghted (Refer Eie 161 7 0111 L
git positon 15 assigied a wcighi in tems
2 0.015625 2x0.015825 lem. 1.ey Hexadocimal Number 1000 10

.
ol powers of 16,
MsD LSD
Since 2 16, we eca * binay dugs o epe Integp Fraction 01
An octal number is length of coresponding binary
number.
hexadecimal digiL. Thus, a hexadecimal number isthe
abie z 1S.l(a) : Octal mumbers and their equivalent binary kength of the corresponding binary number.

umbers ouier operates with 8 bits, 16 bis, 32 bits, 64 bits data,

t umber (ase 8) Equvalent binary E, mupies Hence,
ol 4 bits. easy t is to represent the
numben in hexaieeima.
Postional welghts
e 1 exadectmal humbers and their point
17
Dinary numbers (AnFig. 1.6.1 : Weights for different positions in a Hexadecimal OTHER NUMBER SYSTEMS
Hexadecmal digit number system
1.8
ecima value
16) Base10) Many number systems are used for perftorming dtierent
a1.6.1 Advantages of Hexadecimal ns.
Ase 2
Number System abe 1.8. sbows the commonly used aumber systems along
very easy to represent a group of four bit binary numbers. with their syriboals ag
1.is nence, DC Table 13.1 : Number syslems and their symbos
Adventages asenbiy anguag oa
) The octal number system
is an easier method lo heeEssed as F(15)). a 11
s Diny can Number syskem Bse or DigitsSymbols
ts guivaent
() s S.Hexadecimal numbers are easy to recognise and interpret Binary number
easy to convert a binary
number to its equivaeni octal sysMem
4 Hexaxdecimal numbers can be casily convernicd to binary and
Temary number 3 0, 1.2
H 1.6 HEXADECIMAL NUMBERR 5. Hexadecimal number system is more convenient to express a
SYSTEM number as compared to binary and octal number sysuems. Quatemary Dumber 4 a 1.2.3

Hexadecimal number system H 1.7 RELATION BETWEEN

Is ued n computlensand
r- r ysems. DECIMAL, BINARY, OCTAL
AND HEXADECIMAL NUMBER|ey ubers
Pehntion The number system that
:
ues 14
symbols o, 32, MSES L6: SYSTEMS F
3,4, S, 6, 7, 8, pumber
D,Eand
9, A, 8, C. Fig 16.1 shows the weights
tor diterent posibons n a
Dumber u23,4,5,6
F to represent a
information is called
rumber or nexaeciunal number system
hexadecimal numbe " Eenal, binary, octal
as the Hexadecial;
nor hetecimal (hez) point separales the
and Octal number 0. 1,2,3,4.5,6,7
Table I1.7.1 5ystem

.
uber system Donal part.
*******--*****n*-**- As
As shown in Fig
shows 16.1, the fint digit to
Decimal Binary Octal Hexadecmal Decimal mumber 10
0.1,2.3,4, 5,6, 7,8,9
the left of hex point
has weigt 16. The second digit
to ber
Definition: The number system
nai weight 16.
ic the left
left of the
the he
hex pont (base 10) base 2 bocnary numiber 10.L,2.3.4,5,6,1.8,9, a
that uses 1 The thnd digt
syMbol o, to the et of the hex point
2, 3,4, S, 6, 7, 3, 9,A, B, has weight Duodicnary or 12 0.1.2.3,4,5,6,7.8,9,a, B
C. ,Uwege at every d
DE anaF tor representation is called as pOwer of ieh
greater than the weight
uCcesive rig
lefi is one
of the digit to
its
e duodecimal

0, 1, 2, 3, 4, 5, 6, 7, 8,9, A.
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 Number
Dioital Logie & COA (MUSem.
2- 1.10 BINARY-TO-DECIMAL Diital Logic & COA (MU-Sem. sicomp) Number S
g 18.1 shows the weights for different positions in
H cONVERSION 1.102 Onle
number sysieg with ndis t.
Do the following convesion(1o1.001( ho
MSD nt Number 2| a Dibuy number o oEcia uer, Uere are
0 convet
Ans.:(Refer Fig. Ex. 1.10.2) LSB
. CSB
rosi0 On noabon method sp1:8nanynunber - BinayNu

Dong nedod

cEOODO0EO
Step 1: Poslionat woigrta EJEL
1.10.1 Binary to Decimal Conversion
byY
Positional welghits a
Positional Notation Method
A 12
esor diteret posiltons in a
way in which the position of
Positional notadi on method fs a
The
number A7S
The weight of every position to the left is one power of t each digit has apae
preater thag the weight of the digit to its successive nght
eof
oducts of the digits of that

From Fig. 1.8.1, a number N can be represenicd a5,

nher with their cornesponding positional values or wey a0o alequlvae

r+ Steps to be followed to convert a binary number 1o an

Nd,+d+r+d, 4+d equivalent decimal number are as TouOw
=
Thus, (1101.0011), (13.1875
*d,*4,*d H 1.11 DECIMAL TO
BINARYY

NUMBER SYSTEM p ie E given number. a 1.10.2 Binary to Decimal Converslon by

CONVERSioN
H 1.9 DOUDiingMeuoa
CONVERSSlON convesion is aho called as
1 This mcthod of bnary
Step II: Write the positional weights for each digit. Dob ng tae bina umbes. The given Double Dabble method or Dibbe Dabbe
The decimal number system is important because it 1s
e of 2. hbence doubling can be uscd.
univenaly u
c data Hence, t isStep m: Multiply cach digit in the gven number wilh ts Steps to be followed to convert a ven
nacthoo are as lollows
u n part of the decimal number is converted to
binary

essential to conven the decimal number to binary before it is oondino

coesponding weight to get product of dgits or ng uoag using suceSSYE
ivided by
applied to a digital system and convert the bunay nunier to positional vahue.
Step It Wnte the binary number.
3.In the succe aind divisioo is o
Beginning with MSB, muluply the bit by
2 and add MSB. To obtin the equivalent binay
Step 11: the
are many benary numbers of large bits then it is
" here the total to he next bit to ng remalee ae ead
O
cO venient to express the binary numbers in of octal or tms Step IW: Find the sum of producis to obAun the decimal n suces tional part of the
4. ld hy 2, till the fractional part of
cquivalent of the given binay nuer. Step 112 Repeat sicp u nll all sts the product is O.
vent the binary numbers to octal and Ex. 1.10.3
ice. veraor we need to convert the binary numben o Thequvalenl ouny
Convet (10101h=(\%to decimal.
exadecimal and vice-versa
Ans.:(Refer Fig. Ex. 1.10.3)
the nie
ined o obaia the equivalent binary nber.

Ex. 1.10.11 MSB

1.11. Steps 1or Decimal to Binary
Coavert the folowing number. Show all steps (101101.10101
=( Je Conversion for Integer Part
Ans.:(Refer Fig Ex. 1.10.1) Binary Numb
rite the decimal number,
Bunany rumber
slep 1 :
an add the nextbit
remainde
number by
Step 22*215
Multoy by Sep ieis the LSB of the binary number.
and adc Une
cnl obuained from
step
he
Stp m: Digta wag-
hhi 44 Sne oy by 2s2.0-10 Step 1ut
ohained is the second LSB of e Dnay

Btep IV: Sum of produts3/'t1

ITTTT 05 01250000125 Step V: Mulioly by2 0x3*14
Dumber.

Kepel divo Dy 2 uent becomes 2eT0. 1e.

and add tha hert br Siep 1W:
An
quotient o ois
aaO Dy 4

Resut decimal equlvalent

0.65643
1.103. Slep V he ast remnoer
coa re he

APg. E. MSB of the biny om lo

top.

04 decimal equlvalent
Thus, 0101, ( numb
-ASACHL.S344B Vesiare
Thus, 001.10101= (43.6562)0 A19gE. 1.10.1
er Auibars npurean
inav
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 Numberc Logjc & COA (MU:Sem 3-Comp) Number
aDiital Logic & COA (MU-Sem. 3-Comp) Digtl
Base Quntiend Remainder Module
Ex. 1.11.1 BaseQuotient Remainder
Eanpk,
Cconvert decimal number 19.35 into binay. 2
aseoletHenarder
Ans. 2 un 12
LSB) LS8)
1SB)

2 binary co0n eTNOn O nieger pan by

2 13
0+ Fist remander (LS8) : Decimal
Cessive division by 2.
2 D6 1 Second remainder 2
Thid remarn Base uoen Kcmancer
ead up

u emander 199
1 Fih remanoer (MSBJ LSB) Re p

Bottom ResC up
11
"010 24 1(MSB)

a 1.11.2 Steps for Decimal to Blnary 2 35 (0011011

Conversion for Fractlonal Part Step 11: Decimal to binary convesion of frmcional part by
EYE mplucauion by 2.
StepI: Write the fractional decimal number. 2 3
Thus (199o=(1100011 (Refer Fig. Ex. 1.12)
2
Step Multiply the fractional decimal number by 2 and
(MSB) Decimal Base Product Camy Step II : Decimal to binary conversion of fraectonal pat by
write the cany in integer purt. The fint cary is the
MSB. successive multiplication by 2
...
0 (MSB) (Refer Fig. Ex 1.13)
Saep Il: Multiply the factional ea
and mcond the 0aied
purt of the product obtaincd ec oycues
BUCCessivE muliplicaon by 2.
ouonal paut oy
instep Il (Refer Fig. FEx. 1.1 1L)
"
0.66
Surp Repeal sieps l and all the fractional part of the '
u ro ll ust Camy s the LsB of the
u. Tne
cquivalent binary umber. The equivalent binu
(MSs)

0.375 * (MSB) 0.32

fromton to boitomi MC
Euny
032
(0.3125)0 ( (Refer Fig 1.11.1)
ecima Base Product
0.75 2 doWn

ctiOn ngop
o.28
.3125 O (MSB)
(LSB) 2 0.56 i(LSB)
(A2Fig. Ex. 1.112 2
IAsFig. Ex. 1.11.1

(0375) 0.011 (0.35,(0.0101

Step 111 Combine the answers oblaincd in step Step 111 : Combine the answers obtained in step I and i.
down I and x2 0.4 O (LSB)
85.35 (10011011.0101,
99375h (000111.011,
0252 UEx. 1.112 MU-0. DEx. 1.11.3U-0. 1a, lay 18.1 Mark
1a, Dec. 16,.4 Marks
onvert decimal number 135.33 into biniury, Covert (1473.45, into binay 0
al A Step Il : Combine the unswers obtained in sep I and siep I1.
1.0 Ane Ans.:
(1473.45)% (10111000001.01110,
Step I: Decimal lo binury cuaversion
Step I: Decinal o binary conversioa or 1neger pu"
of integer purt by
(03125) (0.010 successive division by SCCessive division by 2.
2.

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 Digital Logic & COA (MU-Sem. 3-Comp) (1-14)
UEL1.114
Comvent (214.327%
-O.to 1b), tay 15.2 Marks
binary,
DEx1.11.5 MU-0. 10), Dec. 18,1 Mark
Convert decimal number 576.24 into binary.
Digital Logie & COA (MU-Sem.3Comp)
(1-15) Number Syste
1.12 OCTAL TO DECIMAL E. 1.12.1 Module
Ane. Ans. CONVERSION C touowing umber into its equivalent decimal oumber
Sep Decimal o bunay conversion o nege pant oy Sbow siep by step proces5 ot comveion
SepTt Decimai to binuy convesion o egp Step It
CeESSiYE dvision by 2. successive division by 2.
Wnite the gi'ven number
() 357.2% ( 458.54
For 134.06
Base uotient Remainder Base Quotient Remainder
2 576 (1) (3572,: (Refer Fig. Ex. 1.12.1a)

(LSB)
107 (LSB) ep wnle the Positaonal weights for each digit
Octal number
eler Fig. 1.12.1)

Octal number
ET 2
Oclal number Posonal weights
Wegns

P
Digtxweght
Step
Postonal weigns Sum or proxuS
MSB) MSB)
(1001000000) 0.25
(214) (1010110) /0 (Amig 1.121

Sep 1
Decimal to binary convension of fractional
Sep i: Decimal t0 bLnary convEsion o ncuona pant by tep 1 Muluply each dgit in the gven number with its

pat by ou or
UccesSivE mulupucation by 2.
EESSIVE muluplication by 2. nositional ua t agits
(1A)Fg. EL 1.121a)
Declmal
Base dnteger-part)
Decimal Base Product CaTy
fraction
mcton
(unteer Octal number (458.54)
0.24 0 (MSB)
0.32 (Refer Fig. Ex. 1.12.10)
2
0 MSB
Octal number
Digtx wergnt tep
2
12 eal ndmDer
(IA09|Fig. 1.122 Step I
.O 2 1.92 Positional weights
282
O.9e 2 StepI Find the sum of products to obain the decirnal
tep
Digi weight -L
1.84 1 (LSB)
U.6 X 2 1.12. cquvalcat o0he giVEn Otal Dumber Sum of r
2APg. Ex. 1.115
(4x 8)+ (0x 8)*(6 x89
P
Ex I.114 (0.24) 8.0 5)+(X8)+ 0 6875
Ag (0.001

0.0101, Step Ill : Combine the answens obtained Sum of products

in step I and step (304.6875) 1 decimal equvalentAns.
Step Il : Combine the answers obtaioed in step I
and ep I
07624 (1001000000.0011) (13406% 64+24+4+0+0.09375
(214.32 (AyFig. Ex. 1.1216)
(11010110.ot01)
(134.06), (92.09375),
Thus, (4S8.S4, = (0L6875)1»

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&
coA (MU-Sem. 3-Comp)
UEx.1.122 MU-0. 1101. May 16. 1 Aark
$32125, into decimal,
(16) un stemsS Digital

Step IV:
Logic & COA (MU-Sem. 3-Comp)

Repeat sten
step Ita and T till the fractional part of the
camy is the LSB of
heI
(1-17)
UEx 1.13.3 MU . 1a). Dec. 15, 1 Mark
Coevert decimal mumber 199.375 tndo octa.a
Nurmber Systes

Modale

Ans.: Refer Fig. Ex. 1.12.2) ven numoerbe

fractional pat s obtainedy raing
equivalent octal
the inie gers Ans.:
ASB LSS
(Refer Fig. 1.13.1) StepI Decimal to octal conversion of integer part ot gven
step 1: Binay number Example :
(0.3125)(?h 8.
.
number by successive division by
Decimal Base Product Cary

-
SiepIl : Posibional weights- fractuon ntegerp Base UoEnt emanO8

Stap III : DIjix welght T 0.31258 25 2MS8) 8

Stp um ol proous
34 7 uo Equivaert oa
3z0 0.0312so.00976 xB 4.0 4 (LSB) Red Number
(MSB)
0.166011 1.13.1

Thas, (S32.125),= (46.1601) Thus, (0.3125)%%= (0.24) (199)» (07%

Step II : Decimal to octal conversion of fractional part of

UEx. 1.13.1 MU-O. 10.May 15,1 Mark
EVEa numDer Dy succeSsivE muluplicaton by 2
Con
1.13 DECIMAL To OCTAL Convert (126)%0 to octal,
keter Fg. Ex. 1.13.3)
Slep 1ltt Divide the quotent obtained from
CONVERSlON hder oblained is the second LSB of Ans.:
To comverta decimal
D Step Decimal to octal con version ot gven number by Decima b
0ntaoeroat)
number to an equivalen
nieger part1 o the d oc, SUCCessive division by 8.
mber is converted to octal bySiep IV t Repeat division by & till quotient becomes zero,
Ccessive division by 8 and the fract Base Quolent Remainder
i. 0. 375
numocr Is coverted to octal by using
I
en s o mger divIsible by 8,
8
126
mLlplicaluon by 8.
AMeFTg. Ex. 1.13.3
In the
,
successlve diviskon by
ucn heanes zeto.
&, the integer part is divided by
Ihe remu nder to the divIsion
Step Y The last remaunder obtained
MSB o ue
from the division is the
octal umber. Tne equivaicnt
15
ocu
n to top.
N Step M: Combine the answers obtained in step and
I

o obuain the equivalent octal integer, the remainders xample : (128)

rom botom to are read
aen Thus, (126)4 = (76% (L9375) 073
3ase Quobent
Od Remainder
In vucceslve muluiplcation by &, the fractional
decimal number d by 8, e
1s mutupuea
of the
put of
urt 28 .13.2 uEx 1.134 MU 0. 101. Dec. 16.1 Mark
u "
enaoe Convert the following number, show all the steps : (247)%0 (?%
e Ocl number 13133 into octal

De equivalcnt octal fractional

niegern irom top to botton.
paurt is obtained by reading
th 8
2
0
Read up Octal number Ans.: A Ans.:
Esult is combined to obtain
I.e. MSB to LSB. Finally, the
- (MSB)
Decimal to octal number conversion ot gven
Step l: Decimal to octal conversion of integer pat by
the equivalent octal number.
Thus,
(24
Step I: successive division by 8.
a 1.13.1 Steps for Decimal to
Octal
nuimber by sMCCENSIVE divIBION Dy 8.
Base Qvobent Hemainder
Converslon for Integer Part
a1.13.2 Steps for Decimal to
Octal
Converslon of Base Quotient Remajnder
Stepl Wite the decimal number. Fractlonal Part
SiepI Write the fractional de Read upEquhalent octa
Step l1: Divide namber
the decimal number by 8. he
obLained is the L.SB of the octal number
remainder SMep
II Multiply the

MSB ""
fractional decimal
number
mcger part, The fira by 8 and. 8
8
LSB) Read up Numbe

p Il:Multaply (MSB)
the Itactional
part of the product
*
ecord the cary. obainea
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 aDigital Logic & COA (MU-Sem. 3-Comp)
Nuioer cens Number SysIem
Digital Logic & COA M-Sem.omo)
Step I1: Decimal to octal coavenion of fractional part byStep I1: Decimal to octal conversion of fractional part by Module
Slep 1 Decima to cal convenion ot fractonal pat by LSB
multupbcadion byy8,
SUCcessive muloplicua0n by 6. -MSB
ccessive
numer
Product Decimal BaseProduct
imaBase
aon Bas Product fraction
Integer-part) Integer- r-part)
octal 011 010
6 MSB Step
100 101 110 111
3 bit binary
MS6) .24 * 8 1.92 (MSB)
quvaon
(100101110.111011010)%
Equvalent binary number Ans.
U.09

ASpi1.141
ead
down Ex. 1.14.1
0.12 .36
X8 2 Convert (670.17, into binay.
Ans. (Refer Fig. Ex. 114,1)
o4x =
tCsB) (LSB)
8 32 3 (LSB)
-MSB
Octal number
Ex. 1.36
GApFig. Ex. 1.13.4 CAgig. Ex. 1.13.5
(045)1 (0.3463),
(0.33h 0207% Step II1 : Combine the answers obtained in step and
I . Step
Step ITI: Combine the answers obained in siep I and I. Step Il: Combine the answers obtained in step I and 1I. 147545) (27001346J,

(151.33), (27207h (S7624 (0.1727), (110111000.0011)

1.14 OCTAL TO BINARY
UEX. 1.13.6 LMU-0.
UEx. 1.13.5 MU-0. ). Dec. 18,1 Mark 10. May 18,1 Mark cONVERSION
1 Convert (1473.45%% into octal.
nALnE g, ExL 1.141
Coavert decimal number 376.24 into octal number.
Steps to be followed (Refer Fig. 1.14.1) Thus, (670.17% =(11010.00111h
Ans.: Step I: Write the given octal mumber.
Step I Decimal to octal conversion of integer part
by
UEx 1.14.2 MU-O. 10, May 16, 1 Mark
Step1 ? Decimal to octal coavenion of
456.732
integer part by Uccessive dvsIon Dy 8. Convert (532 I29% iato bnay
5UCCesive division by 8.

Base Quotlient Remainder ep ui Kepiace ea Octar digit by s -but bLBary

Refcr Fig. Ex. 1.14.2)
Base Quotient Remainder cquivalen.
- MSB Octai number
8 S76 1473
1

(LSB)
Octal Digit 3 Bit equlalent binary nuber

(5ase 8)
9 (Read up) (Rea up) Step
3 bil binar
101 011 010 pon 00110 101

101011010.001010101)
2 (MSB8) iea lvalent numberAns
(S76) 00
473) (2701,

nus, (332S%=1010O10.0101O101

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Digital Logic &COA (MUSem. 3-Comp) umber Slems
1.15 BINARY TO OCTAL CONVERSION
OOnle
Added bit LSB
" Step I n products to obtain the decimal
StepI: Write the given binary number. f te given octal sumber.
Binary number L (4C 28) (4x 16')+(12 x 16)+ (2x 16 )
Sep : Surting from either side of the binay point, form groups of 3 bits. x16
* toa)*{l2) +(0.125) +(0.0429)

Step II: Replace each 3 bit binay group with its equivaleat octal number.
Groupa of 3 bis
L0 L 101 Ex. 1.16.1

Example: (100101111.010111011% (Refer Flg. 1.15.1 Dothe fouowing converic

igit
Ans. (Refer Fia Ex. 1.16.1)
SB.
Equvalent octal number, Ans.
Binary number Hexadednalnnbe
5tep1: Benay nurie (A38)Flg. Ex. 1.15.3
tep
Ainary decimal
Thus, (10101101)) = (255)%

Step 1 :
Groups of 3 bits
1001 P 1.16 HEXADECIMAL TO DECIMAL stap
cONVERSiON
sap: 3
c Euvalent
of bit binary number 7 2 s O convert a bexadecimal number to an equivalent decimal

(457.273) Equlvalent octal number Ans.

Step I: Wnte the gven number. Step 125
15.1
1001011l1.010111011)h =(457.273), Step I1: Write the positional weighis for each digit
(Refer Fig. 1.16.1) V
1.15.1 (zA134e dcimeauA
Binary number
Convert (110101.101010), to octal MSB (LAAIFE Ex. 1.16.1
Hexadeclmal number
Ans.: Refer Fig. Ex. 1.15.1) inary number haCah% (124125)
Binary number om Ex 1.16.2
5tep 1 Do the following conversion :
(3A 2Pu (a
Groups of 3 bits
Ans. : (Refer Fig. Ex. 1.16.2)

number
LSB
Positional weights
acimel
GrOuDS
Groups of 3
hits 0 Octal Equlvalent
Step
valent
L digit

(53.79% Equvalent octal number Ans.

(ABF 1.16.1 p
-DA
dioiR
Step Il: Multiply each digit in the given number with its Step
IAGg. Ex. 1.152 comesponding weight to gel product ot digis or Posilonal
(65.52 Equvalent octal number -Ans. wegns
positional value. (Refer F% 1.16.2)
IASg. Ex. 1.15.1 Thus,(10101t.10
** Hexadecimal num
Digitx
weight

.
Thus, (110101.101010), (65.524
x. 1.15.3
Convert (10101101),= (-
Ex. 1.15.2
Convent the following numbers, show all steps. Ans.: 0.71
(Refer Fig. Ex. 1.15.3)
(101011.111011(% welght
B16 Digit x
mal equlveent An.
h
Ans. 12-16 Le.11.16 rAFig. Ex. 1.162
(Rerer Fig. Ex. 1.13.2)
Thus, (3A ;2)% (S8.71)%

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 Diotal Logie& COA MU:Sarm 3.Como = Number ysiems Digtal Logie & cOA IMU-Semgcomo)

UEx. 1.17.2 MU-O. 10). Dec. 15.1 tMark,

(1-23)
Product Carry lodule
M1.17 DECIMAL TO HEXADECIMAL a 1.17.2 Steps for Decimal to Hexadecimal fraci nteger pa
Converslon of Fractional Part Convert decimal number 199.375 into hexadecimal system.
CONVERSION
Ans: (MSB)
To convert a decimal number to an cquivaent hexadecimaStepI: Write the fractional decimal number
Step 1: Decimal to hexadecimal convenion of integer part
conec
aunmber, the inieger part of the decimal nurmber is

decimal ep u Muluply the rcthonal oeciml part by 8 And wnie

by succesive division by 16. 12
tional part of the decimal number is converted to
down
cary is the
using succesive multiplication by 16. ca ue cge pant. The linst BUNC
GentKem emainder
by

In he succesive divsoa by the neger part , suvo

MSB.
(LSB) 0.2 18
by 16, ul he quoueat reaches zero.
dviS I8 uhe MSB.
remaino
e
10 oMain the equivalent hekdecimal
o ne
Step 1ll i
Mutiply the fractiomal pan or ue product obtauned 16 12
7 Read up

tnteger, the remaunders are rcad from botom to top. in siep lu ana
cr ney +12 (MSB) 3

ielied h 16 sil
the
fractional
nart of Step IV: Repeal steps Il and II ill the fractional pat of the Thus, (199) (C7
the product is zero. t is
2ero. The last cary
is the (045)%(0.7335)
Step 11: Decimal to bexadecimal conversion of fruectional part
equlvalent hexadecimal number. e cguivacnt Combine the answers obained in step and siep Il.
I
The equivalent hexadecimal part is obtained by reading the Step 11:
Suceessive mutuplication by 16.
t gEs Irom op o Dom, Ie,
MSB LSB. Finaly, ue o bexadecimal fractional purt is Gblaunca Dy readinE Dy
(1473.45% (SC1.78US
result is Combined to obtain the equivalent hexadecimal to
Digens tiom lop lo botiom, 16, MS5 LS5. (Refer Fig. Ex. 1.17.2)
UEx. 1.174 MU-O. 1a) Dec. 16, 1 Mark
mumber.
: (0.575)h7 (Refer Fig. 1.17.
xample convert oecimal numberI3133 1nto hezadecimal system.
a1.17.1 Steps for Decimal to Hexadecimal camy unteger par)
oartl
Ans.
Product
Conversion ror ihteger Fat Bse
6
0.37515 6.00
Step I: Write the decimal number
16 = 10.8 (MSB)
0.675 A (A6Flg. Ex. L172 Base Quouent Remainder
6 (8)
(0.375) 0.6
Sep If: Divide the decimal number by 16. The remainder
C
6
obained is the LSB of the hexadecimal mumber. Step I1: Combine the answers obtained in step I and stepI. *****
(19575u C- DEp u i
ema To
hexadecima conversion
or rchional
UEx. 1.17.3 MU-O.11). May 18.1 Mar
Step
1: Divide the quotient obuined from Step 1. The
emanoer 18 ne second LSB o uie Covert (147345% into hexadecimal.
einea Decimal Base Produci y (ue gapany
hexadecimal number.
0.6 16 128 (LSB) A Ans. :
StepI Decimal to Hexadecimal conversion of integer part
1.17.1
StepIV: Repeat division by 16, till the quotient becomes by successive division by l6.
.3
zero. 1.quotient is no longer divisible by 16. 0.575), (0ACCC)
Base Quotent Kemainder
UEx. 1.17.1 MU-0. 10.May 15, 1 Mark 0.28 * T6
448
(LSB)
Siep The last remainder obtained from the division is theConvert (26)% into hexadecimal nuunber. 6 1475
MS of the hexadecimal number. The equivalent Ans.
6
92 7
Rec
down
hexadecinmal mumber is read trom botom 1o op Step Decimal to hexadecimal coaversion of gven
16 5 C Read up

Example :(2156)a nmber l-=****° (MSB)

by uceessive diVISIOn by 16.

Base Quotient Remainder 3ase Quotient Remainder Thus, (1473)» 4

J.68
0T0.0
2156 6 ot retiona
6 remaunoer (LsB) Step 11: Decimal to Hexadecimal conversicn
34 TiNt
16. E So)
14(E) purt bySuceessive Fuupucation by 14.08
10
6 Second remainder Read up Read 16 Ex. 1.174
(Mig.
8 (MSB) *****7 Keier Fig. Ex. 1.17.3)
(MSB)

(2156)86C) Thus, (126),

7E (033)(s97AE
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 Number Syatoma
oihal Logiu
à COA (MUSem. 3.Comp) Number Systems
Digtal Logle &cOA (MU:Som. 3-Comp) 1-25)
Stry 11 Cwnbine the anvwers obtioeud in Step I and 1.18 BINARY TO HEXADECIMAL lodule
.
t

Step CONVERSION Ex. 1.18.1

Da the following :
(101011.111010,(2 LSB
(1513 7547A p wie e gen Dinay n
ber

Ane (Refer Fig. Bt. 1,18.1)

UE 1.17.5 U 0 1a, Dec. 18. 1 Mark Binary number
oeioiAOIOIgo
into hexadecmal system. Step lU: Starting from either side of the binury pont, fom
Convert decimal sumber 376.4

Ane.
Decimal to hexalecimal convension of integer
groups of
. uay gr
Added bits

Step 1:
diviston by t6.
partSep nerle h win
Cro o04
Oups D
b
00101111O1100
Base,
EAIVe
Quotient Remainder imal numbers and their binary equlvalent,

a AAch

group by
16
---- 2
(576),(240)
MSB) exadecimal digit (Base4bit binary equlvalent (Base 2)
16)
vo
(28EC
hexadecimal equlvelentAN
ANPg EL 1.181

Step I1: Decimal to hexadecimal conversion of fractional Thus, (101011.111011,= (Ehe

part by successive maltiplication by 16.
1.19 HEXADECIMAL TO BINARY CONVERSION
Declmal Bass Produet
recdon gerpart
Steps to be followed (Refer Fig 1.19.1)
:

SAYDAD
0.24 16
AA (MS8) Ste Wriie the given bexadecimanl oumber. e*,
ies bt binary equvalenc
Step l Replace tach hexadecimal digit by
Hexadecimal number

Step:0xa0ELi
3ASi[AoC
T Hadecmal poird
Ioxadecinal poi

0.4 *6 1001 Step :Repace each hey digt0011010

1001 101|1O1O|o00 ulo
y Dnaly oquvalent
ro011101010011101.101000001100)
0.04 16 064 OLS
Equvalent binary numbe
GABig. Ex. 1.175
1JA
1.19
(0.24) 0D70 OAUAU 0010o.00DT00,
Step Il : Combine the answers obaincd inep an nd
Ex.1.19.1
lo binuy
(576.24)j (2403D70), vE AB9)% L

Ans.: (Refer Fig. Ex. 1.19.)

8 4
npie (0010111To0.01101101),= (?) Binarynumber
LSB ma L
rumber
Step:Octal number -gOOEODPHOODODO pc T
Binarý polnt Step O00oT
0010 wis 4 bit binary
Step:Groups of 4 Dils 11| 1100
:| 110101 equivalen
00010101001.10110100%
Binary equNent numba
ArmFig. Ex. 1.19.1

(2FC.60)4 Hexadecimal equlvaien (1010101001.10110100 ASACHEY SLA" Veatare

Thus, (8A9.B4) =
(001011111100.01101101=(2FC.6D) (1AGaig 1.l6.1
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 Diglial Logie & COA (MUSem.3-Comp)
Ex.1.20.1
H1.20 OCTAL TO HEXADECIMAL Convert (615.25), 1o hexadecimal.
UEx. 1.20.3 MU- O. 1a). May 16.1 Mark Exampe: BC2AC lodale

CONVERSION Convent (532.12,to heradecimal. **

number
LS8
Ans. xdecimal
For converting un octal number to a
(Refer Fig. Ex. 1.20.1) Ans.:
hexadecimal mumber, we
(Refer Fig. Ex. 1.20.3)
first convert the octal mumber to binay MSB
equvalent and then we
Octal
convert the binary number lo equivalent hekadecmal number
number
MSB
number
S 1O1T00019 91001od
ep tal
Octal number
Steps to be followed (Refer Fig. 1.20.1)
:

o|11ooolo1oo10o1000
Step Wnie ue givEn ocial number.
pont
423.613 Sian
a 00011d00110 191000 3h ina 0101101 00lo1010oo0
d

(ST02230)
Step 11: Replace each octal dugit by ts equivaicnt s bit
equlvalent
point Octal equlvalet number-Ans
binary number. Step lo0oo10101 o01o101o1000
efA 0011000110101010100 ADPg. 1
Step
Step 111: Staring from eiher side of the binary point, form |5|A:2|A|e
Hexaoen
rOup o Dis. og
alent Ggt equvalen
3A. 2Ahe hezadecimal
number
equvale
ns. Ex. 121.1
(18D. 54)
Step IV Replace each4 bit binary group with
pexadeeima
is nexadecimal equivalent number Ans.
PATFig. Ex. 1.20.3: Hexadecimal equivalent number
eyuivaen
Ans.
(AP)Fig. Ex. 1 20.1
Thus, (52.125, = (15a.248
(Refer Hg. EL 1.21.)
S8 Thus, (615.25), 080.S4)4
Octal number H 1.21 HEXADECIMAL TO OCTAL
CONVERSION
tep
t numoer
UEX. 1.20.2 AMU-O, 10). Dec. 14.2 Marks mber
Convert (670.17), into hexadecimal.
For converting a bexadecimal number to an xal tuiDer,
weumber
Ans. st convet ne nekadkeima nunDE O
a hina
3Digu brary
9oogo1 do1 doeo13o09 (Refer Fig. Ex. 1.20.2)
the we cmvert ihe binary number io cquivalcnt octal number. uivalent
LSB Tans
Sp
tal r Deps to De 1010w ed : (Keter ig. 1.2.1)
Groupr of TToatolat
o1O1|111:110 010 010
000100010011100|01011000 Step
4 bits Octal number Siep Wnie e gven hexadecimal number
p L I3||c | 00010111oo Octal
Step
0110o
I1
binary
(113. C58)4e hexadecimai equlvBlent
3Bit (S187.627, Octal numberAn
equivalent
Sep Keplace cach hexadecimal dgil by its equi'valent
Dit Dinary number. AFlg. Ex. 1211
StepIl 00010111000Jo011110
(1A7Fig. 1 20.1 droups of 4 bits

(423.61J, = (113.cs8)% Step V

Hexadecimal T L 8| Stepl:Slarting from either side of the binary point, form
Thus(A6F.Ch (S157.622,

equivalent d groups of 3 bts.

(1B8.3C).
Hexadecimal equlvalent number
Ans.
(ATE 1g. Ex 12 . Step IV: Replace eachs bit group with its octal cquvaiknt
Thus, (670.17, (1B83C), digit to obtaun the octal ecuivalent number.

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 Diphal Number
Logc & COA MUSm 3omo
Steps for Decimal to redlx r Converslon for Digtal Logic& COA (MU.Sem. 3.Comp)
E 1212 MU-O 1b. Dec 14 2 MarkS
* (0.2145, Base Quodent Remainder fodule
Canet he Tolkeing hetaecimal Dumber (67AAJ into
(LSB)
pI Wrise the dectmal nuimoe Step 151
ietoctal soinber d3 I1: Combine the aswES 0ad ep
4 37
Step l1
Ana Step I1: Divide the decimal number by. Ibe
Sep I: MSB bexaecimal numbn obtained is the LSB of the radix r number. ender
MS UEx 1222 MU-O. 101. Dcc. 18.1 Mark (MSB)

exedec nmbe Coavert decimal mumber 376.24 mto base9 system

tep 11: Divide the quoent obtined trom step The
t tacbona
emainder obeained is the second LSB of the radit ns. Step Decima pat by
na icaio
umber Duiber. Step Decima to base conversion o nteger part by
(Refer Fig. Ex. 1223)
4 BE binary Quok Decimal Base Product amy
ep I Kepeal dv1SI00 Dy Dl quooent oecones zero, ie nagerp
qUucnt s oo longer diviable by . 9 576 LSB) racton

Shep
oo1oou 01001o0 9
9
6
7 Ked up MSB)
p rmaunaer obeained trom the dvision is the
Sp of t
(576% (7104
T S FEad from bonorn to top.
UEL 1.221
Step Is Decimal to base 9 conversidn of fracoonal pant by U.2 4 12
(1472 *
Octaqunt mbe G Dec 161 May 17.21M
(Refer Fig. E 1222)

al432)
1410.
into base 7. Decimal
fraction
Base Product Camy
pary
Thes(744=0 Ans.
ep: Decimal to base
1.22 DECIMAL NTO RADDXR TEoDo nieger part by 2 (MSB) o.12 0.48 bss)
cONVERSiON Base Quctent Reainder
(LSB) ATPE123
(03 (a.110%
e
P decmal uuber is caevened o radt r by Read ep
Sep Combine te aarwers obeained in Sarp
a yrand the tcuo pd te deci ASB)
Serp I

.
aep (151-1,aiuune,
b Decimal1o bse 7 coeveno ot tactional part by
7.
ce d byr, te m p dded by by 96 1.23 RADIX R TO DECIMAL
9 8.64 8 (LSB)
CONVERSION
ATB L1
Ease-Product
: (0.24)» = (02138,

MSE) Step 1 : Combine te answes oained in Sip I

ep E E
(57624)» (102138 Surp I1: Wrie te positical veigs ls eah dá.
a pat B
ed by áng UEL1.223MU-O. 1e. Dec. 16.1 Mark
Convert decimal sumber 15133 isto base 4 sysem.
StrpI1: Mhphy each digit
comespondings wig
a te pvea
to prodat
mbo agss
R Ar POsbona va
Step I: Decimal to base 4 conversion of iegT pt by
successive davision by 4.

7
(LS8)
SEAR Ventare
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SACHIV SHH Teaa
 Digital Logic & COA(MUSem. s bits of the
he numbers and A, and B, ae the least igificant
UEx 123.1 MU-O. 11a tMay 15. 2 Marks of Dumbers. 1he bdditon of the two numbers is done
as follows:
Module
Conyert (1212h into base 10 Ex. 124.1 EL. 124*
Step 1
A0d the LBSA anu g EC d
Perform the addition (1 100010+ 1010001)
Ana caTy as any, is lorwarded lo the next column.
Add the two binay numbers (101.10, and (0101.100)

Refer Fig, Ex. 123.1

A Ans.: Ans. :
y
3 Lob
number -Cary
Base From LSB

11:|2
A A A A mber I10 0 1, 0
Base 3
numbeE2 B 8
adklition ie.

addition of
1.1 0 1*10 o Nurnber 2 _T 0T00
Final Sum
Ag an B 0 0 100 Number 2

Step 11 : Add the bts A, and B, and cay from previous

Final Camy
90 01 1
0 01Sum
addiion. Record the sum as S and caTy C 1 any.
tx wogne Hiral sum Cany
Torwarded lo Bext CoNiTmn,
Tus, (100010+ 1010001) (10110011
Step N -Camy Thus, (1101.101),+(O101.100),(10011.001,
C C
Note Ex. 124.5
Inacokumn, every pair of 1's resufts in a camy that
a4) Solve

(0.0606/10 decimal equvalent Ans. is forwarded to the next higher bit column. 9 (1011011*(10010),= (?
Sun If the number of 1's that are to be added in (1o1101, + (UI001= (7%
ig Ex. 1.2 Step 111: Add the bits A, and B, and camy C, from previous a2 colurmn is odd then the sum bit s one (1) whllo
)
(o100100.1 100+ (11 1m10.011=(0
(121.2,=(16.666) addition. Record the sum as S, and cary 15 i)
the number of 1's to be added is even then the Ans.:
forwarded to the next rolum
H 1.24 BINARY ARITHMETIC y Sum bit is zero (O Cary
G EX. 1.24.2
we wilstudy the anithmetic operations bke additio. e inary anthmetic Number
suberaction, multiplication and division on binary nugmbers. A A
A o.u*o.oh*t2
B B, B, umber 2
Binary rithmetic is required for digital systems and in digital 8, ns.
s. S
S Final Sum o I011 0 1

As binary arithmetic comprises of two dugits 0 and , Sum

t
mucth simpk in comparison to decimal
aridhmetie. 5 Step IV: Add the bits A, and B, and cainy
hopeo T

addhuion. Record the sum as S and cary C Number2 Final Ca

a 124.1 Binary Addition Cary
Final Sum 0 1 00
Thas, (10110114*(10010 (101101
Table 1.24.1 shows the rules of binary addlition.
A A A Ag ) (101101}+(1000=(7
Table 1.24.1: Rules of blnary addition Camy
Cary
Lhus, 1.11+11011.01),= (10111.00),
Cary- S S S Sum
Ex. 1.24.3 T01
Pertormthe addition of given binany aumbers l000011+l10001
Lber 0
Exampk : Add (S9% and (3)jo

Ans.:
Number 2
*0 0
0 Final Sum
0 0.0
I 0
0(0011
Number

ne nni three case, there is no cary. The addation is

similar to the decimal addition. In the fourth case, the addition of
AA
Number 2
Final Sum
,
11 0
0 01
(0h le. Ue additaon resulis in sum
AA Thus, (101101,+(U101,= (0001
camy
0 0
and + B, B B B

ot binay umbes (A,A, A,

and B, are the most siga
Final

S+(n= (0w= (8)j0 Thus, (1000011), + (1110001), = (10110100%

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 NumO
Logia & cOA(MU Sem.8Como)
Drpal Digtal Logie& COA MU.Sem, 3.Comp)

i) (o10010.I100,* (11100100011=%
Example
Ex. 124.7 he remang
The remaining bits represeat the magnitude of the aumber.Module
Subtract (7)o-Sho" (0111h-(011h Perform (10101.100)%-(00111.00
(0) raa represcnt data in u
Perform column by column subtrconi irom LSB 127. The MSH bit is the sign bit.
Step I: to MSB using binary suMrcton nuies.
Ans. ange - I27 to +
Number 1 0100 010 0 1
100 Step p**I: Perform column by
wsine binary
column subraction from LSB t
subtraction nules. Example
Nunber 2
1110 010 00 SB
Fral Sum 0
10 1
0010 BoTTOW
Siga bit-
BOrO

-2
Number 2
Difference
Mumber
Number 2
1 Sinbi-OLIO|
Tbus, (01000100.1100)+(11100100.0111))= (100101001.0011)

&1242 Binary Subtraction anal Dierence 11 1 01

- Convert (- 124)jo lo its equivalent sign maghatade form.

The binay suburaction is same as decimal subtraction. (2) ns. :

Tabie 1.24.2 lists the rules of binany surection.

t (OtO1. from (0110), Fna
borow
Step T: To find the binary equivalent of te given number.
Remainder
Tabie 1.242 : Rnles of Binary Sabtraction olumn subtraction iom LSB dent
Sep* Thus, (10101.100,-(00111.00),= (001110.100),
o MSB using binary subtraction rukes. 24
LSB
H 1.25 REPRESENTATION OF SIGNED
MSB
2 6 LSB)
DorOW NUMBERS
Read up
ube 1
A binary number can be posiive or negative. The symbol
8 sed o"present pe0sidve numbers and the symbolis
e outputs at binary subiraction ane diterence and borrow.
E
In digital computers the sign of a binary number needs to be
DI
osder
onsider
hrsi case : B,=0, B, =0

secood caseiB, =0, 5, =

Final
borrow
For
represented using 0 and
representumg sugned number hete are two meus
(124
- (too),
MSB)

Dgt BB, We Cannot suberact (0-. (00D mpleient tom

(O10-(0101,
Therefore, we have to borow 2, ie, (10), as the base of
complement Step 11 To epresene lj
124.6 The number is negaive, we ill aki a sga bit T to the
DEs
ULgeneries
S 2.

(10, (}h = (0) iePefom (1011.010(0110.10 etmostbit of the nmbet.lHE

borrowI and diference -
&1.25.1 sign Magnitude Form
difereace1, boow Ans.
paurs
L i|olo-14
-Consider third case :B, 1,B,= =
epl Perom column by column subtracticon trom LSB
An n-Dt SIgnca oinay nunber compnSes O wO
Magnude
1-0 I ie. diference 1, borrow =0 sg Sign bit
D Dnay ubuduon nUes.
Consider fourth case:B, 1,B, LSB (ARDFig. Ex. 125.1-124 tn sigp-magnltude form
- Oie difcrence =0, bormow = 0 Refer Fig. 1
Representation of Signed
astepfollow euon for large umbers ar MSB bit/ a1.25.2
sign bit
Number
Numbers using 1's Complement
Ster I In the LSB column, start subtraction by subiracting or 2s Complement Method
rOw irom Uie bit in the upper
EnE 1O

For pertorng binary Nuburction, the digital compulers Use

D Positive
Step : With the help of binary subtraction rules perf
the subraction. 1f the bit in the upper row is less
10 1 0 1
Itbit 1. Negative number
bit=0,
T's and 2's compkment met
is the
Tbe main advantage of using complement method
n ue
Ee wEr row. TOWTom the (1A1Eig. 1.25.1 : n-bit signed binary number reduction in hardware and secondly, they allow the
ue
subtract
e sde The resut of
hus,
cTOW
(1011.010h-(0110.101), sgn bit = , the number s posituive
epresentation of ncgaive number
(00100.101),
Step 1E Repeat step I1 for every columa til the MSB bit. T sagn bit , he numDSE

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 Number y Digital Logie & COA (MSem.scom
Number Sstens
Logic& cOAMIUSem
Digtol number from 2. od
ubiractiog the pven n-bit
a Binary coenplement of 10107 Res
Example To find 2's Ex. 1.25.3
125.2(A) 1's Complement of
:

a medhod.
Number (Refer Fig. 1.25.3) Perfom (S)ho-(2/ho using 's complement

DEL ot the nmber Le. a 0is changed re

gven number
-LOoD0CD Ans.
Step I: Obtain l's compkement of subtrabend.

2 (0010%
's complement of resut

er (kefer Fig. 1.25.2)

p I or (410 (U0%
xample T's compienent nAmFy Ez 1254
*
Step I: Add (5)%, to's complement of (2)o
Gven rumbr
oob0 od1
ThS,
24 »e»
tep IV x 1.25.5
Zs bomplement using one's complement
Ue nunc T's complement of (2)j0 0 Suberact (33)o-(4j
qANFig.12
Amg
125:l's complenmest of a number T
Ans.
It is called as l's complenment because if we subtract the 1.25.3 Binary Subtraction using Step I: Obtain 1's complkment of (44)0
Complement Method
pvet
picnirng
Bunoet rvm
the mambe.
o get the resul, tt 1s ame

compleent method, we add

End around cary 0100
T's complement of (4)ja o0
in binary subaaction using I's 9Step l: Add canry to the resulit obtancd m siep
i 1. 2 to the minuend. If the 9Step I: Add (33) to the l's complement ot (e%o
complement of the subrahend
Obain the 1's compement of the following numbers.
I a cary u is added to the L5B
adition results in
around camy)
Ans.: (Refer Fig Ex. 125.2(a) and (6)) or ie mumber to gel haal
1

sult If the MsB t is u, tien te 1(End

result is positive and in true bunay lor Sep :Check
ue
0 01 1 Answer is postve and in

.
Gven number MSB binary lom +
f the MSB bit is 1, then the resulr is negaive and in 1's
complement df
compiement orm. Conven t o ue inuy l0 oyng 3 's j4jia
menoDoo
Steps to be followed for binar7 sublraction using 1's Ex. 1.25.4
0AFig, Ex. L25.2() MS8
pieentare as followS Perform (2)jo-(S)% usingl's complement method.
MSB= I. Hence, the answer is neganve
Gvon nuber
00 Sepl Dbtain the l's complement of the subtrahend. Ans.: tom.
and in T's compiement

comglenent
o StepII: Add minuend to the l's complement of subtrahend
Step I: To obtain 1's complement of the subtrahend.

T's complement of (5)%o

o (O101,
(1010)
Step l: Take ls complement ot the EIE
ans wer in rue binary form.

Result: 1
0100
to 0odan the

(APlg. Ex. 1.25.20) sUng ruies oT Dinary addituon

I's complement:
Step 11 Add
(toT's completen or (9/jo To
a 1.25.2(8) 2s Complement of a Binary
NUmber
Step 11[i
f cayy is 1, then add it to LSB to get the result or
Thus
subiraetio.
?'s complement arithmeic is used in compulens for handlin
urmiben. Instead of using separate cireuits for EX. 1255

dders
suburaction, ony adding circuits, ie.,
are used. 1he compiement o he suberaieDd is added
P*
n
posive
DB, then resut obtained in step
nd un true binary form. Iif
is
II Result:
T0 0
s
Find tbe one's complement and two complement ot (o

io the miauend raiher than subtracting the

number
the MSB= 1, the
esur oblained in step 1 is negative and in 1's Ans.:
the 2's complement of a binary number can be obained MSB StepI: To obain 1's complement of (57)h
by: pun10rt.
0) Ading 1 to tie LSB of 1's complement ot that
1ake ts T's complement o Hence, the answer is negative and in 1ls
(7)h0 (111001),
number. onvert The MSB 1.
it to urue blnary lom omplk T's complement of (57)- (000110
ompeetls complenmest+1

1B,
d
wnie
a
ooWn eaxch bit up to and
E Cpiement the
Dep u 1ake
s. complement or the result to oban
y Tom.
the

remaining bie
e ExL 1234)
(Refer Fig.

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 Lopic & cOA MUSem.2.Como) Number Systems
Diotal
Lojic & COA JMU-Sem. scoTD NuTber S
Diotal
Quoient Remander
Strp 1: To find 2's coupkment of (57h Base
UEx 125.8 MU-O. 1CL May 15.4 Marks StepN: Compue T's complent to te resut is trueodnle
brnary fom
LSB) Perfarm the subracuon Daho ojag" Gpieme
I's complemeat of (67ho 0001T0 method. cplene of resat: 0 001I00
Add (h ead up Ans.: Ad
cquvaieet of ($2)ho and (65)
T's complement of (57)j0 Strp I: To ind the binay
0001IT| Remainder
Thus, 2's Complement of (57)u (0011 seQuoticnt
0
bus. (53h%-(eS"D»
1.25.4 Binary Subtraction using 22s (MSB) (LSB) UExL 1.25.9
U-0. 11b) Dec. 13. 25 Marks
Complement Method Subeaect the foBoning smng 2s complene (-.
620 (0B00)
Ans
aumbers.
Step I: Fiad te hiaary cquivakent of (1, **Ch
he minuend etbod, we add
cary
is geoerated from the addiion, alw ays ignore the carry. I MSB)

eMSB
andm
t uuE Diny
ot he reult
Ton. ir
is zero then the
e
resut is
or Ue
positive
resu
(52)%%" (110100 Base Quroret Remandr
iSB Dir 5
s Compleent ot (2ho0 1IIT 2 22
Base Quotient Remanoer

0an he result m ue binary form, tuake the 2's 2 65

Rad
Steps to be follow Step II: Add 27)% to 2's complement of (32h%o
Step I: Add minuend to the 2s complemet o
subirahend.
Read op
ep u* nre
a
can, any. " MSB = 0, result is pouove
00000
Ln rebinary form Step l: To find te 2'scenkc of (Ca
N
Sirp MSB 1, resuk is negative and in 2 MSB)
o enttom compute 2s complement u
(65a(100ODI
Step I1: To obtaun 2s complieen or (ohe
MSB 1ndicaies that resull is negabve and in 2's
Ex. 1.25.7
compiement lorm.
(6h 0 0 0 001
Perform the subuaction using 2's complement
Step IV: Take 2's complement of the result.L T's complement of (65)%a 0 1 1It0
's complement of ha-01 010

Ans.
t34/0
Add
Sep u: Aad()ao te
s coeieni dla
Siep I: Comvert the minuend and subrahend to binary. Result:1I101 2's complement of (63)%a
01TT1 Cry
Ts compiement Add T* 0
u emauDdkr
Step I11 : Add ($2),tao the 2'% complkment ot (a5a

o 0 0OT Camy
(B)
Final Result:
h OO R 0
01 0
Read up

2
2s complement of (65)ja01
IIL No Camy MSB

(MSB)
Resul
MSB1, reul s ege
d ns oenes
SASB = 1, esult is neganve and in 2's compkement foem
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 NunierO
Digtal Logic & COA (MUSem.
3comp= Digital Logic & COA (MSem.scomp -39
Modale
of the result Step 1: Add (62) to 2s comple nent ol 9ho Bae QuKient Kemainoer
Sep IV: Take 2s complement

Result Complemet of Resat: 0 01 0 01

Cary s
COnpiement of Result : 0T01 0
(60 0 To Read up -
Add
Final Kesult: Dho
2's complement of (99)0
0 01 101 Thas,
Result-0 01 0 g 3 compkni method

UEx 125.1o MU-O. 10, May 15.4 Marks

76%(1001100
UEx125.12 MU.O 1O. May 18,4 Marks
Perfoma binay subtraction using 23 compliement 10t 0-ho o caTy MSB To oblun l's compiement and 2's complement
o Subratasing 1'sd7snehod:(15)»-2o
and (99)0
Step 11:
Ans.
MSB1, result is negaive and in2's compliement
Ans. (76)h01 001 0 0
I: To obain the binary equvalent of (15)% and (21)h0
form Step
Step I: Find the binary equivalent ot (62)e and (90

Base Quotient mainder

Step I: Comvert the mswer in tre bnay

2s compiemcnl ot the resu

form by taking
1's complement of (76) 0110 0 1 Base Quoocnt KE

6 Add 2
Result10IIOI 2 10 (SB)
(LSB)
2 complement of (76)a
0110 00
T's compkement of result 0To T0 Step I1: Add (56)hoto l's complcment of (76)h0
ary Reai up

Final Result0100101 -(37%0

(62a-(9)ha -37)» T's complement of (76)%o*0
1 0 01 (SB
0T 0I1|
1

UEL. 125.11 MU-O. 1C) May 15. 4 Marks Result0 2h(1010

Subtract using 1's and 25complement meto Step : To tind te Ts a 2* cmpienitE OrLE)»
MSB) MSE
(62)(110 CS6)0-76)ho MSB and in 1's complement
1,1
Ans.: form. To get result in true binary formn, take 1's complement of the 01 0I0
Base Quodient Remainde
result 's compkement of (2ha:
Step I To abiain the binary eguivalent ot (55)%0 and (7%%a
es
299 e emanoer
l's complement of result : D0T000 s0 Add1

's complement of (2 ho 0 0

(56%-70) - -20) using l's compkment method.

m compiement o t41)o
Add (lo '
:
Sep
Step IV: Add (56)to 2's complement of (76)
Read up
eo up

(56) 0
1 000
->
(110001)h
1(MSB) s COmpicncnl or Lojo 0 I's conplement of (2)o
(ho esu Resut 0
9Step I1: To find 2's complement of (

= cany
yMS8 NO

s compiement or
()a00TTo0 Since, MSB 1, result is negative and in compei Since MSH 1, result is negative and in l's complement

Add (o
tom. to obtain the result in true binary Ton, ukE4
3oue form Take 1's coanplement of the result to oa e
binary form.
2's complement ot
(haO01 4SACHIN SiAH Testure
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 Dinital Logie & COA (MU-$em 3.Comp) (1-40) drioe slems umber ys
n s cquivalent odule
Step 11 To
repreet( ho ti
Ex. 127.1
complement of Result :
0 0TT0 *(0 nagnitude, Ts compieen ald d
nplemem ) 101.01X107 Perform the octal akdition af (5), +(b
's
Thus Ans.
1's compkement method. complemeat
(15)-(21),= (-, uing
magnitude's complement2's
umbergni resentationrepresentation Sep I: Add the umbers by asumung the
m oe deia
Step 1V Add (15) to 2% complement of2Dhe epresentation
1010D10 10100111 * 0)*(6)*0
Cary 1000 Step D: The result is preaur than 8.
3 and
15 from the resut (l-(8)o
1 H BINARY MULTIPLICATIODN we wil subtract
1 8
1.26
te camy *
compement al (2)he
Zs '0 1 0 1 1 0 0
Hesul
The nules of binary mulaplication art 1 00 0
0) 0x0=0 (8%
() Oxl= a1.26.1 Binary Division
Cary K
MS8 (i) 1
x0=0 division are
he rules of binary
:

(iv) 1 xl=l 0+1 =0 (i) 1+1

S1, resul is negatve and in 2's complement
n e esul true binay fom, take the 2's EX. 128.1

the folowing binary muliplication.

Ex. 126
UEx. 1272 MU-O. 100.
Perform the lollawing opernions
May 16.2 Marks
witbhout changing he base.
Perfon Perform the following binary division.
Reult: 1 10 1
0
x0101 1001.001 x 1010.101
1011 () () 1001 + 0 (2)
(1.)> +01% 0614,+037
(i) 101.01 xl1.01 Ans.:
1100+1
wheDevET columa aduiDon is gealcr than o eyu o ,
T's complement of Result; 0 01 0 T
Ans. Ans. subuact8 and geerae
x0101
1011x 1001+ (2) (11.11%+(11%
2's complement of Resuk :
DO1 h0

1 4a-6},
UEx. 1.25.13 MU-O. 1C.Dec, 18.4 Marks
sing 2's complement method 11.11 Camy

11
vE - he to is
and 2's complement
equivalecnt siga magninade 1's complement
orm.
o0010
1
o0 11
uT8 and generale cary

Ans. O00 aTy 23 3Result

Stepi To covert (89%into binauy by successive divislon
101+10= 100.1 11.1+11= 1.01 014,+(737 (125%
ase Remainder
C (0 1001.001 x 1010.101 1100 +11 a1.27.2 Octal Subtraction
same as decimal or binary subinctcn
(SB
10
01 001 -Octal suberaction is
can also be done by converUDg he oxa
xIO10101 ""/_ 1
Octal subtrctoa

une

Read up
O0 10 01 penorm suburac.
a
Octal subtraction can ako be done using 7'a complement
00.0 00
ll = 100 8s compkement method

0000 0 00. a 1.27.3 Octal Subtraction using 7'S

H 1.27 OCTAL ARITHMETIC
0010 01 Complement Method
(89)0=(1011001) 1.27.1 Octal Addition e s compieentoan ocal number s 0nainco Dy

7,
dhgit lrom
-890(011001, Octal addition is same us the decimal or binary addition. uD ng h
, while performung the addituon, a camy s The sucps for octal subtraction using 7s compiement neuod

Sign bit
0 0 0 1 IT101 u E sum CxCeeds
ac asfollows
eneruled.
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ASACUY SHI Vnture
 noer Sysems
Digital Logic & COA (MU-Sem. 3-Como) (1-42)
Add camy to the LSB bit of the sum. Digital Logic & COA (MU-Sem 3-Comp) Number Systems
p ind s compic menl or Uhe
subtribeno Step ll:
Ex. 1274 Sp ll :
As camy is grnerated, result is poviove and true
camy.
lodule
Siep ll: AdKI WO numo Use 8's complement method to compute (360), - 715 d

camy, resut A Ans.: Res-A, -(153, (70%

Step
Ill: f the addition generales the 4E
4s9
Step 1 To find 8's complement of the subtrahend
a 1.27.5 Octal Mutiplication
u uon does hox generale caTy. (659-(7% 77
UEx 1276 Dec. 13.25 Marks
kn t ei neeuhive and T
in (i) (25)%-( U-0. 20
complement lorm. Perform the foDowing directy without comverting to amy base.
compiement of subtrabendd
7s complement of the subtrnhend.
Step1: hd ) (63%us
E 1273
Ans.:
Perfom the octal suberaction of 8s complement of (75%
063
73-(65), (m) (655%-( Step Add the two octal umbers.
04 7scomplemeni ot (is%
()25-7 Slep l : Add the two octal umbers.
Ans. 3

0 7-(6
*04
Siepl Find 7s complcment of suburahend. R (: column addition is geater than 8,
12
column addibon is greater than 8, ubtraict B and generate carry) 2 Column additicon is greater than 8.
29
suburact 8 and generale camy) utretš and generaie cam
7 complemeni of (65), Result
12 31
Sep I1:Add the two octal numbes
Add camy to LSB bii of sum
Step 1 As there no carry. esu negae and in 7 result. *x2-(154,
*Step 1i cOmpiernen
o.
e Deeu tod the 7
compiement ot the resul, lo get answer in tre
777 UEx. 127.7 Mu-0 1a May 14, 25 Marks
443 Perform the folewing witheut ccaverting mto other
s complement afr (69)% compicmentor the resull.
bse
17 7,C
335 8'scomplemenit of the result Ans
arry 00),-(715,=-335,
o5 KESu

Add carty lo LsB Dl or sum Ex.1.27.5

Result Use 8s complement method to compule
1.27.4 Octal Subtraction using 8's (245%-(S3h 10
Ans.
*(73%-(a5, (00) Complement Method
Sep1:To hind 8's complement of (153)% 34
(09 be 8s complenent of an octal number oblaunecd by adking
(653-(177% is
lo he rs complement of the octal number
Resuk
24
StepI: Find T's complement of the subtrahend he steps lor perfomming octal subiraction using s conplenent of (135%
method ure: We find the muliple ckosest to each digit. for 28 the closest
iect ,o
StepI: Find the Bs complement of the subtrahend.
623 8s complemeni of (1S3), x
camythe ver eu g
subiret3 by * get4 and

600 74complement of (177% Step 1t Add the two octal number. 8x4 32.
9Step 11 :
Step Il: Add the two octal numbers. by 32 lo get 2
phas previous eary 3 to get 5 and cary 4 over
Add the two octal nuimbers
65 to third dagi
's comple meni of 600 p Cay produced, it indicates that the resuh
For 10 the cosest mulupk is 8 x i = 8, so suberact 8 to get 2
6 00 ue Tm.
plus previous camy 4 o gt 6 and cary over I to the MSB
1253 PDot LIsCUrU the camy.
produced, the result is negatve
I cany Column addition is
Is greater und m qual or greater than 8,
00on Dhan &
camy) complcment lorm. Find the 8's complement ot Subiract 8 or generate camy) (S7,x(4 (1654,
amy14 5 3 Result generale Esn o eapress the resut in true Result
fom
ard camy
Discard camy T
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ASACHY SHAH Ven
 (144) Number Sy
Drgitl Lc& cOA MUSem 30m) Digital Logic & COA MASem.sicomo)
HEXADECIMAL ARITHMETIC UEL. 128.3 MU-0. 1D) Dec. 15.2 Marks Number Sysens
1.28
Perform bexadecimal arithmetic operation; DADA+ BABA
Ans Step I1: As cary is geoerated, resmlt is posai ve and in
ef n rue. Modale
ue.
Add cary to LSB dipit
a1.28.1 Hexadecimal Addition Ans
3
- Hexadecimal asdition is similar to decimal, binary and octal ACA,00%o3ho aTy
addoa BABA (11ho (10)ho (11ho (10/10 Result 5 9

..
e Sun ekCEdS Le.ho a Cny 5 generled tor each
any
er
24so (20)10 (24)%o (20)%0 Subtrac
6 and
9Resut
dgt posbon
(16)10
9enerate cary) a 1.28.3 Hexadeclmal subiractlon using
.128.1 (16ho1010 15's complement Ex.1.
128.8

Perfom the bexadecimal additdon of Camy

19 5 94 Resu The 1S's complement
Dse 15's complemeni method to find
(69B)-(C14)
ol a heandecimal oumber is obtained by
uDUng ech ngit from 15. Ans.:

Ans.: (DACAa + (8 A BA 99j ep ero10wed 0r hexadecimal subtraction using p o td 13 3 compikment of (C14ja

Step I: 6+%(0)%0 15 15
&1.28.2 Hexadecimal Subtraction Step 1: Fina the 19S conmpiCment or de suouranend.
As the result is gealer, than 1b, we nee peo
modificationas In the direct subtraction of hexadeceimal nunbe
munuend i5 iless than the subtrabe nd we borrow (6) and Siep u Add ie two hexadecimal numbers
Subrct (10)j0 trom the result :
(17ho-(l6)}0 (%0 returm carry 3E B compietoent or suberaneDa

eDcsie camy P cany 5 gcnerated in the addition, the Step : Add the two hetaecimal oumber
128.4 aa
resalt is
true Torm. Add cany to the LSB
Step I Suberact (73ha-(1Ch
posDe
of
ne su Cany 15 not generaled in the addition, the
Ans.
(19h0
ESut
nd
ea
scompieene
a In

of the
13s complement
result 1o
form
get the result
SDE *0» (04ho (0
8 3

C(12ho Ex. 128.7

sum
Borow peaier
Compute the hexadecimal subtraction of
(CZA)j6-(921)
UEx. 1.28.2 8sun olo toha 16, suburact 16 and
AU-O. 19) Dec. 14,2 Marks Ans.:
A 6
Add (DDCC and(BBAA) Step I: To find 15's complement of the subunahend
Sp A cany s generaled, result 1s Degative and
Ane.i in 13s
.128.5 onp k mett om ind 139 complement of the
DDCC.(13ha (13)h0 (12%0 (12/h0 Perform (8CS»-A2B%
BBAA- (11)10 (11)10 (10)%0 (10)10
Ans.
u grealer Without coaverting to any other base. 3 Compkement of subtrahend
any (4ho (24}%0 (22)10 (22h0 subtrac 16 and Step 11i Add the two lexadecimal number
Carry) 19he (21)h0
(16%0 (1ho (16h0 (16ho ete BC5 (1h0 (12ho (Sho
C2A 02)10 (02)» (100
S 9 Resuk
canry19 6DE 00ho 5%o p
7 6 Resuit BZB* (02%o (11}10
0ho (698-(CiPA%%(-S79)%
DOnow

(DDCCh+(8 BAAu=(19976)4 1 9 A Resut a 1.28.4 Hexadeclmal subtraçtlon using

b)o (16) Breaier than 16s complement

(BCS-A2Bh = (19A)a l6, suberact 16 and

EX. 1.28.6
3 0 8 generule amy) e
icmpienet o1 a hetakecima mumber is obtained by

Perform The steps the 16s

edm e 1olowing darectly without converting ot follous.
ay Opicaent method are as
base:(9-(80)
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 Digital Logic & COA (MU-Sem. 3Comp)
EX. 1.28.10
StepI: Find the 16's complement of the subirahend. subtraction of (69B)%6-(C14)
Perform the hexadecimal

Ans.
Add the two bexadecimal numbers. subtrahend.
Step I:
StepI: Find 16's complement of

15
it is discarded.
Slep l: cary is generated from the resul,

f cary is not generated, it indicates that result

is C B 15s complement of (CI4)6
3 E

Degative and in 16s complement form. Find 16's

Add
compiement of the result, 16scomplement of (C14)6
E C
3
Ex. 1 8.9 Add hexadecimal numbers.
Step 11:
Perform the hexadecimal subtraction of (D23)%-(A13% using 16s
(06)10 (09)%0 (D%o
complementmethod.
69B
Ans. 3EC+(05)jo (14)jo 4jo
Step I: To obain 16s complement of (A13)r
(09)J0(25)e (23)1o
15
(1610
0o (sum16, is greater
A 3 than suhtract 16

5. EC 1Ss complement of (A15) A nd generate cary)

Add
No cary
16s complement of (A13h
SE D generated
As no camy is generated result is ncgatve and in
Step II: Add the two hexadecimal numbers. Step 111:
105 complement irom. Find TbS
complement of
in trnue form.
D23 (13)o (02)jo (03)ho the result, to obtain the result

SED 4 (13)0
(09)o_
Camry
compiement ol result
(18)0(16ho
8 S
( sum is greater than Add 1

(16)1o complement of result

(16)0 (16)0
16s
e camy)
Discard cary 0 (69B)4-(CI4)%=- 57)%

Step 11: As carry is generated form adition, the resul, s

positive and in true form discard cary.

(O23-(AI3) = (310

..Chapter Ends
DptaLogic& CoA
MSen 3o Codes
24.2 Digtl Logic& cOA MUSem. 3-Comp)
Gray Code to Binary code Comversion Codes
A3 Birary to uray obe Onversioesa *
s

***** 2
H 2.1 BINARY CODES Module
evouS OnivertSIy Paper Questions

UEx. 2.4.1 (MU a. 1b), May 16, 2 Marks). nt s********

:.211What is a code ? whet are binary codes ? Give the advantages of binan codes
**********************
****

***********************
A Ans.:
UE. 24.2 (MU -Q.1@). May 14, 1 Merk) ******************************** When the data or infomation is coded , th»
e group of symbos. The process of
uEL. 243 (MU-a. 1e), May 14,1 Mark). coding these symbols is called as encoding the data
The group of synbols is caled as a code.
2.5 ASC CODE The digtal data 15 represenied, stored and transmitued in the form af a stream (growp) of binary 0's and
Is aso calca As Dunaly l's. This group of binay bis
2.6 Eror Detecdng and comcung odes. The binary codes can be represenied by uhe number, ettes at the
alphabts and peca c
2.6.1 Parity Checking The binary codes are classibed as numenc and alpbanumeric
************nmmeuaetanasassanesnsbuusssas atsaasaaksaasneaassassuss asesamsampummennnmeetawesaa**
E*T9 codes. The numenc codes represent nurmbes.
M E0. even ne alphanumenc codes epresent alphabets and characders.
dS paniy Pariy and O00
T~.panY
m EEaenaaaasenanu"

&0 Ow o0eS paniy checKng delect errors? what are ts drawbacks?

t u C"9 a 2.1.1 Advantages of Binary Codes

.
6.

2.6.3
anming

Eplain
coo8.
with example how hamming code
Prove that hamming code is an eror dotecting and comecting
s usetul for detectng and comectng
****
errors.
1.

3.
Binary codes are suitable for the compuler applications.

Binary codes use only O ad

1
T n sysiems.
code. *y csy.
MU 4. he digital circuis use "
binary codes for their analysis and design
O. 2/b) May 14 10 1Marks
Previous University Paper Questions 2.1.2 Classification of Binary Codes
**************.
16), Dec. 17,5 Mark) . 2.1.2Explain **

UEX. 2.6.1 (MU -a. the classification of binary codes

**********mae,

UEx. 2.6.2 (MU-Q.26), Dec. a. 1(c), May 17, 2 Marka).-

15, OR plain in bner welghtea ana non-weghtea coaes wrEN one cxape eac
UER. 2.6.3 (MU -Q. 1(e), May 15, a. 1(d), May 16, 2 Marks).. Dec. 15.2 Marks
********-------**.-*------ --------- OO,
uEX. 2.6.4 (MU-a.1(e), May 17, 2 Ans.
Marks).
UEx. 2.6.5 (MU-a. 1(e), May ebinary codes are classified as

JEx. 2.6.6 (MU-O. 1b), Dec. 18,4 Marks)

UEx. 2.6.7 MU-0
18, 2 Marks)
.. ****** E°122
Sinary

1eL Dec. 19.4 Marks WeighMed on-weighted Renecive Sequen Jphanumeric Emor etecing
codes COOS ung cooes

Chapter ACC
Ends... inary
Gra FBCDIc .Hammin

21
2421

3S2
5211
5311
5421

742
842
.Clasihcation Binary Codes

A SACHIY SRUR Vonnr

Teeh-Nee Publications here duthars inpire ovala
Tech-Nee Publieations ere Authors inpire ianevatioe ASACHIN SILun Veata
 Digitl Logic &COA (MU.Sem. 3-Comg Codes
Drgital Logic & COAIMsem.scomp (2-5)
Extended Binary Coded Decna uneehange Cod
2
1. Welghhed codes (EBCDIC) E. 22.1 Ex. 2 nle
Add (24) and (15ho is BCD
Nelphtrd codes are the codes

e
thal obey posibonalwegs
Wrghied onde every dagit
positdon of the e bit Binay
ASCu code is a 7-bil code
Co

whereas EBCDIC is an 8-bit code

Comvert the following
(124)% hucD? Ans. 24 0010 0100
eapocce weagnc
codc s more
commonly uscd woridwide
while
8, 4, 2 or Ans.
Dnay codes every digit bas weight
a A 18 0001 1000
.ei
For example, in decimal code, il numer tncn welg EBCDIC 5 Used primanly
in large IEM compuiters.
(124 (0001 0010 0100)%c

of 4 is 100. wepieo
4 0017 100 Invald BCD
conreeung cooe
es 1,
ihted
codes.
242l nd S211 are weighted codes.
6. ETor detecung and a 22.1 BCD Addition dd6

detection and corection are called 0100 0010 Valid BCD resut
The codes that allow error The steps are followed to perform BCD addition:
2 Non-wdghted codes correrti
c OEng and correcting codes.
md
Step1:Add the two BCD numbers. 4 2
-Non-weighod codes ac codes in wtich posidional weights emor delecting
Hamming code is the mosty commonly used Step 2: sum is equal to or less than 9 (1001), R is a
ae gned to evEry dgt posinon, Le, very digit fthe
valid BCD number. (20,+(13)
va and coieeangc
positioa wthin the namber is not assigd de
Step 3: If the sum is greater than y. or cay
y ws ae ne no-weghied codes.
H 2.2 BCD CODE BcD.
a 2.2.2 BCD Subtraction Using 9's

Reñective Codes
waud Complement Method
code cach decimal digit is represented by
a 4-bit Step A0
nthzs d the Following are the steps to be performed for BCD subtractio
A code is reflective if the code is self complementing. ie. the binay mumber
cany to the next digit.
code for 9 is the coplcneot the code for 0, the code for express each of the decirma dagis w a
8is2. BCD is a way to
UEx. 2.2.2
the code for 5is MU-0. 1e). Dec. 14.2 arkS Fid the 9s complement of the negative aumber.
.
I

he code for 6 is the complement for D, with foar bits we can represent sixteen numbers Add (5Da and (26)% in BCD
Slep Using BCD akdition, add the two umbers.
e compliemet tor (0000to 1111)
Ans. Siep ill cary is produced, add camy o the result, ebe
BD, >*41 BLD and EACES de at enieceuve4. But in BCD code only first ten of these are used (0000 to fnd the s Compicneac
codes.
00. Camy
8421 is not areflectuve co to Tl are
S. Tbe rermaining six code combuaations 1.e. 010
0111 2.2.3 BCD Subtraction Using 10's
Sequentlal Codes
0. aso caled as 8421 code because the weights of the
101 Complement Method
a sguenta codes. cvery succesive code is one binay 4 bits are8+2-1 trom leftiMSB) to nght (LSB). 0111 1101 Invalid BCO numbe The steps to be folkowed for performing BCD subrction

unan is previus CcoOE

pulatios of data 8421 BCD and
Table 2.2.1 shows 84-2-1 BCD code.
O10 Add5
sing
Sten I. the of
Excess-3 are seguential codes
Table 2.2.1: 8421 BCD code
esut O00 o011 Valid BcD resuit number. The 10's complemeat is
n ompicnent ot number and axlding '(1)'
lphanumenc eooe Decimal Binary code 8Fig, Ex. 22.2 .
A binary dugpt epresents only two numbers 0 and
digit Step : Using BCD unbon, aki ue tw
DD
1. For (57)(26) (8) in BCD Ep u: Detemnes the 1u's complement of the number, if
o aOm betwen wo computers, we roquire the two
UEx. 22.3 MU-0. 1e). May 17.2 Marks cary is not generaied añer BCD akiion. If carry
gits along wih the ietdicrs and other symbols.
Add (T and (6)h%tn BcD.
Comuter manpulates 00010|00
both nuimbers and symbols.
0 Ans. a 2.2.4 Advantages of BCD Codes
he programs writden by computer usen are in the lorm o
characters ie.a set of symbeols consiss otees, auga It is similar to decimal system.
various special characters, such as coes 1 we need oniy the binary equvale ot ot decimal numbers O to
numbens and alphabetie
consist both numbers phabetic chareiens are h d 000010
alphanumeric codes.
The following three alphanuimenc codes ae very comony
1101 Invalid BCD number 2.2.5 Disadvantages of BCD Codes
used for the data represeaano
0110A0d
The addition and suberac tioa of BCD nuimbers bave different
.Amencan Sundard Code for Infomation
9go valid BCD resuit
Interchange
ASCI) The BCD aridhmetie is litle more complicated.
pBl. Ex. 223 3 BCD aeeds more number of bits than binary to represeat the
. decimal number. So BCD is les eficient thanbinar
(7+6)=(1J), in BCD
Teeh-Mee Publieations bere Autborn ianpire inaevation
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SACHLNSILAH Vestare SACY
 Ex.
EL 22.5 Ohtain excess-3 code
for (25)10 Step I: Complement the subtrahend.
*clmal2l code
4
bit binary code Gray code O
Convert the docimal number 25 into BCD forma. Add the complemented subtrnen
Sepa* B.
Ans. 0. Reult is poritive. Add er
Ans.
(25) » - (O10 0101) 0 acD
carry. If cuy= 0, Result is negative. Subtract 3 or
(25h(0010 010)co
234 MU-o. 10. Dec. 14, 1 Mark add 1
101 and ake i's complement of the result

H 2.3 EXCESS 3 CODE decimal mumber 29 into Excess 3 code. Ex.T Subtract9-
--- -** -Kpreient the 0 09 in XS-3
Q. 2.3.1 Write a note on Excess-3 code Ans. :
Complement of 4 in XS-3.

..
(29)a= (0010100T acn"(001 00
May 15, 1 Mar
UEx. 2.3.5 MU-O. 16),
Ans.
he EACESS-J Code is also called as XS-3 code. Represent (52)% into excess-3 code. +00IT Add
10
Ans.
EMCEsS-3 C0e words are obuned trom the 8421 BCD CD(O0D 0r01ee-
0
wrs ading (00ITh or (3)uo to each code word in
a 23.1 Excess 3 Addition 0 0 0 Sin XS-3=Result 2 00
The excess-3 codes are obtained as follows
addition are as foilows: o
Decimal Number 8421 BCD
Ihe steps to be performed for XS-3
Add two XS-3 numbers.
Ex. 2 Subtract4 -
14
LL5
|| o|o|
o
EXOESS Stepl:
(1101)
C011
Step 11: cany 0, subtruct 0011 (33) or add
Table 2.3.1 shows Excess-3 codes to represent le the sum. If cary=
1, add 0011 (3) to the sum. *
0 Complement of 9 in XS-3. a 2.4.1 Uses of Gray CodeP
decimal digit Ex. 1 A 9 and 4 10 1 0 No cany
Q 2+.2****Explain uses of gray code.
abie z51CesScode
Deciinal BCD Excess 3
0 Subtract 3 or Add 13
-- ----. Dec. 14.4 Marks
umber AS 3 Complement the result
Ans.:
AS=3
4In )in XS in xS-3 0gray coo s ued in the tranmission of dgtal signals as
1
000I 0
l Result of additio
3 as cary is 1
H 2.4 GRAY CODE anple-masuring devices
Add Write note on
Ue of the gay code almo

0 0 0 0 0Excess-3 for 13 Q. 24.1 rau code eliminaies the possibiliy of the angle misread
The gray code is used for labelling the axes of Karnaugh

0
Add 2 and 4.
--.00.6
Ans.
1505 Manksl maps. graphical technique used for mininization of Boolean

0 0
1

Excess 3
5 ue non-wegned co
expressions.
nc c o gray code o adress program memory in
0 for 2
1S noc anuhnetic code. Le. there arc no specific weights compulen munimizes power cosumpaon.
assigned to the bit position. Gray codes are very uetul generalung agontms.
L |o|o|i|T| lt has a very special
in

code.
IT0 0 Kesult of addition
c ume the decimal number is incremented As only one bit
gray coe code is called as a unit
di
unit distance
4.2 * Gray Code
Gray Code to
Conversion
to Binary Code
exces-3 Subiract 3 as cary as
code. The
Ans.:
gnore
uny
Gay code canaot be nsot
cannot be used for d
E anthmetc operali0a. Step 1: Start with the most significant bit (MSB) of the
0 0 Excess 9 1or 6
gray
1

(340h (001101000000) cD= (0110 0i11 0011%m code number.

able 2.4.l : Gray code
Step II: The second most significant bit, ir
2.32 Decimal 8421 code 4 bie binary code the MSA f
a Gray code aumber is obtained by XORing
2.3.2 Excess 3 Subtraction
Obtain cxces-3 code for (428)w Dnaiy number to the second MSB in the Gray code
To pertorm Excess 3 subiraction
,BB,B, G,G,GG, umber.
Ans.: erformed.
folowing are dhe sieps
Sep 111: The third MSB in the binary number is obtained by
(425) (0100 0010 100) sco (O1101011011a
ng
the third MSB
he second MSB in the binary number to
in the Gny code number.
TehNon Pruhliest inne am iam iaata t
 Codes
(2-8)
Digital Loglc & COA
MS ASCir Code Module
IY The proces continues until
we obtain dhe LSH of UEx. 24.2 MU-O. 10. May 14,
1 Mark
-It is a seven-bit coke in which the decimal digits are
is a
Alphabet 7-t
Siep
(20) Unto gmy code. represented by he BcD toie precedkd by 011. As it
the binaiy hun Kepresent
7-bit code, it represenis 2 I28 1ymbols,
Example :
Convert gruy code 1011 to binary
An8. ASCH Code
Tabie 2.5.1 i

Gray code ep To eapres (29)%0 into binary

BANCuoue Kemaunocr Alphabet 7-bit ASCIT Code
Binary code:
1 (S5

0010
Thus ,
((011gr(1101

a 24.3 Binary to Gray Code Converslon

Mep tart with the most sugnutcant bit (MSB) of the

ioary number. The MSB of dhe gray code Seplt: Convert binary lo grey
equivalent is the same as the MSB of the given Binary code : 100 0
binary number.
19 ***
0
uray code: 1

Step I1: The second most significant bit. udjacent the MS,
Thus (1101% = (01
n cnd MSB of the binary
Dumber
(29 (1101=(10011)
that is if the MSB and the bit adjacent to it are both
Tthen the coTEsponding gay code bit would beUEN, 24.3 1U :0.10, Nay 14,1 Mark
code.
Keprtent (2h% into Gny
Sep 1: he
xon
thir
b.
o 5gutcant o
n ie grny cooe numDer 15 o0tined
cn Ans.
1 1101
by XORing the second MSB and the third MSB in StepI: Toexpress (52)%a indo binay.
Bass Quotient Remainder
the binary number. 2.6 ERROR DETECTING AND
Step IV The process coetinues undil we obtain the LSB of cORRECTING CODES
gny code.
Example convert 1000 binary o gray
one sysiem o ouher system in
biay fo
Binary code:
- -0 Read up

01 0100
This indicates that the signal at the receiver end may change a

Gray code : channct.

An additional extra biü is added to the data transmited, in

MSB)
order to mantaun the data iniegnty between trasuner an
Thus
(100h=(l01 Jy (52) O0100
UEx. 24.1 MU.O. 161 May 16, 2 Marks Step 1t Convert binary to guy The extra bit allow the eror detection and comection of the
data
Convet (47.5, into BCD, excess 3. Binany 0
Ans.
codo:1810-001e~0 The dala along with the exa buzbits called parity bits forms
sray code 1 0
1
:
1

(47.3y4x7+7x7+3x7 The codes that support only error detectuon are caled error
deteeting e0des.
28+7+
H 2.5 ASCII CODE The codes that allow eror detection and comecbon are called
35+0.4285S serror de
35.4285 tisa standard alphanumenc coxde. hariy checg o co ed for dctect the eron
(47.3, (65.4285)10 Standard
n o t Code ha
eor detecting
ASCu).
e
(35.4285%0 (0011 0101-0100 0010 1000 0101)C and correcting code.

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 Digtal Logic & coA MUSem.3.Comp) (2-10)
Drawbacks of parity checking method EDgital Logje & cOA (MU:Sm 3-Come)
a 2.6.1 Parity Checking UEx. 2.6.1 MU-O.10. Dec:. SNark Module
() if the number of received coxleword is double or
erors in the P
Wht Haritu bit, even parity and even, the parity of the received data word emun the same. Asume tha the dala has been encoded n 7 bik even parity (3 For Pa: P,checks bits 4, 5, 6 amd7
1.e. even number or erors are undcicelou Dy une receiver. Hamming code and the number 1000010. Correct if for any emors ae wO l's in the group. Therefore. parity checking for
- odd parity bit data. "
There
| (2) If the mumber of errrs in the received code word is odd, the and exract 4
even parity is correct
A Pay o eeceved dla word changes. However, the eor Ans.
Panty bits are the exira biubius addcd to the duata being
cannot e corec ecv Step11 Construct the 7-6it Hamming code. The 7 bit code wond is,
irans mited for detecting the erors in data transnision. emar is there, but does not ate 110010 for even pany
Fig 26.1 shows transmitted data with parity bit
Ir de number of l's in the given word is even( 2,4,6), the
.
which bit is in eror.

Step I:
oo
Check for parity bits
|o o o DEx. 2.6.3 MU-O. 1e, May 15. 0. 1d). May 16.2 Marks
Obtain odd parity Hamming code for 1011.
data word is saud to have Een party. L0.2 Hamming Code
Fur PP,chccks 1,3, 3 and 7 Ana
if the number of l's in the given word is exd (1.35), the data lain wth example
with example how
hamming
word is suid to have Odd parity .
plain_
code isuseful detartina and
for detecting ana
As ee e e puny cee 0r vEn puny 1s wrong
epLeu o g
ASB
correcting" For P',:P, checks 2, 3, 6 and 7.

b Data bis
Prove that hawwng
aeteeting ana comecting code
code i5 an
o There are two I's in the group. eeoepy
even parity is correct.
Step Il: To determune pany o

--**
. O2DAMay 14, 10 Marks
(mFlg. 26.l: Transmitied data word wilh parfy bi 4, 5, 6 and 7.
Ane
Cieck
Q.26.2
*********
How does parity
erorwhat are es arawback
checking detect Hamming cude is ued lo overcome Ue drawbck
checking melhou. i.e. N delccts he
which bil s in e.
errur and alo
or panty
indcaMcs
nere s

* The
one

resul word
ne pany eeck

is (P,PaP)= (l0)
toreven pauniy s wrOng

n indicates thai bit in

.
For
ere areo
**

P: P check bits ,a , n ne goup. eeuE, 00 pay

A The incorect bit can then be cang on in error. gnceiect

uca eron e the Hammng D, bit is 0, it hould be a 1

ny ea lo dclect
heckg reerecting a single error on
:. The correcd code word k 1010010 chec&T DILS 4, , G, 7
EeivEr
ed smitled 7 bit code word as shown n
Fg b 1010
the paity of the signal received s
*
The 4 bit data (D, D, D,DJ
bit mess
.If
sgeu parny, then Uere s an eor is De received gnal,
iicret asSuming a ToNir

This, t is proved thal Hamming code is emor delecting und Checking i3 incomect

E. Ue Wanila datia s assignied oda panty and if the TEetng c

Pg 2.6.3: Bit code worl for 1lamming code bit Hamming codeword is 1011110
receivea han ah even purity, en here is
an errow in lie
Dec. 15, O. 1C. May
7
gnai UEX. 2.6.2 MUO, 26). 17.21arkS
17,2 Marks
264 MU-01e,
Pig 26.2. AMay
gnal received us siwn in
e ONE gnncan Dit m E 4 bil word
iamning code 1or 1010. UEL.
anly DoLun even parly

P Dg Ds D Ans. : Comiet humeuag coe Or BCD a oe eves pniy.a.

e Emor To10JOoo
wanemitled
orect
wOd
101ng ee puny reluons comsering four bil frum de
Step 1:Consinuct the 7-bit Harmming code. Ans.:
Step Ii To comstrat 7 bit Hanuming
coe
ord.

n i To delcrmine the parnty bite

or I, in ordkr to sel oud 7 even parity over bis,
uningE parity checking. s elected U Step
0ng 2.h,.2 i
Error Detectlon
, d 1e. Diis P Dy, D,. Dy. P', checks bets 1, 3, S, and 7.
g
Strp
For P
1
P, checks bitsl,
parity bits.
.3.5.nd7
s 3, and
electod lo wu the grou. 1nerer0e any c
()
*5h positon) is Ae
herEfore, even panly
:
E
uy he transnalleed word chunges
At the receiver end,
e or
, in order to sel oxlal' even purity over tdhe bits 2, 3,0 even purity is coerect. Tere ae ne the

he purty o ie seceveu w
bit indicateN Ihul there
CER
ih u1 etrcN in
N E

ue rrceiveu gnul.
u
erro e
urupJ cumsKer 1, *4=P' Position) P,Is nelecieu
he receiver delects tht ere is uansiic
If a in
oddleven purity over the bits 4, 5, und 7. 1
6
or to sel
ignal, it lgnures the eceiveu
transhiier tn retrins
ie ie se 0ula
ye
uylc.
an
e bitsP' D, D
ad "**
Authurs ai
ASACWY.SHAW Wstu

Treh-Neo Puhlieativn. herr inu"

Teeh-Nra Vaublivatintm hew Aulhors imyir imwwatio
 Codes
Digital Logic & CoA (MOSem. ) parnty checks fo
in the group. herefore
There are two l's
(2) For Pa: P,checks bits 2, 3, 6 and 7

ufanty 1s imcorrect
cHAPTER (
Tbere is one 1 in the group. Therefore, even panty checking

3
is wong
P

For Pai P, checks bits 4,5,6 and 7

2) For

nere s
, checks
onei m
bits 2, 3, 6,7

ne group: herelore panty cneAS for odd

3 Boolean Algebra and
Logic Gates
nere are twOS In the group. 1erelore. parny checkng Tor
ity 1s core
ven panty s cemect. Module 1
.7 bit Hamming code word ik, 0 110011
(3) For P,: P, checks bits 4, S. 6,
There are two 's in the
7

group. 1herelore panty checks tor

University Prescribed SyllabUS
UEx. 2.6.5 MU-0.1e, May 18,2 Marks odd parity is incorect ComputerFunoamenta
Encode the data bits 0101 into a seven bit even pariry Hamming .4 Boolean Aigebra, Loglc Gates : AND, OR, NOT, NAND, NOR, EX-OA
P1
code. is 1011001
*7bit Hamming code for odd parity
Ans.: 3.1 LogicGates....
DEx. 2.6.7 MU-0. 10. Dec. 19.4 Marks a. 3.1.1 What do you mean by bgic gates? Give its characteristics...
Step iver is1011011
I: Construct the 7 bil Hanining coe f the 7 bit hamming co
eid ode word is 3.1.1 Characteristics of Logic Gates.
coect
or wrong? If wroeg locate the bit having error and extract
Q.3.1.2 Which gates are called as basic gates 7 .3-4
comected dala.
52 Postve and Nogalve Logic.
Step 11: To deternine paurty bits. Ans.:
2. 32.1 What do you unde rstand by postlve and negative logic ? .
(0) For P: P, checks bits 1, 3, S, 7 Step I: Construct the 7-bit Hamming code.
There is one 1 is the group. Theretore even panty checking
******

****
for group i5 ncorrect
D, DDP, D,
3.2.2 Negaive LogC.
3.3 Truih
TaDie..u ***

checks bits 2, 3, 6, 7
4 :' the group. Theretore. panty checks tor
a. 3.3.1 What do you mean by truth labie ?
Ihere are two
l'
even parity ib correct
Is

even panty is
3.4 NOT Gate..
* ere e hree S,ne Puy check TOr

a. 3.4.1 Whatsanogare f ** .3-4

(3) For P P, checks hits 4, 5, 6,7 Descnbe NOT gate with its symbol and Boolean expression. *

eE, paniy checks for even For checks 2, 3, 6 and 7,

Which gales can be used as invertersn addibon to he NOT gate
Dariry
i ine There are twoI's in the group. 1therefore parity checking for
0. 3.4.2

en puny
D. Describe the AND gate with the symbol, the lbgical stalement, ana
Dtaming codeword 0101101
is 3.5.1 the Boolean expressicn

For P:P checks 4, 5. 6 and 7. its logical diagram.

UEx. 26.6 MU-O.1b). Dec. 18,4 Marks
Constnct amming code for 1010 using odd pany. here arc thrce l's. The parity check for even parity is wrong D. 3.52 hy is an AND gate called AlLor nothing gate 2..

Ans.
.P Q. 3.5.3 An AND gate in positive logic system is equivalent to which gate in negabve lbgic system ?. .37
The result word is (P, P, P,) = (000) It indicates that bit in
3.6 OH Giale .. **

StepI: Construct 7 bit Hamning code. position s n, errr 0. 3.5.1 Draw symbol for 3 input OR gate with truh tabie. **

Dg Di 1s t should be a 0
D, D, DP, D,
PP *.The correct code word is 1011010 a. 3.6.2 An OR gate in positve logic system is equivalent to which 9ate n negatveogc yxem f

Step 1:1To deiermine the panty bits

* 1he a bit data (D, D, D, D,) is 1010

lus, t 18 proved that Hamming code is eror detecting an

3.7 Universal Gates..
0. 3.7.1
uu ******************aaaaauauasru
Prove that NAND and NOR gates are Universal gates MU-0. 1a). Dec. 19,4 Marks. .-8
m

For P, checks bits 1,3,5,7 coTECtingcode.

( a. 3.7.2 Wnat is AOl and OAl ogc 7
0.37. NAND gate followed by an inverter is equivalent ko which gate 7.
..Chapte E
a. 3.7.4 NOR gate foilowed by an inverter is equnvalent to which" gate**********
How can NAND and NOR gate be used a3 an inverter 7
.3.7
 (3-2)
Boolean Ai Sat
DigilalLopic& COA (MDSem. Scom) Digital LogiescoADSem.scomp) 3-3) Booiean eoa anLoie a
3.8 NAND Gale.. 3.16 NAND Gate as Unversal Gate .. m
3-21 Module
. Draw symbol for 3-input NAND
3.8.1
gate wiuh tnutn 1aiDle.u
UO. 3.16.1 Prove using Boolean algebra "NAND gate is unlversal gate".
F1
*********
... **
39 NOR Gate
Draw symbol for 3 input NOH gale win ruu BO *** s t**** ***************
MU-0.36). Dec. 16 10 M o 1a.
Dec. 17.2M O 10 2Mlay 16.2 *****

.3.9.1 3.16.1
d
OR Draw nn 1aDie 1or ga
* O. 3.162 mpienant or gaies using NAND gates ony.
1
3.10 EXR Gae.. 3.16.2 AND Gale
Q.3.10.1 Which gates are also known as controlied NOI gatef saat antmerm**e*a**e********
a. 3.16.3 implementAND ga18s usng ANO Gales ony..
Input EXOR gate with truth table.m
Draw symbol for
.
3
a.3.10.2 3.16.3 OH Gad

311 EXNOR Gate . a.3.164 Realize sxCuSIve OH gate using NAND kogic.
O.3.11.1 Draw symbol tor 3 input EX-NOR gate with bruh table. 3.16.4 NOR Gate.... ***** ******** ** *********

gates only. .
a.3.112 How will you realze EXOR and XNOR gates with three or more inputs ?
- a.3.16.5 implemeni NOH gales using NAND ****

S.12
Bosan geoia 3.16.5 EXOR Gate using NAND Gale.
a.3.12.1 Whal is Boclean algebra 7 Eplain ts charactensocs.. 0. 3.16.6 Implement EX-OR gates using NAND gates only..
erenane beween ornary ageora and B0010n gra, 3.16.6 EXNOR Gate Using NAND Gate.
***********************************
3.12.1 Variables. Lterals and Terms in Boolean Expressions a. 3.16.7 - AB + A.
Realze y B using NAND gates only AU-0 1a, May 15.2 tMorks
O.3.123Define vanables, Literals and Tems in Boclean Expressions. a*
3.17 NOR Gate as Unversal aalo.
3.12.2 Rules in Boolean Algebra. O.3.17.1 Prove OR:AND conhgurabon is equvalent to NORNOR configurabon.
.1A STne rues or using ooean ge MU-0. 1 May 18. 0. 10), May 19. 4 Marks .
3.13 Theorems and Properbes of Boolean Agebra... 3.17.1 NOT Gate (inverte).
d. d.1a:1 Wnat are axioms or postulates in Boolean algabra 7 ust the postulates, *****

a. 3.17.2 Construct NOT gate using the universal gates. 24

3.13.1 aws of Boolean Algebra... sananneess***** 3.172 AND Gate.. *******************

a. 3.13.2 What do you understand by lews of Boolean algebra **********************e************ats*******a

a.3.17.3 Construct AND gate using the unversal gates
.3.183 Slate the Boolean alpebra laws used in k-map sinmpitication. MO-0.20XO. Dec. 14.5 Marks. 3.17.3 OR Gate
3.13.2 Duality Property.
a.3.174 Implement OH gafes using NOR ale oy.
3.17.4 BOR Gale usng NO Gale
.13.3 Basic heorenm8.- ******************
mpiement Ex-oR gates using NOR g
3.17 1y.. -28
a. 3.13.5 Prove the basic theorems 01 BOCan
a0r
.
***********************************
3.17.5 EXNOR Gale using NOR Gate-
a. 3.13.6 State and prove De Morgans theorem. MU- 0. 10. Dec. 13.5 M. 0. 10. M ay 16. 3.176 implement EX-NOR gates using NOR gates only -
0. 1191, May 16.2 M.O. 1el. Dec. 18, 0. 1d), May 19, 4 Marks.
3.14 Boolean Funcbons. ********* O Chapter Ends.
a. 3.14.1 Whal is Boolean funcbons 7 Explain how n can be represented using: 1. Algebraic equation
2. Tuth table 3. Logie Gagram ******************* *mes auaasau***maanmasta

S.13 Boolearn Function educton using soolean Laws

. ********ms a1
EOUS Onversily Paper Ouestions

DEx. 3.15.3 (MU- 0. 200X, Dec. 13,b Marka).um

DEx. 3.15.4 (MU - 0. 10). Moy 17, 2 Marka).. 34
JEX. 3.15.3 (MO *
'o} ay
******* resaa atmsaasansassssaar**paa****aanREaaaaasseanaaa **

ecb-Nee Publicalioas here Authos inpire inaovati eeb-Nee Publicalions. err Autburs mpere oral A SACIY SII Veture
 Boolean Aigeora and Logi¢ Gate
Digital Logic & COA (MU-Sem. 3-Comp)
Digtal Log
AUSem. scomp) (35) BoOean Aora ano Loc ate
H 3.1 LOGIC GATES Positive Logic C. Logical or Boolean expression Modale
3.2.1 D Logical operation ruth bible of NOTT
Gafe

:93.1.1 What do you mean by logie gates? A positive kogic system is one n w hich a oge level
E. NOT gate using a switch
volage level i e an
ie rs caractnst...
*************************-"
EAndaLOW
. Eg.: g
lo positive logic OY Tepresen ad 3
. Inuth abie
Input ana upul wavefoms
epreenis kEIC
Ans.
gA)
Deinibon and descrpbon of NOT Gete
Deinition of Logie Gates : The tiectronS:
e(G) Input and Output Waveloms ofNOT Ge
circurts that are used for impleMenDing D Oup Defintion
:
NOT gate s a logic circuit whose
logical or boolean expressions are called as Logic 1 HIGH *5V
utput
D Logic o
is always coplcnt
as an inverier.
of the input.
- ANOT gate is also called
*****
**** Positive logie
Dpe wiuh one or more inpus ano 8n Fig, 32.2: one output
A
e& Ogital carcuil
The NOT operation is also called as inverdon
OutputY
3.2.2 Negative Loglic
a3.1.1 Characteristics of Loglc Gates
& complemenlation, Le., uput of dhe NOT gaie will be logie
TATTT
A DEgaive logic systemis one in whch a low voluge level
1The relationship berwen the inpun and output is such that sents logic 1 and a HIGH voltage lkvel repreents lo
E B) Logic uymbol of NOT Gate
Eg. f oV rpreseats lopes
every logic gale is designed to perfom a specific logical 0.
n callcd as negauve lope. 0 Tbe symbal or NoT
expression. Oe stale, 1 operaion
is(bar 342 Wick gates can be usd s verterr
he banc buldingblocks o digia NOT
e t gales E g NogaDve loge in adaition to the NoTsat
ens wolage
A **********************
aklinc to t
ued as imverrten in

----m-- -----------*****
called as
***: BPh 3.23 Negative bogie*
:
nyersion oeration
W3.5
12..Weh gates art basic sates (84 Fig. S.a.liLogc symbol for NOT Eaie (inverler) AND GAT
Ans.: The the mos
OR
a ***

3.3 TRUTH TABLE

As hown
As shown in
in Fig 34.1, aa somall
Fig 3.4.1, small circle, bebble",
called bubbile.
cirtle, caled *3.5.1 ***--*-**---------
Deseribe the AND gate wrtN DNe Symbo%,
ND 2 NOT **************
*****
A digital cireuit of any complexiy can be comstructed withQ3.31What do ygou ean y rt tabe ogical statamenE, Be Boolean
he help or uE
---*************************
prn and ra lcaAl dgr...
Hence, they are called as basic gates or basic building
blocks of a digital cireuits O Definition of Tnuth Table : A truth table sa Y NOTA=A Ans.: Answer inctudes following points:

A Definution and drscnption of AND Cate

3.2 POSITIVE AND NEGATIVE table that shows al te pu-output (O) Logical operatlon of NOT gate B.Lopc symbol of AND Gae
LOGIC Cobraiond or d0ge
In a truth table, all the input combinations
r. of binary 0 and 1s
averion C
D.
Logical or Booicas eapesia
Lope ogeroon
E) NOT gate using a switch
4. 321 what do uou understand bu positive are lisied in numencal oroer. EAND ME using swikhes
neaatie lnele The output conTEsponding to every input combination u aso Tuth uable
-
Ar
---------------.---*-----* hsted, Le.,
wu eaxt o
a tuth lable shows bow a ogie Circuit's
he dilierent input combinations.
outpul np and CulpulWavetarms

3.4 NOT GATTE A) Definltion and Descrigtion of AND Gato

ODefintion. AND gate is a logicho

gn (Logc 1)

io 34.1 What is a NOT aate ?********* irtut whose

Input ga r Low (Logic 0)
Desceribe NOT gate with its symbol;
34.2: NOT ate using switch
utput i RH whn all its inpus are HiGH.
An AND gate has two or me inputs and one output
b4
(oBFig. 3.21 Outpot eves in a digital cireult and Boolean expresion.
i
wcn swich A s open the lamp is ON. An AND gae will have oupurI only if al its inguts are
The output of the AND gae will be lpc 0, any ot he
me output volage levek high and low) thdt are signed to Ans. : Answer includes following points :
amp is OFF.
represent the logic levels 0 and I may be positive kogic or A. Definiton and descnptuon of NOT a n bi nput is Low (dogic 0) output
is

negatlveelogie. B. Logic symbol of NOTGale HIGH logic I) and vice versa

SHUI Veature
Tech-Neu Publications bere Authors inpurt inaoration SACHIYSMUI Vata Tech-Neo P'ublications be Aathas pur 1SCIY
4
 Digtal Logic & COA (MU-Sem. 3Com (-6) Agecn and Logic Gates
Loglcal Opestlon of
AND Gate Dgiaeico o em.scomp) BoCan
odule
E
4. 3.53 An AND gate in positive logie system p Logkeal operon of o
the synbol for AND operaian is " (do). Logical multiplication is equivalent to which gate in nagative Logical addeoon
TrAth Table fogic steN
BeO*AB C
oYABC Table 3.52: Truth table Table 3.5.3 :
Truth table o
********************************|(
Ans.
OR Gete dsing D

2npul AND ate input ANgE Ad AND e oC yietm s equivalent lo

AN Ouput lage
source
Larp
H 3.6 OR GATE
AB CYAB.C 41 Draw symbol for 3 input OR gate
Loglieal or Boolean Expresslon of AND Gste ]J pate sing swiicbes
IO with truth table.
Be Flg 3.6:OR
A AND B Y-A AND BAND C ******************************** When both the switches A md B we opea, ahe anp a
Ans. iAnswer leiuds rolo wng polnts 2When switch A open and swilch B cK, sE np s
YA B Y-A B.C is
Definition and descnption of OK Gale
eA
Sometime
Operior epEens ocauitiplcanon
opucauon L B. Logc ymbol ot Ok Gate wn ON.
A u cosed and swilch B open. the lamp is

ofA B as AB and is read as "A and B". C. Logical or Boolean capression

4When both the swilches A and B t cloned. the lamp s ON.
D. Logical operation
)AND eio using Switche E. OR gae using swilches
Table 34.1 :OR pie esing wiliehes

OUpUl
A
Open Open
Lam
G. Input and Output Waeforms O

)amp E(G) Input and Output Wevelomso1 AND LS

Deflnition and description of OR Gete
CosedON
A)
***** ************************
gare s a ogc circurt whose
usng switcbes PEnationis K
BAPig, 3.52iAND gale output HIGH when any of ts inputs are; Table 36l shows the 4 combunnons of s A

. Whea both the swiches A and B are open, the larmp is OPP HIGH. Es coTEspoDding ouipu
************************* In binary language when any inpuk HIGH he uput is

2When switch A is open and switch B is cloved, the lamp is

An OR gale has two or more inputs and one oulpu.
Output one ot ts input is 1. 1he And whee boh the inpuzs are Low, atput is LOW.
have oltput
3. When switch A s closed and switch B is opea, the lamp is he K gale wl

OPF put o e OK gale s u, it all ot is inputs at in logc 0

4. when bodn Uhe swiicthes A and B are cioned, tne amp s oN lt is called as ALL gale or
1B4,Fig. 3.5.3 : Input and Output waveforms ineuso Table 3.6.2 : Truth table o Table 163 Truth tablek of
:

Table 3.5.1 : Operaton of AND gate using swilches for 2 inputAND gale 2-lnput OR gate
Logic symboi oOR GE
InputOutput
A Lam ) Application oT AND ga
he symbol for OR operaion is *' (Plus.
1. Enable gae 2 Inhibit gate ABYA uA YA*
openclosed OPF
-----------*-** *** or
OR Y=A*8
B YaASB* inpu
Closod Open O .> wy an AND gate called ALL are
Cloed Closed ON otng gate.. (19Ka) Symbol for 2-input OR (BAKb) Symbl for S-input
****

--********** OR gale
TADIe 3.3.1, shows the 4 combinations of inputs A and B and i
s comEspoading output An ANDgale t5 Caled ALL or NOTHING gae because
Loglical or Boolean Expression ol OR Gate
LOW
y guage wiea any nput s w De ouput isprcs oulput HiuR when all its iaputs are HIGH (logic
herwise the output is LoW (logic 0). AOR B=A + B YA OR B OR CA*B*
And when boh the inputs are HIGH, the output is HIGH. o
operalor epresenisgcaadon
inaosglne
ISHCIYSZH bentere
ecb-ieo Frublacations BETE A00o spure insovaiea
Tecb-Nes Publications-hee Autharv inpirr
SACHIY SHAH Veata
A
 Digital Logic & COA (MU-Sem. 3-Como)
OR-AND-NVERT (0A) lopc s a wo level Booe
Digjta
ic s oNMOSem. 3como)
(O) Ingut and Output Wavetorms of OR (Gste Module
capression constnucied from tne combinanon
o one or A NAND gate will bave oupul low (0) when all its inputS ND G
o are Input and Output WaVeronn o1 AN
OR gales followed by a NAD E
Thus, AOl or OAl logic can be converted lo NAND lo
The outpuo AND ae will e logic 1, if any of its
inputs are a 1ogic 0. npts
or NOR logc
.
*************************---.. ca p ie s it can be ued t
S.7S by an
NAND gate tollowed inverter6 BS9 Caled an Bcüre
Output ow OR g le
quivalent to w
****** at... Output joo:1
Ana.: ) Logle Symbol of NAND Gate
ny

.2A
pg 3A: laput and Output wavelorms
NAND gae touowea oy

gate followed by
.-.
walent to AND gate.

an inverter
A
B AS
YABC pat
input
utpurveforms for
NAD
n posrtrE logie system 5:|3.74
NOR
* OK gate
3.9 NOR GATE
quvalent to whch gate in negative : ------ --****
(Ba) Symbol for 2-4input
NAND gate
neyb) Syrmbal tor 3-Hapot
N NAND ale
-- Ans. 3.4. Draw sybol for 3 input NOR gate
wiEh trutN table.
Ans.: An OR gate in poviuve logic sysiem is equivalent NOR
lc
gate followed by an inverter is equi valcnt to OR pale. (B Fig. 3.8.2
.----
AND gate in negadre logkc ystm Q. 3.7.5 How can NAND and NOR gate be used Bubbie on the NAND gale represents NOT operation or *
W 3.7 UNIVERSAL GATES
... -------- -- Compiec
**
Aefinibon and descnptuon of NOR Gate
:
WEn both Uhe inputs al NAND or NOR gates are tied C) Boolean Expresslon of NAND Gate
Prove that NAND and NOR gates are
As. and input is applied to the common terminal the NAND
S.7. together, Y-AB-ABB Y=A B C=ABC D.
*P*****

--
Universal gates or NOR gate functions s an inverier.
B represents AB-Crepresents
Logical operation
uh uble
---. DH0.D di 3.8 NAND GATE AND ernon F.npu ha utaveo
Ans.: OT n OT A Definition and Description of NOR Gate
With the help of three basic gaes AND, OR and NOT, We we.3.8.1 Draw symbol for 3-input NAND gate
can realize any given Boolcan expressio. ... O) Loglcal Operation ol NAND Gate
Defnition : NOR 9ate iš a logic circait whose
NOT AND or NAND utput i5 HIaH
whtn aif ts inputs ar Low
Two more
ied
gaues:
for
imr
NAND gate and NOR ae navE
e M Ans. : Answer includes follaw ing pon
Definition and description of NAND Gate E)Truth Table of NAND Gate
NOR gate mcans NOT-OR operation.
A.
combination of NOr and OR galc. Fig 391 shows
Detintion of Urveral Logic Gate : A universal; B. Logic symbol of NAND Gale tis aOperio0n
OR as Cperbon.NOUK
C. Logical or Boolean expression aDie 3.8.1 Truth table Table 3.8.2: Truth table of
og gate 3 a gare hat can bE useat 3-input NA
arg boocan aprtssion withot 2Hnput NAND gate
singang othEr type of gate. Input and Output waveforms
Input ( g,
39.tNOR operaion as NOT-OR operation
Output lnput Output
Advantage of Unlvernal Getes PAJDeinition and Descrption NAND Gate puts

AND and NO gules are calcd as unvernal loge gales

*
Defintion NAND
******************
is logic
:
gate whese
a circuit
ABYA.A8 CY6 nhe outpul of the NOR gate will be lognc 0, d any of its

, pus
a oer can
*Eaue galcs codco
Output s LOW when afl is inputs art HlaH.

.
oh the NAND and NOR galcs can be used to perform the implement any Boolean function.
NAND gale means NOT-AND operatio t nmhieaicn

r---.-- .
and NOT.
DOR ADd NOT gae. Fig 381 shows NAND operation s 1 C BLogic symbol of NOR Gate
NOT-AND operuti.on.
.3.7.2 What is AOI and OA loge
*****~.-
A Ane.

AND-OR-INVERT (AO) logie s wo ievel logical or

Symbol for 2-4npul b) Symbel for a Jinput
Boolean epresaion consUucico rom the combinalion one (E7) Plg, 3A. : NAND operalion as NOT-AND operabu
(Va) a (14y
of Output is 0 when NOR gate NOR gate
or more AND gaues followed by a NOR gale.
Lal inputs are 1
ANAND gale has two or more unputs and one o
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 Boolean AgEora
Dgilal Logic A COA (MUSem.3.comp 10) dee dates
Digital Logic & COAMGSem.3Como)
Bubble o te NOR ae mgests NOT operasion o 3.10 EX-OR GATE Boclean Agen erd Lo
O cvmpkementanon.
or BooleanExpresslon of
al
C)Loglcal EoR gate 3.11 EX-NOR GATE Modnle
owR as
.
Q.3.10.1 Wch gatesare ao
CLogleal or Boolean Expresslon of NOR Gite

Y-AB YA+B+C
. -------- YAEX-ORB=A®B Y-A EX-ORBEXORC 3.11s Prew ** *

TA+ B represents OR og
represeats NOT operaion
nd the bar
Ans
XOR gate is also called as controlled NOT gate because it
one input of the gale is tied to and the oder is X thien the outpu
AB +AB :A®BOC
*
Ans. Aswer
--.--------
gate with truth table

incades romg Ps
---
a ead as Y equals NOT
O) Truth Table of EX-OR Gate
A. Defhabon and desTpuce d ENOR Ga
t is R)
A OR B)" Table 3.10.1 : Truth table Tabie 3.10.2 : Truth table of C Lopcaor Borleaa etprsnoo
Tnuth able
OLogicl Opersdon (BsFig. J.10.1: XOR as controled NOT gate
nput utput Waveforms
NOT OR or NOR . 3.102
*********** Draw sywbol torSipuE
********--*-***
EXO at
Iniput

ABY=A®B
OUpur Eput Output
Y-AeBeC
and

A) Dfiniton and description of

E) Truth table of NOR Gate with truth tabie. DNOR Gst
Answer includes followine
Ans.:
Ans mointa ,

DefiNtion :
EX-NOR gats a logc cirturt;
Table 3.9.1 : Truth table of Table 3.9.2: Truth table of nd desCripion ofEX-OR Gale 1 wROSE
Ouput is HiaH WHEn botN rE5 inputs are:
2-input NOR ate Jinput NOR gute B. Logic symbol of EX-OR
C Logical or Boolean expression
***

Input Output
D. Iruih iabie

and Output Waveforms

An ENOR
combinanoe of NOT
gate NOT-E OR operon a
s
EInput and ENOR gale. An E NOR gae has
Y-A+B A YABC F Applicabons of EXR gale 1us and 0nc output
o1 Ouput he outpul ot be EXNOR ae will be Bugh (kege 1) hen
Doth the inpuits are same,
An EX-OR gate is
ie. A = B 0 cr A =B -I.
when Definition
wose output
:

is high when both

a
the
logie cincuwit
inputs are:
Output is 1
when inputs
The output of the EX-NOR gae will be low (ogic 0)
both the inpuls are not equal
»hen

npus0 samc. e E) Input and Output Waveloms of BOR Gste s adso called as coincidenct
nEXOR ge s gale hat has two or more inputs and o
paie or eqaiy driecfor.

C8)Loglcal Symbol of the EX-NOR Gate

An EX-OR gate will have output" when the inputs are not

The outpuit of the EX-OR gate is 0 when both the inputs are

t is also called as inequality detecdor or anti-coincldence

Output og0 Ka) Symbel for 2apat (AMD) Symbo lor nput
Input and Output Waveformsof NOR Gate Ouput is 1
when EX-NOR
many digita arcuits. The output of same
din
EX-OR gale or
an
(185jP \g. J.l0.3: lnput and nol
Output waveforms

SAAioP
is modulo-sum the wo for
inputs. input EX-OR Eat
2
Inputs E Logic symbol of lKOR Gate or Boolean Expresslon of BXNOR Gate
cLogical
Applilcalons of EX-0R Gate

cor
Output
eloio Jutput is
oh
when
inputs are 0
A0
(iBiTKa) Symbol for a 2-input
E-r*epec
BiHANb): Symbol for a anny
Magnitude

DnayH0-gry comverietoray-bunay couvENEE

generatioctecker
*AEXNORB=A OB Y-A EX-NOR B EXNORC
AB A A A OB OC

Ex-OR gate nput ExOR gate AB AB ABOC

(BsaFlg, 3.93: lnput and Output waveforms IOdder
Tor 2 input NOR gate Adder aNd suburactor Circuits
Fig. 3.10.2
6. Combinational logic circuit minimization

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 Boolean Ageora and Logic Ga
Digtal Lopic &
oA A0 Sem. 3Como)
O) Truth Table of EoR
Q 3.112 How wilt you reali EK-OR (313) Booiean Agebra and Logc Gates
GAEE
XNOR gates with tree or mor ;Q 3.122 Diifertntiate between ordinars alaebra and Boelen alehre Modale
Table 3.11.1 : Truth lable abie 3.11: lruth able Ans.
*******

- -*************** .
---------------*
of 2-input EX-SOR ale Boo *P grtra The dhfemncs beteeeD the tao are fouo*
A ans.
Input
Output nput
do not exisg o
rdinary agebra

hree or moe input EX-OR and X-NOR gades

ABYAOBAB YAOBOC E Et yns useo id ordinary algebra an In Booleana

mone
used to realize EXOR and EX-NOR gales with three or 2 ortinay agebr a variable has numencalIn Boolean alscbra
Aae as ony opca vaue,
t
t doesn have any
EEAA=A
ageua AAA
in orainay upbcabin, dvtsiom
H3.12 BOOLEAN ALGEBRA
presents muupicaion C md *o egve tumben.
rEpreernts addibon, frctons, s
a. 3.121 What is Boolean algebra 7 Explain its repreents suburun. Boxlcan algeba ndcacs
AND cerabon wheres+ indcatet ORR

- charactersues
**********************
Peron AND, OR and NOT
gctra NAND, NOR, X-OR and XNOR
Bonean perlomed
e the three basuc fancDons or operatioes

Ans

. .
* ************** rOA in Booiean pehra

Output is 1 when bom Definition of Boolean Algebra :

Boolean algebrai 3.12.1 Varlables, Literals and Terms in a 3.12.2 Rules In Boolean Algebra
inguts are same is the mathematics used tor analying tk Boolean Expressionss
*****.******************
---- 512 List t rales for sing Boolean
EInputsnd Output Wavefoms ot EX-NOR Gste
digital gates and circuits.
*******
-
Define Vanables, Lteras*
...-..---
and Tems ih
-- ---- *******

.
Ans
oio Characteristics of Boolean algebra

outpu
oioli
.

2
It was developed

Boole.

Boolcan algebra is
in 1854 by an Insh mathematican

a method to algebracaly
Gen

eapress the logc

Ans.
ODefinition of Variables:

inary
lable r

tahles
compieeuled
Variables art

have only two values, loge1

or uncomplementled
.
symbolsBoolen agebra
ssions

(high) and
mg

anables

1a
ae the et cd

o ymbls

ow.
have
mes

oy
to be

ao
perfomed whie ng

vai: E 10

function. It is also callied as "Binary algebra" or "opio

(54Fig. 3.112: lnput and Output wavedorms for EA. B ae r vanab
DE pieneni of ADA
2 input EX-NOR gale Definition of Literals: Every occu A=Ohen A~l amd

variable or its complement callta ac

; fA= 1
then A
0
( Applications of ENOR Gate J help of a Booiean tunecuon.
eral-********************************** Tbe ORang of vanables can be epresesied by() ugn.

n error detactuing crcuits to dctzt even or odd parnty brts in egA*A*B+ ABC 3.121) E.A*B rai s A OK

dptal data transmision circuits.

an ao be ued 1or the sirnplincabon ot complet o In the above expression, there are 6 (ix) ltenals The e ANDag vanaes aa c epeeale y " D
SAIEtDents wih the help of Kamaugh maps or Quine
Anthmetuc and encryption circuts.
McCluskey method.
a
Defintion of Tenms: A term is defined as the
la Bovkan algebra any Bookan fancticn an be proved by
perfect inductkon method. la ths method. the Boclean
Lonpaa
Boolcan agebra uses a set of rules and laws in order to detar funcion is venfied for every pauible combunation of valus
a1 nae includine three AND of the variables with the help efa bunh ab.
the eperation of a digiual circuit
em
Serms

th combines the first level AND

lerms.
1SACHIV SHAH Veaiar
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 3olean Aigeora and Lopic Gat
Diglal Logic & COA (MUSem.3om9) 3-14) Logic & COA (MU:Se Ageora and Logic G8tes
Dijial adn
H 3.13 THEOREMS AND PROPERTIES| a 3.13.1 Laws of Boolean Algeora Module
Law2:AB BA Law 2:A + BC = (A +B) (A + C)
OF BOOLEAN ALGEBRA
3132 what do you understand by laws A AND B
B AND
states that ANDing of many vanables and Oing
the resu

--
which variahls

S what are auos or posaES

t Boon
qebra ?
--- ---- the order in
change the output'iesalt
is equivaleot to ORing
ariable with eaxh of several variables amd the
tor prVvihg ue resu s
sun
hat
AE
Bolea agebra 7 Lt
*******************
ta pestlates|
*********
Ans.
set
Table 3134 Truth tabke for commutative law for AND ates
sums. The trulh abie
Table 3.15.0.
Nu "

s. o Definition of Laws of Boolean Algebra :

A

Ention
*****************
o7 Aoms or Stiaes i*
Dooa":
of nules that help to rtduce the number of AAB ABA Table 313.6: Truth table for distributve aw oAND pa

Agora boolean agebra, akio ogie gates Equirta ror pEntormr4 a speitic ABCBC ABCABCABACAB)A
" as Laws or Boolcan
postulates art a group of lo91cal prEssions; ogc optration art calita
i
hat we accept WNout ang piroo Algebra.
Atioms are the hasie definitions of the three basic Leics
lopcal
- ------------------------- -o*--.
opertions AND, OR and NOT.
:
3.133 State te Booieang * From ruth 1adie s.l3, t proved that AB = BA.
0111
1

0 1111 1
aIOms, WE can bakd theorems. k-map simpliñcation CommutaDYE law can be extended to any Dumber of oc 1 0 0 11
able 3.13.1: Basic AxkomsPostulats o boolean algebra MU-0. 21aU. Dec. 14, 5 Marks
*************************** *| . wanables.

A*B*L=C*A*B=B*C*A=B*A+C
Operztins Ans.
DE DRE 1aws or Booican nigebra aE AS follows:
(2)A- B .C=B .C:A=B -A-C
PPP
=0 Associative Laws
Lompiementabon laws
NOT operabon
Z. Commutanve laww
From truth Table 3.13.6 i1
is proved tha
»C)
A*BCA* B)CA
S. Assoc1ative laws variables, the result remauns the same.
4. Distnbutve laws Lawl:A +(8 C)=(A +B)+C a 3.13.2 Duality Properny
aw 2iA-BC)AB
O0 AND operabon 1. complementabon Laws .313.4 State and eplain principle of duality **

4 Distributhve LawsJ
Complement means to invert of negale, LE, change 0's to l's Ans.
00=0 D SUppo or actonng ot
piyg Definition
eapiessicns of Dualy
A =0, tben A=l
1+0- OR operaion
Law 1: A (B +C)= AB +AC i saes tha evey Boolean ep dened
Law2:lfA= 1, then A =0
staies that ORing ol many varnables and ANDing the result inulerchag oed
Postulates or boolnA L 2 Commutative Laws wu a sig anane is cqui'valet lo ANDIng thal singi and AND C)and kmiy eements are o Boean
algcbra Py
Tabe Commutative law states that mocitying sequence of terms. The truth table for proving the
J.13.2 : Lsts the postalates of Boolean algebr he
Table 3.1 . If we need
io find the dual of an expreEsion,
ariables does not affect the outputresult. hey
Postulate Postulate Commeat
Law1:A+B =B+A Table 3.135: Truth table for distributive law of OR gaies n vce-verae ANDand
and
oeralon repre
oN
Huntngion postuales ae
ana

he usied in palu

Resull ot Openibon
sT0 o - Baes
B OR A
hat A OK BprUEs ue Sane
ie., the order in which vaniables are ORed does not
;
ouiput ABCC)ABCABcAB AC ABAC
eg.Dual of rrladon A -0 = 0isA + ] =
We can obtain the dual of an eapresson as folows
change the ourput'result

- A+B=B+A JCommutatDve laws

Table .133: Truth table for commutative law for OR gates
O10
Replace
2
OR by AND operubon.
Replace AND by OR operauio.
AB=B-A ABA+B 3. Replace 0 by 1.

daA 8+9=AB+ AC Distributive laws ABA 10 0 0 10o D0 0 eplace

1

by.

dbA+BC= (A+B)(A+) 1 01 101|

n
0 1

n
1
epessis om e given capression.
Sa A*A
omn 1 1 1
Duality theorem can be verified by construrang truth tables
11 1
. eorem ano
-From trvh Table 3.135 it is proved that A (B
O- Table 3.13.7 bss the Boolean bwt md

From tnuth Table 3. 13.3 it is proved

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 Boolean AgaDra Dnd Logic Gateg
A Digital Logic & COA (MUSem. som A DigitalLogc & COA (MO-Sem. 3-Comp)
Table 3.13.7 A+A A+AA
Expresion
('A+BC=(A + B)(A *) postnlate 4b) nvoo Theorem 4b): (Associattve law) Module
= A*0 (A A=0postulate s0b) Theorem 3iA=A(involuton law) A (B-) = A B)C
A*A
It states that A ANDed widh B AND C is same as A AND B I
:A+A A (.A+0=A postulate 2(a)) ANDed with C
Proo LtA* Cmpienct ofA and A be comnplement of A
hus,r proveu Tabie 3.13.9 shows trudh table for associative law of AND
A A+0 A*0mA gates.
postulate 2(a)]
4. .1- 0-0 *Theorem 1(D) :
A -AA (dempolence law)
5. A.0=0 A+1-1 A+AA i S15 rth abie or asoative la o AND Zals
tA*A=Opostulaie b) ABC8-C A-(8-0
6A1=A A+0 A ifA0 ie,A-AsA -A A)Ã+)
A

A:A=A A+AA_ AI 1-1I A*5)lA+ postulale 4(bJ 010 00

A A =0 Proer
L 9 A-B-B.A A A)1 A+A=lpostulate S(a)) 0 1
00 0
A*A A-A+0 (.A+DmA postulate za)
10. A (B C) (A B)CA+(B+C) (A+A) - (A +A) 0111 0 011 0

AD A A = A:A+AA (AA 0postulate 5(b))

A
(A+A=I postulate 5(a))
o 00 0 100 0
AB+C) AB+Ac A BC
1 10 0 10 10 0
A+5)A +9 A*A *
AA+ A) (A(6 +C)- AB+ BC postulate 4fa) A+B)A+C)=A*BC 1 1 00 0 1 10 1
2 AA+ B)=A A ASA AA A* A+A 1 Poxtulate 5a)
postalae
o 1
1
SAA: B)=A-B AA*B=A*B_
L AB-A+B A+B= AB
A**

Thus, prove
CAl=A postulale 2{b) . A

= A
A* AAOpostu

A+0A postulaie aa
latle 5b)) From truth Table 3.13.9
combinarions of
SC1atve
A, B, and C,
aw of AND gates Is proved.
A-(B.O- (A
. R).CT
A+B)A+90+0 AB+AC+BC Hence proved.

A+B)(A +C-AB+AC ldentiy laws DelMorgan

Associative law l
Theorem 2t@) : A + 1
=1 (ldentily law
a 3.13.3 Baslc Theorems Theorem 4(a) : (Associatlve law) :3.13.6 State and prove De Morgans thaortm

. 3.13.5S Prove the basic theorems of Boolean

IfA=0, then 0+1 =]
AI, then 1+ l
=1 A+l=1 A*(B+C)= (A+B)+C LU-O. 1), Dec. 13.5 M,O 1O, May 16
It states thal A ORed with B OR B Sane
algebra C as A oxDO
with C | Ans.
Ans. : Table 3.13.8 : Truth table for associative law of OR gates
** tA) Al=lpostulate 2(b)) Theorem S{@): DeMorgano 1heorem
dempotence Laws A+1 = (A+ A)-(A+) A+A=1postulates S(a) ABIC )A+BC)ABCA+B)|A+B)+C DekMorgan's theorem 1
Theorem 1(@) : A + A=A
Al = A+A-1 DOo 0 0 OD O Definition: DeMorgan's theorems are usea ini
A+BC (A+ B)(A +) postulate 4(b)
NA=1, hen 141=1 empoens hdcaes Boolean algebra. A * B AB. TNS law states:
sane viabe, ls, A +A=A)
A* * A** CA1=1postulate206)]
111 1 HI that
te copleGNt of sum ot variables s
Theorem 1(6):A -A =A (ldempotence law) .A+ 1 = 1
A+A=1postulate 3a)]
11 1 1 gudlo .Prodde er Ser cowpleENES
Thas, proved 000 1 001 1 The LHS of the expression epresents NOR gate with
inputs
1fA = 0 0-0=0
fA =1 1:1 = ie., A A= A *Theorem 20): A -U=oidenuiy
O 1 1 1
1
A and B. Ihe

Bubhed ANN
s
o the expression represenis AND gMe
e is cquivalent o
Proor
law
1 1 1 0
A=0, then 0-0=0
=
NOR-
ew
Bubbled ANDDeMegan's theorem)
betp o lopc diogram and truth
A+A = (A+A)- 1
(*A-1=Apostulaie A=1, then 1.0=0 A0=0-A 0 prOvE wih the

A+A = (A+A)-(A+ A A+A= I postulate

zib)Proof J uun
combinatio0s
ao315.8
B,
of A,
e Cn thal tor
and A*B)*tA*D*
C :
see al possible

A
tabies.

S(a)
A*0 by duality of theorem 2[a)
nus, the associatlve law of OR gales is proved.
A AB

(B15 Fig J.13.1 :

Logic diagram of l.HS of

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 Digtal Logie &COA (MU:Sem. 3-Come) (3-18) B te
Table 3.13.11:Truth table for Demorgans theorem
Dgtal LoOic coA (Sem.3-Com) Boolean Algebra and Logic Gates

Tabe3 od
NOT
M 3.14 BooLEAN FUNCTIONS

4 3.14.Wat B0olan funetions ? Explain

how it can be rnprtsented wsing
OT
Algebraic equation
(814 Pg. 3.132: Logie diagram of RHRS of
Tth table 2. A+BC

hus, ABA+B
Hehice proved Ans.

0
o-100
1 1 ADOpuon theoremes
Booican

n
agebra compises o logic operabons and binary

**
o
Combinations

mbnors
Theorem 6e): Absorptlon ODefinition of B00lean function
expresion : An
that s tormea using binary variables,
and
A+ABA
operators, NOT, AND, OR, partntheses and A Boolean huncbon can be translated / transformed from an
Thus, A B-ÄAB
Proor o pic dhagram comprising of
Hence prvved. .gua tco 1gn I5 called as a Boolean function AND OD

A+ABA-1+AB (A-1=A postulate 2(b)

For agven .

heorem DO): DelMorgan'o iheorem value of variables, the value ofa Boolean Fg 3.14.1 shows the logic diagram for A* BC. 1be
A+AB A+B)
DeMorgan'a theorem2 tA (8+C)=AB + AC postulate 4]
Tuncuon y coprs a
OT gaie for every variable in

****-----.-- 45.14.1) BalE lor combining the terms in the Bookaa corsti
Definition are used in A*AS A (8+1) (.A+B«B+Apostulale 3(a)
: DeMorgan's theorems

law states
A*AB= A+l theorem 2(a)] Bookean
D0Oean c
Soolcan algebra. AB= A B. This postulate 2(6)]
ncD pressi0n

ABC
AB. A
that the complement or the Proauct o
A*i5A
Hence proved.
vanables Is cqual to the sum of their self;
Th
he tunctson =1ifA=1,B =1 and C=,
&D); AD8orpion otherwise,
he Lis ot he theorenm epresents NAND
BE w mpus AA B)=A The Boolcan function F, is an example
sm Pg 3.14l: Loge dlagran for mplementaton of
A and B. The RHS of the theorem of Boolean function
epresents OK Y-A BC
coplienented inputs. This OR gate is called as "Bubbled
Proof epresented as an algebraic equaton.
A (A+B) = A-A+A-B The Boolean function can abo be reprsented with the belp of 3.15 BOOLEAN FUNCTION
hus,
u Depending cn the number of variables in an REDUCTION USING
NAND
(A(B +C)=AB + AC postulate 4a abe
Babbled OR DeMlagan s ueore a truth table has BOOLEAN LAWS
ACA B) A+AB
epression, 2 possible combinatioes of
We will prove this using logic diagram
and DEMOTga
AA=Atheorem 106)] nputs whieren is the number of vaniables in a Boolean
theorem. A(A+B)= A(1+B)
paession. ExL 3.15.1
LHS
A B+C) AB + AC postulae
40 Prove the following Bookean expressios.
g or3 variables there ae 2 = &possible combinaskon of

A AA+B)

AA+B) A
= A*1
TA*l=ltheorem200
IA-l=Apostulate20)
nputs (1's and 0's), ie, there will be 8 ows in the tru A+ AB. A
AB)A*)A+BC
2 A*AB =A*B

816 Fig. 3.133 : Logie diagram

Drmorean'e Ans.
RHS of h provca. he umber of rows in truth table is equal to 2'. For every1. A AB = A

A umma possibie combination of inputs, the value of Boolean function uSA+

LHS

A1
AB- A(l B)
(1+A=1 TDeorem 2a) ldeniy law)
whe Evaluating Boolean expression the oper A (A1=Apostulate21b)
A*BC (3.142)
precedence is,
' RHS. Heoce prove
arentheses pate The tuth table for Equation (3.14.2) is showa in Thus, A + AB A
AND gate
NOT Table 3..14.1.
(819Fig. 3.13.4 : Logie diagram of RHS of
nogaD heorem
Teeh-Neo Publieations Veotare
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A MCEIY SZAr
here Autbors inpue AnaoaUD
 Boolean Ageb
nd Lpgle Ga
Digtnl Logic & COA (MUSem.3Como
C(AB+AC -AB eDigital Logic & COA (MU-Sem. 3-Como) Agebra and Logic Gates
2 A[B UEx. 3.15.4
Boolean
2 A+AB A+B AU-O. 10. May 17.2 1Marks
LHS A [B+C(AB + AC
Loge diagTam (Refer Fig. Ex. 3.15.5) Inle
LHS A*AB Prove that A poIVE gAND Operatioa is equivalent
[B+C(AB AC)) to a
(A+AB= A negaive logIC OR operation'
A*A (A+BA-B AD BC
DeMorgan's la
Ans. For provngA poitive logic AND operation o
BA*A equivalent to a Degauve oge r operation", we will use truth
A B+CA+ B) (A + C)
(A+Al postulate S(a) Compleioentation la Truth table for positive
(. AB =A +B DeMorgan's theom Tnh table tor ne gane
logic AND operation (e Piz Er. 3.155 Logik diagram of (Ex. 315.5)
:

Hence provcd Y A[B +C(A+B)(A +) A =A)

Thus AA
A[B+ CA A+AB +AC + BC)) ABAB A B
AB 3.16 NAND GATE AS UNIVERSAL
ABC Y =
GATE
Y -A [B+C(A+ AB + AC + BC)
A A+A-B A-C+B-C
Y - AB+AC (A+ AB+ AC+BC)
4.3.16.1 Prove sing Boolean alaebra "NAND
A+A-B+A*CB* gate is unversa gate
Idempoieike law ineoren 0 AB +A -AC + AC- AB + AC- AC ACB-C
A*AsA
postulate S50y nsprve
Al+B)+AC + BC Y AB AA=0 Similarly A negalive logic AND operation is equivalent to O. Ta), Dec. 17,210.0 ay 1
A+AC+ BC UExX. 3.15.3 MU-O. 2bIÖ). Dec. 13. 5 Marks a

posiivelogc O Dn0
.A*lTheorem za) ey Simplity the following Boolean cxpresslo UEx. 3.15.5 MU-O. 10. May 17.2 Marks e NAND ate is caled asDaiversal Gate because any
A(1+)+BC Y-ABC+ABC +ABC+ ABC Simplify (B +A) (B +D)A+C)(C+ D) ecphession Can De Implemenied with he heip ot NAND
AtB gales. we wil implement all the basic gates with NAND gate.
A+leI 1dentity law Tbeorem 2(a)) Ans. : Ans.
+ ABC
3.16.1 NOT Gate (Inverter)
RHS
AB*ABC+ABC Y 6*D)8*AJA +C){C+D)
icnce
idenpoiencE aw we wil 3dd two more ******-****
(A +B) (A +C)=A+BC A A*A A Dy
ABC tems
Y B-B+B-D+AB + ADI [AC + C.C+AD +CD] 4. 3.162 Iplement NOT gates using NAND
Y (B+BD+ AB+ ADI [AC +C+AD+CD] . . ********
Ex. 3..15.2 Y = ABC+ ABC+ ABC +ABC+ ABC+ ABCC
Theorem 10b)) Ans
APPIy Deorgan 5 thecortim to olve the following
**A Fig. 3.16.1 shows NOT gate using NAND gaMe. A NAND
(A+BC) (AB + ABC)=0
Y ABC+ ABC+ ABC+ABC+ ABC + ABC
BD) + AB + AD] IC(A+1)+CD+ AD)
1.
guteo
ogether. Both the
inouits of
e A cng s inputs

2 A[B+C(AB + AC)) = AB
Y BC(A +A) + AC BB) + AB (C+C Y = [B+AB + AD] [C+CD+ ADJ
conected
Input= A=R=
Ans. : Y BC+AC+AB (: A+A=1postulate Sa A*l=lTheonem 2a) ldentity law)
AD] [C(l+D)+ AD Output
1. (A+BC) (AB+ ABC) =0 Logie diagram (Refer Fig. Ex. 3.15.3)
)+
Y (8+ AD) (C+AD) A A (A-B)
LHS = (A +BC) AB +ABC)
A+l=ATheorem 2(a) ldentity law) A AA)
(A BC) (AB+ ABC)

D
Y = BC+ ACD+ ABD+AD AD
ABA"B by DeMorgan s theonem) oR BC Y BC+ACD+ ABD+ AD NOT
EA

ABC(AB +ABC)
C-A Iavolutsicn
lw) AA=ATheorem 106)) (812 g. J.l6.l iNOT ate using NANDale
ABC + ABC* ABC
B Y = BC+ ACD+ AD(l +B)
a 3.16.2 AND Gate
0+0 CA:A=0postulate Y BC+ ACD AD
56) (82 Pg
13mplement
E. 3.15.3: Logie diagram y =AB + BC+A ANp gates using NAND
hecorem 2(a) ldentity law)
Thus, (A + BC)AB + ABC)0
BC+ AD (C+ 1)
A*I
A ns.
----- .----------
Y= BC+ AD A*l='
0eo Fig. 3.16.2 shows AND gale uSing NAN

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 Bocon Logle G
oCsan A
Digial Loie& cOA Sem Sp. = Boolean
expressa0m for ue oK gae s
Dital Logio ACOA (MU-Sem. 3-Com
The Boolean epressuonor Circunt Shown Ou

Y *A A B Fig. 3.16.546) 1s,

3.16.3,
BO0ICAN Epressi0n for FiB
Y A*B A=A) AB-AAB
Y
apl 316.2:AND gate using NANp Y A
B Y A+B (AB-A+B DeMorgan's theorem
AB
To construct n AND gate from
NAND gles, we Deed
Y A+B ( AB =A+B DeMorgan's la T AB+
1beorem
inverier or NOT gie t the ouput o NAN ruth tablee A-BaA*B by DeMorgan's
cances outand inal ret A CA=Alavolutioy
eno Y AD
Tr
tor NOR pae
Trath table for NOR ate
ustng NAND pates
. Y AB AB (:=A lavolution law Theorem 3)

Truth table
ne Boolcan epression for AND gade is equadoa or ExD
realizatiom using is the
- AB Table 3.16.2: Truth table for OR
NAND Truth tabies
Tbe output expression of Fig .16.2

AB-AB AAbeorem 3 involution) Truth table for -0R ga

Truth table
for sing NAND
aies.
table
nus, we can reaize NoR gate with NAND ga
Table 3.161

s, we can see unat OK ge Can De reallzcd using 3 NAND &

4.
3.16.5 EX-OR Gate using NAND Gate
3.16.6
A
mpleent EX-OR 9gates using NAND
o oupolol
a 3.16.4 NOA Gate -******* --

0 Ans.
Woloi||0
Iplement NOR 9ars NAND
From the tnuth table also we can see that NAND gates Can be
3.16.5
.
ates ony
i
.. The Boolean expression or EX-OR gade 15,
Thus, we can ealize EN-OR gale using NAND gies.

connected to perform AND functioa & 3.16.6 EX-NOR Gate Using NAND Gate
Ans. Fig 3.16.5 shows the implementation of EX-OR gate using
alized using NAND gate by adding
a a
3.16.3 OR Gate
e
utput of OR gate realized using AND
asic galcs ana E
.3.16.7 Realas 9 AB A8 sing NAN

3.lb.4shows NOR gale using NAND gates.

3.16.4

Ans
logic.
Reala exclusive OR gate sing NAND g

oR ABAB
Ans.
T9tes
-
+
-- only.
9Nd.May 15, 2Marks

gate s,
LnE BoOcan eapression tor Ex-NOR
the coastruction ot an ON gaie usng thiee
.1.3
NAND gates.
hows
AB
8e- B
gS..0a)
As*
snows e mpieme nlabon or EXNOR 8ae

(8 Fig. 3.l16.5(a) :
EX-OR realization using AND-OR-NOT E DSes
Eals A
B Do
gg, J163:OR gaie using NAND gates
AS
o NOR gate
( NOR gate using OR and NoT ga B
The Tint wO NAND es invEt A and B imputs to produce . 3.164
opus A and B.
The Boolcan expresion for NOR
gale is, A
The outputs are applied to inputs another NAND
gale to Y A+B i EA-NOR realizalon using
obtain the OR function. Thus, by using thrte NAND
gates we The Boolean
J.16.4a) is,
expression for diagram show B- 18Flg, 3.l6.5t6) EXOR realizaton using NAND
:
s
a S.l6.0qa)
AND-OR-NOO gau

A SACHIYSAAR Ventue
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A
 Digtal Logjc & COA (MUSem
So) Digtel Logic & coA
MSem. 3Como) Boolean Agebra erd LogeG
shorws inplenenaion of EXNOR gte using 3.17.1 NOT Gate (inverte
aS16D)
AND
. 3172 Construct NO9 Sng th Truth table
Module

Truth table for AND pate esing D

Ans. A NOR
uning NOR gale.
3.171sbows NOT ge
all its inputs together.
can be used as a
o
Boh the inputs of the NOR gate art
connected.

e 3.164b): EX-NOR realizatioo udiag NAND gates Taput

AB=A
The Boolean xpression for irauit shoun
R H
3.16.606) is Y A+A
e ng NOR gades.
YABAB= Y A (A+A»AThecorem 1(a)
Y AB AB s 5 he epresion for NOT gade. Fig 3.17.1 shows NOT a 3.17.3 OR Gate
OR gates using NOR --.
(by DeMorgan's Theorem A-B =A+ B)
.2ent
YAB +A-B NOT Ans.
(A=A lavolustion law Theorem 3) qB) Plg, 3.17.1 :NOT ate using NOR gale The Boolcan expression for OR gae is,
a the equatio0 of EX-OR gate.
AND Gate Y A*B
ngn tables
3.17.2 Fig. 3.173 shows the implementatioa of OR gale using NOR gates.

Truth table Truth table ftor EXNOR gate

forEX-NOR ng NAND gates

Ans.
- -- ****---
A B AOB y he Boolcan expression for AND gate is,
UB)Eig. 3.173: Implementation of OR pate using NOR zats
AB-AB g
Y
3.17.2 shows implementation of AND gate using NOR The Boolean expression tor circuit shown in Fig 3.17.3 is

A+B
A NO
A+B (.A=A Involution law)

AB Is the cquation of OR gate

Truth tables
B
Thus, we can realize X-NOK gaie uung NAND gME.
ruth tabe ror O le Truth table for 0R gate using NOR gates
3.17 NOR GATE AS UNIVERSAL B4Flg. 3.172: AND gate using NOR gate A A+B A D
GATE Tbe Boolean expression for circuit shown in Fig.
3.17.2 15,

Q 3.17.1 Prove OR-AND cOonfiguration

Y*, A+B
equivalentto NOR-NOR Conliguration
AB
A+B=AB DeMorgan's Theorem)
o
AB CA 1 Involution law Theorem 3)
hus, we can realize OR gale using NOR
Ans.
BO0Nan
NOX ale is calle asUnivenal Gale because any
eapresson can e inpienenied
1S e cqualhon of AND
aie.
gatesS.

wiuh the help of NOR

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 olean Algoba End
oic Gate
Drgtal Loe s cOA MUSem.3Comp Dgia Logic& COAD Gates
Fig. 3.16.00a) shows uhe implemendation of EX-NOR gate using basic gates. Fig 3.17.5 shows the implementation of EX-NOR gate
a 3.17.4 EX-OR Gate using NOR Gete using NOR aies.
. *********.
o went EK-OR sates using NOR f= A+B +A+B
1 Ans.
The Boolean expressioa for EX-OR gale 5,

AB +AB gaes.
sbows the implememtation of EXOR gute using basic
.

0Xay
NOR gales.
g ST.4 hows the inmplementation of EX-OR gale using (4Eig. 3.175 : EXOR gale using NOR pats
The Boolcan expression tor logic dingram shown in Fig. 3.17.5 is
A+B
A
v A+B A+B.

Y = A+B-A+B A+B-B eMorgan's aw

Y AB +*B lavolation law Theorem 3)
B Y = A*8)-A +B) A=A
4Fg. 3.17A: EX-OR realization using NOR ptes AA+AB+AB+B-B=0+ B» AB»0 A A-0 posmulate Sb))
Fg. 3.174 is,
ne Boolean epression for logic diagram shown in
Y AB.B
y.
s the equaliom of Ex-NOR galc.
A+B+A*B
Truth tables
Y = A+B A+B (AA lnvolubo
Truth table for X-NOR gale Tuth tabe o O
YAB+AA-B
AB=AB DeMargan's Theore)

C: =A Iavolution law 1Theorem 3)

Y AB+A:B
is the equacion of EX-OR gate.

Truth table

A+A8 A BAA Ulo|o| o

Chapter Eads

hus, we can reallze Ex-OR gate using NOR gaies.

a 3.17.5 EX-NOR Gate using NOR Gate

***

Ans.
The Bookan expression for EX-NOR gateis,

Y AB+ AB

here Aotbars inspire innovetio S4CHEY SHAH Veatur

Tecb-Nee Publications.
 nnoArchitoch
Digtal Logia & COA MU Sem sComp 42Overiew ot our jtal Logic & GoATMUSem.3Comp) ot omputer Oanaton BnA
Oevew
W 4.1 oVERVIEW OF COMPUTER rganlzatlon of computer Atlevel2:CPO structure 0v) Internal bus: Tbe communicadon between coatroi unit ou
ARCHITECTURE AND 4.1.2D okLevel Description or The ALU and regsn happets uugn net u
There areuan DuEral componends
ORGANIZATION Functlonal Unlts t controls At Level 3 : Control Unit Structure
Coiron all the component by sending ou

4.1.1 Introduction Complex mactunes ke co sg Ceneraly contirol "

Cutes
hierarchical moe (
petie and kogc unil performs data yprocessing
uel 1here is struci icheovErBs functionality the cou
control
a414 Define the terms compu and their descnpaoa, Ate
roonnections of compoIELS And
some

GH) Registersi 1bese are enporary storage mer uons e

wnict0 gOVErUS te rupctonality of
of the

.
emerm
organgation and eomputer ices of individual component jasidethe CPO.
1arctectur . h eacu iemet o SuUcture and Tunction of
Multlcore Processor Structure
The term computer architecture and computer organizañion is Twuter,

USUy Sed inierchangeably but there i5 some distinction between Level Mothertoard
DOdh e ies ruenure
Lauer Architecture
r pEtspecuve that 15
his em 5 uSd
it deSCriDes o eeu
r ne inlemal Structure
mumber of processors Lt us
ow
compuler is

st ue aoe
descnbed with respectto

fomal, reeiser inctho processor structure and then proeenng win Level 2 n o dhipe

computer architecture is also called as Instruction set Single core 8trucu

titecture ( ComputerS
Compute System Bus Intarconie wve Cache
ouroraalzabon he compuier organzabon es L3
operabonaruns ana
descnbes

example conrol
eu etcdneu
signals, interface between computer and l 2

-----.------- --
UQ 4.1.2 Ditertntiatebrtween Compue
organzatIon
Lvl3 Contral Unit
and Computer RegistersALU
Pig 4.12: Malbicore procesor srne
Arctectun
-0. 1b), Dec. 15

Computer ay,15, ArchltectureCompun

0 1G. Dec. 16.5anks ea When muliple processing umts aE 1mplemented on single chip they ar
imed a core processing compuici.

At Levekl and 2 side core for better throughput. Cache memory is divided as
Na
: Motherboard and lts elements
Control unt instruction cache (l-cache) and data cache (Dala- Cache),
structure.
Computcr Architecture Computer Organization
and There are different levels of cache memones generaly caed

hardware compoentsa ehaviour oherr a singe a ngid board which bolds s LEvEIL, LEve-aa) an0 LevEkS
ekctroic npooents their interconoections. contains
and It unctions i here are majorty 4 busic functons hat a

form a computer systcm.by

ser ontol
Memon sockets and slots for memory chips, VO controiler chup, and conpuicr performs
rOcessr chup.
s *he intcraction deals with the Plg 4.11 Singe core structure
1

Toesr nep
t consist of multiple cores (ALU, Control
and gisters)
aDyiem. ARTEl 1: Computer structure element
undertandinaofh at There are main four structural componenls t
ible to connect external peripherals to
VO chip: It is responsible Data Data Dota
unctionalities al sysiem arrangement of units in the the computer.
cir enira Processing Unit (CPU) : I handles the data

4. A Or
nereas
e computer. A level S: Core Structure Fig 4.13:Punctions
pESES 1

ahitee
ganization
O o e s useu to $10re prograrn and dala. logie this section in coe is resposible to fetch
nsruction decode and calculale operand etNOy
4.2 VON NEUMANN
addressing modes and Qinpuboutpul (Vo):tis used to communicate between struedaon,isiruton
ARCHITECTURE
computet aDd eAIrnal ocalions.
environment
5.While desgning Arithmetic and logic unit : This section operales on dala
compuler
An
system the
organization is done on
basis of arthitecture.
) syslem lnterconpectioD : All the above components 1e.
according to the specilied operaluon.
The Stored Program Concept
CPU, memory and vo are connected through
conduu Load Store Instruction : This section handles the ransfer
oU 421 What stored prpgram concept
first wires called a systems bus data from and to main memory through cache
I
digital computer
Lache Memory Usually small and fast memory
: is built in
15.3 Marks
Tech-Nee Publications- bere Autbor
0101.May
Mpure inaeatioe 5ACHIY5ELAR Vevture
A
A SACHIY SuH Yenture Tech-Neo Pablications.-Fbere Authars iapire innoratioa
Dtal Logic &COA (MU-Sem. 3-Come 44)vesnew c lect
4.3 HARVARD ARCHITECTURE
ie n Ceees te idea that the instrarbions

in a benary form in order to perform a vanety of usks The name he arhilcunes 0 worid's
Harvand Mart 1
l cHAPTERR
U euy cu ckualo
memory
es oeparale

auie yce
ctu Fmgram)
msrucn and dala

For beter efhicieney and hgc

a buses
5 Data Representation and
TtiOns could be mod his rchitecture is more stable
fo 2Modaule 2 Arithmetic Algorithms
e computaboaal results. ineliming and faster execudon.
r therefore used in this concept for shon
i miermedae sorage of andhmebc and ogr oaa
Unlversity Prescribed Syllabus
progran ceEp gave ne ko the Van Neumann
Data Hepreentauon and
At Arithmetic Algorthms

Byain
************* *
**************
von euaA archtacur in g4: Hanard architecture
2.1bunay
:
Aodnn, Subtraction, Multiplication, Division using Sign
ICD and ex ANUneBcOperon. Magnituxde, 1's and Zs complirment

22 Booths Muiplicabcon Agorithm, Restoring

i.. -tauN00. Ta).Dec. 16. 5 Marks
UQ. 43.1 Compare Von Neumann architecture ** 2.3 IEEE754 Floaing point Hepresentabon,
and Non-restoning Civision Algornthm.
sachitecture is narmed after the machematician John Von and Harvard Architecture.
Neuann. wons oo he concep or the stored progran
was first impkmented m the year O n
-- OaY18.SMarks 5.1 Data Representatbon and Anthmetic
This archiecture relies on three Algorthm.
kty concepis an Neumann
An Arhiecfure 5.1.1
aihed memory for data and progr S
nfeger Data Computabon Addibon :
and Subtracton of Signed Nurpen
Acubon of program, In this architecture only one n this architecture two
5.1.104)Fastaooer
. memory with umique adiess location.
421 memory is used to sore both separade memones are used
5.1.1(8) Cary Look Ahead Addition ****
eumann
Uc coeptual and basic stracture of Von data and rogra sonng data And program. 5.1.2 Mulbpicabom: unsigned
architecture
Or can be 5.1.2(4)BootnS Algontnm a
Mupucauon.
The data and codeb areAs the data and code can be m
feched sequentialy
s
****
Inified the Ua.5.1.1 Explan Booths algorithm with an example.
Processor Programm the exerution is slours MU-0. 201, May 18, 0 16). Dec. 18.5 Marks
NE ENECUuon is slowe. Ua.5.1.2 Draw the flow chart for Booth's algorithm
Data Bus for two's complement mubplicanon
ta Memary
AOZaMay 14, O. Id, Dec. 14. 0. 1a). May 15. 0. 21aX. Dec. 15,
O.20). Dec. 17,4 Marks- 5-5
ns pe or actiectaure us pe of architecture is Previous University Paper Ouestions
ig 421: Von Neumann Architecture

tsupports lower degree

VExX.5.1.1 (MU a. 3(@), May 17, 10 Marks)
Central rocessing Unit (CPU) : This clement is the beart ott supports hgher de gree of
. rchitecture, wich has major rwo paralle lism. parallelism
DEX. S.1.2(MO-a.zaX0), Dec. 17,8 Marks).
uEX. .1.3 (MO-0.21a), May 18, S
components VIZ Conrol Unit (CU) and Arithmetic
and lope Marks)... s -7
UEx.5.1.4 (MU- a. 5[b), May 16,10 Marka).
-7
OEX. S.1.5 MU-0.Dec. 16,10 Marks)..
D),
Lapler 7
Ends UEX. S.1.5 (MU-0.20X), Dec. 15, 6
Marks).. 5-8
DEX. S.1.7 (Ad- 0. 26), Dec. 14, 10
Marks).. -8
DEX. S.1.8 (MU-a. 2(6), May 14,7 Marks)...

.1.3 nteger Division..

a.5.1.3 Explalin the restoring mathod of binary division with algorithm.

U-O 26, My 16 5 tlanks 5
u. 3.14 Draw he flow chat tor restore Division Ajgorithm IL.0.2a0. May 17.5 Mauks.. 9
OEX. 8.1.9 MU-0.2b). May 15. 0.2010, May 17,61anRS w *******
 Dgral (5-2) D n Algori
LagieCOAMS
Digital Logie & COA (MU-Sem. 3-Co
UEL. 5.1.10 MU.0. 216)., tMay 18. 5MarkS).
Data Represantation and Anthmetic Agorithms
S.1.36) Non- Restoring Dvision.. 1 5.1 DATA REPRESENTATION
AND ARITHMETIC
a.s.15 Draw liow chart lor non-restonng cson The combined circuit is called as full adder

5.1.4 Poating Point Arithmetic..u

******* ****** *******5 ALGORITHM
5.14/4) IEEE-754 Standad. This unit performs
AU- O. 116, May 15,5 Marks *tunumelc ad logical operation d
16 Explain IEEE 754 floating point representaion fomats. 12 dala operas
tor 82 bt single tormat and 64 bit
a.6.7.7 Show IEEE-754 standards for Binary Floating Point Representaton ts an cieeu
onen ach is based on simple diptal
double omal. o stonng binary digits and
c
14.3 Marks0. el. Dec. 15.5 Marks O.Sb) May. 10 Marks.
May 17, operations,
LAUO. 1, Module
sianals
Dain IEEE 754 standards for toeing Point number representation Ar
and
MU O 21G May 15 6Marks 12 Fig S.13: Lope
perang Resuit
ua. 5.1.9 In toating point representation how io identily sign of exponent? MU-O 1ek Dec. 17.5 aarks
Previous University Paper Ouestions
UEx. 5.1.11 (MU -a. 1(b), May 18, 10 Marks). a5.1.1 Integer Data Computatlon: Addition
UEx. 5.1.12 (MU a. 10b), May 16, 5 Marks). and Subtraction of signed (MSB) 8)
UEx. 5.1.13 (MU -O. 2(a), Dec. 16, 10 Marks).
Numbers
gSl4iCacade

.
Let us consider singe stage abdition
of an n bit sumber X

S.1.416) Anhmebe perabonsn

.
-
Thei stage bis are Y , he tuth lable is given as
For n bit

n ne
addition n stage cacade full sdder is used
Fig .1.4 the camy ot prevos sage for arded o
a. 5.1.10 Draw and explain floeling point aditon subtrachon agonm BE hs Conngurabion is calkd as b-bit npple
any aider.
MU 06B), May 19. 10 Marks. O. 6/b), Dec. 18. 10 1Marks 515 0 0 0 0 0
x
andy. plement
tumbers X and Y where

OmX*T,23 complement of Y is otained and added

Chapter Ends. *******
1 DA
The complete adde t'subtraction logic circuit is shown in
Fig. 5.15.

ut hasa asub inpu coetrol line. The ccntrol

set
0 1 1
the Y is 1's compkemented by XOR gates and set c
is to

1 1 1o complele the 2's complement ofT.

Tberefore according lo above output tbe logic for sum and n AddbuD

S,-,6i+ 4G nd 3,,6,*4

g S.151AddSub logle

Fig. S.1.2: Cireuit

A SACHLY SILAW Vestare

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Tech-Neo Publications Fhere Authors inpire ianonation

A
 s
ln above impke XY are applied
C ane
signal A, Y and Cg
applied.
83 Hepresentanon and AnnneDc Ago
delays a'ter the input Muticticacd
& 5.1.1(A) Fast edder
Multiplication: Unslgned
In the pple cay
cany bit Irom LSB er is propagaled fo MIBB
ition. u
posuo: t is deu 5.1.2
Multilplcation
Partil product
(PPO)

nal to propagate depends upon te

delay produced by logic gates therefore the cary signal
, s Let us consider wo n bi non nega e ue imben
can produce
muitplita. ne wo
n
produced un2 (-1) gale delays whereas g and T 1o be
D Ols
maximum of 2n bil result. o
NA sum bits re otaineo aier 2 0eys ge explainea using exaimple of 4
The above algonthm 1s
the delay through the XOR gates on the Y input
cadng Module
Therefore there is a peed of faster adder whch
u propugae number as X1101 andY=10
2
he cary muD ar
0c soch approach is camy look aead aoituon. Multiplier

5.1.1(B) Cary Look Ahead Addition

Paral 0
For fast operntion of adder circuit the cary signal mus
Product-1
EDETailcd which in turn geDerakons the sum ouiput.

ary out (C e
Partial
Product-2
P7 Pe - Po FrOGue

Partial
1 0 1 X

eynierAeialy O)
Bit of incoming product (PPI)
artial

Product 4
X X
BIS ot coming parial product (PPI)
g

wDere y, 5 generale and P propagale

tiplier Q
ddiNoado
generase and propagate functioms are calculated parallel in Multiplication in binary is simple as it has basic three steps:
c gae oclay. Fig S.1.6 shows the implementation of
ook ahcad addition. Step 1i f the mutiplier is 0 replace the all multiplicand
ypical cu

ontrol
gy puer suhet wnle the cer
mulbplicand dipits.

Step 2 : For cach mulbplier bit posibon shift te

ulupucanu
malplicand digits appropriaely for eg. for 3" ro F. 5.1.8: Multiplier
oKAnead Logc
Ue
E Bts of oulgoing partal product (PPd+ 1
purual proxuct parual prodUE3)
5.1.2(A) Booth's Algorithmn
multuplhcand number is shifted two bit position.
Aray implementation
6) S.1.7 uQ. s.11 Explain Booths algorithm wth an
Sep 3: Finally each all the partial products are added Fig. :Arrny mulupluer
generaie the final product. Caple
The basic components are full adder and an AND gate which
detemines whether a bit is to be forwarded or a 0 is to be LAU-O. 201 May 18 O IDL Dec. 18.5 Marks
Bit wise Shifting the Adding resut
all
mutiplication Dartial resut 0arial orwarded. UQ. s.1.2 praw tN fow chart for Bootks
ach rows partial product is shifted to next level for addinoa algorithm for two's complament
if the muliplier is a 0 then partial product is vertically shined
Fg 3.l.7 shows the actual implementation of mulupucau downward by shifting I bit position at each level.
wultiplication
Inside the processor the adder circuit is used for AU-0.21)lay 14,0. 1t0). Dec 14
multiplicaion for a number of sequential saeps. 0 1d. May 15. 0 21aX0. Dec. 15
Teeb-Neo Publications -Bocoth's algonhm is wudely used tor muluplication and
here Authors ingin
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SACHIYSHUH Ventare
here Authors inspire ianoratioa
 Data Represento
gorithm Digital LOIE A
Sem. s-Comp) is in2icompiement tO
holds upper n bits including Me Table Ex. As MSB =I the number
0. Register A 111001010
faster result compard to on holds lower n bits of the resu
O
apprua.
*
Vdes and Kegisie
A
Acto Initaization
g depcts tbe tiow chart ot uc Upper pat Lower part
50000011011 O001 10101 00110110,-ho
Resut
Step 1: laidialize te registers i.e. place the mulpier 1 101 0AA-M
multiplication UEx. 5.14 MU-O. Sb). LMay 16.10 Marks
shit night
lso A andQ, is initialized
to zero. (ApFlg. S.1.10: Resault of
411001010 Aritmetc Multiply (-10) and -4) using Booth s
agonu
Step 2: The coatrol logic scans the bit of the mulnplie 11100 10110: Athmec sht ng ln.
1s examined with bit is its oed EMmple
mulpluet Maleiplicant = (M) =(-10)% (101 10%
UExS.1.1 MU.0. 3ta) May 17, 10 Marks 0101001101A=A+M Muliplier(Q)=(-4)%(
Modnle
A Muliphy -5) and (2) using Booth 3Agontnm. Lnitializatio
and Q, [Anithanetic shift). *** Soln. 10111|101 AA-M A
= (00O00 - (11I00
St=p 22: If te of te ES%=(lo 11011 1010 Anihmetic shit ng .
.
wo bis are form. [O I Multiplicant

n e murupucant s suburie Mulbpler (0 Table ExL S.14

ton ( added). Or

shifted nght by I bit.

Instialze
0 (0010),
Rasu- A a Actton

As MSBT Uhe number is in 2's complement fom

STARI 1.1
II10111010 4 00000 01110 Ametc B g
A 1 Action
Initialization
's
o1000101
3000000011 Ahmebc shit nght

0-iniler 000000100 2's 01010 0011 AA-

n Count
00000001 Anthmetic shift register (00010001
10)%>E0a 2
0010100011 rimeoc shit ngn
0101 0001 A=A-M UEx. 6.1.3 MU-0, 20). May 18. 5 Marks
ocaion Booth's algorithm
o0010 10001 1 Aithmebc
AnthmecS
st ngt g
20010| 1000 Anthmatic shift registe (6)
using
o00001 010
M--9)Q
1101 1000 AA+M Soln. :
posia ve
1 1110 1100 ritimeic shitregister can9
(10111 As MSB 0 the number is

Arlthmetic shit (001 10 (CO001010

Aaa, 1111O110 Arithmetlc shift register
aitializatio UEx5.1.5MU-O. 56), Dec. 16.10 Marks
count
LL Resul A 00000)* Q(00110)
. Multiply 7 with (4) by using Booth's algorithm
As MSB=Ihe numer is id & Sconpliement toena
0. a 05 Multiplication
Soln.
Table Ex. S.13

ves 0000I001
n A
1 Action ulbplicant (M)
Multiplier=(Q)= (4ha
=(-7)o (1001)
(

END Initializacio
(00001010), 4 0000o 0001 Aithmetc shit nght A (0000) Q (O100)
(0APg. S.1.9 UEK5.12HU-O. -0 01001 00011 0 A=A-M
Note ine proces s sach thatthe
The sbifting ing Boot's dgorithan 2a). Dec.
c 17,6 Marks
17.6 Marks
nupty
kfhunot bit o 14 times-5. oO100 1000 1Aithmetc shit ght
retainedaand a
shifting is
on Soin.
shifting knoun as Anthmetic shit right
of is knowa Aridmeic Malplcant (M) = (14)0 (01110 200010°
*%%=(01011), 11001 01000
1
AA*M
Step: Deceent coNnt va Anthmelic shit nght
acnek u count cquals
10100
zero. O
A (00000
Sep 3.1:f (1011 o Aithmetic shit nght
count 0. Repet sep 2. O111100101
" 05
Result
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EA wabee
ASACHIYSHAH Veatur
ech-Nee Publications bere Authars mprT n
AALHAN SHAH Vene
 Algonij
Digital Logie & COA (MU-Sem. 3.Comp)
eOC6.17 LA0-0.2b. Dec. 14, 10
UEL
1Marks
Digital Logic oAMUSem.
comp)
Table Ex. 5.15 Boodsgonthm. fable Ez. 5
Mupiy(2a and (- S)jo usUng TART
000 O 1
0100
Action
oln. A Acton

Muliplicant= (M) =(-2h0(l110 4 00o Ializaion

Q-Dvident
30000| 0010 oAnthmetic shit right Multiplier (Q)=(-5ha=(01
Initializabion AA-M
2 0000 0001 Uebc shih nght 3 o Ameic shi nght

111 001 AA-M A 0h (0 O0T O0 AA +M

Arthmetic shit nght
-1
2 0001
O Anthmetic shft nght
Module
00 A*M
Table Ex. s. 2
on
00 100 110 AA+MM
0000 1011
1011
n
0A-A -M
As MSB= I the number is in 2's complement form 0010 L
t10o100 0010 1011 0

0101 Arhmetic shit ngh

0001 As MSB = 0 the number is positive
00O11011
me
01 AA*M
shit ngnt
D)
(O011110,F2he a 5.1.3 Integer Divlsion Fig. S.1.nb) : Plowchart of divson ireslorning)

e T 10101
s-28
Aswer
1111 0101 Anthmelic 8nint ngh
5.1.3(A) Restoring Division The pmcedure starts by laading the dividead and divisor

E16MUO. 200. Dec. 15.6 Marks

Using Boohs lgorithm show the mulriplicañon of - 3-7.
0010 01010 AA-M AS
Fgsier and M rEspezivel

Soln.:
0001
O0 10101
A
Anthmelic shit right uQ. s.13 Explain the restoring method of :
binary division with algorithm
K AS ntlized o U
-6NE QEgsier (Qucocal) e rul
and n-bit A tgser
of divsion is placed
(Keminder).
Detailed siepwise procedure is as follows
Muliplicant = (M) = (-3)jo(1101) MU-0.21b1.May18.Sanks
Step1: Load rgister A with 0's Q with divideod and M
Multiplier= (0=-7j0= (1001)h number is positdlve
D0he S.1 Draw the low chart tor
store
niaainzaO Step 2
DIISan Algorthm
Aaswer is +10 Step3: Regiser A is (lulnplicaar) and
A*C (O00D, (1001), The dmA
the result is suored in A.
4 UEx 5.1.8 LMU-0. 26. May 14.7 Marks
Using Boodr's algonthm show the muluplicalnon or x3.
. Fig. 5.1.11 shows the hardware implementation of restoring Suep : 1. fMSB of A rgster is '0, then set Q =1.
Table Ex. 5.1.6 r NESB ot A
Soln. division and dhe lowchant of the process tder shen O0 and

n A
Action4Action
Q
Multiplicant= M) =(0=
(011 Step S:
restore the value ot prtviousA
Repeat the process as muny times s there are bit
40000 100 niualzaon Multiplier = ()= (S\%=(0l101
Taicialization Sep : e resut or aiisda s storeu as
0011 1001 A
A-M
Remainder
3 0001 1100 1Arthmetic shift rght
A = (000) (0101), Quobeat
Muupuer
1110 OEL S.19
n 04 ADONODD
Conira ATU-O.261.tay May 17
211110110 nthimetc shit right Contr 15.0.2e.
Using unsgned binary dvaoe meto, divake by
Marks
6
Aithmabic sht ngnt
MUx Sequence
OR Dvide using restore division method 73.

O0010 A=A -M Multioliand

Sol.:
AEnmeic ng Dvident=Q= (Ma=(011
(A) Fig. S.1.11a): Hardware implemenlatioo
Divisor = M = (3)a = (0011

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-A SACHIN SnUI Vena
 nebc Algo
e
Diotal Logie & COA (MU-Sem 3Come Digtal Logc & COA (MU-Sem 3
Representabon and Antime0CAUOUL
Step :Table Data
Saep :Oain 2's complement of M Flowchart or hon-estoring divlsion
Hesuit
011 11001101 A Action
MS8 o registcr A 0. Hence shilt leit and. Subkract A

Sae 2:TaNe 40000 011 na romM.

1110 Shit A and to ieit

0000 Divisor Regster ARegister
PA 0000 10001
40000. 011 nualizalio
Shit lert00001 00 OCye
100 0 AA-M
SB
Og-0 1101 00l Module
0000 A=A-M

A
Shit let 1
1100 00
Shit A and0 to lett Shi lt
30001 1100 Ca0 0111100o
0001 AA-M LAA*M
0000 10Set Q,0 Restore A Shit left 1110o Thied
I100
to
S 1
10Shift A and Q let 1101
ct C,O Restore A
i00
4EA-
00 Shtieno000O Fu
e
.. 1111
1 00 1

001 L
emainie
100010
1111 O00 AA-M_
1101
ooon 001 100Set ,=0 Restore A razFlg

AEA-M 5.14 Floating Point Arithmetlc

O111 To represent large range of integers and smal fractiona
0001 SnuntA ana to left svstem
mast use mumbers with variable posidion binary poind
1100 numbers. Such aumbers where the is called tkoafing point

1101 sumplicity he pont posIDOa

pieenbo
iO0010 AA-M_
Restore
Lo1 001 Set O=1
RemainderA=(001Dh
must be fixed eg the point is placed to the ight of the firsd
0001 0010 Set = O
Q-0Resiore A =0)» (A1Fig.S.1.l2 cn-2ero sugutcanl dgits
Remainder A = (001), =(Do Quotient-Q(000 rmalized umber
Folowing sIeps are pertormieu on-esnng g 10-10341 x 10'-7.3000x 10.
in
6.0247 x 10". 66254 x
uodient=(0010), = (2)o T MSB ot A is 0, shaft A andQ gister
ETS1101MU 0 26.May 18.5 1Marks
a6.1.3(B) Non- Restoring Divislon Step 1: 1.
eft and suburact M from A, olherwise sat
1 bit
as sig e
DAvO ***** and Q left and add M to AA. simificamt digit and the exponent in the scale factor.
(a by (9h using restoring method of binary division.
Praw flow For non-restoring
5.5 chart Hence to represent a oacing point eumber there elements
Soln 2 MSB ofA is 0, set Q to I oherwise, *i d 5.
.avision must be use
Divident Q)%= (011
orithm
****** arer
Mantissa (siguificant digt
elimin her need estore A Kepeut sicp ern uns
Dvisor Ma4%*(000h unsuccessful subtraction is ) Eupoecat [with scak iaztir
unaa wncn provkae yv pt Ater n umes it MSB ot A Is then add M toA or
Step 1:0Obtain 2's complement of M
in calculation.
E
(c) Sign [uga ot sgucat g pount aumber has been
nitalize the register contents S Dt epreentaion at doaing
(O100) 0011 100
.A devekpeu by IEPE ID choice of 2 bit
is docided based on
Divided 1000 (Register Q)
e sabard conpuier word length.
visor 00011 (Register )

Partial 0000 (Register )

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A SACHIN SHUI Veah eeh-Neo Publicalions. ere Aubars inure a
 12) Data HepresBU e Agortm Digtalogcs odA Sem. 3-Como) aton and Arithimeic Aug

be S2 bits are divded as UQ.S.I Bplaln EEE *taNdards is E: used to skore the sgD
the decimal number
0.1S626
UQ. S.1 In Hoating pont reprsenEation
numer Roating Point nuMDEpresentation eenied i
*
manuss providecs dagit decimal binary is D.00101, In the single precision fo to sdentity 4gn ot ePonentr
precision be reprEencO
(b) 8 bit -eaponent [to base of 985 D.00101,
2]
he EEE- wa pu 101,x*2. Inflonting peoint number epreentalion. Eponens E Dae
1 bit sign is
superseded in T98, erelorE preenieu eapone ns ae aeay
32 bi
sponsored by CMSC-Microprocessor stant pOstve umbers. due io tnis p
commitee.
Dumber represenabon.
be standard specifies interenange nals sExponent Mnts eu EE*
Module
Sign of exponent in mantissa fraction methous Tor nay tna
pogrammng envronnen
a nebe i
Pig. 5.1.16 nge ecEsiCa would beEE 127 wbere EIs
eaponet. TbeTetoe, we would get
Mased

o Signifies cOmpe oDeaG E B

Sgnines-Lv
The standard can be implementea e
bard ware or n any coo
ircly
e or i As illustraled in the
hg 3.1.16, the dhee helids in the
E-3127= 14
Double Precision woukd be E = E +l023 where Es
biased
***
we ou E
eapobent and E is actual exponent. 1herelore,
s as Single
he bove represcntation of number calld or binary and decimal floating-PoInt dala, fy
expoe D E--3+1023= 1020
prectian epesra computation and data inierchange. piased v* mben tual
wne Sale tactor he nnge ot
abovE
pproximatcly qual to 10 t 38 (2to 2
esenton
I
s
And 24 bit | puy o npare oher
Smge preison It is evident that for
exponcnt range is - 127
Sung
o*
0 to 254

nuabion. Similarty. for Double

operuons. inthe Basru
9. ers.
Conversions berwen intcger ant lioauingEpont tota
01111100 l exponcnt range is gven as- 103
in te Based
IEFE has increased the number of bits from 32 to 64 whichis
Conversions bew
-in double precision, the bias is 1023, 1020. t0o 1023 getung converted as 0 o 2047
allca as duubie precision unbet. raxdon exponent representaben.
T.n doOUDIe precison
exponent or
number the mantissa is rEpresented using emal reoresentaions as character sequences. Doubie FirE herefore, tbe sign ef the Eaponent can
be determined from
3 bis, bils and1 sign but.
Floating-point exceptions and tbeir handung. inc lading o n double precision lormal, Lsing unary base. te les therpresenied biased epooent a
I1. With above bits the total range of foating significant 52 bits from bit D0 to D51 are used to store s
dala thal are aot numbers (NaNs). For Single Precékn numbers -Epoeni *** "
a) Scale factor range = 1o 12t 2 he fractional pan
Manussa=
Ine stanuru species nve
s o
DOe ae uvcd to store
0
the 11-bit he biased eponent s having vaDE qual o
( 10 dcmu Tiree
,
binary formats, with encoding
and 128 brts
n lengths of 32, * EXponeni s **E, "
For >unge Vreaa bum ben
oBit 63 is used to store the sign bL.
Two decimal formats, with encodings in lengths of 64
"presenied
M
E-g he decimai number
100
th formats is represented oy as,
VE.5.1.11 MU-0. 1b. May 18, Mars
*epresented 10
11 bit eD]x[b']xm 0.00101,10 754 Nosting peint epresentaion
formats
heexcess 1023 manussa lrecion
here TLAAal
o loo'ol!!!!ID1SoloopoEplain
IE
is the sign bit which can take either I or 0 o ipo| o| epresent (34.2)%a 1o sungie precia 10m

so
S.1.15
bis the base for binary b=2 and for decimal b=10 ffaS|ILHILAAAT
e is the esponen Exponen
Step : Coaven the number to biary
a5.1.4(A) IEEE-754 Standard n is the mantissa Fig.S.1.17 For inte
The formal supports infinities (- ,+a)
Cwo and two Na the three fie kds ia the
IEEE o As illustraled in the Fig. 5.1.17 ,

UQ. S.16 Explain

754 foating point gNaN (guct) and sNaN (signalling)
TEEE 754 representahon or Uis u
reprsentation fomats The most commonly used precision in the format are:
D
ositive.)
MU-O. 16). May 18. 5 tdarks sign
Single precsion (32 bit)
exponeat value + "bias" Therefore the binay mumber s
UQ. 5.1.7 Show IEEE-754 standards for Binary Eponent
precision (64 bit) a
Dube precisic
(4.3 (00.
bit single format and 64 bit double inge Preciulon Die Step 2 i Adjusting the maumber in manusaa and exponent
format ge gninicant
prcisio ormal, using binary base, the icaut
1.0001001 X

3 Dits from bit Do to LDZL are used oa O11111100 Mantissa-0.0001001

MU-0. 1b). May 14.3 Marks. 1e 0.

he Iracuonal part 1.e. Manussa. Expooent05 and

----- D9Nd5: 0, 8ONay. 1Y, 10 Marks Next bits from D23 to D30 are used to store the
uble precision, the bias is 1023, 10
b ASACHIN SHAI Vesture
*poue.
npomalie
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A SACHIY SHun Veatue
 AnOtiC Algot
Dgital Logic & COA (MD-Sem. B-COm9 EN Digtal Logic & CoA MUSem 3Como)
Step 2: Adjusting the number in caponcnt and Mantisa D88 Representaion and ArneeAonnn
Step 3 : EEE-75- Forma D
1.0001 101 x 2 a 5.1.445) Arithmetic Operations . 0.029400x 10
e annssa Mantissa-0.0001101 The mumbeT is shifted right wth incremenng
Exponent-0 secunn ngn
This
L 127;05 23 bis
Siep 3 1
TEEE 754 Tormal
netc operations which
>et the txpunent orhe result equal o he ge
section deals with foating poiM
he p4
nunbor Exponent division and mmpicam.
0cA00x
132
000
.
Exponent 127+5 = 132
Perform adbos/subuaecticn on the maotissa o
O100 Proceaure 1or Badnonvsubtraction Step 3 :
(132)%(000 Ol00), Draw andarela
16, 10 Marks
x. 5.1.13 MU- 0. 21a). Dec. Precision
UEx.
inele and Double Precoie
11o
D plain loating ****
point 4.3100x 10
Sign Exponent adaition Subtraction algorithm Module
EEE-754 numbers.
AO. 5B May 19. 10 Marks
2
CL O00000000* 0001001
Soln.
4.394 x 10
bit
8 bits 23 s
Step 4: Normalize the resulting vabe. if necessany
single Preclslon P
UEx.5.1.12 MU-O. i i mantieta ioht mh A.3394 x 10 No need to mormalize the sume.
16 May 16.5 Marks e
Espressrepresena
Here 127- 1111111 and 0.125 = 0.001 in Binary number ditfereace in exponents The following ikowchat Sumnuns
in the 1EEE single precision standard of tioaluing
Dcess of ahfitionvsubtracton
Point 5ystem. eg. 20Wx I0)+8,3IO0x l0
Therefore, 127.125 = 11l1lii.001 in Binary mumber system
soln. We mormalize this number a 1.111i01 X
2
manfissa
Siep1:

For
Convert the number into binary in 1.M format is 1.111111001 whid
SUBTRAGT Ad Re Roun
inep means M
11ii001
630 (0011)
Furtber, the actual expone nt E so Change
For fraction part REUR
(0.25)o 01
Thercfore, biased exponentE =Ee*127=6+ 127= 133
L No Increment Shit
n B1nary number system
iererore he iniy numDCr s positon, iherefore, sign bil S=
1OOand Dumber &
right
No
oU01.01) ETOR Decemen
Therefore, the IEEE-754 Single Precision number representation of 127.125 woukd be
Y
RETURN

O0 o0101 as 111111 0 01 0 0000000000000 significant

L
Doube
e DE ouO >C2PE 4000 be gveEn

11 and 0.125 = 0.001 in Binary number system.

Therefore, 127.125= I111111.001 in Binary number system RETURN
We nomalize this number as+1.1111001 X2; comparing with (-1f 1M X2., we get
RETURN)
Normalized mantissa in 1.M format is 1.111111001 which means M = 1ilii001
Further, the tual Eaponcn Eo Yes
Therefore, biased exponentE -E*l023 =6+ lU23= I029 Repot
In Binary number systemE*
l00010 ad nuimber 15 posiuon, therefore, sign bil S=] RETURoeto
Therefore, the 1EEET54 Single TecsiOn Duner representalcn Dr 121.125 would be-
AIS,.

100000001 01 oo100000000000000000000000000
In Hexadecimal, the number would be gven as 7051 FC3O OUO0 0O00

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 Arithmof
hneb Alp
B0
Diptal LozeAcOAMS Procedure tor Dvis/on
an akd 127.
multlpllcation
Procedure foreaponents Step1: Subirkt
ueiens
sep 1 and sutkret
Add the Step 1: DhYIDE deicine thee sip cHAPTER (
resui

6
Step 21 Multiply the mantissa and deerinin
NOmne ue esung
value, if necessary.
StepJ:
theEulong valie, if bessy
mialire COM
Combinational Logic Design
2Hodule 3K
FETURD Unlversty Precrip
ponen RETURN

L o Exponent
overio
Repor
overt
Processor organizabon and Architecture
o 3.1 Introducbon : Halt adoer, Full adder, MUX, DMUx, Encoder, Decoder (IC leve).
Exponent es
Overflow opot
Mullpl

DOe
6.1 Introcducbon
a.6.1.1
owhat do you understand by a digtal logic circult 7 What are its diferent ypes ?
*******

Nomatze
6.2 Combinabonal Circuts...
Raund RETURN Nomaliz a. 6.2.1 What is a combinational cireuit ?..
(1420ig. 1.19 a.6.2.2 Explain the procedure for designing combinatonal circuits.
Round
REURN O.6.2.3 Why are comblnational logic circuits called as decision making creuits 7.
Fig. 5.1.20 .6.2.4
a 6.2.5
How are functions of combinaional logic circuits speficfed
Classity combinational Circuires.
7...
..Chapter End

. 6.3.1 what do you undestand by binary adders 7 Give their classiicaton.

D. 5.4.1 What do you mean by nalr &ooer T

u. 6.8.2 Design a ull adder using hat adder and addibonal gates. 1MU-0. 1ic,
May 14, 5
Marks.
6.5.1 Advantages ot ul Aooe.

u. D.3.3 What are he ul adders inputs hal wIl proouce oach of ne ouwg oupue

Full Adder using NAND Gates.. **sssarnstststamanesmeunmmsmautta pnae********aatapm wr*********am **************

6.5.3
a. 6.5.4
Design tull adder using NAND gafes..
6.5.4 Full adder using Half Adders
dircuit dlagram
ua. 6.5. How will you implement hull adder using haf adder7 Draw the
8iC. Dec. 19.51Marks.
O-0.
Design a full adder using half adder and
addiional gates. May 13.5 Marks.
u-0.G.
6-9
0.6.5.6
Diterence behween Hall Adder and Full Ao0e .. ****
rtas
adoer. lU Dec. 18 **aammtaana
d..6.1 State the diference beween half and ul ************ massssmesane"
8.7 Multiplexers (MUX)
wtntaa
 Digtal Logic& cOA (MUSem 3-Comg Combinauo
gtal Logic & COA(MU Sam 3Comp)

6.1 INTRODUCTIiON (i) Half Suhtractor (v) Full SubMractor 23 Why an comanatona
(6-5) Combinabonal Logic e
logic cirtuits The circuits can be ciassihed ino
BCD Adder comB
cOmbiabonal lope
()Binary Adder () callea as decision meki
4 s what de you udarstand by a digital (vi) Multiplexer (vii) Demultiplexer

y Ans.

- .. ogc cirut ? What are its

-
-~*****T
diterent:.
me.
The combinational cituits do mt
memoy &a
erd
outputs are dependent on the presemnpus ar ny tnstant
Comhinalicia g
dine n the lorie
combening the logic
Eat
gae.
one
1.
There are 3 main types of combinational circuts. They are
Arthmetic and logic Nnes
or implememti logcal functions we
he block diagram or a combrnational ci
The combinational
eh
logic cireuits
logkc
following combinational circuits
Digtal Logle Cireult e sing
individual g e y ee s decisin Adders subractor

..
caikd
C Block Diegram making «
Comparnos Lok ahead carry genenior
********
Defintion : A digital logic cireuit is a circut
a am ****** ata handiling/data transmisslon and recepon
: ER one or moE gates are compine Q. b oS O cOmbinatioral
combinarional logic cicuis used for daa handliog are
ertO ronm a complx switching circurt. pu Output *****---- .he Multiplexer 2Demulapkver
anaoES analbies
e dhgital logic circuits are aso alled as switchine rirrmits
circut Ans. he
ncos coDaonal 1opc curcuits can be S. Encoder Decoders

wolage eves ae
assumed
to peciheu un o 5. Parity checkergeneraio
Pg. 6.2li Block duagram ol a combinatlonal BODepaession
tnstantaneousaly from one value to another value.
opk direuit
Truth table code comverter

dal ope gales are the basie bailding blocks of a Combinational lopie circuis ar wed for implemening
ihey are used kgic circut can bave x bumber of inpu differenl code converters luke binary gay. B
hke moble phooes, cakculators, compulers etc. i digital electronic
devices.A combinational mumber output variables. There
variables and Y of are excEss 3 ec. lodule
The output ot a combinaboa ote cicut can be enpressed
E Cessieation combnabons.
6.3 BINARY ADDES
n ne ronu
The digital logic cireuits are classifhed as: rutputEvEyepeSsed ueen temset one
1npur w oupur combinalon, Each C epiession using Bo0kean algebra
expression is called as Boolean erpresion.
Cireuits
is te Inpuits x This
whtd wOu understand by binary
Loie The Boolean expressioa shows the operasion of te
---
8 Combinational logic cicuits can be very simple or complez
quentaal Logc Curcuts
aL22 Eynlai #he eneedare fa dee Omounau

DpuL
" -
adders ? Give their elassification
-*******************
W

:Q621What
6.2
is
COMBINATIONAL CIRCUITS
a conmbinational cireuit
? ....
-------
Ana
mbinationd cit
- -------- 2
he
n

truth able B
1abie
anie
Binary Adder
********** ************
***********..
Ans: Procedure for Designing Combinational te
combinañons of inpuls and the corespooding outputs. Defntion
coMDinationat
BinaryAdders
logic circars sea o
arE

peo
e
A combinational circuit can be designed using the following The graphical representation of a combinational logic circuit
eACombinational Logie Circulta E adein
using logic Batcs is callcd as a logic diagram.
FIg .3.1 shows the block diagran ol a bunary der.
O Deinition Combinational logic cirturs
:
art: Stepl: Define and understand the problem. ldentily and E2 Clare ohitileie
dehined as the circuits whose output depend5 determine the mumber of input variables avaslable and te ******************* *********|
Ans. 1
ang************ instant of time output varñables required. Combinatonal
Logic cireuit
9 Step I1 : Represent each input
B) Chercesc belp of symbo
and output vanapik wi

. The Jope gaics ae the basic bulding blocks of y

the StepP 1 Derive the truth table for deseribing u
Combinaonal circunts. onleal functlons handllng converters
eaonsup bween te input and output vanaDies
The name combinanonaB Block diagram odf biaary sdaer
combination o ex paa E * ua
Sep V Obuain the Boolean eapression
for evey c
gaml.6i
.Adders 1. Mulbplexers
A combinaional circut performs an operation that s or e input variables. Simplily e Subtract 2. Demuitpexers
The aubom operalon as pssuE coun
is
ogically assigned by: Booiean eprtsion tor ouiput vanabies. omparato 3. Encoder
4. Decooe
.r 3
.000
one bit u
(a) Bo0ean capressaon (b) Truth table () Logic diagram NgIe daagrn is drawn by implementing the
4. Look ahead
.7
01-lprxt
carry
De exAnpes or Cmbnaional logic Circuits are minumized Boolean eapressions 9 Generalc 3 "" 10} produce rwo bit sum with cary
() Half-Adders Full Adder Logic Devices
4 11=
cirnuis
g 6.22: Classification of combinatoaal
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 Logc & coA MU-Sem, 3Como na Looiet
2. 0) produce a sum whose length is
mepa 1o SUnm) and c (Camy
one it Da Sem 3Cor
a dhe operaion (4), the binary sum consists of 2 digits
ror Kmaptorcamy Howeer o n of the
ne bit we need to
hit
or
of the resu is caled as the Cary and the LS5 e cayC hree
resut is called as Sum
the
he types of Binary
no
ie e
half-sdders are
to d three bits with t
Adders a
Henee,
not kuADie lor ms
adders art
oa half-adder
addition.
notuse in
Half Adder practice. Full
2 ull Ado ne has Adders a
drawback of half-dde *
W 6.4 HALF ADDER 9ApP n OHat Adder
SAB +AB =A®B
Ca/ AB 1.
he ALU (arithmetic
..wkat do you mean by half adder?
(roga) K-map tor S
(u N K-map for Ce dder to compute the binary a computer s
YAns.
*********
Pig6.4.2
= A ®B=AB
Cay ar aer 1s used to make full addee m
wo bits.
O Operndon
(A) Hatf Adder Expresslon for S (sum)
AB 6.5 FULL ADDERS Ihefull-ade
Expression for C{ carry) = AB additdon of three binary di performs the

Defintion : A combinational logie circuitt at;

that *- 6.5
Q w gou mean by fall
. B Aong with previous carry C and produces outus
cowputes the addition of O Logie dlagram of Half Adder 0
adder ? StSum) and Cout
**°two binary
binary digit
agTs s
E
s Block Diegram
a HalfA A A UQ 6.52 Design a full adder using
and additional
half adder
gateci
8 Kmpsfor SSum) and Cout
Kmap for S(Sum)
(92
ANO C(cary)
JN:0.10,Ma 145Marks
Ahalf adder has two inputs Ans. BC.

LAA and B be the wo

and two ouputs
BC BC BC B Module
puts. 3
Lnput A is
alled as the sugmd.
(DpFig. 6.43i Legc dagram
realuzation of half
adder
Full Adder
Inpat B is called as **
he
the addend. (G) Logle Dlagram of Halt Adder Dehnition : A
combinational logic circuit
that
fwo outputs are S(Sasm) and computes thE addition of thrte
C(Cery Ung 5a5i¢ gëtes binary digits
6.4.1 show tie block diagram of a halr aier callead as a Full-Adder. i
binary
Hal sum) Inputs
r(B) Block dlagram
*********----
s ABcaÄBAB,+ABC
8
de CcaryOuputs
(0mFg. 64.l:
A full-Adder has three inputs and
two outputs.
S-
CABAB)(B AÐ)
Blodk diagam of haif s Ae)
sdder LeA, B and
inPrevious carry) be the three inputs
CA®B
Trth Table The two outputs are S (Sum) and
Cout (Carry). Fig 65.1
(:AB AB =
A9 B) EX-NOR opermtiona
Table 64.1 C(Camy shows the block diagram a AB AB A®8)
:Truth table of Hall-Adder akie ol tul
aomFlg 644 : Logik
realizatioa A S AB
of half adder using basic inputs
Inputs 0ut gils AderL"oputs om Fg 6.5.2a): K-map lor Sur
A Rs c.. Drawback of Halil-Adder K-map for C
.1i DOeK Ongram oa full adder
f we want to add
two 2-bit binary numbers A BC BC
A Ap and B=B,B% and B. La
(G] ruth Table BC
*00 01 11 10
Table 6.5.l: Truth table of Full-Adder

Ouputs
D C Cary rom addition of Ag
Operation and Bo
S S ACSSum
o 0o
CouC
CAB+AG+BC
The halr-dder an anthmetic
is
circuit hat perfoms
0 0
addition of two binary the (rOTA|Pig. 6.4.S:
digits using he rules Two bit binary (O19 Pg D) i Kmap tor ar)
addition. of binary addition
When we add Ag Expression for S (sum) = A Be
and Bg, the half adder produces outputs
Tecb-Neo Publications anacaTy Expresion for C.(ay)- AB + AC,+ BC.
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 ombinabo
Logic D
Design
DgiaLogic & COA
(MSS of Full Adder aDigtal Logiea oAtSem. 3-Comp Combinational Loglc
Aelestons enting the logic expressioms in NANDNAND logc,.
OLoge Diegrem of Ful Add
appllcatons or Puil aBdder are
as follows
lows: dder. Ans wo halt adder and An
The order to realiic ul
in A ful adder can be constructed using
A@BOC Arithneic Loge e oceier uses full
s shown in Fg. 6.5.6.
I.
ddibon. LOgic aa Ouelng NAND gatee OR gate
compute bunary
S(Sum)
prceong ngraphicsprocesing
F
In CPU (cent pr
(GPU) Iorgrancs e pans, where there j
complex computarions,
much oed or PU u
made up of fullaadders
ay) opimiztd ALU wmch
uputs
Dipital cakculaiDrs foperiomng aninetice addition. o19Pig. 65.6 Full adder two using ball
:

T 5:Loge dlagrem of fal sdder

la microcontrolers. for anhineoc additions, to
ddern anda OR gate
O)Logle Dlagram of Pul Adder unng Baslc Gsins memory ouses, r ner) to point the hg 65.7 shows the logic diaram of rull boer using wo

Fg 6.54 shows the iomplementasion of full adder using basic Instrikuon, tue ALU Uses hul adder. PE half adders.
ates.
6 Digital sgnal processoS and netw orking Systems --****
6. arte uil addede ***thet
adders inputs s- ABC, AC, BT, ABC
:4653What Sum)
w proauee ach of the follow s- ABC,ABC,»ABE, A6C,

. -
Modnle
Outputs?
(: A-B*A*B DeMorgan's theorem)pas
X:o, 3
Co Adoer
2

S ABCABC, * ABCABC HafAdder1 Ha

(:A-A)
sAS 1,Ce
o3Ka) upuBs

qD19Flg, 6.5.7: Pull adder using two half adders

*NBGn
------------- Prool
I
Ans.
From the truth Table 6.5.1 of full adder From Fig. 65.7 the expression for S (sum) is,

CoAB 2-0, C=0is when Sum)ABBOC

* S (sum) for full adder.
A=u, B =0,C0 tis the expression of

Opus
,*0is when CAB-AC B Ccary) A®BC+ AB
(i01Plg. 6AiLogk diaggm of full adder ssing besik ptes **,B =0, or A =0, B =
1,C,= Caut ABAC+BC C AB + AB) C+AB(*G
&5.5.1 or A=1,B 0,C=0 (A B A+B DeMorgan's theorem)
Advantages of Full Adder C:A+l =)
The addition of multiple )2-1,Clis when u AB*AC*BC
bits can be obained by increasing (A A) C ABC*AB C+AB +AB
o ders in a Circuit A1,B=1,G
of full NO
adde
-N binay aumbens, then the number
o the number ofbits want
, l is when 6.5.5: Implementing fall adder using NAND gates
C BCA+A)+ AB C,+AB (1C
each binary Dumer" of 1g C BC+AC, (BB)+AB
A=0,81,Cl« A=i, B =0, C
a 6.5.2 Dlsadvantages of Fulil Adder A1,B-1,C0 a 6.5.4 Full adder uslng Half Adders A*A=)

When a full adder is implemealed 6.5.3 Full Adderusing S.S How will you implement all adde
C BC*AG+AB A+A-)
using two half-adden NAND Gates
n OK
cessive gm
gete bis ed to propagate through
and
many Designm full adder
using halF adder ? Draw cirturt te The expression for i5 ame as the expressio0 for full

usingANO
NAR
9NAND ates-
gates diagram MU 0. 3C), Dec. 19. Marks
5
This increases thetoa propagaion
delay in comparison Ana * ae two halr adders and oene OR pale can be used to
Ppon
ogic
Oeay of the full adder cimuit
ing
eAOI
to
5.6 pesign a full adder using hair Thus,
lmplement a hull adder.

.
S
ABC B+ ABC.+ AB C and
and additional gates"
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 (610
ComannaLoge D
Digtnl Logc & COA (MU:Sem. 3-Comp)
ADDERR
Dighal LocscoAMU- Sem 3.Comp)
ADDER AND FULL Desig
DIFFERENCE BETWEEN HALF A multiplexer has any
es
The select inputs e epouce. For adsingie output E Types of Multpiezers)
a 6.6.3 . seiecting A specilic

- Statr th
-
da between half and fal addar
********

Full AdO
der
input line.
he types of mulüplexers are,

2:1 mulbplexer
.
. 416:1 u
mulupueke
A maltipleser

.
N 4
ombinational logic Dala
on

binary
.
combinational logc cireu
of two binay digits Is
n
Ckd a a 4tion
Adder.
of three hinarv dioi

A
Full
cmputes

S(um
inputs
uuplexer
tpu
6.7.1

na.
Advantages of Multiplexers

.
t can be used lo impiement combinauo0
. crues
(ONFig. 6.6.2: Block diagram ofa full The logic design is simplifioa
sNe g, 6.6.I :
Block digram of half adder
adde The logic expressions eed 0o be simpute

The transmission circuit is less complez and economacal.

puts
n r er has Two nputs (A and B).
AFU
0 ne inputs A, B and Cin.
Outputs A half adder has two outputs S{Sum) and
CicanyA Full adder has two outpuls S{Sum) and C
eeledru f 10
MUX Swisch digital signals an be ied
to switch to audio signals, vidco signal etc.
4.Carry
Components
Input Half adder does not have cary
Half addes
input.
Caryunput.
E
eare (029Fig. 6.7.10): Block dingram of 2': l multiplexer reouces the number ot wies. Module
3
Ad 00e AND gule for itsFul 6.7.2 Applications of Mutiplexers
implementatic AOK and onc ORate o AND P

6.Bolean S (sum) = A ®R 4c 6.75plain the applications of tipier

eresakon AB=AB AB
C cay) AB+AC%* BC 2 An ***************
D3 rouing can
7. of logic gstes usei

ed
Logie
noer
gates The number O ogEC gaies used is les. nE numbe or ogie gates used is more.
1
muliple
Data : Multiplexer
data lines to a single destination
be wsed io oute the data from

APpucanons
1. Constructing full adders 1. Arithmetic Logic laxer 2 Panllel to señial converter.
2. Compuler ALU . D

3. Digital coa
They are used in eiephone mo
4 Digua sugnal processors S. o sugnals on
a
newOs
singie irninsimission ube.
egrale

omputer
W 6.7 MULTIPLEXERS (MUX) nput unes and the dala from that
selected line is availatie o to system through GSM

.
te ground
n221*0 communicat

.
6.7.1 What S ultiplexing
--*************|
? Explain the multiple
------..
DIscus
e mput And connects
eeor.
Multiplexer
it to he ouluru Select mputs

(i030 Fig. 6.7.16): Equivalent cirtuut

7.

hey
They are used

Ne uSeu in D
in compuier memor7

and DA convenicrs.
Ans. with Surtab
1e. dhey can be
*********** **********************
u a ge nncbon generators
FOr a multiplexer there are n selection lines, 2 dala
2I
O apiExing i5 thE Method
of Ans.: **************** nput lines and one output.
:sEEcEing one or thE available data
inputs and; *****. he select inputs are also called as address inputs, -------- --***
i.-- utput ennOn Multiplexer a combinational on the input combinaluon appliea lo ue e Q6.7.5 What s te NwuM nUmber of
DEeing salection lines needed tor selecting one
Need or
uupieken*n
present on mulaple lines.
augiu yaiem, gal dalaa u
cE
ourEs
Cat

te
selects one of the n data inpus
o e nay inputs se
data from the selected data as
"many into oDe". Thus, t
axts
In order to rule ence, multiplexer is
this data over a single linc, we need to a
u number of selection lines n oqurcd
line,
sclect
*********** digitally controlled multposi Ans.:one Thetheminimum
iput une
for

tacieve Dy a device called multiplexer. is also called as

a elector.
******r*** Eaable input (E) is active low
input used for cascadidg. electing of 2

.7.
*" *
* ne om
he mulbiple muliplexer.
e functional diagram o
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Digtal Logic & coA LogeD
Function C Funcu Table Digtal Logic A COA (MU.Sem.
Table 6.7.1 :Puncton
table of 2:1 MUX AND8e 1
The enabied and AND2
ge is dissbled. The
pne ne is D hs
ut LED
n8Ttme mutiplexing is used in display systems os Logic Dlagram ofd A

...
powe.
when E = 1, S=1
Q.6.7.7 Cthte Enabie
Eenable input of te
can The ANDI

ule
disabled and AND2
YD. be
x0 puher 1apuk ANDZ gate is
D,
plexer to incrsase
besad. : 6.7.4 41 MuitplexXer
:|EDnuth 1able
Ans:
to increase is suze.
The E *enable" linput of the muliplexef un beused
Eaable ()e Output Y a.67.10***--ii
***
Explain a4:1input
.
Multinlava
TE
6.7.8 List the mmuttiolever tne
Ans ES,S.D ES8%P
ES,SD
********~ ********
Ans.
1 A4:1 multuplexer seies one 01 the toar mpurts and coenects EEs,sp,
Multlplexer ICa

me Descrpudon Outpu
B) Block dlagram
( 67.5: Logk diagram ef4: 1 MUK
AT Fig 6.74 shows te D.
bloct daem
A1S picxe vered input
Y I whea ESD,= I or ESD, =I four data inputs D,
0 wiee A
D, and D, two s
and oneDutpu Module
74152 p
74153 Dual 4 Logle reallzation of 2 1 MUX nputs D. 4:1 Inputs Oput Y
data pxer
74158 Quad 2: 1 multiplexer Iavened input ines
Autplexer
4157 Quad 2:1 multiplexer Same as input 1 D
A 6.7.3 2:1 Multiplexer
-*** ****** (E)
e working of a 2 :1 Select inpus

(06921g. 6.7A1 Bkock diagram of 4;1 MUX

S
Ans. inguts
Select
B(C) Funetion table of4:1 MUX
L (A) Functlon &7.6: Logk symbel of
8 : 1
MUX
Fucion table of4:
1 MUX l
AZ:I muluplexer elects one of he wo inputs and connects
o he outpu.
0g, 6.7.3: Logic realization of 2 : 1 MUX
L0nction bilines Output
Enable (E) Selet
(B) Block Dlegram L D Construction of 2:1 MUX
Fig. 6.7.2 shows the block diagram of a 2:1 MUX It has
Dg is applied aa one input to ANDI gate and D, is aplied ES, SP
po e ANDE Ble.
wO dala inputs ES,S,5, Do
D and D. 00e selkct input and one output
ne Eaabie (E) input is applied to both the AND gales.
kiG 3) unput is applied to AND2 gate 55,5P
ES,5P
Output Y
complement
The
() is aplied to the ANDI gate.
outputs from both the AND gates are applicd
11D,J for output H,
EApression
Enable- O 0ain dhe desirmd output Y. +ES,SP,+ES,) D ESsSP
Y
E5, 5P,5,SD,
Selec inp
LE (G) Workng ESS,SD,
qoay.6.7: Block dlagram ofa 2: 1 MUX wen
2.
E=0, imespective of the select inputs the outpul
When E 1,S =
T

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 Combinstuonal Logi

EDigital LoiG& COA(MU.Sem.

3-0
Digital Logic & COA (MU-Sem. so Loglc Dlagrann O10 ET MUX
(&-15) Combinational Loic Des

Enable (E) Select lines Output Multiplexer

s,S,S, 56.7.6 16:1 .---*
o1 P Es5,5 aman
67.12 Eplain worinf116
the working of
. -

***********
ES,S,5D,
111| D+ A Function
AND3
O Ooeraton ofa 4: 1 MUX A 16:1 muupexc, e one
O e l6 data inputs and
and sy l ou
whea E0, outpul Y - O inespectve of5,
Logical symbo Of 16:1 MUX
The logic levels applied to the select inputs (5, 59)
which AND gate is emabied.
0r )
npu of that AND gate passes through the OR ga
ted to datia
ata D2
= 1,
inpurD is caabled as E S=1, 5y *l. MUX
o is 0 as atleast ane
Out the ather three AND gales Output Y D
be outpul or OK ae h eq Enabie
ES,S,Š,P,_
YES,SD=1.1.1 D, =D, Module
D, is connected to the cutput when S,S,

y D coanecied 1o the unput when S,5%=00.

10
ESo Slec Inputs
3

to the cutput when 5,=07 (io37Fig. 6.7.8: Logic symbol of 16: 1 MUX
coecicd
D, is conpected to the output whea 5,s%=11
and EnabieE It contains 16 data Inputs (-D». four select inputs
S.
a 6.7.5. 8:1 Multiplexer ig6.7.7: Logic diagram of 8 : 1
MUx
(C) Operation Enable S (select input)
ogue diagram of:1 ado When E=0, output Y=0 iTespectve
of S,9,S
input

wn Ans.
s trut
********
table.
2
When E,

When E=
Cuput Ts
iTEspective to S,S,5, inputs.
1,S,5,5, 00, the AND gate related to data ianpa
WhenE =1, the logic evels applied to the
detemine which AND gale is enabled.
S,5SS, nputs
The data input of that
(i9mig 6.7.9:2to 1 line quadruple moltiplezer
(Nibble mutipkzer)
ANDgc souico 1o he ouput
D, is enabled. Operation
(A) Funetlon
6.7.7 Quadruple 2 to 1 Multiplexer
he output of remaiaing 7 AND gales is
8:I zero, as it at lkau when E= 1, ourput is zero. Yo = 0, Y 0. Y, 0 and
muluplexer selects one of the eigi inpuls
and one input to those AND gales is (2:1 Multiplexer)
connects (routes) it lo ue zero

() Logle uymbol of B:1 MUX

The output of OR gale is
cqual to De 6.7.33 WhatiSQuadrupie Mutpiexer wben
E0.=0, the AND cs.2.3 and 4 a enabied.
Fig
ght
6.7.6 shows the logic symbol a

data inputs D D, D, D, D,.

of 8:1 multiplexer. It has
D s coanected to the outpul
ay, D, 15
when S,S,S,
connected to the output when
000, E = 1.

Ans.:
EXPiain
**********
W
-- . will be Y= AY, =A. Y, =Ag and Y, = A
When E = 0, S=1, the AND gales 1,2, 3 and 4 are disabled.
D, D, and D, thre S5,5=001,E=1. -When four 2 : mutiplexensae wth in an The AND gats 5, 6, 7 and 8 are enabled.
select inputs
5, S5. S, and o0e output Y. D, is connected to the output
when S,S,S,=010,
integraled cicuit ncosed e
Thus, the outputs of multiplexer are
The ogic evels applied
to the selectadress inputs D,is connected to the EL multiplexer. A Quadruple 2 to line multiplexer contains
1
Y,B, Y, =B,. Y, =B, and Y,=8,
outpuf when S,S,5,=011, E=1. four muluplexers.
S.S,.S) delerunine which AND
D s conected to the output when
gale is enabled. multiplexer selects one of the two input lines.
The data input of that AND
S,S,S,= 100, E. 1 eY shows a quadruple 2 to
6.7.8 74151 Multlplexer
gaie is routed to the output. D, s connected to the
output when S,S,S = 101,
E=.
0.9 I line molupiexet.

The expression for Y is, D, 1s conDecled to the

output when S,S,S,= I10,
E=1.
Functon Table 6.7.14 Write short on 74151 Mutiplexer.
******************************

Y ES5,5,0+ES5,SD+E5,5Sp+E5,S5A u,1sconpected
totheoutput whenS,S,S,= 1,E ESOutput Y
.

74151 is an 8: maltiplser that provides two

ESS,SPA+ESS,SA ESS5,A
ESSSD
1X0 complementary outpus Y and Y. The output Y is same as the
Teeb-Neo Publicatinas 00 Select A
ere Authars iapire innoabioe 01 Select B nput selectcd, and output YIS Its complement
SACRIY SRAUH Veatare
A SACHIY .SUR Veat Tecb-Neo Publication.-Where Authors iapire ianovatoa
 tona
gab Digital Logie & coA MU-Sem. 3-c
Logis & COA (MUSems
Dt r contains twO meeu muftiplexers
6-17) Ombinatona Lo

compaubk wh TLcircuits. Ans. I

nis fuly mulp avlable
151 19 3 10 h has enabie
(6u ne or casCIading. Hence.
*O
eker
multiplexer IC.
with more numberof
mulbpieimE esS to hine. I

multiplexers. l cascade
seeral
4 llows to sernal convesion, nputs
Stperfomssparliel pefinition The multieleve
more D1-D N2
MUX2
D D2: D nume
oumber of puts
inputs N
can be obtained 10 2
cascaaing
inlexers with 1ess
wIt less mumber
number
by
LEnab
w
Voc 2 A 3
C 74XX153
*2 20
inputs.ucN 4
CoNiguration is called
oof;
S S, So
74151
lg, 67.10: Pla coafguratioe af 10 1D, 1
There
Dac
are8
D.
data inputs "
three select lines (S, S,. S) ano O
uos 18 A number
tain a m
o tapexen
bger mpeker
arrangcd in a tree topology to
s
calea a multpexer tree
eec
nes Output
wnete m
(Y and Y).
(pAFg 6.7-l:c74XXI153 iplexers Can be cacbec o obtai big88
The enable E is m actie ow pin. Heac mo multiplexer.
have to apply a low kvel sgna o the E IG and 2G are he Bctive low enable
U uplcKEr We npula
pin.
mulupeter D
abe 6.721
E
1huth table of 7015
for 74XX153 dual 4:1 multiplezer Design 16:1 multiplexer using 8 : 1 multiplexer DgD 8:1 Module
Inpu Output A Ans. Data D4 MUX 1

Table truh tablefor 742153 dual 4 to

I mutiplene Step I: To oban a mulpleser Using&

Outputs multiplcker, we Deed fwo 8: 1 muliplexers.

Step l: The S S And Sa eieet unes at wo B

multiplexes are connected in paralletl.

Step 1l : lhe most sgnahcant seiect line S. is used for g.Ex. b.7.1 :
16 :
multplexer xing woB:l
ID, 2D enabing one muplexet at once When S, = 0, MUX-1l is
000 202D, enabled and wnen ds , muAE
s enaoied. dy s aureEeuy
multipkesen

00 0 connecied to the enable input of MUX-2 S, is connected toEX6.72

0 'D,20, the enable (E) input of MUX- Design 8:1 multplexer using 4:1 multiplexer.
Step IV : The output of both the multiplexers are logically
o 0ID, ORed to obtain final output Y. Fig. Ex. 6.7.1 shows
mulfiplexer using two 8 : I mutiplexers.
a 16: 1 Ans.

Sep li or obtaining 8 multiplexer, using 4

npleker *e EEd twO mupiee.

NOTES
L 00020, Step 1: The select lines S, S, are connecied m parilet

n aDie Tor 4AAIDI 8:1 mulupezer.

I00 02D, Step 11l: The most significant ekct line S s used lor
ooce. Whea S, = 0 MUX-1 is
A mulupleacr routes the input data from the sclected inpuf lo enabling ane muluplexer

H 2D, enabled and when S MUNZ Is enabled. d s directly

connecied to tne
Hence, the iwo output columas indicaie data
D, and cOnnected to the enable ot MUx2 and S 18

enable of MUX-1.
a 6.7.9 IC 74153 Multlplexer 6.7.10 Multiplexer Tree
Step N; The output ot both the mulliplerers are logically
4.6.7.15Bolain wi :67.16 **
What do you mean by muttipiex ORed to obain the tanal output.
74153 Mut ... Explain
Ans.1Fig 6.7.1) shows the logic symbol for IC 74153 dual
..3
4
lomuliplexer. what 5 Mutipiexer tree ?

Teeh-Nee Publicaliona 0.2 Dec. 15.24 A 3MCHZY SAH Veature

erT Avden mpT maeabe Teeb-Neo Publications bee Aathwrs inspire innovalioa
 Combinational
Diital Logic a COA MUSem.sco Loge

Digta LoaOA TMU-Sen. 3-Comg

Comoirabonai
n
oD
ble
E Selet lpats MUXOtpu
MUX-2
Output D S Y

Y Di8

01
0D, MUX-I sekced)
D,MUXl eecied)
10D,CMUX-2 wieced)
L LD, 0Mx2 ws
a 6.7.11 Implementing sOP and POS
using

D ge.
e Ex.6.72 1B:1 Mahiplezer unn D43 MUX-
a
bhe OR

This faue
S In SUP form using a uipkxer.
UEx 6.73 DA-
EZ. 6.7.6
AO O. a(b). May 18. 5 Marks. o. 31a), Dec. 19. 10 1MarksS mpement the following funcbu ning : 1mipleter
Design 16:1 muliplexer using4:1muluipieaer gIDAgF g h.ia *
Diuupexer using two 16: 1 multiplexers La ,s,6)
Ans. :

StepI: For obtaining a 16:1 munplexer, sng

Ex. 6.7.5 Ans.: Sekct the muhipleaer
Design 4 : mulnplexer using 2 : 1
mulsiplexers. pi
muluplexeTs. we Deed four 4:1 mulaplexcrs. 1e or
to obtain Ans.: a Lm 3.3,6)
the final output y T
pleked be function bas three variables. Hence w* ueed 2-3:1|
Step Fr obtaining4*1 mutipleset, we need wo 2 : 1
matpleser
mulnplexer, we need five 4 : 1
multiplexers. mulpekers.
Siep : Comnect the data inputs (3. 5. 6) tm kgic, 1 and
YSlepl: Connect Step 1 : he S, lines of both the muiplexers are connected
the S,. Sg select lines eof the 4 muliplexers °0

Sep
"panue
:The most significant select line 5, and Eg 910:1ulupiexer using 4:1 multiplsen
Sep ihe ot siicant seket Fne S, is used for
enabling one muipieket 0A*TD
Step : Coaect the inpur variables to the select Enes of

connected
S are
enablcd and when s, = 1. MUX- 2 is enabled.
to MUX-S. Ex.6.7.4 Slep L dagram.
Strp IV: The outputs from tour mulbpleiers ae appiae
Obtain 32:1 multiplexer using 16:1 mulupicKers.
o teuu plicaers are logicaly

ata inputs to the multiplexer-5.

A s.:
Data 2:1
NOTES Siep For obtauning a s2 : 1
muluplexer, we Deed
e inputs
a MUX2
1
Step :
The select lines S, S,
I1
S, S, of bo
U Oplt Fa.b.c)
moltiplexens are connected in parallel.
o oR Y

Step 111: The most significant line S, is used for enahirg

one muuplexer at a time. When S, = 0, MUX-1 is ena
O wIED S,1, MUX-2 is enabled. S, is directly cean aa
lo the enable inpurt of MUX-2 and S, is connecte
enable of MUX-1, 6.7.5 4 11 NlaltipleEr using
wo
EA.
1

icaly mulupiee
Step IV i'The outputs of both the maltiplexers
ORed to obaia the final
ed iputs
outpuit.

ingpire ianosate
Tee-Neo Publications -Wbere Autbarr
Teeb-Neo Publications- he Authors inpire inovation Ten
AMCHIY.SMW
 Ex. 678
Bokan funoe ng:
LogcaASem 3Coro)
Da MU-0.201.1ay
L&7 12.5 Marks
lpeme
Ceect te pos (1,24.79kpe
Rvkcan funthe me RAROa (1,ASo
Ans AR.CD) Zm (0236, 8.9, 12. 14) Fr ary: Ccenect s 35, 6 7) b*I
pepare mpke
pl:To Ans
tabtle
Impiemenabon Tablee Sirpl

Ans
p:Seet e
** e tmt has te
te inplemeststa arE N

Sp
e need 2'= 8:1 matipleser kr ilenentae
lli Fad be mnt eres TIIL T ode
S

a Lgc dagnnbr Gay Lgr dgnnrs

mlmetai ef adder
MUX EA7.19:
2f
E &711
Sep: Lept dagnn Desga l akier eing 4 : 1 eper
f the minterms, in the fint row is circod and mints
n the sevbd ro Is D Cch. oanci the mumiea S S1 Ans:
Refer Tabe ELAT

is ue Spl: To epae
od ow is cinld,
ent
A
EL 6.7.10

Tement full adder using 8: 1 mutplexar and cra

enntoe tahle far Sn
aon abie fr Cery

Loge
Ans.:
Sep 1: Tnuth tahle ot full adier.
MUX Outpu 03 Tnth abe« hall adser
:OL|0|©l A A 1

rDePy. EL627: Loge diagram

e.E678a): Logik diagram

ee-Nre sikatieas
rr Aatan inpe insabee

nabe
 CombinatNa
LoicbD
Dlital Locgic & cOA (MUSem. 3como
Dgiol Lo&COA MU-Sem. 3C0m
Ane. mbinabonal Lopio DEs
Step : Implementation.
StepI: 1o prepare e npiementation tal Step : Implenentabion using 4 : 1
MU
Suep Hi Implementation using 4:I multipkexers

In dhe given nuacu Logic 1

pecied. Hene

e Do prescn ncuon
cce A-
.DD,D,DDD 41 Y

BD
ioslg. Es. 67.11e): Implementation of tull adder
sgMUX
AA A1 A
ia8:1ay
UEx.6.7.12 AU -Q. 14 10 Larks
folfowing MUX 9 Step : LmpiementauDn using 8 :I MUX
he
FABCD)-tn1,459.1,12,159.
Ans MUX 2
StepIt To prepare D2

la given
te implememao0
the fun Da 8:1
crck tie terms that are not present MUX Module
in the function D Oulput
aESig. Ex 6.7.15 : Implementatloa using 4: I matiplezers
DD,D,D, D, D,
3
UEx. 6.7.16 MU-O. 3b). May 16,5 Marks
Loge 2E4Fg, Ex 6.7.14 1
Lmplementation using piemeat the tollowing using ony onc 8:I MUX and few gales
A 111213 two 4:1 multiplexer FAB,C D) =2m (0.3.5,7,9, 13, 15)
1
pg, Ex. 67.13 Ans.:

Step UEL6.7.15 MU-O. 26). May 15, 5 Marks

1: lmplementation using 8 :1 MUX UEx6.7.14 MU-0. 2b1. Dec.
16. 5 Marks The function has four varnables. To umpement Tuncood
wEneed 8 munplexer 1e. Two
Implementthe following function
using4:1 multiplexer sad
Implemcnt the roulowing eapression using singieETMUA 8l multiplexers

DD,D D,D,D,|D,
FAB,CD)=2m (0.1,2.4,6,9,12, 14

D MUX
FABCD)
u
.
FABCD)-2n(0.1,2,3,6,7,9, 10. 13,
Ans.:
15)

Step
ans.

I : To prepare implementation tabie

A A
Sep 1iTo prepare implementation table
Step : lmplementation using 8: l multplezer
The function has four variables. To implement this function
H The function has four
variables. To implement uhis hubex
weseed
8:1maliplexerie.two e epd one 8:1 mltiplexer ie. two4:1 multiplexen.
4:1mulupiekca
Fl. Ex 67.12
D,DD,D,|D D,D, Y Output
UEx. 5.7.13 MU-0 4a1 Dec. 14.5 Mark MUX
FAB,C,D)
0. 31D May 17.5 Marks
Inplement the folowing esing
8:1 MUX
FABCD)-En(0.1.3,5,7.10,1, Lo 10
13,14,15)ae

A A A
AI 1 0 oEnFig. Ex. 6.7.16: Implementation uslng 8:1 multiplexer
h-Nco Pablicationa
bere Authors ianpire insovati
A SACHAY SZH Ventare
Tecb-Neo Publications. ere Authers impun
 DNital Logic & COA (MU.Sem. 3-Come)

Dec. 1E, 1011A

a Logic&oATSem SCome)
17 MU- 0 36 Dec 13 10 Marks O da as "B C,D, F only.
Comioinabna og
with select inputs Logie
eat
AB,CDD-2na1.2
the following logic function uning all4;1 multplexs
144,.10 1315,17,20,24,30)
EL 6.720
follovwing using 8:
he
FA. B,CD) =IM (0, 3. 3,7,
I mulbplexern
Ans lL
*oa. 7
Ane.
Step 1:Lmplementon

maxterms a spechfied. Hence, we will circe the ierms ur

MUY
T

A A A
A 0 A A
pikmenlation using 4 Table Ex 7.18 of u
; 1
MUX
' A
to form a MT Deed 3, 4:1 muliplexers
16:1 o* MOA as 4 selcct lincS. inputs B, A BRD e
BoutBorow
The don't care conditions are considered o be l's
GD,E will be select lines. Mep MUX
(rog Ex. 6.7.1(a) 1: Implementation using8:1
LOgic
Ex. 6.7.19
Design the Toowing ogc epression using single 8
Loge 1 I 4:1
multiplexer. FA, B, C, D) = Zm (0,2.3,6, 8,9, 14) +d (12, 13) Module

1 Ans.:
Stepl: Implementation table utut

ru dhe ruth table. D D

DD,| D,| D,D,D, MUx
MUX
D Zm(1,2,4,7)
Output
2m(1,2,3,
EAB.CD Step11 B fference
7)D
1
o cannot the inputs (,2. 4, 1) D A A
A
We Ear ue don
T
care condalions 12, 13 to be 0
TOW Canno the (1, 2, 3, 7) inputs to logie 1
amd

MUK reangp Step Il: Implementation.

rioenFig, Ex. 6.7.0: Lopc dgr

S
Step : Connect the input variables to the select
MUX.
lines LOgC 6.8 DEMULTIPLEXER

Step IV: Implemestaluon ** iolexer ? wh

demaoplexer Why s tE
63 what
L12
LOgic1 distnbutor
alled data

L -********************
8:1 Y Oupur
Ans Donal logic cct that receives
AO sinle liae and traasinis n.
6.7.17 Drerence his iaformatica/
data is rouied lo one or ihe ouar ane

.
Ex. 6.7.18 MUX The ouput une lo *

Design full subractor using multiplexer binational logic circut tha

IC74151.
A ehatupie set a
Ans.: of the select inputs, routes the dala
d*peiN
to one of the weveral ua
Step I: Truth table of full subtractor Ex. 6.7.19 lmpikm
:

1Ds0jE lg.

B AS4CNIY SLAM Ventae

(1onPig. EL. B.7.18
Tecb-Neo PablicatioBs-here Autbos inspire inaovatioa
Tecb-Meu Where Autbur y D
ASACHIY Snut Voat Publicatia
 Looc De
Digtal Logic &COA (MUSem. Sco The system reliability i5 mproc Digtaio 0A (MU-Sem. 6-27) Combinatona Loi
over the senai Tfabie
convert ala
C)Function
As demulipkezer
Emlbple data output
hs n a
line, it is cau
disribator.
PPlicati
lications Table 6.8.1 : Funcdom table of 1 : 2 DEMUX EG Function tabie

-
DEMUX
Tabie 6.82: Function table I :4
o 6.8 olf
blck diagram
sbows the fuctioaal
08.a) EaableSclect Output
Select lines
An8.i art as follows:
nput Appbcations r dEmuiekC 0 Da
Comnunn ysies =ES, Y,-ES,S.
Annnea
senial lo pur
2DEMUX Outpuis

hey ae used m one ormuplcking systcms

) Logic
ezaOn o11 :2 Demultiplexer o -YES, S, D
m compuier me0y.
Enable
nhey ae uscd
They are used m dala aequisibon systems.
1lo lo o |n.j-Yy-ES, S,D

aeMultiplexer Le(D) Logic Reallzatlon of 1i41DEMUK

6.5.5L 90 Lie elact ines
Select

7An
Ans
***. are
S So
OT
input
piexes Modale
demalipiexer
(1019) Block diagram ola roltiplexer
dmeltiplexer ):4 demebpieker
Efenable)
3
() (d) 1:16 demultiplexer
Demulipleier i ES
TC Function
a6.8.2 1:4 De-multiplexer Outputs

Tc74154 o Denmuliplexer 6.8.7 Praw the logical circuit diagrans and

put deseribe the workun
1Dual 4 Demuliplxer a
a6.8.1 1:2 Demultiplexer Ans. EEnabie
Q.6.8.6 Explaln the workina
(A) Function (o11PT, 6.KS : Logic Realization of 1:4 Demaltipleser
demuttieleve
------- ---- . Al:4demultuplxer depending on the stalus ot ts scieet unes
routcs the ingput, to one of its four outputs.
a6.8.3 1:8 Demultiplexer
Select lines
Functlon (B) Block Diagram 6.8.8 praw the logical cireuit aag aa
(oTN D) Equlvalent drcuit
plain working of a
t has one input data line
Pg 6.8.1

D7 ouiput lioes, a select lines

Al:2 demultuplexer roules the input to one of
png00 Ue sanus or the selkect hne.
Fig. 6.8.4 shows the block diagram of al:4DEMU.
data
nahle ss4g
cnanic
input, two select lines, four output lines and one
tns damu
*******************- .-- ---*****
caabe 1npul. The select lines are Ans.
puis
also called as select
90cK DIegram
. 6.83Explain the advantages o
g 6.82 shows the block
diagram of a I:2 demulipletz
Daa
npu
A Function

A, staus ot the seiect ines

a ooe dala input,
one sclect input and two oulpuls. Oupus l;8 demuluplexer depending the
DEMOA
***
A Ans. ****

EnableE
oupus Enable
vg or demulplexer are
as follows: Fig 686 shows the block diagram of a démulipkxer. It has
g OESIgn need not be simplified. oe input, o0e caable ingput, three select ines and eight
2 1n mulbple output cireuits uE outputs.
IpacaE coun
is decreased. Selet ine Select ines
eh-Neo Publicalions
bert Aetben inp
(0110Flg. 8.2; Block diagram of
inaevalioe 1 :
2 Demalup D112)Fg. 6.84 :
1
:4 Demultiplexer

A SACHLN SHAH Veatare

1S5MCHIV.SLUH Wate Tecb-Neo Publications Wbere Authurs inpire innovalioo
 Loglc Dlegram
(D) a6.8.5 Demultplexer 1ree

nputs
data

PMXY Ouputs ..
46.8.10

Ana
What do
.. you udsrita

ICa.
LEnse Hence, in order to obtain a demultipleter with
re un

De
demaie
d more mumber of outputs can be

Seledt lines chtained by cascading demuktiplexers with less number or

Di14Plg. 6.8.6 ; Bock dlagram or

t
Deux
A oumber oft dcmanpee aled
a() Functlon Teble
demultlplexer tree where m>:2.
Table 6.8.3 : Punction table
of 1
:8 DEMUX o obLain a bigzer
hus, small demultiplesers can be cacade

Fasble
Ex.
aee lodule
.8.1 3
Design 1:8 de-multiplexer using 14 demutiplexer.
Ans.
Y,-ES,S, S, D StepIi To obeain a :8 demultipkxer usingI:4
ocmatplexet, we need two
1
: 4 demultiplexern.
Enabie (E)
Step Il: Conect the D, signul of boh demultipkexen.
(po11Fig 6.8.7 : Logic diagram of 1 :8 DEMUX
YES, S, S% D, Step 1n Connect the mon sugnilicant line s
DeMUX-I s enabicd and when
that wct
> *
h DEMUA
1,
6.8.4 1:16 DeMultiplexer 0,

YES,5,
, D.
Q.6.8.9 Writebriefbout 16 Suep IW : mpk
o D.0 -Y,Es,5, 5, ..----********
DeMultiplexer.
*************
put
D
DEMUX Y
0 0 | YES, S, S, D. A
demultiplexer routes theguoo
16
NOTES Oupu

C B Logical oymbol of 1E16DEMUA

input

DEMUX:18 upus
Enabie , S2S
:
1
: 8 demultiplexer using
rD1 1Pg. EL 6.8.1
demukiplexer
demultiplexer
I4
6.8.8 : 1: 16
OnoF. A SACHIY SIAH Veatun

ecb- -Nee ublicalions. bere -Neo P'ublicatiens. ene Authus inpare o

Awban re
movatea
ASACHIN SLAN Vate
 CL
Combinational
Logjie
Digital Logic & COA (MU-Sem.se
Digtal LogcaOA (MUSom.3.C
UEx. 6.8.2 MU O. 4/D). May 17,5 Marks
|EX. .8.3
Implement1:16 demutplexer using1:8 demu
conbinabonaLo g
Design 1:16 Demultiplex.cr using 1:4 demuluplieke.
Siep Il:
oE
In oru
et he Bookan functions wee
nicms
ns Sep I1: lmplementation
Ans. need
Ex. 6.8.* Show ue peentaion
StepI: To obtain a 1:16 demultiplexer of Y, ad Y

To obain demulhiplexer, we need two I demultiplexen,

Sep: a I:
iemulioplexes, we Deed 4, 1
16 demulupieker

:4 demultüplexen.
ng'*

ue D
:8
and Sa S,
functio

Step 1: Conmect S libes of

bot
Step ultpleken.
1l: Conaect the 5, S, lines of four demuup moltipexen. B.C)
Y
Step Il : Conmect one moe demutiplexer so that is four Step 11: Ceapect the
DEMUA"
ost signiicant line S, such
Is enuoied an0 whien S,= 1, DE
2 1 DEMUX
DEMUA
Ouputs e routed to the data inputs of the four S,0, EMUX-2
enabled.
demuliplexer. Connect the select lines S, S 10in DEMUX

Step V; Implementaton.

DEMX
D Y D Select lines
pata DEMUX() YYit A oPg EL 685: Full »dder using demultiplener

Select lines
UEx. 6.8.6 MU-0. 4b May 16.5 Marks
(roraFig. Ex. 6.5.4 : lmpiementation of Ya ad Y, functions mplement fall ubtator using demaltiplkser. odule
7J UEL. 6.85 May 16. 10 Marks Ans.:
U-0.26.
oEMUK Implement full adder using demultiplexersn
Y B C D
Ans.:
YoY 9 Step 1 1
Tuth table ot Tul addkr

1:8 T3
10
Y

AB
.
Select input

cSum ()Camy (C
Sum (S)Cary
Output

DEMUX(2)
YY2
s-Y 13
(1.2
, 7)
D =Zm(,24,7) B,Zm
11 1
lmpkementation
Step
Y
(io119ig. EL 6.8.3 : 1 : 16 demuluplexer using
"12
lfiplexer

a 6.8.6 Implementation of SOP and Pos DEMUX

using DEMUX
6.8.4
impie ment the following functions
using demulliplexer. L
A, 8, C)= Zn (0.3,7)
(1011%Fig. Ex. 68.2: Y,A. B, C) = 2n(1,4,6)
l:16 demultiplexer using 1 :4
C 2m (0,5, 6, 7)

demultiplezers
Ans.: LE. B.ALb
:
limpletbentae oe ruader Subenctor
(o12/.
log 1
:8 Demup
pWih D, al the output of demuliplexet
e Veotare
munierns A SACHIY SHAN
Tecb-Neo Publicatiens. here Authors imspire inaovation
Tecb-Neo Publications--ert
 Combin
Dgial Logie& cOA (MUSenm. &-Come
D Logic& COA[MOSem. 3-Comp)
6.9 ENCODERS Noc

************-- *

NC
Anllc
APPeuonu of Encoders
9.. What do you mean by encoders
****************
Ane. 1. 74138 is mont widely used 38 line decoder io microproceswo
An
microcompuler bused
hoder 1s a comhinational logiC cireuil
tal Onetworking 14138 is high speed 1 of 8 decoder/ demutiplerer.
E cOe l ts outputs. 13
3. Com *
Pin names and descnp0
e ne inlomaljon from 2 inputs inlo an n bif code
&Encoder 2 12
74147
H 6.10
DECODER
Block dlagram Descriptlon

g .9.1shows the block diagram ot an cheoue .6.101 Explain in brief the workina
wong ofA.B.C
ofA. B,C
decoders.
dala
************* -E, (GA, G,B) Enae inputs (Acuve LOW)
Ans.
GND E^(G) Enable input (Actve HIGH)
F pu ndala decoder s a
connnal oe cireunt hat converter an
pus Active LOW
Enabe (o1o|Flg,
6.921an dagran ra1d0:4 line encoder L
5 p p Ouput cambinational logie
L
(o10 ng.6.9.1 : Block diagram an encoder
of The input and output codes are different.

C-
cders,
to
n:2 LZoupuis 8 74138 Module
BCD encoder.
Qtal to biAhuy cncoder. cimal ouipus Enable LI A1 3

..
4 Hexadecimal to binary 1
9 Out
cncoder. ine
(o12ig. 6.10.1 : Block diagram of a decoder ine
6
a6.9.1 Priority Encoder (IC74147) The decoder has n inputs and 2' outputs. The enable inputs Vee
*********** ******* are used to conrol the operation of the decoder.
Nn aetal pnonty encoder any ot the enable inpuis is disabled, al outputs of the 6.1.1
t
74138
pg
*****

Ans. : b.9.b) 1
Lage sy mbol Tor 74NAI7 priority encoder decoder are disabled.
4138 chip is l6 pin chip with A. B and C select hnes to
A priority encoder is a combinational logic fruth table : 1able 6.9.1 shows the tnuth select required output line o be actve. and., nao inputs are
circuit that table of 74147. H 6.11 74138 : 3: 8 LINE DECODER uve LDW enahe npus
TEsponds lo one input depending on
the pnonties assugned to Table 9.
dec e for 74XX147 inany hiee Me, eigntDeuve LOw puks
sAE
presD
he inpuis. 1
note on to une
IC 74147 is a decimal to BCD encodes.
IE has
Decimal 6.111 Wite short To undentand the working of functional diagram, let's see
10 input hacs decodar. bruth Lable ol the chup
pur for the encoder, vle
The cncoder has tour oulput
ouput is available.
It is aso called 10 to 4 line

Y
for 741
shar
encoder.

P
lines on which

gran
encoded BC

ana logic symbol

. 1

1|1
2 3 A
56

111
11
7 7
9DC|B

1|1111
1
1 1
1 01
H Xx
xXXX|H
Tih
tabie of B: B decoder

tis a A D1 1 11 LX H X X|XX
" eoded. ensures Uhal only the highest
order XXH

.
nc XXX011 X X
The 9 inputs as well as 4 BCD
outputs anre active low. AXIXX H
HL H H
There is no input lhne for the decimal 0. A zero is encoded L H H H H
when all dala ines are al hugh ogIC evel.
Al the inputs are
O1 11000 HI " H H L H
buffered.
IA AXXX01 1 H H HH H L
1XX|x al u H H
HH H HIL
Aaicaes don't care conditin HH H H H H HL
ech-Nee Fublicatons wDere Aothers tapire
innevatio 1SACHIIN SHAN Venture

ASACHIY SIMUW Veat ecd-Neo Publicationt bere Authon pere aDa

 Combinational
Logie
wialLoic A
coUSA Digtal Loic oNMOSem. 3-Comp)
(0.5,6,7)
Cry2m Combinational Logic Design
A-LSB, C-MSB, H-HIGH Voliage Leves

Wotage Level, X=lmmaierial

Step 11: Conncct e untion

inputs of the decode

ariabies (A, B
varables (A, B,
C fapats Outpat
Q. Ch de 0ersnca (D)

**
6.112
*- f--- - Step 11t Logicaly IC oupats corespondir
BB Decoder
Ans.: pesent np c oupur
Bco 7segment decoder.
decoding.
o5s
4.
e converters
D uncuon
Bomow)
m(4,5, 6,7) G, n2,3,4.5)
Ex6.11.1 3 (10135)P g Ex. .I13: Lnmplernentatio 1,25.6)
upement oolean functon Decoder
VEX 6.114 MU-0.5@. Dec. 16,10 Mark
F2m(l, 4, 6) using 3:8 decodes.
a3 bit binary to Dit gray code converter using 3
An Design
decoder.
Sep: Connect the variables of the given function as inputs
Ans. 2
Step1: To oblain truth table ot 3 :
8 decoder
Slep l: Logically OR the outputs coresponauE
(10131gEL. 6.11.21 lmplementation
c oulput Table Ex. d.1 100 Coo coverer Module
Ex. 6.11.3
a implement a ruu subuaetor
B B
sign Cireuit using
3:8 si
CC Ans.:
F(AB,C)
Stepl: 1o obtan truth tabie of tul subtractor

Table Ex. 6.1l3: Truth table of full subiractor

o13g Ex. 6.11.1 : Implementation

H 6.12 COMPARISONS
*********i
EX, 6.11.2 encoder and decoder.
ABB Diference .6.12.1. Diferentiate between -.
Design ful adder using 3:8 decoder with actve ow outputs 000 Ans. : Difterence betwen eno
and NAND gates. ecoder
Ans. : raramer
Combunanonal logc arcut that converts
decooer is a
Step I : To obtain tnuth table of full adder
An cnc O0et is 8 combinanooal oE cutuit hatA
DE ay coe 0 codied Oupal
Table Ex. 6.112: Truth table of fulladder

puts Ou 0 2. Block diagram

AB oupus

Enable

0 Dhtierence D "Lm(l,2,4,7) (0Ilg &122: Block diagram

of a decoder
1 Borrow B, 2n(1.2,3,7) (D106Flg. 6121: Bock dlagram of
an encader

Step 11: To connect function variables A, B, B, Coded binary in

0
3 Input appliedActive input sgna - Active

Sten
p Logically OR outputs corresponding0
4Ott Coded binary ou
SHAN Venture
Sum-2m (1, 2,4,7)
put.
generaled ASACHLY

Teeh-Neo Publications er Authors inpie oeefion ech-Neo Publications here Au

S4CHN SHUN Teta
 C Dipital Logic & COA (MUASem.se hination
Decoder Oes Digtal
S Parameter oder Loglco oem. 3Comp)
23 pifferentiate betw Combinabcnal Logic Des

-
Input laneS

oy encoder
2to
le

4 liee decoder
-**********-
Ans. Dneae
Sr.
peter
nd
and demultiplexer
opleser
damultiplaxer.
******************

38 line decoder
T * inch ouput Dem
3. Quite has
1.
3. 416 line decoder tomcnanal kbgie eircuit thatA demultiplexer is a combinalucnal uE* Euo
that

4Hexadecianal to Dn cno mbo oules the data iaput o the selected data outpuL
Cormmunication systcms and berwonlng
Wireless Communieation
Ppucaons
email Me ldress decotinn
mon nout n
.1deo cocodes
4, Code converics

i
.
****------------********
rNEate betwen deder anr ad ..
*****
.---.-------
****--.
puts
:1
DEMUX
Aultplexer
AnS Derence beween decoder and OEp Output
Demultiplexer
ameler
Ne
Decoder

Definition Decoder
coDvEs
is a combinational
an n bit binary coe inlo
bgic ciruit
coueu ouupun
tharDemulplexer
OCpenaing On E
sa combinational logic-cieui t
U Seicet
rput(E)
inpts, roukes
Jata input O onE O E Nevera a aup
DOCk diagram

nout in "o Sele pus

diagram ofa Demultiplexer
2 outputss EoTBEk
2 1
2
1029Flg, 6.125: Boek diagram ef ?" : 1

der
nputs
indeer

Number of dala
DIFig. 6.123: Block diagram of a decoder DEMUX
4 Number of data 1
uputs u behaves asa data selecOr salz2 device u behaves as a data dininbute
w Tdevice
Enabie
ion
of (a)4:1 multiplever
multiplexer. b) 8 1 nitpic
:
ieh: 16 emukigleser
(c) 16:I mulüplexer SEdemuia
(d)TE
(dh 32:1 mulupies
Select ines

(11Fg. 6.124 : Block dingram of a Demulpr

3. Characieristic A decoder takes n input lines and produces 2 output A demultiplexer transmits data frum one inpu
e

2 possiblk ourput lines

to
4 Keverse "peros e reverse lunction of an encoder t perfo the reverse function of a multiplexe.

S.Selection lines here art no selection lines.

Catt lane is determined by the combinalion or

(o) tone deco cma tuplexer

(b) T:8 demuluplexet
I c) 4 to 16 line decoder C) TE16 demultiplexers

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 Digital
Lgie&COA(MU.Sem.Soms
Digial Legc& CoA MU-Sem. 3Como)
W 7.1 The sequential circunt s a Eeursave system;
SEQUENTIAL CIRCUIT ie,
a sequen depends on s Flip-Fops
711 Explain present
stae of 7.2 COMPARISON OF COMBINATIONAL
the need of saquential cireuits also on is past Out. inp.
AND SEQUENTIAL CIRCUT
A Ans.: --***** tt iscombination o combinational 7.21
724 What is
5 Ethe difference be
dterence between combinational
feedback/me mory and ssquentiel circuits
DE Cmbunational cireuits art eienent he ?
aieus no eedback tleme
peent memory slorage devce (ualeh or -********
o0 the inputs lip-loP *************** 1le, Dec. 15. Dec. 18):
*-*----******* AO.
present at thal time.
The binary
EIE Are many applcations where inlormaova sd e memory
it
is desired to
y ge
y elemenda
utput acconding to the sequence in which the d o s he present st
Paramete
nDdAonal ercuits
"psgnas ae received. Combinaional arcuts
canno
quenual eue o Na
P Dca oupus. The combinational circut perfoms operatioes
ln such applications,
the outputs generaied
depend a
aputs and on peseat stae
a
c o cueis, the output variables at any In sequential circuits, the output varuabiesau
ie bew oupa e pendcnt on the presen ieput
present state inpuits and nhey ae stortd in the memory iestant of time are dcpenaenI o ue Peeu put
also on the past staie of the inputs. element and swe called
he past state is gven s
feedback from the outpurt bt state of the sequental circut.
as
e vanables. variablesand ao apa the input

.
t 1hus. the oup
he inpuL Such cim equential circuit 5 a tunctaon me
d
**------... uenal drrlts ot the soqueace d
:72

. --
***
xternal inputs, Me
Deine Sequential cireuit. 1aiema
Su uE present and nen eienent is nol required in combiaaional Memory elemeni is necdcd to cre ue past nus
tej
na outputs.
713 Whet s sequential cireuit? Write dow of the input vAniabk. Modnle

Ans. ---- **
NOTES.
Speed he combinational circuits are faster in sped. This is

ecaue e ocay eween the input nd ourput is

The sequendil circuts

the cambenaticnal circuits.

are siower in companson io

Sequenial Cireults
Definition ** whose
Te circuits
Definition: : The *****

4 De They art easy to desigm

output at ang;
instant tine is dependent on the present
of
here i3 no eeuback besC nupu The
state or nput as weil as past
state of inputs: 6. Time Combinational circuits aE me-ileput Sequeeua circuits ae umede pendem
re caiea as sequential cirtuits Flin
FUp-toys
Examples : Counters, .
shift egisten, enal adders,
7 Elementary
equence
generilos, logie hunction generatos, building blocks
et. masniy ued lor skonng data
Combinational circuits ae mainly ued lor anthmedceuenaal circuas ae
D Dgrinora Sequential circult
Please Refer Fig 7.1.1.
heap ciunt
***------ Cos

rau uus
puts
nputs Combinationa 10. Block diagramm nput Combinaioral Outputs
inpus L

Memory
olements L
atch
ra
(1E1Fig. 7.1.1 : Block diagram
of a sequential cdreult
dders, suberactors.COunc, s *
charecterstice .Examples ParniciaJocs,
ot a Sequentel Cireut cheoders, o
ers,

.Tbe sequential Cfeuit 1s a closed-loop system.

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Publicatiens-bee u
 FLIP-FLOPS

TYPES OF SEQUENTIAL
There are two types
of sequental circuits. They are
7.5 - L, the fip-flop is said to be in "Togic staie or
sad to be
d
H 7.3 1.Symchronous Seguental Clrcults
75 What s a rup-tlop ? or Define fip-
state or SET stale andd
ifQ-0 the nip- flop is

CIRCuTs opc 0' sate or LOW state or RESET or CLEAR stale

-- flop. Wnte down s characteristics
Definition *ea Circuits
*ptmp can have one or more mpus
73.1 Define ard elassify sequential circurs peration can E conrOlea by a cloe with the kelp of a diagram tate is
********
olled as sncrord uential circuitg 1-bit memory cell.
piam:. An input signal thal controls the fip-tiop o y
ns. aexcaton.
pes o Sequential Cireuts 2 Asynchronous Sequential Clreuts ,7.53 Explain how the fip-lop acts ike a9 A urigger pube oeeds to be splied o a fup-1op o
ODefinition The sequential circui
storage device. hange in
s ouput suaie.
he tupP-TRg wu
whoge hus, a up-ty
Synchronous sequenfal circuits
operations art not conErolea by a clock a With the heip or diagram,
vEn it the aoplied pulse s emoved.
***
xplain a lorage device. when the output -0, the tapy sol

as bistable multivibrator.
callea ayeroN qential circuits I
*****************************
and when the output Q=1, the ip-tIop stres
synchronous Sequential circuits, *
EP 71: 1ypes of Sequential Cincuits the outputi
And
10. Fip flops are commonly used in shift egsters and cone
can occur at ang tie the inputs are applie e diferent flhp-tlops used 1or vancus applications
are S*

. Comparison of Asynchronous and Synchronous Sequential Circuits

A Hup-1op
Definition : A
A in-Floni
PtoP
: p-tiop. J lp-tlop. D thp-flop and TPhp-tlopP
Po o7ss What do you understand bya s
memorg an
Ans
2 .. U-May 18

a55e*
icer
.
t conStructea using

Ans.
-- ---***
**
Module

neler yDchronous sequential circuits S sequern - A logic gate is not capable of storing data or information.
However, i" a Tnp-tlup many logIC gales are connected in be stable state 1s a SEle mwch e u
eindon Such a manner that uney allow dala or inlormatuon to be permanently retain or hold itser
Suential Cireuits whose operation can be The sequential
t not
* EK are called synchronous sequential
controlled by a clock
A a
Cea
O
as The circuit will change its state only on the application ot an
asynchironous
Sequentia circuits. Loglcal Symbol
Memory The memory tlements (6) external signal

eobus
are clockod
Sequenial circuis.
tip-tlops inThe memory ciemients are tume-dclay elements or Fig.75.I shows logical symbol of a lip-flop. ** what ip-fop callea
.*****
How ang
unclocked flip-flips in 75.6

e
5yncaronous sequcnuia Carcuis, there
t 4 a chanEe
pt agnals, uien t can atteet the suatus of
circuits.
asynchronous sequr

syachronous sequential circuits, if

there is a
rputs FF
Flp-nop)
a (homal outpu
ns.
***********-- - -.
thechange in the inpul sig (everted output)
ment only when he the
afect A Tup-tlop Is Called sa bstable mativibrator r
ctvated.
clock gnal
salus ot ne metmoy element at any nsu ou
Speed ESFg.7S.l i
>ymbol or Tup-nop
The synchronous sequential circuiS are a
little skower nas stue.
Decause timedel The asynchronous sequential
E
two stales stale and

ce of cloe
circuits operale aster (C) Charac s
Easy cteneie of

.
ESEn bsence vanous me using
Ditficult
pops can be constructed by
Us
nerent gate aangenents, Fup-tops ar he Das
H 7.4 cLOCK SIGNAL building blocks of sequential cireuits
A 1up-flop is called as a binary or l-bit memory ceu as
Ans.:
o7 "*****r~--- can store 1-bit data. It is a bitable multivibralor win
A gger puse needs o e appluied a a thp-tiop to cause a

4 clock signal ? Falling.

in its
ns. --- table states.
may suy in
stale.

the stale even the applied pulse is

The clock signalis a uming Iwo states are, state 0 and state 1. A lip-flop The tüp-tlop will etan
signal. in the sequential
he required openno cur ouy circuits, either of state 0 or state 1 indetinitely emove
i
on ie
aon ot the state, an appropriate triggering signal
necu
asa stornge devike. when the output
*51gnal. the
0dity Thus,a ip-lop acts
me output
Hg 7.4.1 shows a
clock sugnal wih S0s duty
oe applied to the 1up-1lop
0. he tup-P soes when uhe
cycle. On the 1 Clock
cycle or NOR gaies. t
can he constnucted using NAND
Tence or cioca pue
circuits.
Ga ow begns in sequeotial Cockfrequency f p-op in Fig. 7.5.1, Q and Q1,the fip-tlop sauresT
s wo outputs s
the fip-tlop whuk Q 15 e
This 15 eeoy carnsae Or up-thops
Teeh-Neo Publicationa (E4Fig. 7,4.1:Clock s he normal output from
-DerT Authan Apere innoation signal d output.
A MCHIYAAH Vestu
ie ingoatiaa
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 Digital Logic & COA(M Fip-Ee
Ans. Digtal LogcsCoA (MU.Sem. 3-Comp)
*
many Aip-Rops are requr Ans
How
..torgn bits of information or dataS|L A
atch 1.7 CoMAKISN BETWEEN FLIP-FLOPS
AND LATCHES
What is difference
***

**
Ans. : Definition :A fipaop
lardh 5 a Kon-elocked UQ. 7.7-1 betwe latchand op ?
---*****
AMUMay 16
checks all its inputs continu *******
B p-top Can sMore 1-bit informatioo at a tie. that continuousy
ousiy
and
, T0r sEonng nbits of information or data we will need modiries pac a g
i time, indepe Latcbes

..
of the clock signal.

Lalchesae *
os O equental Fip-lops are the basic bunaing o
7-5. What do you mean by
1. As soom as a lalch reeetS pue, "latches
n on"b
circuits. Lac m DE ogC Baes. Fip-lops are coostructed trom alches and chde a cioct

.ing0p-op.. .
1
if pulse is high or SET and latches to a 0 if s
Ans.: RESET. Tbus. a lazch ipenaent Bs
or Ne clock
ic is low latch checKS AIl
s mpans conunusly ahd modáfies isA tip-fop checks all es put conuno **

signa or tie clot 5ig

Seting monton ue inputs and as soon as

fip-lop
of Pip Pop
i
i The process o soug into 2 A latch contanuousiy
inpu
ip-ilops are edge-mggered
cal g ae up-op. pulse is received, it latchess to thal state.
Reseting
PA
af Pip Flop : Tbe process of storinga U' mo a 4. Latches are sensitive to the imput swilches As long as Flüp-flops are sensitive to the ckck signa. 1bey ao Dx
|L ©Classhcaion o Latches latches are os, ey can send da
------
: UQ
lip-lop is e
-
The types of latches are:
They canno be used as registers.
uput unless theit 15 a change ln
Fip-tlops can be used as registers. They inchlade the nput sugnals a
TS10 HPop quenaal cascaied fbpI0s
--
ciE
Ltches egsen
well as a clock signal that enables
Modale
Dec. 18 3
Ans. : In a sequestial circui, the outnut deends on
utput depends a
the 6 Latcbes arc asynefironous, as they arc iDdrpendent of thePlip-lops are sypchronous, s they ae depeboene a u c
presenl state of input as wel as past output rot latc AcOve-OW elock signal. signal.

input
Ee . 70l 1
Cassithcation of Latches
E 0n e cck sigmal

.Active-LOW input latch n opeRE SIOwer u

Output operate Taster in companso0 to Tup-tlbps oue
CLK AcUVE-LOW indicales that the SET and
9. hey
RESET nputs art in absence ot cloc Sgnal
tne HuGH state and one of
them will be pulsed LOW
wenever it 5 reuired to change the output of Uhe latch
10 Larches ane simple to desi ,

ig. 752: A symbol of a fip-lop Latches are more proe lo gu

From Hig 7.52, we can see tha
AcUve HIGHlnput latch 1. tauns oeuning oa Pp ae prclcie l eseR T.
Outpu, Q t (input, Q) where, Q = Paut output
ACuve-Hugh tnput latch indicates
RESEI Inpus are 1n
that both the SET es are spansive wwius uhe

the LOW stale and one or

uE Construction and OperaiDOn

M 7.6
la

no past oo
flip-tlop. the output depends on the present
Hee, pop

LATCHES
s a quenal cireu.
stae of input
---.
Q7.6.3
pulsco uuH wheneverHis equied to chan8e ue oup

How can you build an SR

7.8
7.8.1Dee*
4
7.8.1 Deseribe
S-R LATCH
Logic *****
symbol Cor ruction
- t is te simpe
NAND o« o
inicates RESET «
astructed
be le

CEA
u sing

lateh S indcaies SET a

e
-
S
Operation of an S-R latek
unversal g (Reet-se) latch. 1
- .and
********
******* tis releed or RS
SC (Set-Clear) hutcb.
7.6.1 What is a latch ? **** Ans. *** -
Ans. S-R lach is also called
as the S-C

and K (Eset) and two outputs, Q and

npuls, s(et)
:.7.62Define latck Write down
its "*c can be constructed si (A)Cogle Symbol
wo

apcharacteristics. Desenibe its rOCDUpied NOR gates or two

cross-coupled NAND Logic symbol of SR latch
is shown in Fg 7.8.
Aa cüve-LowW
CasSincationa
*********
SR laich can be constnucted
with two
************.- coupled NAND gales NOK gas
and an xtive-HiGH SK stracted with twO crOss
constructed using actveLw dk
aive-HIGH SR lasch can e
An
two cross-COupled
NOR gae
coupku NAND Sa
ss coupled NOR 8

onstrucied using wo
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 (MU_Sem
Digital Logic & COA (MU-Sem.
Sc
stale of the S-R latch
determines tbe 9ruth
Table
D oA Som)
cpondi.ng able 72 u e-high SR L Initialy R0, both the inpuuts
to the
urputQ and in verted outpuk NOK- put Q.
a s", R =0 the output i
The R0 1 Sale S = 0. one input to NOR-2 is a
opic 1.T
Duputs
Output
0 No change Nge wst
R=1, the output Q =U Ana
** o0 Ho Fig.7.8.20) i condition.
0,
() r both S=R = 0, the output ot e th = 1, R =0 SET state)
staie t does not change.
in HOLD state or tr 78.2e) :S

= o, the olpu
NO CHANGE
state p Ouuts s, when SESET) = 1
and RIRESE)
a hich will aways be SET (Q-.
(d)
f bocb S =
R = 1, ie. both the inpuls ae gh S{set)o
and Q may be For SET stale :Q=1 ,0.
o and Q are unpredictable, ie.
Q

high or low or aay ooc of them can be high or Indeterminate (invalid)

esFig. 1.8.2c):S=0, R=0(Q-1,0=9 Hold State) o L E stat
condition is not allowed. It is caled as va 1nd R(RESED-1
delrmunate conditon.
Ddelerninate or invabd or probibrted stale.
e- Thus, wien
(low stale). E s
(SET) and RIRESET) both
0e n nge.
aea pE

7.8.1 S-R Latch using NOR Gates The outputof the NOR gatt wil be1 any ot 1ts linput is -
logic 1. Hence, t 15 caLR aeuNE ale a" tere 5 Bo change in Module
(Actlve-High SR Latch) Initially the S(SET) and RIKESEI) nputs are a k O
782 Explain the, working of SR latch by opc 0) staie. hus, for bold stale Qs Q. Q0.
:4 ant to latch the outpus, WE pie S{Sat)o
Stng NOR Jate Rto locic I. RESETslale

.2783
Ans.
.
Draw &uplain in brief, a high
-
Sr.
will analyze the active-high S-*
inputoutput combinabons, w

Hold
No. State S(SET1)R(RESET)
latch for difeme
ae s Tolows: TR=1,
L DUs,
R ingpul of the NOR-1 gate is at logic

CuupuiU
L. (APe 7N

Output.
:S=1,

uR=1,Q=.
R
=1 (lndeterminale state)

the R input of NORe1 gie s a

B(A) Cireuit dlagram producing output Q1. logic 1 producing output Q

L 2)RESET The oupul Q is ot complement of Q. Hence,
this condition
Cirnt diagriani
keset)
orS-K lalch Using NOK gAes 1sSOWn n
codiios is called asiavalid or
. 7.8.20). Dxallwed. Thas

L4) |NDETERMINATE1 adeterminate coolition

R(Reset)e Hold state R(RESET) the outpat of - 1,
1. Tbes, wbes SSET) = and
1

s (SET) =0 and R (RESE)= the latch is unpredietable. This

coedhdion must be avoided

state is the normal resting state SSetyo

inpues This of the S-R latch. :
Q.1*1 1
ocC For determinale stale
(RESET Raie)
The latch will remain in the state it was hefore the
as belore the
oxtn (EPig. 7.8.2d) :S=0, R -1
1, the output ofSummary of Operadon
(Sejo
utntaly if Q= 0 and Q = I, one input af oe Dus, when S[SET) = 0 and R[RESET) =
gae 15 gC1. Hence, its output is Q= 0. atch will always RESET (Q=0),
oth the npuis to NOR-2 gate are at logic 0, making ou
(EFi%. 728.2(a)1 Acdvehigh SR latch using NOR gales For RESET state :
Q0 ,Q.oi
e, here is no change in the oupu
.
) Construction g .8.21b) shows this condition. SETstate
S(SET)= 1, R (RESET) 0
Two NOR gades ire cross-coupied lo each other. elje 1. producing ouiput
RESE
1, S input to NOR-2 is at logic
The output O NO ge s conneci "S=
1o mgul o NOR-2
the inputs io the NOR-I
gae ae SE 1
boh 4)DNDETERMINAE |
gate and ouur or
R
NOR-1 gate, as shown in Fig. 7.8.2(a).
Be coneelie mput to >Oupus 0.R0Q=0,
, producing output Q= 1. Hg 7.8)
C
conditioa.
The two outputs of the latch are, Q and Q S(Ser
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'8.2(6)
Tech-Neo Publications Fhere durtbors inspire ianovation S0, R=0(Q 0,0 1)(Hold sial
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 DigtalLoic & COA(MUSem.
S(SET) and R(RESET) inputs are at Joeia
7.8.2 Tbe DiitalLoia MO Sem. 3Come
SR Latch using NANDD niay wan
lo latch the outnhigh)

GateswActive-Low SH LarCh
Ths,
we*,KI the output of
ip-2ops
We will analye ue
gn S-R latch
fo called as Inactlve kned in the prevoes sate. it
9Opration of sctve.high
7.84 Explain the working
of actve SR tloutpul combma wnu 2E follows: SRch
lateh by using NAND ates. Sr. No. Thus, Tor hotd slale p tbe NAND pte
D|RESE 0. .Q.. will be"TEany of Its lnput
Summary of operatlon
.Praw low asertion iNput SR
tN nidially the S(SET) and R(RESETD inputs are
ab
Ans. State weever we want 1

A 3 RESET
ircuilt Dlagram Hold E w analyze the cüve-high S-R atch
(4) NDETERMINATE for different
dagram of S-R latch using NAND gailes IN Sn
S10Uow
Fig l

NDETE ATE SaleiS=0,R

2)SET
)RESET SE)ROR SETRRESETD
IfS=0, mput or NAND aie will
S
be 0. (4)
Q=1.R=0,91, R input of NAND-2
producia Hold
gate will RESET
nipus producing outpur
Outputs 7.8.6 EXplain the workina of acti
Thus,
eeto J saeu
Q=1.Q; Ene
hus when S(SET) =
s vaI or Indeterminate condition.De BVoided
0 and R[RESET) = 0, the ...-.
lateh by Sing
NND g
0N Nt
yNgh

SR latehes
SR
. DEERMINATE
Hold state S

This staie
(SE)
:

=0 and R(RESED
g 29i
Actve-low SR latch using NAND e aich i5 unpredictable.
i
g*
An8. The latch wil remain
) Construetion For Indelerminate stale
:Qa1,9o1. ef this inpe
is the suie t wa DEE E

wO NAND Bates are cross-coupled Circuit diagram

ne output of NAND- L
to ech ohe. SET state : S=0,
R1 using
and consinactuon of
actve-agh S-* lcth
When S (SE) and RORESET) both ae t
logic 0 (ow saae
2 gade and ted to input
of NAND- 7.8.4. e e
outpul of NAND-2 ge orNAND-1 gate will be 0. producing e SR latchis
0 ouput does not chang
NAND-1 is connected as input
o ,K I. bhe output of NAND-2 gate wil ve-low e
lalch i s previous sal
The output emains
using NAND gales by sdding erters te te
iavertes S adK nput
The two outputs of 0. Hence, it is called as inactive
the laach are, Q and Q state, s there is o change
C)
...
Truth table
Table 752: Truth table
henwil SSET)
ich
0 and R(RESET)
always be set (Q
For SET stale :
1
= 1, theOutpu
e

nputs
Sset- T9) Thes,for hold state Q-Q0.. .
CT
of Acthve-Low SR aich Q1,Q0 OMputs L RESET sate :S(SET
&RESET state : S=1, R =0 R (RESET)=1
SuE = UR 0, the R input
of NAND-2 gate will keg
Whea SSET)=0
will abways RESET
amd

(Q=
RIRESE)= 1, the outpul o atch
etertninale be (E1i
(un valid 784: Actdve-bigh SR latch wsing NAND
putAND-I gale 1. 1fS =
1,Q= 1,
ie, both the iagas
pas For RESET stale : Q0,Q.
are at logic 1
Thus, w Eg Truth table of acthvehlgh
S-R ltch SET sale : 5(SET)= 1,R (RESET)-
flof ach
latch will always nd R(RESE)-0, the outpst
ETruth table of active-lhigh SR latch
Keset
For RESET
state :
RESET (Q=0).

Q0,Q1
s R.. hus, wben sET)=1

laichwil always be SET(QD

and R[KRESED - 0, te ourput Qof

4HOLD stale : ForSET state :Q1,Q

S=1,Ral No change NCJor oN
0 ge Ncer HoLD Sl NAND-1
and if Q= 0
and o
pae are high., producing
NDETERMINATË
s(SET) 1und R (RESE1)=
state

ouUNLOWNAND Q= 0. If R =1 Reset
Dhe operation latch poAND-2 wilN be Q MhenS(SET)
of active-low
SR laich is
exactly
= 1; i.c, therc IN no ange l and R(RESE)= 1. the output of tbe laich
SR latch. The outna revere of the
1s unpredactable. 1as
ve-gh e condiioe must be avouded. It is called
any IfS Ifs=1 and if Set as lnvalid or lbdederminate coedlidn
of fits input is 0. NAND is logic
QI and Q0, then Q input to
Tech-Neo Publiatiwn
(
NA 1
or indelerminale saie Q1*1
here Qof NAA.
Oof
, .R=1 and Q= 1, hence o 1
Authors iapire
inoevatise NAND-2 ndeterminate (lavalbd) ,Qi-
gale
1e, is 1, there is no change in s

ublicaliuna bee Autburs inpure 34CHIN

SI Veoture
 Dlgtal Logc & coA MUSem 3com
2dge-irgrered ip-lops Diotal Log COA (MU-Sem
Summary of s that respond on the changes -15) Flio-Flops
operation nosidve or negative-edpe of the clock are caPu
led
sitive-coe CRerlng
eteoutput mespónds
trlgrered ip-opx*
. ck pulse at th cot i
Neralive-
pesitive-edge of e ae wo ypes of edge-irggered ip-tlops

Define wh
-
triggerine, edge ti

Hok e 9 ip-
d hanges in the input only
a
Input
the n
ts
dge
to the
of
ypes dge iggered nip-no

"uCEK
eDP
ESET Ans. i
***. 18. e and negative-e
SET R A)Triggering ** siuons of the clock. 2. Negative edge triggered ip-nlops
NDETERNIINATE | nng
:
W 7.9 CLoCKED FLIP-FLOPS Definition The cloCk signal is distnibu.
EF 710.1: F4ge-triggered Füip-Flops
Postbve edge
all parts ot tE circuit ana most of the cir egabve edge
Poitive (Rising) edge-triggered ip-fopsae those in
what is an agnchronos lteh 7 (EFig79S* PoIave
791 outputs change state only when the
clock
and
negaüveedge t
n he level trigg
which outputs can change state only at the posidive (ising
************ ************* makes a transition, S rangitiOn s Leve
Ans. of cloc
r noD-gated laich is called as asynchironous
signal trom postivE to negative or vice verse
tve ceai when active b
rotveedge
a
ciock of
tnggering s idicated
flhp-flop.
bya hangie a ue

known as triga are two types of level triggered latcbes: able inpat

-in asynchronous latch, the clock signal is not applied. ********* aPositive-level trigsered The
Whcnever input is upplid, the lach wil latch s output to 0 6) Methods of riggering responds to the input chaages only when iser odge (1 to 0 or EOGH to LOW) of the clock pulse
ychronously. he different methods used tor trggening are as follows gggenng 3 indicaled by a trange wth
Module
o. 79.2 2 (b) Negatve-leve
esponds to he
Eea
input
e
canges ony wen
ougut ot p-top
s echabie or 3
Ans. : (a) Posidive pulse clock nput isLOW).
SR lip-flop () Dip-flep tip-lop
ch 1s calked as gated o synchrono0us latch
(6) Negative pulse
e triggering
Triggering
UL
Positiv
UU g 7.10.2 shows the edge-inggered flip-flops. D and
Jue nup
op are usad in many appbcations tn-compunison t SK
C (a) Positive-edge tnggenng ip-fhop.
Snal 15 uppiied, the oulpul latches onto
or (ESFig. 7.9.A: Positive and negative-kved triggering
-
Io
------ oizaAion with the clock. (b) Negative-edge tnggeing The Sk flip-lop is cousidered because
t is easy to coastract

4.7.93 What are clocked Hlip-iops? Deseribe Level triggering H 7.10 EDGE-TRIGGERED FLIP-FLOPS
(a) Positive-level yaamk
triggered triggernd ip- lons
* 3
.
triggered
What is difference betwen
lip-lop
Ane.
(6) Negative-level triggered
710.z
up-ops ue constructed fr clock Palse triggering
..e aNd An edgergertd tlup-flop?
ignal. Hence, they are caled
as ele dea There are fwO tYpes or
Ans.: CLK
he outpur ot puSes gated- latch is a level tri ed flip-tlop that responds to
he uptop wil oe caange uniess here s
a (Posiuve pube : A waveform in which
*
A

e e
input clock signal. the normial 1 changes in inputs as long as their clock or enable is high.
K Flip-Bop
gC und changes to logicI momenaniy SR Fig-top
There are twO Ypes of elocked
1ip-1ops
* pulse.
An edge-triggered fip-nop is tip-flop that responds to the
CLK
Enanges in nput at po511ve änd bCganveugO
ypes O clocked
ciocKed pnops e pulse t A waveform in which the Positve edge is indicaed by a trlangle ()

ges
nomal
to logic 0 momentarily R
710
waE ao goM dand
understand by edge- (E14 Fig. 7.10.2/a) : Positive edge-triuered tp-hops
a
produce clock
puE trnggerea
ered Edpo-trigpered Pulse
flip-lops ? Deseribe its classificatior
Er 7l: 1ypes of ecocked Flip-P}ops
Tngering
Ostve
UL UL 1
vegative
7.10.3 What is dynamic trig9enng
pulse
1. Leveltriggered ip-fops (EnEig. 7.92: Positive and
pulse --***------*-****************
Negative pube triggerun
pon that 10 Uhe changes in inputs only as 2
ng
Ans. respona on
S-R Flip-op oFp-cP JRFp-noP
long as their clock or enable is bigh ae called UDefinition: The flip-flops that toe:CLK
as level- by a triangie with bubble ()
irggered ip-o ops. erimg means that the
output state changes Changes in input at the poSEIVE Negative edge is indicaled
e -edge (rising cdge) il or falling tdge) o tE ciock ""
aling edge) of the or at the negativecu age (nsing EIsMb) Negative edge-tregered np-ops
clock pulse.
called as edge-triggerd tup-top Fig.7.10.2 Edge-triggered hip-hopa
Tech-Neo Pabheations ee Authors inepire *********************
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 Digital Logic & cOA (IMU-Sem 3.Com
H7.11 TRUTH TABLE, E Excltation Table Diota Log2OA MUSom3
CHARACTERISTIC TABLE, A *
O Definition An p-Hop
CHARACTERISTIC ecitation table show dliagram
EQUATIONS && EXCITATION excitations that are neeata to change
th
ock 12.1 show e o
TABLE OF FLIP-FLOPS cors S*po
lops presnt 3
E.ate.
97111 Define
****

Truth table An excitation table is also called as

trandtie
***** ***
Ppllcation abie. it oiained rom the tnuth laf
table

ar Truth Table 9. 7 *Direrentiate pEWeen

:ODefinition
all the
: A truth table is a table that shows ----.-. -
itation tab
ND-4-
input-output comiNattoo Clecked S-a Flp-op (Gated SR

Circurt : S. Escitatioe table

ruth tabl 121
aCh)

*****************-----**********-- * No
1's are listed
U the nput combinabons or Dinary os 2na
(C)Symbol
ne output corresponding to everv inma 1.An
ne
eKCaion
o ine 15 a table thu
a truth table shows how a logic circ exelos
ue input-culpu
o e olterent Lhpait combinalions. ax Module

7112 Define charactenistic equation ad

-----Ans. 2
aractenistic table.
--- - * 2 An excitation table s
asoAUn taDe w (D) Truth tabie J
EP 7.lL1a)t Lope symbol of clocked Sk tlp-tlop

alled as transition table or able 7.12.1iiruth tahe at clocked SR up-ip

haracteristics Equstion3
eloeea ****
application
en table. Tt
s spu
O Definition
Dehnrtion :
The charactenstic
The equation a
able.
obuained from the rh combnaions. EN (CLK)
sR G
oP Provides the relation between the
M 7.12 CLOCKED SR FLIP-FLOP
Cherecterlestle Table
O
eDefinition
on Charactenistictableic
Characteristic table lists the
na next
Q. 7.121 Draw
NAND
and explain
gates.
SR flip lop sing
o
*********-*-- **-*********

.of the flip-flop. Ans. :

In order to obtain the charnaieritie
****

Indeterminaie (mvubai)
a K-map for aext
state DeBcrption
wnie the characteristic table, draw of
he t0p tn ems ot the present sate and inputs and is also calld as gated SR latch. It needs a Enabie (EN
itL No change NC)
Simplity EiOCE (CLR) input
Q. 7.11.3 What do you4 understand by an ouy whicn the ENCLK) is HIGH, the S and R inpus
hange their Laie.
Ana. t is also called as synchronous SR latch.
t the EN(CLK) is low, there will be no stade
Excitation chau
p-1iop changes its state only when the clock is

ODefinition : An nput signal that controls thej fence, they are called level-triggered fnlp-flops. SMCRIY SAP Vntare
flip-flop to modity ts state is called as an A

excrtatie ********* .

********** redibw
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 Digtal Logic&COA(MO-

EOporation Characterlatie Equstion -Sem.

** wu

SSELD
,
analyze the clocked S-R lip-flop for dilferen

ch ac AS tolo
ESE
Table 7.122:Charictersuc Table
for S

LreentsenpuSNe
op
(Truthtk
able)

state
00 transition

r he pr
0,
of the
and if
the
the inputs can be either S = R=0(no
-lop
he next state
On
pube, then
is 0traneldon
ent state of flip-flop is 1 and next
Fig-

state at
FRops

tp-llop
Hold Q SR9... S =0, R
reet
condition). condition) o
$-0 EU0the application of the oext ckock pulse, the inpuks
Hene, D**0r00 transicion e or 1
KESET 0
transitlon
,R=1 Reset conditiom). Tbus, SR 01 for 1

nition
SET 0 1+1 tranedon
NDETEN If the present stale or one tup-tlop is 0, and if
or te nes
a Sle of
Tupy be 1 . epresent stale of the flip-flep is 1 and next state of tlip-
Hold DeRt clock pulse, the
state i S(SET) = 0 and R(RESET) = nis gmust be S = 1, R=0(set condition). Thus, SR of aeat clock pulse, thea the
This slale is normal resting 10 for imputs ca
pBDO
state of the S-R tch 1anson a change codidion) or S= 1, R=
he
Or his
lalch will remain in
inputL
the state it was betorE he
ocne
1 01 o Ofet condibo8).
Vet conditioe) R -0,
but S can be 0 or 1. Hence, SRx0
for
When S (SET) and
R(RESET) both are
1trmibon
00w SIC), ne stalle ot oulput
ope
oes Bot cag
Ouput remauns latcbed nap SunplnbcaDon lor S-R
in its previous staie Hence, it p-top C Tmng Dlsgram

..
is
ESiale ae
at o cnange in stale.
Thus, for Hold state
SR - Fig 1.l2.3 SowS E
pa a pwavetorims lor a clocked S-R Fip-flap.
Q 10
aL RESET tate : S Module
(SET)=, R(RESET)=
When S(SET) = 0 and
R(RESE)= 1, the output of latch
ways be RESET Q
ForRESET tate : Q
,Q1 8+R0.
S. SET state :
S (SET-1, R(RESE)** EMFlg. 7.12.2: K-map
for S-R nip-lop
Thus, when SCSET) = Input
I and R(RESET)=0, the output Characteristics equatlon
atch will always be Q of wavelom
sET Q=1.
The characteistic equation
For SET state for SR flip-thop is,
: Q1,Qm0 (CLK
a4 NDETERMINATE state RQ,
dtE1)*l 9BKcitatilon Table of SR Flp-Flop
and
R (RESE)=1
When S(SET) = and
R(RESET)= 1, the output ot We
Is unpredictable. the latch excitation table of S-R Ap
s invalid

For INDETERMINATE
1his conditon must avoided.
or Indeterminate
be It is called
condition
state :Q
ans.
----- --. ****

,Q Tbe 7.12.3 shows the

excitation table of SR
Summary of operation fip-top Output
Table 7.123 : Excltation waveron
table of SR nip-op
Sr. No State
aNext state Required inputs 2

L
Hold
S R Egeg- 7.lInput and oupar wao x Eup-top

RESET
E SET
L INDETERMINATE

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 Digital Logle& COA (MU-Sem. 3-Come

Step ,R0att otal Loe Comp)

I :Before time the cuitput Q does not ch
Truth tabie
becuse the EN or Clock (CLK) is LOW. ponuve Flip-ic
Sep At oime instant
t, ,R=l, CLK s ooo rabie
caggeredtip-p
Thun,
S0
e dQuQ..Q
*

Inputs Outputs held state

for hold
Thus, for
w reset the fig-nop output to Q = 0 and R Clock s R
Se
Q.. ai

Sep I:
Q=t.
At tme instant t- , S-1, R =Q. CLKI wi"

Tg:
oo0b
0NC) or
u>*,R
RESET State 1S-0, R 1,dlock

m1, the output Q

T

becomes LOW on positive cdg

Q*0
e u-lop
,
changing its outpu to Q=1 and
Before time though 3 k5
Flipop Rese ip-lopsSt
kHoia

he SR ls
l, lp-fop RESET (ceared Q-0).
utput Q and Q does not change becase Co
7.13 POsITiVE EDGE-TRIGGERED oESET For RESET state : Qu Q
SR FLIP-FLOP
is LOW.
Suep SET State tS 1, R -0, cdock T
I: At time
I instant
istant t = S=0,
t= R= 1, CLK=
4, S = 0, R
CLK-I wil
1,
wilt I
743.3 Draw the logic diagram
-- ET
of a pos fS-1. R =0, the output Q becomes HIGH on

StepV
reset the tlp-flop output Q*0
and Q= edge-trigseredsKFp-Flop cdge
the ponitive
of the clock pulse. The SR fip-flop is SET(Q .
:At üme instanl
set the 1lip-lop outpul
tl,S*1,
Q=1 and Q= 0
K*u,c *"

A Ans.
-- describe (
-
***-.- ----
and

i
Cnale (invalid)
For SET state
:Qi,Q.ut
:Q 7.12 Fill
in ee vales ror
SR to cause the NoChange(NC) INDETERMINATE state
olu LA BlocK DIagraim_J ,R= 1, cock T
Block diagram of a
posiuve cogeinEed S-* fip-flop E 0 0peration F S =1, R n
, and positive edge-uiggeed clock pulse is
own in Fig. 7.13.1. is pued,
**** the output of the ip-fop is unpredictable.
The S(SET) and K(KESE) inputs are called as synchronous Module
s cobaibon is indeterminate (invalid) coodition
conto npus and must
D e avOkded,
TO Only when he SR Tup-tlops
clock is positive edge-riggered,
puts the output of the thp-1lop wl For INDETERMINATE state : Q
Clock (CLK) change. x,Q=
Flg. 7.124 The S and R inputs cannct alter the flip-tlops Summary of operatlon
output in the
Ans absence or the ciock pulse.
Output
Step Att=S=0, R=0. We will analyze the posiavE edge-nggered SR Tap-fiop State
(iE19 7B.I: Cocked SR ip-flop for Q
The SR tp-flop is in hold state with output (positive edgeiriggered) Hiierent mpuvouput comenanoas, wnc are as louows
Q=.
Sep i Att (B) Symbol Hold
Sr. SUte sSETD RRESETD Clock
Fg
flip-lop.
7.13.2 shows the
symbol of positive RESET
The transition edge-tiggered Sk
of output from 0 s ()
)
SE
R=1(Reset condition). when S 0 (4) NT
*s =
0, R=1 at 4 RESET 0
L DETERlNATE
Step ta4
1ft Att uputs
(3) SET
1 L(5 1Tlming diagram
The output Q
The transiton of output
0.
9 NDETERMINATE hg 13.3 shows the input and output waveforms of positive
from 0 0 is when S
no change) state or S =0, R =
0 Fig 7.132 : Logic &L Hod State : S = 0, R=0, clockT edge triggered SR ip-tlop
symbol of positive
*8
Keet condition).
edge-tnggered
SR ip-nop
*
0, R=zatt= 4 it S 0, R =0 and positive edge-trnggered
Step IV : BC) cioxa poe
Atts Tuth Table
output of the tip-flop remains in its previou
The output Q
1. e 713.1 shows he Tbere is no ehange in the flip-top
The transibion of output inom
e:.
p-Top.
dhe ruth
table ot positive .1)
0I is when edge-tngge output
S=1,R=0 (Set condition).
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 Dgtal Logic & COA (MU-Sem. 3-Comp)
(22)
Digtal Logics cOA (MUSam. 3-Comp
sIse ip-FiCps
o
nn
irguCleck (CUK
Table 7.14.1 shows the truth table of negative edge-triggered
tip-flop will trgger on the falling dge ot e
h
L L naye the positive cdgc-tnggered S-R 1up-1iop
R(Reeet) uoutput combinabons, wich are as follows
le SEDRESETD
Wavefom No
-R aFig. 7.14.1
1
Chcked SR nip-lop (a
e edge-triggered) )Hokd
Symbol (2) RESET
B)
3) SET
ol of a negatve eoge-nggereo
* 1p- tlop is shows in NDETERMENAIE
ig 1.14.2.
)Hold Stale :S = 0, R*0, cock

wavefoms inputs SR-0 and negaive edge-triggered clock pulse is

ped, the output of the fip-fop remains its previous in

here 1s Bo change 1a une ep 1g sc

riEzz]eg. 7.1l4.2 : Logic s nepauve

Step
139: Input and output waveforms of posiuve
edge-iriggered SK nin-
edge-triggered SR in
a )
as, I0r hald staie Q

RESET State : S , O.G-Q.

R-1,cock
Module

I: taitially we assumes = 0, R IfS=

on ncsive (daliees of the ctoc
=0, Q= 1. At time StepV: A time instant t se, when the fifth posiive ede
eder
Truth tabie ot a egatve edge-mggered S-R ip-lop is
the
tTSR i
pulse is applied S-
e edge clock
B applied,
S=0 R ive ahow in iaDIe. .19.- fop is RESET (cleared Q0 Thas, for RESET state
of up-tlop will remain in its p
netap-lop Table 7.14.l: Truth table of negative edge-triggered SR
will be Reset. The output Q(low) and Q=1
Oa0,Qa1
p-tiop
0 till tbe sero
Q1,Q = thigh).
second clock pulse is & 3) SET State : S = l1,R=0, clock*
applicd.
Inputs Outputs u the ouput becomes GH) 0 the
Suep VI : At time nstant Degatve edge ot the cloct puse.
Step 1T: At time ist
tt, whcn the suzih pouve
o
n
cona postive ,S ,R=0. The p-op 0 0 o he SR fip-Dop is SET (Q =1
edge clock Dule
0,
willb nd
the output hange (NC)
Thus , for SET state Qu1,Q=0
** Hence, the S-R Q
=
(hi
p wll RESET
1

Fig.7.13.3.
and Q =0 (low), as shown in
causing Q=0 (low) and Q-1 a9 ndeterminaie State :S=1, R =1, cbck
(high).
T RESET fS 1, R =l and negaive odge-tnggered clock puse is
H 7.14 NEGATIVE EDGE-TRIGGERED
Step Ppbed, the oulput of the tup-llop is unprodictable.
M: At dme instant tc,
whea the third posituve
edge SR FLIP-FLOP This conditon is indeerrninate (unvalid) condition and must
8 C puse sPpuea, s SET
R
1, =0 will e avO
Draw* logie diagranm of S-R ipRop
l ouput
DC (low)
be Q will e 1igh) and
*p-op
with negative edge-triggering Lndetermunale (invaliad)
For NDETERMINATE state: Q Q
ar
and Sr.No. State Output
Write its truth 9genng 11||| J
p At ume tnstant
d, when the fourth positive Ans *******------ -- - *| No Change (N
Opulse
R*0
isapplied, S
will set the flip-lop. Output Q will
(high) and Q wil be 0 (kow
be 5iock dlagram
LO (D) operation (2) RESET

Slock diagram of a negative

ywnen the SR 1mp-tops ciock nega
canno
SET
edge-triggered S-R (4)INDETERMINATE
show 1
ig 2.14.1. tup-u,
putot tup-flop will change.
o
eo k pulse.
aller the flip-tlops output in absence

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 Dgtal
Tmg
hows
Logic
á COA (MUSem 3:Compl
Dlegan
the input and outpul wavefornis
of negive cgeue
Digia
a 1..5.5
**********
R
OA MUSem.
and CR
1
can a
respond to its contrel
and cleck
, .
Comp)
PR (Preset)
in-F

*
. inputs?
--****-*** - noutsCeaPFLO
An
PR and CK are n active low inputs. when PR1 R
CR 1,aug-op po
elbrme 1s control and clock i

eg 7.16Z: Loge symbol of SR p-top wth prea

With PR pexet
and clear inputs do not
allect une up-liop operation. and ciar

7.15A W asynchronous ine Preset (PR) and Clear (CR) are activc-iow mpuy

.. **************
...-
overmaing
- y Bubbles as showp in hg 7.6.
(C 0p
Ans.
a
heare caneu EPR) and CLEAR (CR) Normal SR fip-fop : PR1, CR
Olpt
npus
s " y overnde the control
rPR =1, CR=1, the SR ip-op operates ike standard SR

t indicates that in the prEsence ot the asynchronous inputs the Module

other inputs become inetfecve. 3
a SET state PR -0, CR=1
:

1E7Pg. 7.143: lnput and output waveforms of negatdve H 7.16 SR FLIP-FLOP WITH PRESET e output of NANDI will be "logic I
edge-triggered S nip-flop AND CLEAK Al the inputs to NAND2 gate will be "".
StepI : Iniially we assume or NANDZ will e - 0. Thus
S=0, R =0.Q1.At Explain preset and clear pin
EDN, 0utput logie 0' (Q

int cloct pule is

ime
aptiod* 7.15 PRESET AND CLEAR :a.7.16.1 i Pk =, CR1 wil t ue u
at the allingedge
p-liop wil remain in perevious

Q=0ill te falling edge of seceod clocl

stade
o= 1.o714
pulse
Plain
----.
the neca of preset and elear Ans.
Hop ?
-**************************** 3 RESET state t PR=1,CR*0

f CR = 0, the output of NANDZ gaue will be ogic

Sep 1: At ime instant t b
A) cireult Dlagram
*n cdock pulse, S =0, R =1 .7.152 wkat are PRESET ana
CLAR IPw
the fip-flop will be
Reset Q-0 and Q=1.
" ***************-
Ans.
irut diagram ol S-k Tup:-tlop with preset and clear is
All he unpurs D NANDI gate wl beT
Suep l i Al ime indtant tc, on the Hence, the ouput of NANDl gaie will be "logc 0' (Q=0
falling odge of thind PRESET PR
we eSRTp-log

Y
Spiv*
*u be set Q-l and
Q=0.
1.R 0. T

At ume instant t d,on the falling

polse, S
I, R»0. De
p-tkop

edge of fourh
lourh
QRDd Q is uncertain.

However, inm some

Ever,
s powered om, the state

The outputs can be (Q

Pplicabions it is essential
ot the outpuis

0,Q= )a

nputs OUtputs
. s, PR = 1, CR =0 will reset the fip- fop

Ihdeberminate state
PR = 0 and CR
:

0 condibon
CR

eas to uncertainor
to set or resei te
will be set
Q=1.0=0.
p uput Tup-ps, e, an 1aihal
stale must be aSSgned to a
L indetermiaate stale of outputs, Q and Q Hence, it shouid e
Sep V At ame
w ined with the help of preset
(PR) and cear
NAND2
istat ,ohe falling edge of fith
avcided.
pulse, R S dge af th ER
hal
And CR are
ynchrunous or direet inpub
Etlip-flop ime between SR p-Mop at any CLEAR (CR) Table 7.16.1: Operation df SR ip-nop
utput Q=O and
Q. instanl a
Suep SRThip-nop with preset and ckar
te 7.16.1

..
:

V: A time instant tf,

00 the falling edge
ofsixth
synchronizatkon
The peesel and
with clock
rrespective of Eg
Inputs Outputs Operation
puise,s ciear inputs ovemide
Output Q=1 and
u
Etlp- flop IS aso called as
DC S
all other inputs (8) Logle Symbol CLK
RCR
Q=0, as shown in Fig.
7.14.3. sDC RESET or
RESET or DC CLFA
DC CLEAR et (S,). CR is called
or Direct Reset
Logic symbol of SR flip-flop with preset and clear is shown
Nomal SR
ip fNp
eprseiinput forces ouitput (R. ,7.16.2.
ip-liop 1s se
s00ow) Q1 (high)
(high) and clcar
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Uo 0 |p-top is neset
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 MUSem. 34
Dpi Loo s cOA.MUSem 3Cemo Dip 0A -Flops
H 7.17 CLOCKED JK FLIP-FLOP
)Logicyesymbol Opertion
y mbol of clockeo K nlip-flop E
elkedloguc ugr Fig
Loge
7.17.1c%
Show
ation of the J-K fip-nop 1ss similar t
Op
smlar to the
7 Draw the
Descrnbe wo
io-oe operation

K p-Rop.
LAO SD), Dec.SR19.
5Marks
CLK
I analyze the
input'output r are as follows:
oper00
conons, Whuch p-tGp 1or ked
p
a. 7-172 Druw JK Aip-Rop using p- upus S. No Stae
and additiomal gatas
(1)Ho
EASEI
Dec 16.3Marks
.0.0 Fig 7.17.1c) Lgeymo CEd JK nip-ton
J = 0, K =0,0-1,0-0 Hokd state)
Deserplon )SET 146):
E A Cireut Dlagram 19 4 |TOGGLEI us, when K =0, CLK 1,
output remasns
there5 DO change the
Jk ip-flop s sowa tisa modifcason of fip-flop. ln JK fip-lop, te kter or
Cireuit diagram of cocked " SR Ouput. 1The in t5 previous
Fig 7.17.1(a) and (b). Hold stale i
9 * u, =, CLK = 1

stands for SET and A stands for RESET. The imots a1. Thas, for HOLD state Q,. Q, O
cNe S Snd R inputs to the SR ip-on Initialy Q , Q=1, Js0, K=0
T 2 RESET sate : J = a, K=1, CLK 1

npus The unpredsctabie siale > = , K 5

1

3 delined in the JK 0.1=0

nop as toggie sLaite s , *I% R= KQ0.0
WhenJ Q, CLK
1 both the
Q the

o NAND 3
ale will De log 1. both the inputst
inpuits

his aso called asIK ialch or ieve -nggcred JK Mip-lop. When J=0, Q=1, CLK=T the cutput of NAND-3 gate wil Module
NAND-I gae ar at logic 1, the output Q 0
3
neme7.17.10):Logie diagram of docked JK flp-lop anus and R mpus.
a ANDEG oupus Q and Q o ge de s The rwo npu
output ot NAND-1 AD
15Q=0
gale ane al lopie1. Hence, the fK=
logic 1.
1,Q= 0, CLK = 1, he output of NAND

Wheo K s 0, 0=0 CLK = 1, the ouput of NAND4 gate s he input to NAND-I gue is a logic 0, the output o
S
NAND gute will be logic (Q * 1 3 show in
The Qinput to NAND2 pale is at logic O,
esuling in output
= KQ 1.114C).

T-K-0Fe 7132
State of output when

Q=0.
Thus, when
J -, K - 1, CLK = 1, the fnp-Dop reets

nEzmPig. 7.17.1(b) : Loge diagram of clocked Initially ir

g SRIip-nop
JK =
0 Thu, for kESET State Q,.i, 1.

=
Q=0, CLK = 1, he output of
When J
.0,
NAND-3 gate will
) Truth table be logic

logc 0, resulting n
inenput o te NAND- gaie 15 at
Table 721A: truth table of docked
Jkp-tlop nputs Outpus
Inputs Outputs Lapats to SR ip-lop
State When K 0, Q=1, CLK = 1, the output of NAND-4 gale
EN (CLKx will be logic 1. Both the inputs to NAND-2 gaic e a
logic 1. K
No ange(NC
InputsOutputs enE, e output of the NAND-2 gale is
717.20),
Q0 ie, theres
(E3ig 7.172Mc):J=, k-1,CLK=1 (RESET state)

SET state 1, K =,CLK L.

E JK Q1 NAND1 1
ai : J

the output of NAND 4 will be kogic

00 Wben K=0, CLK 1,
=

f both the inputs to NANDgaie ae ogc ,e op

puts Outputs Q=0.
be
output of NAND 3 gate will
Ifj= 1, CLK 1.Q=0, the
gade is a logic 0. Hence,
The Q input to NAND
I
1.
logic

butput of NAND-1
gate is
91,ie, J K tlip-fop is et
N Change(NC)
eFig.7.17.2ta) : J = 0, K=0,0=0,0=l (Hold stat
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SACHIY SELAH Vestur inavwabioe
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 LOgiu a LoTP)
(728 unpredictable. Tis condition
Diital Logs A cOA (MUSem.so ransition he output is

ben. K*0, CLK I, the

mp hp k *L
Table 7.17.2: CaAracersue r K Nip-oo 01 present state of the lip1op is 0 and next state is to
e
PE
o-(O=.
" he

, hen
the inputs can be 1, K =0 (cet condision) Fig 7.174 shows the tining diagram of
the clocked k u
Thus, for SET state Q,.1-1,0=0 or
] = K= I (toggle condition),. I = 1
bat K -0or 1. hop
anno be
the JK latch or clocked K
sp-tiop
trnsition. eticaly.
ience. J
0r 0* ed s s because the oup eud
the nput
oupos
10no ue
y change in the output will
alfect
present state ol 1pIOp " 1 ad nest sale is to be FIg 7.17.4 hows this.
ue inputs can be 0, K )= 0. K=I, tbe outpur
0, then =I (rEset conditdon) belorei Qis HIGH. Alhoogh
.
ogcon
.
or ' 0or 1, K=1. w O Cnge becauseCkBL
-0ransiton. 1
Hence JKXI Tor i
Step 1: During interval .-0, K=1.cLkl.
amg 1372N):J=1, K-GC=1(SET)
p-top is reset and

state : J - 1, K=1, CLK=I

11 transion e
TocGLE
Step 2: During interval 1
J=1,K1,CLK=1.
. if the present state 0r Une tup-1op 1s I and the next state is to
Whea ckock pulse is applied, kt Q -0, Q= As
*K-map stmplification for clocked JK Hp-flop be 1, then the pues can e either 0. K 0
CLK=1Q1, the output of NAND-3 gle will be logic 0. or 1. K = 0 (set condition).
(0o change conditon)
As one input
gae is hogic 1
o NAND-I gale
(Q=).
is logic 0. the output NAND-1
01
11 10 , 0r
.
ough
JK Modulee
CLK=
JK x0for 11 transition 3
irK=
ogic
1,9-0,
1. As
CLK = 1, the output of NAND4 gate will be
both the inputs to NAND-2 gae are logic 1, the d d : Step 4: During interval -,1,K=1,
up-nop 1ogzles.
CLK.
1
utput of NAND 2 gte is Q-0
Ans.: Step 5: During interval t,-J =0, K - 0, CLK = 1. Te
When clock puse is applied, lt Q=1.9=0 *, On every clock pulse, chunging the output to Rs opposite st fip-flop remains in the same state, eved ater
AsK 1, CLK= 1.Q =1, the output of the NAND-4 g Esg.7.173: Kmap for docked JK nip-lop CLK 0.
or complementing the output is caled as togling
w Deog 0. As one inpul lo the NAND-2 gate is lopic Characteritic equaton for clocked JK nip-lop
its output is
Q=1 7.17.1 Race Around Condition Step 6: During interval,- 1, K0. CLKI will
..30,K,Q,
AsJ-1,CLK=1,Q=0,de
logic
e

Thus,
1. As bodh
the
otput of the NAND
when J-K=1, CLK= 1, the
I
gde is

JK nig-fop togzles
putofNAND 3
inputs to ibe NANDI gue
Q=0.
art al op. . .
Q7.17.
Ans
(G)Excltation Table

Draw exeitation table of

Jk Hip Rop.
UQ. 7.17.S EXplan
K

overcome
the race around
flip-fiop. State vanious methods
condtion
to
in

Step
Step 7:

8:
set the fip-flop and Q= 1.
Dunng interval

Duriog iaterval
-
h-J=1.K
,i,K51,C

-1,CK
-0. The
MO.16) Dec. 15, 2 1M.0 1e). Dec. 16. 5 M
-
Thus, for TOGGLE nip-flop remains in the same state and Q- 0
state Q..0.0.. Tnble 1A13E Excitatioa
Summary ot operaton table of Jk fnlip-hop
7.27.6 What is race around condition ? How Step 9: Daring interval K=1, cLK = 1. The
l-1,
t Be |Net state| Required lnpats to overcome
t 1p-top ogges.
Slale Output
LO Sa Dec. 1/ 10arkS Sep 10: Durning interval
K=
Tip-thop remains in same state Q-0
1, CLK =0. The
OQ. 7.17.7 Write short nots onRace arour
condrtion Step 1l: During interval o =K=1,CK=1, the
ip-tlop toggles
RESET
o 0Oransroon
*---..
Ans.
QAAY 15, 5 Marks

SET when J = K = I and clock is applied, the output wil

L ToGLE O , then
Uhe preser
the
0 Uie
1up-lop is 0 and next statc piement itself till the clock is present. Hence, al the end
put can be=
(resetcondition).J 0. K = 0 or J = 0, K
5
= 0 and K = 0 ar
-Neo Palblications Hence,
bere Autborsin JK = x for 00 transitio.

-A SACHIYSHUI Veatore Torb-heoP

CLODs berr Authors Lpare AnaD -A SACHIYSHAH Venture
 tal Logic A
Dgita Logic & CoA (MU-Sem. sc009
naster flip-lep is ponitively chcked
31)
and the slave
negatively clocked. t indhca
fip- Ans.
master is inactive and slave is
alwben thecioxk
nctve,
(A
-
ahrn the clock is high. the masier flip-tlop ALogc dlegram
willbe active and
dagram for positve edge-inggered Tp- *
ave lip-flop wil
clock inpul
e nuNG,

ee es negalive edge n its

around condition is avid
LOBiC

own in Fig. 7

Aster-slae p0p.

a 7.37 w Most widely used

JUL
-- (C

Ans. ip-lop 8 mos wiaety usea ip-tlop. It is the mos

TheJ
erseeou pog.
47.1o
Q How d pes JK fip-Rop differ foc (EPlg.7.18.1 : Positive edge-trigzered Jk up-top

1011 flp-op in s operation ? What is its 6) Logic symbol

Emig. 7.17.4: Lapat and outpet wavelorms for JK ip-lop_ Eie ymbol ot positive edge-unggered IK lip-flop is shown

-During instants p, q, r. s and t as shown in ig. 1.1*

Ans. rg i8.4

Ouo onunucsiy togs

)4<2t<T (Fg 711a 100

E CRK* puise-wMn and, 1s ong, ien nc oupur -la order to avold the race Dirierence
, is Teduced such thatcondion,
around
he p-flop
an so0m
conbouously changes from 0 to I,T o u, D to
puse-width of clock puise , <21«T. In a sR p-lop, ne
comaaton R=ls invalid or s=. Oupus
indeterminatc comdition, as output becomes unpredictabNe.
C
Le, the output oscillates (toggles) between
propagation delay 2t can be increased with the help of
e
In a JK lip-lop, the condition J = 1, K=l is toggle mode;
At the end of the clock the lumped delay lines in senes with he leedbuck. However, f s
npredictable,. This condition is called
condition.
not feasible
E
, p-ilop swILtes

T he propagation deluy of each NAND Bale and Advantage over SR 1p-fiop C Trvth Table
T, tnen uhe up-lop ouput os te Tor every 4t
The loggle mode operation of IK fip-fop is an advatage Table 7.18.1: Truth table of posicve edgetrierered
(0.8, propagalion delay through two NAND gates
in series).
cver SR fip- op. which makes them suitable to be esed in npple JK up-toP

counters. Ripple counters need the flip-tlops to be in togge mode.

***
Q. ****
.....
7.17.11 Whch lp-op P Cock
ioC pLse
(EsgFig. 7.17.6:t, <2t <T
otngr

- :
..
Ans.:The J tup-
)Using edge-itriggered K nip-flop
4 7.17.12 Which flip-flop d tor da 0
In

ng
cocked JK fip-flop. the clock or enable signal
ume penod.Hence, 5 ..... lo
RESET
MetnodS TO BVOIo
Tace around condidion the problem
0
mpie loging) takes pluce. Ans.: The D-ip-lop is used for data trasier.
a 7.17.s Explain different
aurerenE methods to ***
av
"c ered k 11ip-Hlop, the rising or pošiuve
POSITIVE EDGE-TRIGGERED
PI availiable for a short time. Hlence, mu 7.18

.
Egw not occur.
JK FLIP-FLOP
Ans.: The race around condition cun
Toske
c2t<Tcdge-inigered JK
Cing ip-lop
be avoided if:
(l) Using masterslave
n masler-slave JK
nip-flop, two
JK nip-lop -
9. 7.18.1 Praw t
raM of a
diagran
clam
positive

(ii) flip-lops are used. ne No Change (NC)

Using master-slave JK nip-flop Op s as a master and
the second fip-flop acts hke a s
*--*---*****
deseribe e * SACHIYSHAB Veature
Teeh-Neo Publirations-"hee Authors inpire A
inoenatiae

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 3-Comp)
Digital Logic & COA (MU-Sem. 3-Como DigitaloioA Sm
Thas, for REsET state Q, 0,Qa-1
operoa as 3 SET state i
J*1,k=G, LKT,
sep:ni and CLK
edge of
=
0. Let the

instant I= a
initdial
Loge uymbol
K inputs are synchroooas cootrol InpuBs, da| the positive
nd Logic synbol of negative edge-uriggered
u hodity the state of tlip-tlop oa the Posive c When
J 1, K=, on poAGvE
NAND
(ising) edge o
gate becomes HiC
K=0. Hence, the fip-flop
sets The

till tic posiuve ege of the next k

ot
s in Fige 7.19.2
palse, the output of pulse,
) and K inputs wl not A
(Q
Aence of the clock pulse, the
affect the output of the flip-tlop. IK ip-flop is SET (Q=. p2 At timeinstantb, at the positie e of the Outpus
red JK secod clock puse, 0, K=L The fip-fop
We will analyze the operation of
Ps Ths, for SET state Q, .
1,
0=0
uupur comoinanns n resets. Hence, Q gDES LDQ=0) and Q goes

a4 TOGGLE state
:J1, K=1, CLKt. HIGH (Q 1
Pg 7.19.2: Legic symbol ol Degative
edge-tngio
S.NoStJSEK(RESETD Clo When I 1, K=1, on positive (rising) edge of the
Step 3: posive edge of the
pp oes; ie, output changes to 1 ifit was
9or Mo eles: ic o changes from 0 to I and (C Tuth b
2)RESET 0 Table 7.19.1:Truth table
o epaave gtnua
Q changes from to 0.
Thus, for TOGGLE state Q,
3)SET 9,.O0 JKip-Do
Step 4
A pats Outputs Sate
Summary gf operauon fourth clock pulse, 0, K=1. 1he lup
LO |1oGGLE |1
E Outpur0 Q1.
and
KESET,
&1
Sr. No.State 0utput Modn
HoLD state : J,

,
KG,CLKI. P0sive edge or the
wen and K are Low, the output does not change
StepS:At ume insuant
tifth cioc P
he No change NC) 3
ois 0
bodni O= and
ron spreous staie remains in KESUI Suewu
Le, there
is no change in he p-1l (1Hold
Ouput(ur1.G5 anO
rou 1 RESET Al time imstant
o RESET
Thas, for HOLD state O..-Q,, aQ, Step 6: sixUh c ee State with cutput Q=
a remains in RESET ate 0
0 I SET
2 RESET state : J-0, K= 1, CLKT.
4TOOGLE
When J= 0, K= 1, on positive (rising) edge of the clock
EDGE-TRIGGERED
pulse, the fliplop is ckear or RESET with (Q0 NEGATIVE 0. TOCGL
H 7.19
JK FLIP-FLOP
logic diagram of a
nagative No CchangE N
(E) Tming Dlagram 4.7.19.1 Draw the D

4ge-triggered k Fp-Fopana O
Fg .18.3 shows the input and output waveforms ot the positüve edge-irniggered JK ip-flop. O Operat
ae *******

of the clock pulse. mputs will no

LES (A) Logle dlagram of the coct pulse, te aodK
Cn the ubicre
he ogc gran negative edge-inggered k
Fig 7.19.l shows re as
JK tlp-tlop and nts symbul we w
et inputioutput com
trggered
xRSEDClodk
T StateJSET
Ovputs Hokd
(1)

wavom t- (4) 0
edgetrigeemed JK p-o ASACHLYSEAN Veature
Negatlve
(EFlg 1.19.1
1

ESnFie. 7.183: Input and oulpul wavefoms for

i,
poSItive edge-trtgrered JK
Tp-lop P.JbJir
eeB-NcoruDaoo
Tech-Neo Publications here Authors inspire sanowa tios SACHINSHAH Vestu
A
 Diplial Logic & COA (MU-Sem. 3Come 3-Co
Diotn Lo c&COAMOSSm
a. HOb state : J=0, TORGLE state
i, k1, CLK4 35 F
K*G,c* Iaitially=0,
on the negative (ralking) K =0 and CLK = 0. Let
K
when1.K1, 1:
Loglesymbol of JK nip-lop positve dge
d ae o
LOW, the cuput does oges; edge
e ef
the
i.e., atput changes clad state of lip-lop be
the initial (6)
PRESE
cutpur (af Q=
1.. dirO0.00vea ier t was and to 1i Q. Q=1.Attime instant cuveOw
,
vice-versa
DEga Ve edge of ckck pulse i npplied.
a ue egave edge of the i clack puls

Tha,for HOLD state ...-0,

Thus, for 0KLE stale Q-0, J=1. K. The ik tip-tlop sets and output
or operalon Q=1 (HIG)
a Summary and Q=0 LOW).
ae: J
RESET
, KT, cn
4K=1,Ck
the negati ve (alling) edge of the ckoce
** Tp-lop is cleared ar
Sr No Stale Output Step 2 Ae

secoBd clock pulse, J

, uie negaive edge of the
1, K =1. The fip lop

.
RESET (Q=0
Q togee, 1.e. Q changes
hus, for RESET suate
trom 1
to 0 and Q
Q,. changes tromOto l.
SET tate :-1, Hold
K=d, CLK Step 3iAt e insuant t C, al the traling edge of the (Epl. 7202: Logic symbol of JKip-op
A, 00the negarive (falling) edge of the clock RESET 0 third cock pule, J = 0, K = 1. The ip-lops
(posttive edge-triggered) with active-LOW PRSE

a ae
GH(Q=
Thus, for SET state
The ip-0on
) The S
lip-tlops sET(Qs
becones
0)SET RESET with Q-0and Q= PR aad CR are both axtive-low asyochrooous inputs.
Q,.,
p n ant=d ate fulinag edge of te goperaton
tourthcck puise, ,K u ie tp-tiop wi"
1. Normal JK ip-Dop -
: PR CR=
SET with Q=1 and Q =0
B9 mngdiagrem I PR = 1, CR- 1,ie. both are inacive, the fip-thkop wll

HE7.193 sbows the input 9Step 5 : At time instant e, at the falling edge of the operate as a mormal k up- ttop
aad output waveforms
of the negative edge-aniggered finh clock pulse 0,
Jk flip-flop. K= 0 the tlp-flop wl a 2 Preet state : PR G, CR=
CLK
ne saDe 0=1 and Q =0.
in stale with
0. the ouput of NAND-I gale will be logic 1, iL
H 7.20 J-K FLIP-FLOP WITH PRESET .he nup-tlop is SET. A" the three inputs to the

AND CLEAR NAND-2 are logic 1. Hence its output,

9-0
Thus, if PR =0, CR-1, the IK nip-flop is SET.
wavelorms Descnbe the funetion of preset and
7.20.1
: Ar Sate i
PR 1, CR -0.
clear terminals in JK fip-Rop. Wnite
truth table o -
1.CRa0, the Jk fip-op is RESET, ie.Q-0.
A Ans. : a4 Indeterminate state : PR= 0, CR-0

A) Circui Dagrm c
resuts in invalid or iaEtetnaunae 0 shold be avoided because it

Circuit diagram of IK ip-tlop with preset and cicar 1s Own

fable 7.20.I shows the summan of operanoa of positive
in Fig. .201.
Ik Tip-flop.

Table 720l : Summary o openn or peanutive edge-inpered

JK dp-hoP

penomed
Eselg. 7.19.3: lnput
put Normal JK fip-lop
Tec-Nee Publicatioes.
and output
waveforuas |G
Pbere Autbars ol negaive
inpire edetriggered PRESE
iseatioe JK ip-dop
(EGFig. 1.20.1: JK nip-fop with preset and dear L0T|0|_0
A 4CHIY SHAH Ventue
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bere Autbors inpire inaosatio
 Digital Logic & COA (MU-Sem.
3com)
OLoglc aymbol of negatve edge-trg9ered Digtal Logia coA (MU-Sem. 3c
EN CGUVEhlgh PR and CR
EN Thus, when he Edoc) high, a high
D pe Fpops
Refer Fig. 7.
.3 yCLK)
p-hep n low D put wa RESET e p-Dop nmleg Dlegrem
Q-0e, euput folows the D input at t
the cx Pae ence, thls
leh h eled
parent latc. FloFeo
Ougus
Or Fig noa
g grm of ged D-latch
Itsabo callea as Delay (D) ip-lop
tEMF. 7.21.l : Logie duagram of galed as thers
toere
D-latch

S Negative edge-triggered JK ip-lop with CLogic symbol B

delay r nng
Cnaracteniie
data from Impet le outp
Equatlon

Table 7.20.2 shows summary

g PR and CR
of operaton of negabve e
The D fip-flop
flip-flop by inserang
1s constnst
ann
no
een
ie dR uip-flop
or e
Table 721.2: Characteristic table for D ip-fop U
gered IK lip-flop with active-high PR and CR.
the S
and R ino Pent D
sNat ale eFiE. 1214 : Cocked D Flp-Fop
or and npuis, as snow in ig 21.2.
Table 7.20.2: Negative
edge-triggered JK ip-flop with active Appllenion
s used as a htch or a delay elemet ftr moning 1-bu

nputs Output Operation performed

nary dta
dule
CLK H 7.22 POSITIVE EDGE-TRIGGEREDD
PRCR qEAFlg.7212: Logic symbol of a clocked D ip-lop
uput
K-map simpunc 0 1or docsed D hip-lop FLIP-FLOP
3
Q. Normal
K flip-tlop e o) Trath Table 47221 Dra the logic dingram of positive a
cEAR
0 PRESET
Table 7.21.1 : Tuth table of gated D-latch
dge-triggered
desene 0
D p-Flop
..
and

ENC)
va
D.. Sate Ana.
Lnoeteminale state. Hence,
I RESET D qEcpFig. 1.213: K-map for docked D ip-op
not used.

7.21 CLOCKED D FLIP-FLOOP 1

SET
(G) Excltatlon Table
praw Table 7.213: Excitatioa Tabie lor D np-top
723 the ogic diagram ot D fip-ioP
No charge
using NAND gates Wnte its truth CLK
tabie - e Opeuou
a1 mputs UL
Ans.
when the ENclocE) 1s LOW, the clocked D
ip-g R
E (A) Deacription Ay cnange in the value of D will not moduty u

Clocked D nip-lop is also called as D (data) latch or

When the ENiclock) is HIGH, a low value on the D inpat
transparent latch or Delay nip-lop. Ibe D input wilwaya
Mne a
Dcaies S =0, R =1. lt causes the clockod D ip-fhop o ifthe next stade requir
Clocked D1lip-llop has a single input called D or data input. Tespecuve o ne pe tee e D
nex Sate reuined s
1,
RESET(Q=0,0 then D input 1s to be 0 ad if the

(B) Logte diagram J When the EN(clock) is HIGH, a high value on theD inpul is 1 imespective of Q,
present state value).

= 0.
Logic diagram of clocked D ip-nop is shown in Fig. 7.211.
cEs
(Q=1,0.Q-0).
1, R h causes the nip-fop to SE

#bcre Autbars iapirr e

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 Digital Logic & COA (MU-Sem. SComo (738) Digtal Logic &cOA M-Sem. 3-Comp)
FHg
() Logic Symbo
Truth Table

Logymbol
in Fig.7.
of positive edge-triggered D nip-lop 15 show" Table 723.1i fruth table of
lnuth tabie negat
o negadve

DptpP
edgeiriggered 7.24 T FLIP-FLOP
7222 uth tabie
table for
for T
Draw th truth

--.
he tnuth table, derive oplain
State
CD 9..|
Ans
ntable ofTFF. **

0 ESET Symbol J
rEpfig." 7.222 : Logie symbol of positive edge-irie Loic s also called as Togpe tip-op.
p-op J
a JK fip top the
(C) Truth Table and K both the inputs are tied ogether, as show
Fig 1241.
Table 7221 : Truth table of positive edgeriggered D fip-lop
NEmFig. 7.22.: Pesitdve Edgr-irgered D Flip-Plop
lnputs Output Stat
CLKICD H 7.23 NEGATIVE EDGE-TRIGGERED ) Operation
mputy
D FLIP-FLOP
D(data) input s ue ony synenenous comuot put apat EsTna) JK fip-nop converted to T ip-top
RESET ------**** e
4.7.23.1 Draw the logie diagram of
a negative from clock.

affect the hp-iop

winour

ouput
clock pulsc, the D mput will not

upus
Module
3
edge-trggerta Fp-Fiop
d
SET

-*--*--------
Ans.:
descn working
.--- -
At the negaluve (tallng) edge of the clock pulse, the lip-lopP
output Q will be same as its D input, ie., if D is low wbes the 1E2b) Loge symbol ofpasitve edgeireerdT
Fg 7.41
p-op

trailing edge of the clock pukse is appliod, thena the flip-flop

nnge (NC)
L A) Loglc Diagram
Logic Diagram ot Negauve
RESETS producing output ( 0 aod Q= l. E 9) Tuth Table
cuge-inggeredD thp-lop FD is HIGH when the trauling edge of the clock pulie is
hown in Table 7.24.1: Truth table of poitive Tab
data) applied, then the fip-flop SETs producing ouput Iad
e of T ip-fDop
input is the only ynchronous control inputL In the
absence of the clock pulse, Q=0.
he D inpul wll not atet e p
lop output. Inouts
Thus, on the neganive (Uraling) edge ot the ckck pulse, the CT
Due to the presence of iaverter, the S
o Chang
l
and R inputs always be eve present ar ue D nput 1s storrd in the up-loy
unverted: e., t S »0, R =I and
pusw
if S = 1, R =0. Boh the SR
never be 0 or 11, avoiding
in Uipus

Togge J
the race around
condiion. LboNND4 E (9Timing blagram
.
Al de positve
(nsing) tnansituon of the clock pulse,
NOT ***
0 0No NC) Change

UL
the fip- 723.1 : Negative edge-iriggered ox1||
flop outpur Q will be same as the D fnip-Dop
value of D input, ie, if Dis E

low when nsing

cdge of elock pulse is applied, then L 0) Le symbol
the tlip- |
op resets producing output
Q0 and Q-I. yniboot Degli've cdge-tnggered D
fip-flop is sibowa
p-top
DIs high when the nsing edge
n g.725.2 cultput.
1, iT=0
of clock pulse is applied, the On the ps le ia the hp-to
lig-nlop sets producing output Q=l o change
and Q=0 nputs D
Thus, on the rsing (positive) and

-
edge of the clock pube, the ouipu,
Outputs On the pusidve (nising) edge
of the ckck pulse, T
1 ie,
evel present at D input is stored in
the nip-flop. JUL e fip-lop ouput togges; Le. f Q = 0uhen

Negatuve Edge-lrngrered Dup-F ap -Iorvice-vers

(Esoig. 7.23.2: Logie symbel (nePg. 733 1
1, then the Ihp-lop uput will calioucusiy logEle 0n
of negative fT=
ggered D nip-lop every naung euge
or u pae
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MCN SZAN Vean
 DigtalLoea oonO-Sem. 3-Compy Fip-F
(D) Characterietdc Equntion 00 trnsdtoa
Tabe 724Charnt
Preee
p-nop
If the present state or une p-lop
op s o, wu u pd,
is

Ue
u and dext
inputmu
sg
uteof
beT canbe uea . uB also used in ripple
1)
n
Operaton

abence of ckxk. the T input will so afleet the

t-o
coun
hes
p 9*o en Q,. 0 nd if Q
If the present saie ot te ts 0 and next
staie sf
7.25 NEGATIVE EDGE-TRIGGERED
nig-lop is then the aput souid be Ts (toggle
1, 1
T FLIP-FLOP
rn egaive 1alling edge or uE C
0 a ers e mo chngs n g- tope mr
f the present stale o ne tup-op 3 and the next 2.7153 Draw the logis diegram of a n4getive il
pu SnouN De T 0 (toggle
s
-hap Mmplitcatdon for T ip-nop up-s,e e
eage-tdgerd Fip-Flop and
.0T+9,T
11tant
fthe presert state or ue lup-ip is i una the next state
6nesong. On ******

L,JK-
e eralling ndg
1, the
decd
flip-fop ontput togzes;
a le. f Q*
use
Timing dlagram
(no change). Ans.
A) Logle Symbol en 1er viee ver

Simi le to the positive edge- uigeed T lip-lop, the segaive

Logic symb T0 negaue euge-iunggrred T ip-flop is shown
aat der with
FTg .24.3 shows the input and output wav edge-trggered T like a freqseney
pesPlg. 724.2: Kmap for T np-ihop Fig 1.25.1
, ip-op axts
fiop. Fip-flop output toggles al every positive edpe
he charcterstic equatioa of T nip-op is,
lodule
...T0T
9 Exeltation Table 1
Clock treqieEncy
cyce for Q output=
axT
2T
M 7.26 APPLICATlONS OF FLIP
FLOP
. ******
P
:
Table 7.244 Exditation table ofT p-top Output frequency of fip-flop. I 27 (EsAFg S11Lope symbol for negadive
Q. 7.26 List aPplicationo g-tops.
-***
F Tp-flop
euired input irggered
Ana
Truth Table
if
ie, the T ip-lop divldes the clock frequency by 2.
can be used as a freqeeney divder.
Heace ) e appluctions of flip-tlops are
2

Table 7.25.li Trath table for negatdvet edgelriggired

Bince eunanan
Tip-fop
eguers
1s Outputs Sute hut
3. Counters

CT Change (NC) 4Memeny

0No S. Frequency dividers

avdom

LA A Chapter ends

Output
wavek T

(1E5F1g, ** poa 0put Wavetorims for 1 ip-lop

Tech-Nco Publicaliens ere Autbor Ampure LaoHtien

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 t Logic& cO(MU-Sem
scono) n and Arch
Digital 3-Comp)
* 8.1 REGISTER ORGANIZATION Index registes re used 10
LogisoSem.
hold inde
e ddeta ig8.2.1 A Sruction format
GQ s.11 Whe ndateet This is dedicated 4 Bits
T What .* * register used as 6Bs
register organgation
are diferent typas of registes wa point to the top of the stack memor
poune
Opcode Operand fiekd
Oreld
bo ae
p
(ii) Control Codes
ncreased then d
plain i'n detail Fig.
8.211- matruction forma
te bits of operand
edcee resung field hich directly
ecs
These are parually v ran
.12 How registers are organad in t mmer. These
are used to hokk the cobaiuonal bits which
consists otan
eIDe
Baandio9 fekd and
size. d 1
Eng

fred ength
d

iastructoe there is a aeof

Processor or CPU archtecture? processur ae
are set
and N g in
he o eae ie stadus
of the oey he opcoe e s e ype of opertic
be her facton which affects tdhe operand addressing bits are
4 8.1S Eplain role of diferent ero
registers lik control code. Some machine instoct these sa he method n e
d
ua
feld indikaes
ernd
a Couned and operaied
Number of addressing moes
control wond o
9 G, MAR and MDR used st the condiuon as a part o Dran operalion.
von aInstruction format Deslgn lssues
Neumann model. (b) Control Register and Status
DO. T0. Dec. 15.5 Marks Ga B.2-2 EXplain key dasign issues ine
O
ser ets

his Tegistes a e
UB.L Descnbe t register organzation proeessor, m
operation
ofe
an instruction fonmat aess uaelany
wrthin the CPU. invisible to th ale an insrridtion fommas foe *****
ome of the
coni Esor is a c) Yariable lengih instiruction
are visible in machine cont complex uask several design
J-a rgistes
mooes.
contol o
ng syslen an qpumm instruction format. sur ue engh 0
addresse tooa
d
Cessor n
main memory in the hierh ory e
above
man
BaSE TOur egisies aie pesent in control and statas gro Following ae oc key design sues which are Deed to be orodes ahresing modes
with various combination of
Modue
Dee wO

TOBam counter aareeu

(a)User Visible registers nsuneon register (iR)
(a) sc ion knguh 0) Alocabon ot Bis s be length of the mstraetio0 s no
| (0) Ccontrol and Status registers Mey aidress register (MAR) al inaweioe can be
Memory butfer regster (MBR) Sesched in oe fetch cycE
() Instruciion kngt
()User Visible registers
Progmm regialer ( s uea 1o ou ne ddressi ol the As cxh instnactias is of vanable m kngth thas equarEs more
nekt instructuon to be fetched from the memory. For any proES curtry
These registers are used by the pro
u
epro 0EDIag

nimizing
memo
the usage of
Peranmmer
Egsie
for
recently fctched
from the e truction mos
pcodes which demands more bits. M8.3 ADDRESSING MODE AND
nir ciassined as Memory address reglsters (MAR) : t bolds the address na evey prceser eues on me mory o felch is da and FORMATS
of
G) General Purpose registers the meimary Ocauon. struc aons T equires larger meuy boursaDly ao
varnus adkiressing modes which requires more Addressing Modes
() Dala Registers and Address register y uer regster (N1BR) or It is a buffer which
a
holds
The size ot
time
& 8.31
Cii) Condidional codes e Oa TO De wnteD to hemDry most fecenlly rEad tum derESSOM larger the iae of
d Explain in detail difterent types o
memory. UQ 83
Io
e eller computation capabilties, bnng addressing
processor contains set or registens
()General Purpose Register Os Or
which are used
number ot bits are requireu wnch Turer nei
These registers are used to hold operand for status word (PSW). PSw contains
ci of instructon lormal.
dressing modes Descnbing the cperand and is an e
en restictions like some dedicaied repien Stalus infomation, commonly used fields re sign, ze,
All o e
and address
s the ength of the instruction korma esing
ior 1koating pOLnI and stack operaions. y a, overtlow, intemupi enableldisable, supervis.
ccied by several other lxton surh B D
( Duect
ESets ae also used 1or addressing functions. memory ganizalbon. Regisie
H8.2 INSTRUCTION FORMAT
() complexity. proxesso Register indirect Dspa
Data and Addres registers
UQ. .21 All he nsEueons ae astruction. the Sack
Data registers are used Give different instruction format
to hold expliciuly the duta used for pluy is usunlly kept equal to
bus ranietS
are used as general May 195Mas
pressing. whe address registes
pose a wel as address pointers in some addressing
ODec18.0.10. mliple of the bus transier eng net
) Immedaie Addressng
Computing machine requires instructions, wh
considerable iradeoT Derween this addressing th
praos
poe
In
Address registers includes; segment registes, Index instructie
ions a
is in o opimiue u
and set v
Eghsics, and Stack poiaters. which every bit has its own significance, the layout of each Allocatioa of Bs
(b) e
ruco
Segment registers: These registers hold the segment base ens or 1s tields position is called as
a every innucaon
torma
ddress in Scgmented addressing. Awh field has
severuunoc
Au
apure rublicslions.
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 Processorg On and Arc Comp
Digital Logic & CO (MU-Sem 3-Com Digtalg
no memory instrucd0n. 1ee de So Dits for address . d or n
-The to 8 to 2 Base-Regster Addressing :
advantage of this addressing m provides relerence this ade
the operand
rege
" S2 general
the effective a y Ee The Fig
4.1 shows the stale diagran of an tmu
value stored in twos complement form displacement vaue o ue referenced egister va rwo ecbas nE uppr
is
The main advange
oy pct or implicit Ilo mEmory procev and -p
opcode ence aa
ference
efe regie
etwees
while the second secticn caters to ntermap
ma
of this mode is that it has im
ageme ed number
)Indexung**
aaess ieid
uve adess
lo a positive displac
is formedd
g& mmediaie Addresing
hich requires ga g effons e
by adding value
6)
Direct Addressing mode
nmeram
mer sid
given y
e e

insaruehon
the deripion of ech

address calculbon luA

stage

la this addnessing moe

psents a part of the
i ss of the operand
a simplest form of
Displacement

Jing (ID)
ddie ssing mode as it requires only one memory reference. T OA
he major disadvantage of this addressing mode it can access (e) Operand fesch (0F)
amuicd ranE O
D Data operabon( DO or EXEC)
opcode Address Relatlve s-oger Operund Store (05)
ndexing
Mermory ddressing OrsSng (1AC)
a Instruction address calculation
mputed
Fig. 834 Kejer s g a this suage the address of the next ms e
ddress.
y King a hteu u calculanons are
opcode Register Addess
(e) Register Indirect Addressing mode
Pad nsrc tion adtress
Modue
The ddress ot the OPerand 1s provided by the register
nsiead
ot memory,
to Ue . po v nS 0ae 15 proportion b) Instructuon etch (F)
nt on the
of this mode is it requires anly scm Uhe
coe
Fhz. 83.2 : Direct Addresing mode nemory fetch cycle. i eched from the inu the processor or r

Usually, it gets stored in the lestruethon Kep

c Indirect Addressing mode opcodeRegise Procesor ar CPU.
Memoryy
n nis aressing mode the operand address tron (D)
(e) Instruction operation decoding
Is oblained Fegster
word or me thoiy aidressed by Uhe instructuan address e
isenctieon s Exunied whch
The main sdvantage of dhis addressing mode is that it can
vapuktenent Aduresung bode e meanine ooft e

operation o e pero
of
operands to be used.
Let say if N Stack Addresing
memory then the total available
spae i a AOOreBs nd

s nessig m
o thus mode is that it requires two memory references to
fetch ue oper whicn Dometnuy relerence is ienoned.
1ne
ess or u Decoer
Hegislers 15 alwuys the top of the stack. (OAC)
opcode
operand d) Uperand address calculabon
Address Pig. &3.5 : Regster Indirect Addressing mode
of the operand is computed thal is o e feahed
Memory Ihe address
(9 Displacement addressing mode from metnoo eing used by
This Nage ne rueu
peeded by tbe
hs acdresSing mode rquires two address lields in whicn Uhe insurxtUon ahc u r
isexplicit.
Addre or)
Dc nCE Lmpucit relerence address reiers to a regsler was (e) perand teen
ack

ae
ellecuve
added to the explicit address to torm the
address or the operund.
Fig. 83.7: Stack Add ressing
CYCLE
mooe
In thas
read roe
sage. he og
a ae, over the dulress
aidiress
baus a
THE INSTRUCTION coppu
Flg. 8.33: Indirect Addressing mode
) Kelatuve Addressing : In
this addressing moe B.4 ******
gner
the daa bus

plicit askdies is given by the program counter 1e

Explain Instruction ara nstruction operand cUuld be
a
Egt,"**
*

a) Kegsier Addressing mode 0ESs Tield 18 added with dhe next insu
cycle
a0dress lo tonn the etfectuve addres.
n this addressing mode the operands are placed in he
egister and the address of register is indicated in tbe
SCHY.SHAI Vontare
ati
au
Terh-Nee Publications-here Authors inspine unnovatioa SACHIY SHAL Veature Tech-Neo ublicaliuns D
 processo
and Ar
LDigtal Logle& COA (MUSem. 3como

HAPTER/

(9
nsucton
Muftiple
Operand
asuits Control Unit Design
Oneaod
ton Operand Address
lnstruotion
Calculation Module 4
nverety Prescribed Syllabus
nsiucbon coe
fotch next nstucbion control Unit Deslgn
Hardwired Control unit: slate Table Method, Delay
Eement Methods.
icroprogrammed ControlUnit : Micro
Dat operaton(DO or XDC) is undersiood.
cono gnais
1is n
se
over the
Tor
Cro
generating
as well as*uffe
ExAmples of microprograms. Instructon-Format, Sequencing
uDon-FoTat, Sequencing and exacuoon, M
Dons,

hs stage performs operation indicated in extema

the instraction.
pndenstanding
he stage where he Asurucbon cuEy the instructions is ingcalle ad . Control unit.
PESung: Interpretatioa. Based on the interpretation of the i
s Actunly executed tio Ua.9.1.1 State ne unctionS of control unit MU-0. 5(b), May
Operand
Store (05) P
n ruet to ExCcule that instruri o Types of Control unit.
18.5 Marks
Write he eult iado memory nstructlon Sequencing Ua. 9.2.1 plain rerent techniques tor design of control
or out to o deve. in this unit of computer.
he
MU-0.3IA), May 19. 10 Marks
operand
the
in the processor or CPU is stored back to
Once the instneons ae
ecoe a ntcrpreteddahey
a
he destinatioO signa 9.3 HardwireoCon Onit u

cou be a tgster,
required for the executing the instruction uD Ua. 9.3.1 Describe hardmred control
a memory location or aa /O port by unit and specity ts advantages.
Ppopae contro unt (either handwire
W8.5 NSTRUCTION P
fint reading Uhe
te insuction is executed in sequen
opernas neessay Tor the instructe
dals Ua. 9.3.2
M0.26. May 12.0. 26). Dec.17. 0. 4(O, Dec. 16. 0.
with diagram
Explain
3a). Dec. 15. 10 Marks wwww- **

INTERPRETATION unctioning of Hardwired Control unit. MU-0. 2a) May 15.8 Marks
AND the subsequenuy ue insurueuon opres ad 9.3.10) taie-1abie or Classical Hardwired Control Unit..
SEQUENCING
stored back to their d
executes
esulant operinds or he instruction,
are
oe tdhe
9.3.1(0) A Mubplier
Menod

implementabon for Hardwired Control Unit (State Table Mehod)..

m
nstructions art fetched or received Lnstruction sequencing and executi
ns
process is
termed as 9.3.2(a) Delay Element Method
-
.
um
from the program
N
be -For the purpose of intepreation
of instructions,
9.3.2(D) MUbplier implementation lor Hardwired control
unit 9-7
ey Ahoukd be seguenced for their
execution
is needed that 15 provided m
uhe ontro unit
digital logie
of the CPU. For
9.3.3[a) Sequence Counter Method..
(Delay Eement MouO
.9-8
mportant aspect is erpretanon d sequencTng oueocang anu execuuo0, gain
the life cycle of Instructioas runctuonal logic b S.3.3(0)Mdpler mplementaion Hartuirad
tor aromred control
over the CHU: Tequired tha ae provided through the Data Path
COnuol ioit
uni Seen
(Sequence counisr euoussen a ****

..
Instruction Interpretation of the C3

Iastructioesae letched
ith
next section *e discuss
C
h Conrols
e difierent ypes
and types of Control units.
of Data path
9.3.4
9.3.5
DivIision Implementabon tor HardWired onuo
Advantages of Hardwire ono o
o.o
from the program memory
elhe lastructioe Decoder.
structlots are decoded In instruction d
and they S.3.6 DIsadvantages or HarOwired ontor dnt
oe sas
*******************a**ammeas*********memnes****************************

and their meaning

and functionality
.
S*erOograinming ierminologies..
nascroprograim t MO0. SI Dec. 18,. SI8), May
9. 10 MarkS
.9-12
SE
er Das
. oncept or control Memory. 1,
9.7 Micro Programmed Control Unit..
.

Ua. 9.7.1 Explain Micro-programmed control unt MU-0. 5D), Aayl8.S Marks 9-14
9.7.1 Mcro Programmed Control Unit: Concept 14

contreo
./2 Funcloning of MCroprogrammed Oni.
.*
Ua.9.7.2 Explain with diagram functioning of Micro programmed Control Unit
MU-0. 2b), May 14, 8 Marks.. 4
 ConMro
Digtal Logie & COA (MUSemSeca Desig DpaLucOA MU-Sem.3-0
Comp)
9.73 MeroprDgrammed Comtro
onm
Advenagso
e *a**** CONTROL UNIT Control CnD
9.1
-.
******
0.7.4 Disadvantage Microprogrammed Control on,a*saa

8.7.5
of
Wke's Control Dec. 14, 1O
o --------
U

nity n oeta. L0 O.Ja. of contref n

einction

9.9
.9.73
arlson
Oadwed
Micro
a.B.9.1
of Hared
Control niy
Eplain Wike's Engine (Harcwired Cmtrol
and Micro Programmed Cono
Instruction sequenca
Explain mcro Instruction sequencing.
o
****
**
*****ttr

&18
1
a
** ---
4.13 rNtons
:05/b)
unctlonal Requirement of Control
Un
t May 18.5Marks

Status
E
Instruction
regicter

.9
**
MAU Sc). Aitay 15, 7 AMarks. Q. 2/b), Dec. 15.
O.
eUontial Techniques -Micro Instructon
wde Branch Addressing.
samumeam
CS

with Naxd AD0rs59 ro

1M

*******senen
. ******

te
91
The Instruicuon
sUg
which
yce stated
o
above has
peration Decoe
a

decoding the instuctio

Condiion

9.10 Microoperations . ********** ** 1a undcr g E Or the instruction.

the exact uncuonalnty ot
the specificd instructioe
3.10.1 Register Transier Microope asmeasesessunse is Clock
*** known, ponant task is to contro
n suctesstully eecuted Block Sehematic of Centr
S.T0.3 oduce specified outputs. and
Logical Microoperaton
10.4 This forms the very basic necessi pcode of the instructdon
Mmory Faad Transfers (Fekching a Word from Mermoy) ************sseseun
would perfom the control operaionsT ogic that
9.10.5 eOTy Wnle TransSters (Slomg a word The operational code of the instruction embeds te eus
9.10.6
or nUcbon Mcro-operabons..
****e
cof ne
O
the CPU. The functional unit th
osss
as the control unit. Thberefore,
ead t
of instruction.
contains informaion about the instruchon functio0auty
8.10.64) Uncondional Branch Ihstructons coatrol unit
the
becomes tne most cetuical part in the processor locaion and encoding of the operands used and the
of
*

Oonoi3ona Branch Instrucions. aa CPU.

*me O
Ing 0E O the nstrction.
ouucDn ExeCunon-Execution of a complete instrucic).
ua. 9.11.1 Explain Operations Functons of the Control Unit (B) The Condition codes and status rgs
micro hstuction execudon. [NU-O.5e). IMay 15.2lMarks,
O.26: Dec. 16, 08 Marks3 The control unit operales by receiving The condidion codes reflect the cuen s
Wne
wite
contro sequence ior the mstructOn ADD
* s
*23
which t covEns o corol
the imput nformabon gene i
conbol sequence for the instruction suS), signals. t is then sent to the
cootrol signals are generated.
d. 8.14 Write control sequence lor the instruction nl.. ********
Penoming the desired
a.wnte
ADD (HSIc}+, Hast.
Microprogram for the instruction i) ADD R1,
24 operations in the desired sequence.
ce
yus tlags reiect the curreEnt staie ot operaihon
m the ALU and the control signals gencrated are
M ) MOL H1, H2. .24 The internal and extemal perimed
a. 9.11.6 d Dec. 18, May 19 ianr
operaiot by the pene this state.
6paBons
Write control sequence for
of Microprogramming.
the
instruction MOV (RI]. R2.
OOa
ay 16.
Darks
. -25
cary
units of the CPU. This
out control
Cn

current state of the processor Modale

w.9-26 result in the successful execution ofC) The
4 wnat are applicabons of microprogramming the speccin
9.13 Nano Programming.. -0 1G.NOY 1E, C.u8.MBy
E.5 Marks
26 The functions ot the contrl unit are as follows
The control signals and the next staie of the processor is
directly dependent on the current state of the processor.
a
Da. 9.13.1
26
Wnte short note on Nano O Crdinanon or data movement betwen processors
Piogrammng. (D) Clock signal
6Ib. Dec.
Dec. 1
U0.6b
14. 0. 6c, Dec. 16. 10 14arksS Essemaas sms nan
**semmasemana*
SuDuns S Seuencng.
Da. 9.132 Eplain conceph of Nano
programiming MU-0.
3cl. May 15.6
2
ntepretali on of dhe instructions fetched from the
seuor synchronizauon ot tne mings
raasibon and actvation of control signas.
1or stale
9.13.1 Concept of Marks
Nano Progratmifng. The control logic that resides on the control unit, receives
9.132 Advantages of .Contoling uhe daa Tfow over ue CrU.
Nano progranmng.. y sgas a
9.13.3 Dsadvantage of Nano
Progranming *********assgmmsebes** m
uen uene c
or exlernal

conrol
instnictions or commands into
signals.
t

the subunits of the CPU such as ALU, na control sugnas

Chapter ontroling
Ends.. registers data buffers ete. ese conrol sagnals aressueu lo exiernal components in the

ae a****** 28
O Seheduling tie operations of the CPUin an
ppropriale low so as to complete the execution of
systein sucn as meiory
1. RD:
and vo aevics
Read Control signal. It mesans that the
data will be
instruction. read from SMemory or Io device to the CPU. RD
indicates active high and #RD indicaies active low
3. Block Schematic & Control Signals
Fig. 9.1.1 shows the block schematic of the control unit. The 2
WWnte coug
perations or tne control unis ae baseu on ne tolowing nputs.
R indicates active high and #wR indicates active low
feeb-Nes Pablicatiens
here Authors ingaire imoovatiooa control signal.

SACHIY SHAM TVentwe 0.a0aoa

A SACHIN SHAA Vewhure
Teeb-Neo Publications. here Authors inpire
 Coital Logie & cOA IMUSem.Seon= (FSM). In the
process, Uhe digital FSM nstructon
ehioe
A:ferenhai
gnal diflerentiating the
memary e
eied sequence and cou S4gnals R uction
*c Microprogrumanu o 0rEware implem
emeut
stores a pecirk eq mico-instr
rueions fer eve
CA9
() Internal control sipnals
sued inside the CPU
ana instruct
conu iastruction
bich is accessed by M re storedin
sg
a-Muplier
abmis io cogtrol dbe data fow and fuactionality. to be executed on the s
ecded and
Sequenãal
Keghter control Skgnals : Fo managing e tnecific sequence o c and seque
is ope
s A Condu
generate the desired coDInaton of
exccunng the specific i
equirod aamely ln and uL or e and therefore, eXCEL
ereloxe, nstnuction,

Frrontrolling the data f e mgister

9.3 HARDWIRED CONTROL UNIT
RxFor controling data flow out of the Negsier
Fig. 9.3.1: Basic Hardwired Control Unit
Differeat registen used ar UQ. .3.1 Deseribe hardwired control unt
- nera upose Kegsers specify its advantages.
nd
MAR: Memory Adiress Kegset 9.3.1(a) State-table Method or Classical Coun
MDR: Memory Data Register
MU-O.2b). May 17.0.2
Hardwired Control Unit
H1Ol. Dec. 16. 0. 3a). Dec. 15, 10
a Counter ount
State transition tabie are creaied in the State-table method
UQ9.3.2 Explain wrEh aagram functionine of

ALU
TMP, Z: Te
oatrol Slemalk:
Kegies
4Oay
drawirta controi unit.
15, 8 Marks
control unt
r ee or control signals. As
the states are transled, sequence of appropriate control signal
Sets ge Specihc instructon. P 932i Flow chart for muftiplier lmplementaon
ALU Dala Plow Control signals: Hardwired control unit mpicmen is done with the hetb gE E
ALU has ln and Our control signals to control the data Flow
of handwae ie. It consists ot digtal combinational ad ne ur curet T
Conpoments. asis of Cament state and the
yA
KCgister la and Out signal
These ignals operale similar to rcuit. "*
cndes, thev oneate a Ete sof condiúon
The book implements Hardwired control unit design taking A
ALU Functlon Control slgnals process, the digital FSM generates they require corml
In the
the example of an unsigned muluplication operation..
o co sgal nes ae ssociated thaf specily
aDd sequence of coatroal signals needed to suceesshi
D e pertormed in the ALU. For each function in the eEue he mstruction. 9.3.1(6) A Mutipler Implementation for
"* cooon or rucuo coe
Design ofHadwired conror unit is guided by following Hardwired Control Unit (State Modnle
functions
Uch as ADD, SUB, MUL Dry ni EuC Table Method) Couninbus Co
Lpca ucuons (such as AND, OR, XOR,
and Lopieuly and amoaunt of
Hardware used
NOT, ete.) esired speed of generation of Fig. 9.3.2 shows the flowchart explaining the unsigned
control signals
9.2 TYPES OF cONTROL ) ostir Multiplication logic. Let us have Multiplicand in M register
the
UNIT Hard wired
Omy) of design
and Muupuer in Q egister respecavely. C contains Camy
ua 21 Eplain diferent e pfor design using dif us are po%sible to genetalco anng any aoanons
cCoy.
ecnigues
ot contrel unit of computer.
the technique used itsi
r its implementation, methods
for ues. Based a
*ger san accumiator and used tor computabonal
Haruwired coatrol units are classified o he nuupucon. LEt n be ne count qLie. umber
as: uNe
of bits to be muluplied.
0ks conpuler systeim is very important
ethod: t is a method classical The states of muliplication logic are as follows:
cOpooent of the systen
decoied
creles Moore or ealy stale tabies to Eere
: Start Sta
instruction, it Sgnal outputs.
Nbie for generating all internal
er
Unit can be nrina
e npuier syet so as to
etmal kement
clocked De lav
Method:I is the method o S: Initialization State-In this stale, regisiers are m
And A Are Ced. an NCourt-0
eentaions
n e.So
of the Coetrol building blocks of
eder to geoerate Senes of D-Flipflops) ia
Handwied Control the desired THEN GO TO state S, ELSE GO TO state S
.

Unit control signals. FO-1

SOutbus A
2 Microprogrimmed
Contol Unit
*
er Methods -Sequen S: Additicn State In this state, addition operaion 5 00
-
Uethods: Thisunter
-

ardwired control unit implem Method and PLA cary C cary

of hardware
1e. t do wth the elp nouRt of Seen
methoe
ncrs, t tries to A-AMif S+bia:
consis of and Sy: Shift State In this state shifting is done, Right:- Shift C,
n
-
sequendal ogIC
conpoets. 1ey operae and
e ue desired control
signals. PL A, Q count-count-
State
-Nee P'ublications. - Bere Aatb Fhte LRIC
lards Armays to impiecmcnt the IF count > 0 THEN GOTO state S, ELSE Done. Fig. 933: Flow chart for multiplier Implementaton (added
iyw anwa o no unit with comtro sgnals)

MIIW SILAH Ventue A SACHIY SHAH Venture

Tech-Neo Publications. ere Authors inpure innoraLuo
 Dlgial Logic & COA(MSem Contro ic& COAMSem.3-Comp)
SComp
Dgin
O Signal Generatlonfor Multlplier the States and State transitions descibed Control Unt Desu
Using 93.2(b)Muuplier lmplementation for
Control signals are needed to be determinod
for the mulpue
mentioned table, we are able to determin
e
n ahove
functlicng
9 Hardwired Control
Unit(Delay
Fvery
enen e LDeay eeient
blocks neded to implkment the multiplier unit
implemesd
Element Method)
"pienentaion with control signals. signals oeeded tor thie hard ware tmplementation.
In order to handle single transfer
of conteats on the buscs It is cear that the implenenenon neeas negister, Begin)
y gvenstant, we are needed comparators, multiplication hardware and dders,
to modis
shaten.
atadding 2 moe
states. The flowchart of Multiplier 1npiemention is as given in Fig. 9.3.4. A-0 C Co
d unit amplementation with control signals is
Oubus
S nbus
gven in Fig 9.3.3.
aDie
9.3. Stade table describes the States of Multiplier M
Mabplicand
S, inbusC
plementation of Hardwired controls, input signals L T
10
tnggenngthe stade uransitions, output cono
BDercd
sra
and their detai ls;
Table 93.1l: State Diagram for Multiplier Implementa
tion allel
Dte abie Method Address (n-bit)
State
P Deas or control ignal C
C S
valuated Slenal A-AM
eated AcumUlator ant- Count-1
Degin
Beaaias Count-Count C.
Multiplication operation T
Co Transfe
Multiplicand M from labus
C Clear 5 AO 2
Register A and Carrv Renister
Module
puer 10
Q from Inh

Cro Transfer
value f Oun

count register. Count

Fig 934: Hardware Bkock Diagram
of Multiplier Unit
lmplementation
SOutbus-A
Tansfer M to the adder .

unit for ad
C,
a 9.3.2(a) Delay Element Method
7 ubus
Transfer A to the adder
unit for addition The control signals from the
Transfer addition results t necded Beneralca
t
Hardwired contro
m an appropriate sequence. SInce e
n Ed impienmenaooa nE
A upon addition g.93.5: Plow chart for mulbpber
states are drawn to kdentuly
the control signals to be gener eayeement Diethod
Transfer cary out to C aneously
after additiona * OT CODO1 S1gnals
in a state. As the state
15
transition oceu
gcnerated in the next state and so o 8. 9.3.5 shbows the lowehart
of the Flardwied
useu
coauo re
ount Right-shitt conients or nethod impienientatuon
nee specitie bime delay between the generaion
CAQby 1
bit consecuve sets of control signals.
Mulupuer

Decrement the Count by Therefore, a seu ol unit usingE ig. 93.6t Pow chart or
y ciens can be used to generate Delayeknea
controi sug The impieu ved
and derived from
the tiow
n contents to the alier the other. To cnsureepr
proper operationm synchronic elements c roptrol signal sequences.
utous the ciock signal, the delay ekements that specn
contents p-lops. A common clock
are
mpie same Mulupue
it implementation examie
Output Q lo the signal is uscd to synchroize ASACHEY SRAB Vesure
purpos
a

Tech-Neo Publications. here Authors inspire inoovation Publications bere Autbors

SACHIV SHAH Veoture
lecb-Nee
-A
 LDloital Logle & cOA (M-Sem. 3Come tal Logic & COA MU-Sem. 3-Cor

e exponentialy
ponensauly or symthe sizing the functions
signals, in diferent gaies iena
that a lmplene Control Unit Design
caly OR d to get ooe como ouput
sectioes dernoastrate the Hardwired
control
Mulsiple
monly one state cee implementations for multiplier un ad d
simply wimd OP Sequence counter method. Usie
BEGIN II
e es ipes
point then these lnes are
coonecied
te owchart merge
to a"
9.3.3(b) Mutpuer npeentatlon for
ade
Hardwlred control unit
A decision bax is implemeated by two 2-iaput AND gates. (Sequence counter method) CODN
Laa
O
conpiement
cach AND gate is diven by the desired
of the desired input respecti vely, while
Referencing the State table generated for the
nurtplier,
e
can derive dhe functions for Next state variaby
the second nput
ot both gates is commoa, a output euntnt siale vanabEs and input variables f
a
of he D Fip-flop representing the
LDeayien .
ates are dentibed at caxch of the Delay-slement up-Tp
P Do BEGIN
D,
ommon synchronizing clock signal is connected to all Delay DBEGIN
element Fip-flops.
BLDg DESe
gudelines for the
had ware implememauon o Q0+DQ10] COUNT7
puer unt or
constructing the Delayelement no
Dased Hardwired Control Unit The resultant handwar DD 01 +D,+D, Q07 COUNT 7

aon of the Maltiplier unit is as shown is

D-D 0)- coUNT7
D D+D Q0. CoUNT7
9.3.3(a) Sequence Counter Method D,

.
>equence Counter method is the classical digital design Simlarty, we can oenve une runcons output variables in Resel
BINMealy tables generatod s Or cuent staie vainaDies and input vauriable as :
t e
in the
derivation for the e method tao fiod the funcional synthesis snd
in
Cu
s
D =D,+D,
of cumrent state variables and input
tems 0ns
varnabies.
This method uses either AND-OR-Inverter AND-NAND
or NAND-NAND
or NOR-NOR Jogic
imels
p-lops oen o he den ved Nezt states and COutput variables
combinational circuits and uses JK nio-lons
O ne cncoding of states and thereby the Finite Se
vanabies, using ue auNAND-NAD 08c
Machine of the sequential logic to be mplenented. npienenaa Hardwired control unit
he method achieves the hardware circuit implementation of
for combtnational circuits and using D tup-tops tor
9.3.4 Divislon lmplementatlon for epenve suberation, ia
is
sequental cucut, the hard wired contro properny of Dvision as the
as well sequential digital logic with minimum
unit (using Beues the remainder is
O or postive. Using this
combinadonal
counter method) repraled subiraction bl D CCD) which can be
impementation for Mulbplier u 3 DvESion is
poblem staliemen or reuisto
uimber of sae nip-flops. However, as the pumber of state ogic. Let us consder
the
and YK a eneral
and input variables incease, dhe complexity increases
comstructed. The implementation is as shown in Fhg. 9.3.7. possible to impiemen
on* tne dvO
an SAK
as the pplbicatioa that 1copories na ypeni
enbnsraled wouikd ue amuipieer, suisiN
a
the impkementanon
Pupose reg1stes. Aso,
implcmenang
barware
howsthe scbematic of
38

SAOMIYSMAN Venture
A

Autbow"
Tech-Neo Publicatioas bere Autber inpüre inoeration Tech-Nee Publicatioas bere
 Control
untDevig (MU-S
Digtal Loge & cOA (MUSom 3 Comp) DIO SmO
Contro un De
siog
this stae table, lor implementing e
required combiaational
fo Next state aNa Gupot
co gnal vanabiles
and equerntial
C, lope. we
** synthesize and deme he g
unlt CU The sipals are derived as

SubOa D,D0AR>-|*R2XRD R»0)-XR2)

MUX D DR >)-(R&2R)+D,+D,:0R0)-0R2X
utplezers
Y
Load XR
Subract D
Load YR
Register XR
SelectA
T
LoadXR D+D+D
Load YR D*D
the ocnveu
On the basis of
NERT SISES NOd
Oviput variables (Control signals) in
2 YR) tems of carent states and Input vanaoe,
al-NANDNAN tor combinational cireuits
D fip
DP XR0) and using lops for the sequental cireut, e
unit cootrol unit (using sequeneE CUcE nhd)

showD in Fig.9.3.9.
umplcmetation for GCD unit is comstructed.

Pg, 9JL8 z GCD implementation The imple mentadon is

ue net
Uung the GCD implementation logic, we can amive at the excitatioa state iabe 0r ue D bues Stales And output

control signals in terms of current states and input variables of tie sysem

Select XY
Present state Next sate
Subiraect Seap Select
XY Load XR Load YR
OXCR0 UR2 YRD, D,DD
AR> 0)

Load XR

Suberct

CIR

LI| Fig 939

ASICHI SRAI Veature

Tech-Neo Publications here Authers inpire ianovatio gnatm
MCHY MIAN Teaiu
Tech-Mee Publieations bereA
 n3-Comni
ControUn pigita S
DigitnLogic & coA (MUSem. De
Control Unit Des
A sequenct 0
c 1s
known
R 2 9.6 CONCEPT OF CONTKO
9.3.5 Advantages of Hardwired Control
Unit
:
the hardwu
O progTAM is

ware than e
midway betwees

on aidress
MEMORY

he execution speed of Hardwire comtrol unit is fast programmed contro are prefe
uits a
E, Deno
is ued to skore ail te mico instiructioas for
npred to micro progrummed control unit. wired control uniHs. MErO POBrams are stored in the d comro mt. There ve
t can accommodate less number of instructions, it is beter Functon.
"des rctioes ina mte
tor the conioun op eriions shou
-Once
e
ued RUSC architccture impiemenac Fig. 95.2: Verdeal Miera instractioe ends with a branch
na
not be or jump instraction that
a 9.3.6 Disadvantages of Hardwire
made as the
ed read only memory oy
B
in e 00he next mstrucbon or rou
ch a micro instreonErpreted
as folows
Control Unit The micro pmgram is se plare aTo the control vari micr ro i The control micro
prunabiny ol eTor IN
Hard wire contDI un
more
0ning a wonu Ko cane uscd by the cotm
through successive reao5. EaC word in the ROM atia specife
should be tumed ON, indicated by
bi
ines
eas turn
operadions eo he performed durieg each of the fetch or
in
OFF he com ncaled by bit 0, The ml rrp ycle. aso spenu
urDeut to handle complex instructions. address cansAsts or amicro msuuEuDn. control Bga o
o0e or moe
mico
mg f these cycke

complicas
PGeSS TOr hardwire control unt s more
4. Micro-code
operations 1o e penormed.
If the co
meoury forms a way to mpiemeta
u
instruction in Fbonal
se bits ls talse,
The chp area of Hardwire control unit is more and the cost of e micro progr e called
ute the next micro
icro codes. Eg The sequee f the condition indicaMed by the cod
rucun Sequencing and decoding are needed to generaie the etective address of an operand
15 diincuE lo lmplemen. i execute the net mcto caon wboe ad is
.

W 9.4
Enture control
ew 1nsirucoons
unit design
tor the system.

MICRO PROGRAMMING
needs to be changed in order0 a

Thas
an nsiredi0 1s

sScquence or ni
a micro coxae
"operu
DPur
es
nstrnuctions
ogcther to fom s
specitiea
shawn
ave indivio
in
in

ue F , e.
e De2aotal microinstructions
eretore they are
Jump to Indrect or axect

direcuy cou
TERMINOLOGIES 9.5 MICRO INSTRUCTIONS AND roinstructions, individual control signal is pot

TS FORMAT erated rather a funcuon coue is geernaied depcnding wpon

e e
T. Micra-operation these contro Sglas e sing vecal mico
Micro nstrctons consitOne operation, Dext instructuns, Ue conuo unes ot OUECUy connected to te routine
MCrooperations are the smallest low-level, detailed
n5tcaons used to develop complex machine instructions.
instructions * register (Command u n ne
co

w
generales a r evey thicrD-operaian,
Net or conrO
Sgs
the control unit only micro instruction or control word is as follows:
Tbere is one bil for each intemal control unit's control line
O he
thenconnected to individual coetrol signa
Vertdical Mkre Jump to opcode rovtine
Exscuhe
begng
cyca

Thaus for each micro-operaio0, dhe control lines from tho orizonlal bcfo
and one bit cach for the sysiem Du cu Dne Dere Isa nstructos
having bin
esentation,
epresent
Soevev i ls conihonal hela, comsusng or conaiuonal 1lags, that indicate
the condition for branching. Also, one address field thal has ndavidua conuroi Control sgnals im the lom
by a pattem of 1s and Os in the control word Coetrol
Signalsae
takes place.
Mro-nstrucuon Beneraicu
e ADO ou
Yes. To transNe
ErO
ue dons are a
pposea to De exeued ar oe E.
set or miero ~operall0ns Unat a Decooer No
functon co
acn aeoy age
instruction addres gnal.
a symboie CT0-instructu0n Micro insirueuo
Micro
denes
Traneltd rcon 1s the one that can be
ump Condion (uncondiboral, mnectionFach control signalThe
nancun c
CF rou

to control decoeu
symbolic micro instnuction can be divided into five fields is direcuy

namely: aDei, microoperalaon, condition, branch and onaccleu ocou" ump h

address. ysem Bus control Signals
bnc.
NOTO of Coatrol
Memory
Access of
Internal CPU Control Signals
Possible flg 9A110rganiuation
individual
UQ 94. What is Microprogram ? control bit or
SHAH Veature
signal
0.30 Dec 180.39May 19 10 Manks Fig.9.5.1: Horizontal Miero instruction ASMCHIY

Fbere Avtbos upur

Tech-Neo Publieationa. here Authors pure nnonalion etb-Neo Publications
A MCUIY SHAI Vesture
 Dl Logc A COA MUSem.
3Comel (9-14) Control
ng
9.7 MICRO PROGRAMMED micro instructions have fields
The bus contral that describe
the Syw
gic deciies
CONTROL UNIT and the iniemal CPU control sig ress
dependt e DeT

7 Bplaim Mieno-prograMmed contro um

naor
Ue Control unit.
control line
naling
fied fomation
dec1si
given by CHR
erale
and ATR
the next i
e
e of the h ATl yce, one row of the matrix is
actvacd by

*******-*- MU O
Thos, reahng

wnlet
a

o eseins
vaent to chan ()
he
et the next
instrt
ding
iress,
o
fiodes are peien f a
t dhone pamts wbere
tha miem
inct ch in t 1 secti
A micrvimstruction.
t coesets o
S.T1 Micro Programmed Control Unlt O ALI a roune donmico instruction he contel g lor he nernal worung of

Concept a 9.7.2 Functioning or Microprogramme. instructhon, load the CAR w Deld of the econd ectioe
Control un Conm Buer Register ie. the add ield ot din the eet machine eycle The enir mris lava
miCTO Insrue held c t NMonge area for all micrO insuucbons.
ecauuse it needs to have
loge aneunt ask D 9.7.2 Plam with diagram funet jump to a
fotine: Ue the opco
Two mgi e mory.
obs, log* Tor Micro programwed Control Unit. Epsiet-
eNeCuting those micro-openuons, from ue ik to oad
ed to store the adidress

based
on AlT s,
ic
and logic for making decisions -- o 4.8 Marks Therea
roetrol Unit pan teo
the CAR

esent in
e CAR, CBR, control
the Micro
ycie.
of the ov
The address from Registet-ts gven to

will be very *****************************----

hartware, Also, if es
And implement ing ge
memory and
such complex Control unit Seque
al at nstruction
The upp
Micm
DeTOproTmmed
wu be even more difficul Intead gser (IR) e be opcode
of the R
Control Unit 15 impiemes Tis element is present in both
Horizonal and Verical
iastructions. micro
******

LDecoder
Cor For ve
geter
aons, sice the control ignal ddress
ncing Register (CAR) ntrol Address ode
ather than direct signals, tis
code needs to be converted into individual
(CAR), contre Mgnals. Address
ihe o Cnvering this functional
LRead
control memory LRea code to
inao o e coced to control line
Control Memory signal
a9.7.3 Advantages o Microprogrammed ***|
Control Bufer Control Bufie Control Unit
Controlunit
Regster ( Heg'ster (CBR)
** **************** ************* e c coorl unit is that
trol condiuonal
Flg.9.7.1 : Micro Architecture of a control undt tis cheuper and is less emor prone to implement.
2
Thus, a micro programned control unit s a The decoder and the sequencing logic is simple. g9.791ukes Sieroprogramaed control a
contol
whose binary co 4Fasy to implement hence used for CISC and mainframes Wben a cock pulse is applied to the decoder it activis the
DOy. -.
he
tain
conirol memory contain no snas Control signals mamt row gen
by Regsict epending upua une
v the control unit. In micro pro
within CPU 0 5yse D
a 9.7.4 Disadvantage of Microprogrammed g *ess or e Dell ow s eer
or te
uaken
mn ne
rom ue
exo
,9.:72: Functioning of thbe Micro programmed Control ontrol Unit pcode in he lasuon Regsier
enenong the control unit would be equivalent to Unit
executing this progrum in the
ocay The control unit has three inputs namely: ALU nags, clock .The main disadvantage of micro programmed conirol unit
is This address is given the Register-11 during the cycle. Next
Fig 9.7.1 shows the Microarchitecture ot comgol n and nsiuon Kegisler (u). it gives two groups of control Signals that it 1s slower as compared to hardwired conurol uni.
tbasicaly

B
consists of
Control
Control Memory, Control Buffer
Address Register
c ekternal sysien bus and oet niermu wiuin cru. 10

Unit
(CAR, nor ue pertoris tne ToowIng As S.7.3 wiIke's control t nalse w gueser address from regisuer-1 o

Control me choe
urtons he CAR a READ command for the UQ. 9.7.3 Explain Wilke's Engine (Hardwired giter- boriaontal
Stores the of ogic sDes eumtru ilbehavesake
a dress f the wilkes
The CBR stores micro instruction after it has been ieiched The instruction from the address specified in the CAR
Control UNG) in attal
OArA
ge sett aldress

from the control memory. into CBR.

S FE
--- - dD:DEC the nicru
consis of Two aldresses.
h micro instructon

sequencing unit koads the CAR with the address of de be contents of the CBR, ie. the micro instruction, generales Wilkes first proposed the use 0r
ma r"
Ooe hrched
brunched adiress and he xx
*xt instncuon depending upon brancting and issuCS a reaxd Uc cotrol sgnals for internal as well as external bus and he Ocsign Is basically based
uon a

e
command. nomaon aboul the next address for the sequencing unit aled with diodes as sthown in Fig. 9..2* 4SACHIY SWAW Vealre

lech-Neo rubliauons WDere AuLbon mpur movatD ech-Neo herrAwtbon y

4CUY S2A/ Ventu
 Dipital Logic & GOA (MUASem. S Conto Digtal Log n3Comp)
UntDe
MICRO INSTRUCTION as sequentaal lechniqoes Control Unit Desie
total of 38 micro instructions 9.9 aled
ecoutrol unit has a
SEQUENCING techniqucs can
ed c he format of
Address field,
Insanuctbi Next sequential code.
and total seve ddress informaton in he rmcToinstrucxtion. Te Branch logie b
Theve ddress selecu
A uQ 9.9.1 Explain miero instruction seo can be g
ud es s signal is given to metiplexer which seites oue
encing. t te above-menbne
address fields
MU- 0. 5tc). May Marks Two
-- 2b). Dec
rSingle address fiekd oress docoder

Aculador (MSH)_
***
two basie tasks Penomedb s (_Vanabie tona
memory
control unit ie. microiastruction sequencing and mio Cortrd
Shut Register
cxecuooa.
d Two"
address fields
Regster (MAR) as well as
Aoaress Mierolnstrocon >eueacn nce a microinstractio This is the s e sed for geoering address of
brarbrdds "
eecuied,
e cOnol memory he nekt
This
icusuu
wo es
Microlnstrucuon
* B es the requin tecnidpr felds in esch
control signals tor ue mncuens to get ncro
LGJTemporay Repster tot coi executed
.99.1 shows how this technique is inplemented
In the following section we w disCuss in detai
ontrol buffer register contains two sepuate fields for
9.8 cOMPARIsON OF address. A multipleier is USed to elect any one of the wo singe
ed EE
HARDWIRED AND MICRO consideratons Fe992SU
DeSign addresses.
PROGRAMMED The address seiecon 1 Ung Bnch
inputien
Deciding the sie or he mucroistruction and the
addi logic block wtich takes from differeen fag bis and () Yariablek Pormat
CONTROL UNIT orapprebensions fa
designing
crotu E
ectinigqpes
control bits. 1nE eiee cE n his approach. the ires DER C
Minimizing the size ol microinstrucion also reduces t
Eadoa Hardwired Mieroprogrammed ddress decoder then decodes the address present in the
Cro Uat generation time faster wit er
the addess
Control Address Register to get the next microinstructioe to The atber farmat cvatains soume bits coatains branch loge
Execution Speed Comparatively Comparatively Slow microinstruction. be execured. Oule and the remanDg
s conaas a
Emor Probahility
Fast he adiress generated by microinstruction can be of cne d
he rouowng 80dress Te lo onder to ekct one
itis
Mor Less alcgo Cono tefnt format. he
0 Next address Is deterrmined by he instruction rgisier oleser velets address form Instrucuon g
Control Function Hardware Module
o Next address can be the next sequenaal address the eLE equena *
nplementation Address decode et address 1s
4
Branch
Complex
o
etactions
Inst
Handie
Ey
Le.
u
once per instnuction cycle.
wnen a new nstrucuon 1s Teked Control memay

The second category ocus normally in aimost all e

LControl Asress 1Adress 2 Conb
COst eisi
Design Process Complicated Simple, Orderty and design should not be included.

Sequencing and Complez

Systematic
Easy
pe ranchung gves fexibility for the programmer
duerent logical cases. Both copdinoal a
in

PhgsBranch Mutilerer
s
on

Decoding
Capability to ompl
na branching
croprogramming.
are very important part d

beids
ncon
asOe t0 icr
branching is more often used. Henee ing tO Addres
incorporate ndesien is
since
DEraiming. 9 Mieroprogram SequeDcng
changes (new equirea. software portant to design compact, time-efficient techm
fheld eencg anabie Format
() Single address P 9991
NUETOprogrh
bu
epicrplement
&9.9.1 Sequential Techniques- Micr e met
Number of Preferably Less eferably More
O of bits in
mirs Address Ge
instruction with Next Address r eld anpicnen
The seqaenda

CISC pr a icroprogran is

eEver
APPucan00 RSCprocessors geting executed, the aidres ction konis.

Main frare scucn to be eACCuled is Beneraieu.

are aved by implemerng
of single address fiea
ES
ent
1S generafed by co4sidenng Hg 9.9.2 shows ae inple ddress fieN* ASACHA MAN eate
reSUcr like instruction register, conu
Tbe opuons tor bet
be iechnáque used to generate address ot structo duchars inp
ne Ieeb-Neu Publicatiens here
Teeb-Nee hublealbens ere ublicalions.
Aurlbes anpT LRND
SACHHY SHU lanb
 Dihl LaeacOAMUS t Des
ogic&
Sn 3-Comp)

ddres
E
anferent ways to compute next As a resun
routine (logca
Ees
su
eocro-1nstructions
staring address of
e A
Common
1
Control LUnit Design

ous techniques of compuiting next address can ekeeute

natructon that has Just
on
been loaded
that
into the I
De
Address of
er transfer micro-operaion may be writtrn in
Ri
n hto wo Calegones Dy
If we take an exampk ot Additon instruction ADI
iier Languge) as:
DD. Re
unsies
o
menuone co deender generates
the mIcrstnction
cong.
tor which
kressing
*emple.
elu. Tbese echniquessae ireay ource Eier
discussed inthe addre ent i KBhe *

techaiqaes such as Two-Beldlcondie However, this address be R

ribztng. Coditional branching mHcrprogrAirn counier.
s
as
that the source operan nto th 1001 detinsion m urce egiter and R is the

Png
dciress
dhniques reguire additional logc tor
are
ADD Instrdeoa can e peened in several dit 40 OperstionsInvolved in Reg
Dese iechnigues Mapping. Addibon,
Control Consider that
may
there are nve possioe branches
that t e ac 0040 oT Tasfer the contents of egisler R, lo egster Kg *

P
echnic
cnique i This is the commonly used impicit instruction rolow Dasea On ue nve different ac
tssing sier art oeded to be read end pat on th

machine instructjion i e Pordon of dhe

namly - indexed, auto d
ADD
nstnctiono be forSimlary Au
0Auo-Incre rOS as can De me amg C

TemenL lor Auto * Of egister R.

is dooe once per instractioncye direct and register indirect addressing modes. mode 1031, for Diect adde.
s.1his t
l nd coetro sgnal a opera
is,
wu e
echngue: ln this technigue,
two portions of the Wide branch addressing en sartung address
e Register Indirect ressing mode
pered on R. Fig 9.101 sbows the xhemanc tar such
a cotnpieE Bciress 1s formed. Ts at micro-roune be cakcualed dafterenuy for each addressin generaica O-itruction address in
npemented in 1BMSO55 mode 1e control mode based ADD nstructo. micro-routinte to exeuuOn o ADD instructior
s of 5MS033 is shown in Fig. 9.94 This is achieved by bitwIse- ng specific addressing modes respectively.
Inngue to modify the
07 08 09 10 11 12 starting adkdress generated by ue insuneuon decoder
e ppipaaiC patn.
to reach
9.10 MICROOPERATIONS
irwise-OR ing
hanees the Mdse ed T he fve
Primary hunctionaly or any Compater ar Processor based
A) possible address values 1011, 1021, 1031, system is to exeue
e nsucoa. 1be lnstroction excwrion
RW signal s 1-Raad operation
BB(0) BD) BF) depending on the addressing mode used in the instruction.
Start Branch
is operah onauy o
ae called as Mictoopetsons.
o Btct gcal
Ibertiore,
tasks. These tasks
Instruction can be
0-we ope

Pg 994: Miroprugranm Address Kegsier 1sler ucre-openbon

Generation dress field nstruction Addressing mode en as ue seqcnce or cTDoperalions,
d
Data moving on inte rnal CPU bus ean be s
As shown in Fig 9.94, the control address is 13 bit long and coding mcrO-adon is a runaaneal ketion performed by a Module
nachine on the data storcd ia the repsters asi sep owards
wO parts. The higher order bits remain 0 or part of tnstruction eecubon. 1beretort, sequenoe
sE
10r he microliastructaons.
OO0 1 0 0
0000 o o Micro-operalions makes an istniction D eierae aa e
Dnng the execudion of the microinstruction, the 8 bits of
conrol
ons
ses mgiser are moved
of control
fsrom the higher onder 8
RRR Based on Type ofnstrnactions to be execuled,
address.
Say ror indexca adessing
RytR
Tbe remaining 5 bits of coatrol address rEgister specilhes
wbether the microinstruction is guing to be executed peut or
Kegster transter mcTDorerations lavalid
ot. 1If these bits are set, the microinstruction will be executed
Anthmetic micopa Rgister unSTer Dpeduons non
o 1 o 0 o00|oi|0|0]0 Logical micro-operations
ext. Sgna
(FetchingWod rom
f not set, the microinstruction will not be
iemory Read Transfers
executed Memory)
Residual Control : In this technique, (Stoning a Wond to
Memony) facibitating Reguter ansler bticrerab
the microinstruction Flg.9.9.5 Transfers
iemory Wnte Usually, in and out signal
convenboes e uSed for ontro
addresses which are previously used and stored in temporay transfemiag
Tberefore, Startuing micro-instruction address 1or Indekeu Branch Instructuon micro-opero lar runsiermag daia in
the Kegster and
stornge within coetrol umit ae ued aga ode ADD Instrucuon would be generaled as unplemenie Dy eaec a
et or snals
l011 nstruction is
dalia oe trane g
in a pre-de incu sey
9.9.2 Wlde Branch Addressing tncro-ope rations

Reglster Transfer
Microoperaion Coearol signal Ri 5 equivaient o RwI
e tstructon decoder decodes the instructions and 3.10.1
ines on ouc g
to transfers informuaon
DNe
generated for the execution of
s
this
pecnc
ccded
instructuon.
icro-operation ASACRY.SRAH Yewtere
to another regisier.
Teeh-Nee Publications here Aothors inpire innevatio inoe Na
hore dutbars
-A SACHIN SHUu Vetne Ne
e-Neo Publieations Deno
 Control ogic& COA MO-Sem. 3-Comp)
Digital Logic & COA (MU-Sem. 3como uniDesign Dot
For example, the addtion microoperation can be lc,Forample, the bitwise Au mcrooperation can
Control signas Data TransferOpar be Read the
da
or Arithmetic microoperation
R,-R,+R S
ic fo
Arithmetie microcperation
R,-R+R,
puitting the MAR
aa s operatuon is achiewed by
On address bus (Part of the Systenm
e of operations to ad conents of register us) along with a me c
The sequence ot operanos o
register R and to stonE
conienis of register
m
R,
and
ee
mgister Ra and to
store the esu n egsler Kg may
R, and
be aa
us (Pht of the system
bus).
signal on the contro

lo 1ntema. bus uES register R may be The rEsult of memory read operation is put om
lntermal bus to regisier Ka
follows olows
ration 1 yiem
Sysirm
bus). whach in turn stores the daia a
u nl:
of Ri are stored in regisier t dontrol signals: Ria
emory Data Register (MDR) Tbis
opertioe can be
Register R, to internal bus of R, are
Contents oR. are stored in
in register Y
conto sgnals: KM(MAR)
eretoe the
he openation epresented by RTL Ri addre

-
Operation 2
K Can be perfored using the set of control sgnalis*
of Rg and y are sent to ALU and contro
roopern**
RiR signal ADD Coetents or and y are sent to ALU and control signal
ADD
mlariy, the operabon represenied by RIL:
Control signals: R2 me ALUa. ALU Control signal indicates.
Rg- Rg can be performed using the set of control
Cetrol signais: Roa ALU.
signals* ADD operañon ALU control signal indicales
Now the result gets stored in Z egister. operatioa
AND
FE102
pArale conol
shows the Register transfer operations using
signals.
Microoperation 3
Contents of register Z are transieried to the CPU register
Now ther Suit gets stored in Z register

Comtrol signals: Z Ra
R droperauonJ:
Zz are transferred to the CPU register Rg
Contents of regisler
an- R2ou-
RTL Statement for the Anthmeuc
Microoperabonoperiuon
30n Opeuon Ryf-R+ R
Control s ontrol sugni

Y+R RI Y RTL Statement for the Anthrnenc aaiaon operauon Ry- R+R ema
2 Z-Y+R, |Rza, ALU, ALu COnuoi ADD n Operation Control signals 9.105: Memory Read Tranders
Pg.9.102: Register Tnnsfer Microoperation (with separ teo a Yn (Fetching a word from tbe Memo)
cotrol ignals)
Z-Y+ Ro ALU ALU control Sequence of control signals for read operaton
When the controller sends the control
signals Kia and R2 oun .10.3 Logical Microoperation
wO Switches are operate T Mierooperadoa MARac(On lntermal Bus)
:

Tis forms a path from register R to Ri, via internal CPU Logical microoperations are performed by the ALU inside
the
Zout Rain crooperaion iMAR oAM Address (ou Syste
us, effoctively transfeming data
from Rz to R, ncoperauons perform some fundamental Bus), RAM R#RD Coarol Sinal
logcal operation on the nunenc da Memory Transter Microoperatlon 3Microoperation : RAM MDR on Syie Bu)
9.10.2 Arfthmetic Microoperation These basiC operations are that of bitwise AND, bitwise OR,
Memory transfer is achieved via the system bus ot te a
-
Arithmetic microoperations are
bitwise Exclusive-OR XOR) and complement operanon
ec. computer 5ystem. Memonies are accessed by isuing the 9.10.5 Memory Write Transfers (storing
perfomed by the ALU inside
0dress at e memory cauon toe cesse Word to Memory)
hese microoperations
the address buis
nDC operaion on the numeric data. he address is supplied by the CPU through Transfer Microoperation can be achicve

sc operaluons are thut of addition, suberaction wcn s part or the system bus rougn ue u he Mcmary Write
aence-
anneuc Memory Address Register)
ou m
compans00, IDCrement and decrement operation ddress in Memany
etc.
drection of the data-tlow, there are nwO ys l
geoeraing the conarol nal
sienal
cPU
wern R ALUu Based on the
memory transter operatuou
(MAR) This can be do0e by

Word rom iem) or tie 3ysteam Bus).

Ra mOy Kead Transfers (Fetching a AES DS
wnten to memory. This
Ra Memory Wnite Transfers (Storing a
Word to Meman uDR, thal is to be
Rin wnte tbe dula
openion is
in
achaeveu by
on local bus and
Purgu
CPU (Fetching a From here, it goes over the
nternal a9.10.4 Memory Read Transfers hen on toMMDK
Pat of the System Bus).
bus System Da
-R Word from Memory)
Ran S0i Lopcal Micro-operations (Ex. Bitwise AND Micro-operution can be axieved
Ra Microoperatioa
ne Memory Read Transfer
RY 0Owing step seque
in Memory Adiress Kegs
Fig. 9.10.3 Arithmetic Micro-operations (Ex. Microoperation 2 :
Raa ALU ALU control ADD ace the memory address
1
Addition)
Microcperabion
S:, Rain his is completed by generating e ASMCHIYSHU Vinture
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iecb-Neo Publications. bere Autbos p
 Digital Logic & CoA(MUSm
(9-22) CO
NDesign Ogic Com)
ess bus along with a memory reai cono
pan or he 5ysicm buS). The
Targot
aire. nstraction is fetched
chcd trom he Fig. 9.10.
snows the schematic
Branch control Unit Dasipn
micro-operarions. strection
result of memor a) dress. staring Cxecution from anches to | Microoeraioa
MDR).
pOu s pur on aa bus Let us take example of Unconditional branch
reie : 11 RAMMDR D
address Ucdon; 9.10.6(6) Conditlonal Brancl hstructions : MDRu au. PC%
N DR dar Branch to addr) bo
c uon te *9.14
ncopditiona stroctions, MICRO INSTRUCTIOR
Memory where BR
oc Unconditio branch aly it
the
the
is satisfied
takes

WR- RD instruecaond
wOuld be taked
ar he s
1arget address where
progran, upon execution
oy uE
of thieCh
thech
jinsurcranch is taken), get
and therefone dhe
didres (address
ne EXECUTION EXECUTION
OF A COMPLETE
instruction. The RTL for the instruction is
PC addr
C
oD dition is nosaseUQ.
INSTRUCTION
MAR ADR tially in the ongnal program. The cont 1311 Erplain micro inctetivio
The microxperlonseeoe De performed
vatem f
eeded to take any acton, 1 the condition is not satis fied
lnicially, MAR, cu from the nterma bus loads For such n>u SMisfied, it is hDec 16. 08 Marks
MAR the address ary that the Pc e o wn e
MR prograrm localion where "addr' is stored, of pece ge dress. Since GQ1.112 Writs contro

MARn MDR MOR

en An
e uo
memoy
vn uc dysiem Address buss d
On
reau comtrol signal #RD
Oy
to
PC alway
the P
d
at instractio
from that address and therefore, o
obe fetched, once
is

on ADD (R3),
..
RI- We know thal the standard
-
**
PU The on e oyiem (arget) address, starting Exeu
CPU
ntermal
to bedelivetsr
read MDR. Therefore,
in
bus, which
opersion needed i
Data
is
program branches lo at
from there
ener
ADD destinatian.
souE
Bus ex branch iestruction:
Pg. 9.10.6: MMemory Write Trarnsfers Let us lnse
l Themefore, first operand wcold be destiation operand and

Which
0
in turn stores
o the Memory)
the data in Memory. 1hais operlioa ca
ronied
operation needed is MDRu ru PC
get
Oked m .
address for the bras

hercfore,
BEQ address (Branch f Equal to addr)
.Where BEQ I the maemonic tor conditdonal braoch
second aperaad would be souroe
s uhe daa contents ot memory
openn.
on
wnuEn as M (MAR) =MDR iostruction and
e
conton s satshed (which is EQ-
t
Equal) addr is the 1arget uress wtiee the branch woukd be
in
by register
the same
me mory locabon (poeu

Sequence of control signals for write operation Memory KRS)

"Mierooperation : MAR-ou{on Intemal

tuken oy ea po eecuon a his brech
instruction. 1he KiL lor the instnucton is:
nE KL 1aeenl tor the instruction
Bus) WR YRD M(RS) = UR3) +*I
Mkrooperation : MDR. au (on Internal Bus) IF EQ= Ine THEN PC-nddr ne equehce o Muctooperces neeua w ccessiun7
Mcrooperation : MAR *yam, RAM Address, stem FLSE Contnue CAEDe us suuc boe-
RAM #WR Control Signal MDR Module
-MAR Din To check whether EQIrue, conrol unit evaluales the statuis T Microoperation i

System
Microoperation : MDR vmRAMu (on System Bus) of ZF (Zero Flag). If ZF fiag is Se, indicang EQ c0 BM
ned. radon, the cotents of RU egistet are loaeo
to be true. i the coDaiacn
9.10.6 Branch Instructlon Micro- MDR te lenoey Adess Regisuer (A
micro-operalions needed to be performed for this
The Micreoperation
OPerations oyem
Brahch Instruction add decision
iastruction are MA e AM AOUFESSa
RDLonrol Signa
making and therefore at NAN
logac to
MAR CPU PCn from the intermal bus
-Iaitally. MARa cwhere
loads the address
egisier os
ne progranming wiun systems.

Branch instructions can be broadly classified into

JL
Initally.
"addr is
stE
the System Address ous
on
the Sys
sends the conitnts of MAR

enory.
Re Coetrol signal
Unco uonal Branch Instnuctions and conditional Branch tenal ,
MAR siem On
instructior Bus Memory along-with Memory read control
signau
wu
D
a 9.10.6(A) Unconditlonal Branch
Fig9.10.7 : Branch Instructions

sequence of microoperations for unconditional

ne memory delivers addr
acedcd lo be read in MLDR.
on de sysiem daa bus, NDR
outputs
ca data
>y
is receive m the Memory
in he Menoy aa
he brancn The memory

Instructionss nseUcuon are

Mierooperaton : MAKu GU
Therefore, operation
Now the "ddr (whicn
c s
ded
for the braacb)is
m
Therefore
R IDEelo
in PC.
Tn unconditional Branch ns S equircd
to be aded
aksthe branch and therefore the next instruction to be 2Microoperation
icrooperation :: MAR
MARa owe KAN AO System MDR
Peron nceoed is ou CU
nicro-operaticns for
cuadiboaal brabcb MDKaN loaded in the ALU aS nput (Whicn are
e get adires5 (address where the branch e
is taken). Dus), KAM #RD Control Signal Sequence of
is sabshed, at- te conients of the meiy oibieu
if the condition eto
Microoperation cthon,
For such nstruction to work out, it necessary thar : RAMu. MDRa. auem (on System Bus
oe
is
with the target address. Since PC alu uer crooperation
:

aa CPU

oed Mierooperation : MDRu CPU

K MAR RAM
AiFS O
ASacHIN SRAur Ventere
he next instruction to be fetched, once the PC is loaded with crperation :

RD Cotrol
Sigma
Hus), RAM #
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 C Digi p) Control UnitDes
Digtal Logic & cOA MOS
3Mierooperation :
Rrc Write Microprogram for the
Microuperallon
RAMa a gaton ysem Bus) The qu Poms needed to cCessuly 33s
RIa YALT Puncice ADD e)
in to Y register and The memory outputs o8tat evea in the Memory Ds R
herefoe d in to the second input of the ALU. Also, te
Register (MLDRJ u Ueee, eesover the Sysem Da rMerooperauon 0 ADD R, M
HuLR, 19
ALO cOmmanded by
IS n appropriale control signal, lo cany bus Dc10,Moy
ou Addiuon operuu o
Mikrooper
lo ths ddess Beit AD
"Microoperation : MDKOu Joaded in 9 ADOH,
ts of MMDR are louded in the ALU as input (Which know that the suandard
RI, M-*e
operation gets loaded in Z register, from
effectively, the contents of the memoy a ponied
g
ed by Merp
MAR
AM Address (oo System Bus), ADD
where it the microoperation loads the cootents in to MDR R
pster erperTauon
RAM #RD Cootrol Signal -ADD destination, source
operan
Rsrc ALU, (On CPU itermal bos) eretore, first operand would be destinalbon
e nsruon
Mkroopemdon
MAR RAM Address (on Systesm Bus,
Rla Yg ALU Funcuoa SUB

Coateats of Regisier e
0Tgser and
ALU Function INC (+1) ana
adds the data
wod

conts
SOurce operant

cam Th
ration sends the contents of MAR register on eios is stored back in

his r Is of MAR egistet on

ALU is commanded by an appropriale control signal, to Adess
bus. Simultaneously, Read Conbrol signal RI
the Systcn Address bus Simularneously, Write Control aDis issued for the memoy The RTL StaMe ment for the insiruconB

10 e MMicrooper bus, Rsre cootents are

E
MCrOperauoa
B SO eioy *

t the same thme, on the CPO rernal

Deeued o cceSstuly
ouput and eceived i he Alu. ALO functioo control signal ouct0persdoas
MDR u RAM, The output ofALD Operuon gets loaded in Z regiser, Iom Jor Incre imEenng s gven. Lnas, he coenenis ol Kare regisier E s nstrucbon-
n e ges sored in
he memoy as MDR Conicats *De e HUer00 10005 uE contens in to MDR are incremenicd by i
an 1oaea n ALD Dpur l Kepsa) Mroperao

poinied by R3 mgisier as that address from MAR is sent u Microoperation: sleromperaraaoa icrooperation, the memory address value M loaed
a. ysiem Bus)
yeopero MAR AM Address (on System Bus) AMau:
CPU intemal bys)
in the Memory Address Regisir (MAR

GQ. 9.113 Write control sequence for RAM

WR L TEOn bUCroperabon i
the Duta
has microoperaton sends the contents ot MAR Tegster on memory outputs dafa, it 1s receivea in AK=yam RAM Addiess (on System Bus),
instructonsUB R the 5ystem Address bus. Register (MDR) and therefore,
1E
gos RAM #RD Coerol ga
Simuianeousily.ne Lonu on
ction suB (RSJ, RI =
We know that the stardard
e conne MAR egsler
*DR O 5.
generic forn followed is:
At the same time on the CPU
inernal bus Z conients are pusly, Read Control signal loduie
B 0esnaaon, source. MDR RAM, gister. Effectively. Rsrc coptenis
get
RDis isued
for the memory. 4
neretore, nn operand would be destunaban operand and in ally, the resut gets stared in the memory as MDR COmies st-incre mented by 1. Mcrooperation:
Second operand woul source uperano. bus
DR yMem
be Ie nsincHon

R3 wih De reicte PDcd by register to the memary. This is the memory locion
s
at aidress trom MAR IS seei out
Microoperation: RA
The memory outps dala, l 1s receve y

opcralion.
MDRaCu ALD
addition is slored back in the same memory location (poinied Wnie ntents of MDR are loaded in the
ALU as inpat
y glsicr RI) memory kocao poni
9.114 Write control sequence for the elfectively, the contents of the raton
The RTL stasemeni for the instnuettos s

MR3) MR3) -
RI
In the
n
Instruction ADD (Rsre)+,
D0 CSre) Rast Kare
SMicrooperation : Contents
CAL
of MDR are loaded in the ALU pu Weh ae
hesequcace Rdst- We know thal
of Microoperaions need0d tosuccessfuuly
anard genenc form followed is: Kastu YALU Function ADD ()
ae io theSMicrooperation
"Microop
wue, OESunalion. Contents of Register Rdst Aka.eay
RM
MAR neretone, ini operand would be source operand and
he p cona
eroT, laaded in tobytheun appropnae
seconu
aded in to Y register and
In this micnrooperation, the contents of R3 registcr u opera ndicales thiat the operuno
ou cOmmanded goes oALU
outpu Z Conens e the secaed inpuk of the ALU. AIS0, e

n ue Memory Address Register (MAR)

are loaded
.e
destination o
Mecond operand wou be Aditon erabon 1he esull
is commanded by an apPprupriaie conu signal,
0 cany

Mcroope egister. Addiion oP

The insuruction adds
o
oeut

MARa ewen RALM Adiress (on system Bus), RAM

the data o
Pmied by register Rsre: c Microoperation Microoper
RDControl Signal Rdsta
This microoperalion sends the contens
wthe
Esul ot
the register contents of Rdst and ue
result which is there in Lg
Kl
gets loaded ia
Z. register, trom

0 MAR Tegster on adition i back in Uhe register Rdst y. Lhe The oupu
u
mcratjon loads the conlens n
RD is issu ** OSghal TOr Uhe instraction is
in the Rdst egsier where
or the am
Kast + M[Rsrc) ASACNIYSHAN Vrwture
Tech-Nre Publicatioena here duthars inpure Anaovsoa
MUZYSHUI leatan leh-Neo Publicatiens-ee
 OA (MU-Som.
3-0
Control Digital LoI
Un Desin
Dta Loyic & MUSem. S he help o
egagrenig. iferem conto c
gt KI, ertoetively conpeting the execuion NENpH funetons pes i are sub
Thus,aamcro
mcoinetration is in primary coentrol-store memoy
RMDRa microprvgnn makes compilatio henhas the rnals generaid
The contents of regisier K: Ae cdas the comten
eftice g mpoxsible. a ecomlay comiroi se nen The
MUL R1, R2 MDRmgister
Micro- ys called Nano
rming is osed for

Om
h the Instrution MUL RI, R2-We know that the stanaurd
tolowed is
TMAR RAM Address (on Sysiem Bus) detecthon
emors ana
t Om of system
fuhs and T

Ed tpars. fom nCM

KAN N gnificantly enhances the fa t gneraie control signals. Thrs, Nano programmung gves
and
eed eperand would he sure corrad crion Adiss as. Simaslrane
Simultaneour
gister o serviceabilty ot the sysiCm.
n es ue a cootents of RI wth the contents of R2 signal WR is issued for the emory. Efectively Re-connguroe
5. ESos :Using RAM
srac tbons s shown in Fs9.131.
KL Sienent for e insEruk thn
B*. conients of RI egster as the memry address. implementang conurI memoy (CM) alows the Micro
4MUcroopna instne no he Control
eieute thus
tinstrutioe
NroopeTabons eedad to sactsy Memory
sonirce or
niecn

0n-syi
a

au.
u ceachangng
enory
By the
The next address of nlR is directly obeamed The next aktress
esun ges so n ey
Finaly, the as MDR coteats
eTed by ether inceentng the sano pin co
are wriien in o ue memoy ns urausies he contentof
egser Ras the contents of memory kcation pointed device or by burning it into the g rm Elma une (orn nea o kiress
AL S C t hashd in the ALU s one of the inputs. Thas efecovely competes ue ckeeunon or the instruction
possibieto talor Uhe machine to have diferent
trom mcrO nstnucthon opeode ).

Instruction et tor u aietet From sequencer

Mierooper 40cabons. Changing
R2YALU Functice MUL( 9.12 APPLICATIONS OF the Mict0-insurdeuc erelie, 0ws e
PTessn t0 *econfhgurabk.
Conients of Register R ar ladod in to MICROPROGRAMMING Mcro Program Courter
Emulation efern o thetr
tbeetor, laaded
ALO B Commanded by
in to the second inpu
of the
AAto -------- --- - 6 mulalan
mcroprogran ou onc macie ko eaene progams
a appopnaie controi sgnal, caryUQ 1.121 What are applications of
plkaoa operanon. Micro Contro Menoy
microprograrmming ? widely as an aid for users in migraing from on
icrooperatioe:
computer to another.
Rl GDyE01934ey158Mark Micro Insructon Regstor
Micmeme
her i
operibon Fes kaed n Z egister,in from to
apable imnlemes 5 Simple to impler W 9.13 NANO PROGRAMMING
mtinlicaos ients to RI
tEngaging in to hardware completiy srctos **********"********************
Hence the
compleung the execution of the
nauely
***
yu
**
UQ. 9.13.1 Wnte short note on Nano
aro Program counternPC) Module
instructios. truwred cootrol unit needs.
ad

Further,Mcroprrgramimed control unit offers fherubuliy

o Frogramung 4
w Contr sequence for the adding instructions and/or modiftying existing
nstructions 5(e), Dec. 15. 10
Marks ano Coo MemoryMnM)

on MOV (RI), R2 MUa. 5b). Dec. 14, 0.

AD annstnuction u
*-n the Instruction MOv (RI,
9 5.5Marks the instructon set ot the Processor
MiCro-instruction
:Q. 9.15.2 Explain concept of Nano Nano Instruction Registers (niR)
R We inow that the
few locarions
-
(e. adding a
programing
form follow ed
DenC
--
is
vee
0:0.Sg.ay 155AS
-

source. roprogram.med control unit. a

Onaton, Control vgas
. first peraod would be destinaton
uDy cnging uhe definitions of the instructions.
S.13.1 Concept of Nano Programming
opernnd nd eEOrE, dterent upplications can be derived based on ue g.. t Nano Progrmming
moves te daes operaod
e concept ot Ueroprograng
programmed processors, an instraction fetcbed ron
or ano progiramimng
locaion pointed by registerlo
the memory pREmentauo0 a
RI. ol control unit : Microprogammed
nuor units make use
ot
micro program sioed
y a aS.13.2 Advantages
Microprogramming ts nromemory CM; wheneas in
Te RTL stdenent for the instruction
is: r Keduces lotal sze of required cootrol memory
npiementing the control unit or micro instuuctons
are Dt d X
MRI)
1)ER2 O,theto generate conrol gna n o eve coara den echnaq, the toa control
The sequence of Microoperalions 2Implementation r ntro
eecute this instruction
needed to successfully
m
of
Microprograms.rting
Operalng. e a second control me0g HasWn
memory (nCsi). Himtwt
I'Mleroeperatoa r Operating system. Jt provides
the
ser with coatrol emoes um of wors in the high
bs the
there are two levels of were
Km WARou nOw nasmicro cou
s and
pnvileged Instructions. nemw
contro
In
n
this mcrooperatioa, the coatents KRI
the Memory Address Register
of regster are loaded penomabce
peralbon system implenentation a
of the operabng
(uC urr kvcl control memony is
n
o epreseats the size of wod ia the high evel memo
(MAR). 3. Higb-Leved
Languz
sysien
control memory (nCM). This is shown F
Teeb-Nee
e support : High-Level angus
Pnbbratises.-bee Autben aper provded in processors al the machine 4 S4CHIY SHAH Ventmre
inae
A5ACHLN SHAH Tatu Tech-Ne Publications kore detbos ny
 Control Unit
Desio
Digilal Logie & COA (MUSem.3Come
flexibility
Greater deslgn
eens the programssizeof wond in the low ievel mem 2
Himis f
two level memonies organi zation moe
are verticealy organize o
y, mcr
ange and Wmis small. n Nano programinung
Beca
nexibilnye
its hetween instructions and handware
hich akes Wa
highly parallel honzonta g
s unal. 1hus gives the compabble
size for
9.13.3 Disadvantage orNano
Programming
Sl Hms
access time
Wa which is larger than S2. The reduced size of
conro Ipereased memory
memory redaces the total chip area
The main disaovanta o Ony aPproache
is the loss of speed due
10 e ekue y access required
for Nano control memoy
..Chapter Ends
 Digital Logic & COA (MU moryrgarzaon gje&COAUSem.&com
Sem.scu D
L

what is the necessity of cache memory? Mu-0. 310). May 18.3 Marks
Ua.10.8.1
10.9 cache Memory Principles / Princples O
LDy * May 18, 13 10.1 INTRODUCTION T Memory ornzu
UO. 10 on Pncipie of locality of referenoe, U.o. 6(al.
0.6a.May 10 Marks
18, 10 Mar
U- 0-13 MEMORY

.
nole
cne Cahe demory Terminology/ Perfomance Metncs and mprove
10.10
10.2 CLASSIFICATION

.
114 OF
* ***
0.nEoments of Cache Design
TO.11.1
.
are the features of cache memary design?
m ananssnaaana***********a*** i
, 10,1
yis an essential
asic function s o comt o the computer sysem
D
PRIMARY AND SECONDARY
hat B Marks. 0. 5a), May 16.10 Marks.
iormaion in tems
of
MEMORIES
O, Nay 15. dau p The organization,
Ua.14 10.112 Expkain in detail. MU-Q, 4(b), Mav 1a .10-14
gn beavily impacts the system's
heThe most essential clement n a compou
0.11.1 Cache Address
********
14 d the
emory syslem
T0.11.2 Cache Size
*******
*****. e syskem memory cost is a significan f
Aio, since aeg
RAM. R
with the magnetic disks form the important
n overall
13 Cache Mapping Techniques.. **

*
16
16
st of the systern, the system designer must pay
aestion to
sorage memes
ue
mapping techniques. MU0.6a). Dec. 15.5 Marks
C
uT0.114 ain associatve cache
Draw organizabon direct mapped cache
of speccancns ne or Biock,
with o
10-16
memary desigming

nenoy pon their utility and accessibiliy For

uyscde
The computcr cah be classified
either c
cane
Gu.T0.11.5
No memoY, 20 BitOoresses
Draw organization of tully Associative cache P s or block,
9Eneruy
10-17
upon ue rganizanon sde au
Mructüre dE
or Dsea
based on h
0n the memory
1021
specihicahons Bytescache with 16 line jechnology Primary Memony
32 KB cache memory, 20 Bit Address is 9eneraied Dy he processol.
a. 10.11.6 MU-o4 D
mapping. 10-18 Clasilication o
an e siownas roows
arcay or memory organizatioan memory that ia directly addressabke or accesible on the
ey map ce he procEssor N caul pay
Ga. 10.11.7 Draw organization of 2-way
16 Bytes/cache line
10-20 1. Primary y emory organizationally
32 KB cache (16 KBway), 20 Bit Address is ger
aDons conssts D e
e es, Ce and the muin
AL 9pes of RAMs and ROMs form the primary memory of a

M 10-21 memory o COmpuer sysem. f

3/ D Ct Mapped, Sel Associative and Fuly Associative Cache Memone fist with he processor. They fom the intermal memcnee
1011 10-21 computer Systeim wiere all the actve p
OrOems based m acne Mapping ecn.ues
use data are stored. Ccne are usuay oo
Du. T0.1.8 Consder a cache memony of 16 words. ERCn DioCK COnsisis Or
wor0s. oEE Ue
meinoy
22
i
cp
exiemal to the CPU. Main
uie ro
E
aures
Feature o Primary Memory
z6 yles. Draw associabve nmapping ane caicuiare TAG "
9
May 19, 10 Marks, 56), Dec. 18, 10 Marks OnDSed.
Bnd
MU-O.5B). 0. nooeeor memory.
a. 10.11.9 35socaalve cache consIsts of 64 DiocKS divided in 4 biockx sels.
smemory contains
10-22 tions of the
A
As à resul, s aruy
acCess timeie
it resOds fster than the secendan
so96 blocks
The main

. How many, bits are therein c cache

e
many hits are there
g, 0r and word terds)?
in r

Bddress?
2.
good speed.
Secondary Memory: Secandary memory is an extemal
2 Prinary memory is acesed directly by te proe E
Every mcmory neterence by the processor for data and code is

MU-0.36)1, May 17, 10 Marks memory after the main meory used to store system
10.11.3(C) Handing Cache Capacioes compar Ko eltermal Le.
Misses and wntos- Progransand data hat s Dot used cordinuously. It has thiemory.
EAy
n
********anasas

huge cupaciyu s siower unan pr y Few mary are volatile in nahure

10.T1.9
i.beir onsents are loxt once power is suitc hed oft
.
Numbe or
ecneeS. sa disks, CD-ROMS, ete. are exampls of seconday
anemmmse 10-24
J0.11.8 Cache
10.11.10
tonerency..
Explain in
m
brief cache coherency prablem. 10-26 Primary memory is expensive as compad o secoadary

ua. 1MU-0.6b. Dec. 17, 10 Marks DSeu 0ne semconduetor lketDgs uEG, mmary memary consIS ot he Su pats * SO*n n
snon noles on Cache onerency.
writo
Ua. 10.11.12 0.bO. DeC. 16, 10AarkSS
in in detals cache cofherency MU-0. 1C), Dec. 14.3 Marks, 0. 4(C). May 15, 7 Marks
e csiea as Tollows 21.

T0.11.7 Line Size 10-26 1. Access Memory

Random (RAM)E ie ey i

. mterleaved Memory System.. seu tor reau operilom as weu as w

Modale
and part of the mam metmory
plain Memory Interleaving Techniques. MU.o 10 th O **ssessssa Cuied as RAM. The cache 5
D. T0.12 Expiain the inteneaved memOy-
0-26 Tequire RAM technokogy Impiemcntalion. KAN
Ua. 10.12.3 d. 20. MBy 610 1BarkS. Stuaric RAM and bynae
Eplain vanouS nign sp
MU-0.5B), Dec. 14. 10 Marks
oe dv a o
urnther classified into
Only Memory (RONI) : tte neny
10.12.1 Higher Order usmsmessssesse. Read
inteneavod (RO) Memory. a97
OIg he bool prcesses or
.
10.13. Lower Order Interleaved (LO) Memory .
. 10 ouy Is called as ROM.
ROMS
e oR RA

Ua. 10.13.1
0.13.1 wha *
What is Associauve memory 7 MU-O. 1e. May 15, 4 Marks 10-28 volatile memories on
ROM
the curguu
inpicaica
is

n memoy requines e d e-
pon the
DaMcally classified depenuing
0-20 wnung nethodologies used tor Ks Flg. 10.21l:anie
SACHY.SHANVentare

Tech-Neo Publications here Aothors inpire inaevalioa

d 5ACHIY SHAM Veture Adulhors
lacalions. bee
 DgtaLogic & coA (OSem oryOrgan DigtalLog
Sem. 3Comp)
a10.2.2 Secondery Memory
that 1s
not direcuy addressable or
acEsabie
In case ofRAM, rcading as well as writing

eanng nate
p cnea sgnals. Also R
dais ts lntH
performedwis
power is cut to the menle,
AM is further ca
SDRAM and DDR RAM.
DRAM (SDRAM)
E DeNIS of data trasder nae
.
(10-5)

u be taken that here is so eer in

Synchronous
accessed as th B Called secondary
Dcinory. It is Reau
niy u y
cuNN OB permanent patterm
ot fabricaned D drtng o the KONs
etched into the memy nar cann
but c sn
be modified
tisa ype synchroeiz
exiena devices torm the secondary memory. The writra. thev
so d Don- volatile i.
Onc
memoy
vES information in
u with he

cOponled asa fixed device or a Uscd 1or ROMs t using c

nerefore, microprogramming ae t
ovable dev
or
wite system programs, function tables or library t
Features of secondany memory
The classification ot RAM and KOM 15 L
Being8 eriermal memory, the secoedary memory hown in Fig 1021 Transistor
requires mo Features of different mencnes are
given in Table l10.31.

xoRES
Siower than the primary memory. Capadtor
eoy CAnnot be Table 103.1 : Memory Techologies
accessed directly by the Comparison
3. MemoryypeVoletlty Slorage
ReadE
B ne Ground
thenaccr *
nto primary memory and Bemen Wcie
Fig 1031: DRAM c
* bey Memory i st ine
have bigger apacibes
ecoly memory.
compared Intemal E. Due to
ey s wih motherboend
one
Dyrame HaoomVoheCapadlorReed da
Secodary ES Sre
hon-volatile in nature. Electnca. Electrcal uait is uransferred synchronous every
to ckoct cyce. and gremmable Reed Only Memory (PROM)
o.>ondary memory u cheaper as
compared to primary.
.DepeDding on whether seco0dary memary Double Data Rate RAM (DDR RAM) -Vie nes e

.
device is part ofSatle Random M
YPs o ecodry
memory-fxedAcess Memory This RAM has wice uie aaa ransier raie as compaured to eromed fer the chip fabricaion by any chip developers
and convenience in wting PROMs
SHAN buiry
endy This 1s achicvea oyuansietng ne daa two mes per o Ehp develkopments
a Ory Mamory Non Wrod
transfer cycE, Gnce a uenng
= n(
Coe
FOM Volatie uing Esable Programmable Read Only Menoly

hdee ven though the same clock and tming sigais a

(EPROM

PrOs used the effective transfer raue gets doubled. EPROMs ie read as well wnte memories but are d

P DDRANs are usea s coenplet main memoy wih data enuy h

frequenty or ad
wnted
mosuly
a ence
memones
a
aso caled as rmad
Prograrmable ROM o aa te Over he penoa bey i opcaly
:
habon of Secondary Memory
PROM VnbsHis
Non
ved Haa ny
wyNot .. Eecthal
rceda DDK
following
rale
VErSIIS
*
Dave
D1s
evoive EPeOM
the memory cells ae required to be erposed to
chip O DDRI: Maximum transfer rate of 1600 MBA ulkraviolet ight cqualy. As a result, the ernsue ppens for
SD
solid-stale drive (SsD) o DDR2: Maximum transfer rate of 4266 MBs.
B
o EEsabie RON (Electricaly Erabe Prgrammabe Heed only
moy t sused to store data Non
ans Pead UW ight, Eectical DURS: Mazimuim tranisier rale o
Memory (EEPRO)
oate NAND flash memory ted either using mon- Vlatile
p DDR4: Maximum transfer rale
of 106 GBA.
EEPROMs are also read oquenuy Ype or eDones. 1bese Module
also refered to as a selid-state device. Electricsly EPRO Nen ies ce be eraued elecically. Rhet tban ernsng.
SSDs are more resistant to physical
shock and have essHdd Eecta,beCTC Slatc Random Access Memory (GHA the meenes we
access ume thereby reaucing quickerEtPHOM
en n SRAM, binary values are stored with
the beip or p 1
ae
without
e in FEPROMs, EEPROM is

W 10.3 TYPES OF RAM AND ROM FHash Monory Non

raiHead ricalElectcal ges. As a result, they store
Unlike DRAMS ey
ue
00
e iodic efemore costly tha EPROML A y

Volatle eicd.
Write short note on Types of ROM.
efreshing o save compa o EPROMS.
UQ. 30.3.1
. .O. 6a. Dec. 16,10arksl
MU-0.50:Dec.15 1O Marks
0 Dynamic Random Access Head Only Memory (RO
ash
Memory
memory (DRAM) poces by*ing
Flash memines aperformaeletical
ms
-The memories are always accest of enGng de dat
a
wnether they are RAM or ROM. Rand be menory cells in DRAM are made up of capa
The dala is stored dunng
o as crating
is called process,
a ma cnsing or oaauy a
sene ol charge is interpreted asonaryo fEEPRONL Bu e eau
eu
memory uhroug wind-in
e
words are durectly accessed from the
reSSing ogic.
EO
periodic nefo nd
binary G
discharee
to dischiar
ge. ee KAMS T
ata. The
r
creation
copy of ROMBD
is a costly ernaing prueM

SOAY MAS Wesfure

tuple
n the dala.
Tech-Neo Publications - be Authors nspire innovatina
-- 4CHINSMH Veoture leeb-Nee Publications Were Authwn
 LogC& COAMOSem. 3Compl
Dgta LoE & COA (MGSem.scomo
aton Dta
eased like EPROM. I is Therefore, an intermediale between These C
Frequency Memory
RONAD EEPROM. Though individual byies can 1Caon in MeAddressabilityny resa Oana
of
araSoon
without affecting
of
the
memory cells can e rcu a a
contents or uE ene
d ofusagee Capacty
aAnu mumber ber words :This speciñes the
Y r bow
LO thal are adrrs
Comparison Hege decre Ueit of Dals iransfer ods
of DAAM and SRAM paity of the memory is Word Size X No.
of Words
LT Cachne Access Method a

.
Denory device is specilied as BK s 16. Tis
Dtrentiate between SRAM and
12 Cache
Physical ye E OEVIGe has a word size of byses (6
2 bits) ano
SK) wonisn nemog.
d0.SDN. Dec. 17S L3 Cache
Tabie 1032:Comparison of DRAM and SRANI memory Volaay nit of Transfer
Main yc Sustenance
Secondary memor ntabie an" s be mazimam sumber e
A
Memory ceu constructu0nSimplke and
Perfortnanceranmeies
Ino)
y
by the memory a
memories uned as primary memery,
e

Complez and ertiary memory I5 erally

ord suze. ln the ase or
Ee ue.
7
Ceu Densiy (no o ceils iONe y b be ae as thai of its word It s usAuy
Fig. 10.4.1 :Memory tiearny or orEanization

Cos As o0e gocs down the hierarchy, following observations

() Location in he iemory Hierarchy (d) Aecess Methods
as
eensiveCoster
Increase in the capacity.
deals
dca wth nc
ene meneny in

e
te
ar
ste fmdamental chancterissic
of te memery memor
Auured possible locations for the mCmeres ue netod or order in wtch memey eks
Sght sloweras Faster as CPU: CPU consiss of many CPU regisers
3 u ESS me
Procesor sow pnvate memory storge space for
seorn.
Aetes Mage locatios i aparticular memy
Usaee yor sage of the memory by
mos required0 ot data refcrences, instructioe
cincs
e in amy order ie. The xcess me of
references and adueses. any urnies, R iS efemed to as LO achme
W10.4 MEMORY HIERARCHY Thus, smaller, costlier, faster memones are
suppictnenied by ceed Any location in

vO. 10.1
104LDece -
Dgeer, cheaper, slower memories. This is term
uerareny.be key to success for the hierarchy is that the Cache Mienoy i c ueOy thal i5 iroduce
axa This ype of memory is sid to have a
y
DQ. Desenbe ***-
the memory kierarchy in the requeocy or acess so reduces ks one goes down ia the sysem rganzaton with procesor proximity and dcor memones aad primay memones ae Random
the
EOpeter system Pyra rp sales nde Serial Acce
MU-O. 1C May 18.O. 10. Dec. 18.5 Marks
10.5 MEMORY CHARACTERISTICS hiph-speed memories qualify to
become
memory device, can be aed e "
UQ. s042 Eplain in detais MHemorg ierarey Currently up to 3 levels - Level-l (LI), Levek-2 (2) and determined sequence or order, thea the access method is

with aKamples Uo. 10.5.1 List different memory organization. Level-3 (L3) - of cache memorics are used in the computer
sionge dees hke magnetc apes exhbt Sequential cress
----. @Nay14.6Marks rcenstics
sysiecms.

aE emory i it 5 the bulk memory the syiem. Ae : Met

May 14. 8 Marks
0stlyid secompulers used
1c),
LA0.3e),
Dec. 15. 0. 10). Dec. 17.5 Marks
anu program (unsunactucs
Ga su
tnes
main memory. Main memory and Cache memory are direcay
ameis Hnd diks and Opical disks use this type
axntional sorage beyond t prdhog sces sarfae has an iniependent
metbod. Here each dic
akdressable by the processor or CPU and theelore lorm be
caogh to store all the prugrams and
coatinuo di 10.52 Desenbe the characteristics of
y Memory of the system.
eadwnic bead thus cach saurtae can e
nnaomy
ata. Also not all the data and programs are Memory. External or secondan
equired simultaneously. co
De U oem't d setir aTangeu ca
Single memy impicnenano MU-0. 4b). Dec. 16. 10 Marks
E sysiem
e UQ.
10.s3 Wnte notes on t uses device coecolles o od aSemi random or Pseudo Random
euireeots Or nugn snge and
taiet etecud0n the characterus o cess
Hene secondary storage devices Aeces
stoe actve eprograms and
e used to
--. O0.6(0), May 15,8 Marks
Pbysical ype
maller t) Capacity and Addressability
nes, whereas, save the rest of the daia
sTeanures and Uheir
s or Memory devices are measured for heir
performance based on difterent This type u euennuy c e nEy by which the
ugn se nuge menoy Oevces. This techniquw charaxtemsu Capacity of the memory or memory devi
emory
erned as eoly aray. erms of: i) Word size and )
Semiconductor memories.
Lne taster m uenones consist oregusde, ddressal
cxhe and buts e mmories are further clasuhed based 0n u
main memknes. NiagiEUe ord si
aisAs, CDs, DD. upes, etc. form
eWonds areexpreSu mber Write charnctensts as RAN - AceEss Memory
K0n
the iulhary or low cos
Siower memones. A Ypical memory wor ca mAnure) adKOM- Read Only
Dts). A
hte (8 bis). 2 byies usualyof Reiw nit
icratny Pyramid is shown in Fig 10.4.1. yles. Commonly used word sizes at
nes (64 bis) us
Tecb-Nee Publications bere.Autbos inpire inaenatin is) and 4 bytes (32 bis) oro ASACHLY SHZUH Vewture
led as the data width 01u
A SACHIN SIzUa Veature
Publications
herr Aou
 Mermo
Digital Logic & COA (MUSem
(10-8)
Digtlal Logeaa :Som. 3-Comp)
is also called as memory bus bandw Memory Oganzaoo
There are other physical types of memanies such aS ugneuA. os Kilo-Byte secc mcaud in
AS Mtga-BytevSecond memory spaxe or uie nenram papa
Access/ Recording type (ex. Hard disks_orp
Cost is the comuner ned by markes
fortes (MBS) or uga-byievsecond (GB). evSecond aeared ams
Access'Recording type (ex. CD, DVD, Blu-Ray Dsks) It comes inio pretuew ing the me
exam CUTentty acuve on the system are far grater han the
0Volatility mplemenanon ur o easibility. The
Co i Performnce easurement
meAsu
t s the characteristics that ideotifies the capacity o ic, Costbit or Cost/MB (Meoa.D 10.6.1
e)o E access o phyca ney
heny to retain or hold its data contents when the power to CesGB iga-byle). paricular ype of DEAM memory device
i Btven
ea
emones
on. BASd on this parainees we Cosulier is he meioY
"ny
rore difficul
necded to
x32 Bit It has access ume ar 100 ne
upeormaac
pmgrammers nie pograms »ith all ddress refertoces
adresses and herefon. er progr* o
implementecoou of 25 ns. Deiemne of the this memory gOcal
Voatile : The memory that loses its dals conients o s
locations (or not able to retain) is callod as Yolatule Memory.
Cosen
ffordable
pu in whic
o and cosl-ertecuve
memory is installe toe
ice on the basis of Pertarmance metrics or parametens, ayces
w
or coerol over the
hEr Pprogram woudeloaed
pbya ass
M
vareties a
found to be Soln
il ie ealled
as Non-Volatile computer systems while Flash
mem
Performance metics of parelers for theis oemory a
programwould be fited in the phyacal meuxy pae
as
Aemnory
sed for extemal dnves along-wiuh the Hard disks
menones have lowr
id follows: ahe locbon m pycal
eut ie
In case of Non-volatile memories, data can be retained ot a secondary stonge oIes a
Memory Access 1ime : l00 ns (as per he gven data) ESs.
**ne amouint time prupery
is oo- Memory Cyce Tune s
Memory Access time ny g pli00 pgrans
Demonies is called as Data Retainance. For example additional time needed betwen algorithm, the pbysucal memcery space thai would be aleeaied
ERON B saud o have Data Ketainance ot 10 y eniormance
pgran 1s
**
(g)Wriable and Write Cycle Sustenanee The performance ot te Memoy delenioes ts usage in the

Not all memory technologies allow WTiimg Dala to the

system he peno
for u eir perfo anson of
This means uie Meoy yce can tasiest be completed in The Os kemel then loads the progrm m he
EOa the

D Onng
herelor.Non-volatile
daa miupic
memones,
usUSuallyKOMs e
basis of follaowing Perfomance paramelers. 125
B)
Peak Data Transfer Rate Memory Word size x (UMemory
would be loaded
Addres.
in physucal address space is aled s UE

classifed baxed on whether they are wniable or not. they at C. Performance Parameters Oycle tims

owocreEpy es
end
E e that they he pertonnance or e memoy systetn IS Oetemined using
4Bytes (32 BIs)

Cycle 1ime)
x(NMemory
suect to tbe basc ddres, Pg
hoen
can sustain This property is called as Wnie Cycle Uhree paurnee
4Byes x(WI3as)
Usnance. or Example,
ROs can DewE D Memor CEESS
cess or
BM
ow, many progrins having theu memry uiemests
s
x
DuewneeAN Fiash KOM can be writien l00,000 ames. Semiconduct Ype menes, aen oy memoy 4Bytes

h) Performance Parameters
ocopee E pcu uwne operauon trom the

meihory pae aoieu o paegra

lower is the memory access time, faster the memory 10.7 VIRTUAL MEMORY wns and applicabons
These cnarcu d eaue esponse an0 15 a oesiraDe Teature. 95
is
mcasured in iernsDt - m code and data s koade inlo a
These parameters are discussed in detail, in the pext aPprop.ale unit ot ume sucn as Nucro-ecmas ius) or Nano- UQ. 10.7.1 what is virtual memory? very bits ncmory pace virtaaly and conpleicu aNincicu
Seconds (ns ey space, called as the Virtual
sectuon 10..
MU-O.1d, May 14.4 Marks. a. 1d1 Dec. 15
y
Memory cyele time : lt 15 defined only tor Random Acces
ost

10.6
.
r's a commercial characteristic of the memory and

discussed in detaul, in ue nekt NEn

MEMORY CoST AND

us apect isay
any)
memory under consideration. It is usually the sum af the
access time ot the memary and the addiuonal tume reure
berore the seccnd access cun comene
measured in terms of appropriate unit of time such as Mico
Q. 10.72

0.7s
Explain Virtual Mamarg

EXplain
to
AMU- O. 1al. May 17.5

irtual aory
memory Nerdng
Marks

wit rG
Virtual

kresaing e y
utual ue
L
aoars
he ogcal lartss

*
whch wr
id
programs and daa

he
s whcre the prograia or daa
Adlrtss.
use tor

base address or
na
ne
Module
5

conds (gs) r Nano-Seconds (ns). S01.Dec. 14. 10arks

PERFORMANCE loaed ia the phynical me
ansier rate 15 detined as the maxi U0,
MEASUREMENT
It is dependent on both the Memory Cycle time and the Wand 10.7.1 Virtual Memory: Concep
The memory selection is caried out on the basis ol memory base
Sze of Uhe memory. Feak dala irasier ac e can be compuie syslem evuidk
e ulta-tasking mulüuser nanagee
charactenstiCs. he domunant detemunung lactos In determinin8
rogrums nun a the sae vinualMemoiy
the feasiblty or ue memay ppe 2 Peak Dala Transfer Rate = Memory Word size rside in
the
system main memory and
tms ae sored The alkxabce an ngcoerung ues ang e
anu
factor) x (IMemory Cycie ume) physical memory allocauoa oe programs.
physical memory pr by
giea ind E
rammer
s abstracted from the prog ASACHIY SKUI Venture

Teeh-Nea Publications.-*ae Authars snpure tnawatun

A SACHIN SMUW Veature
eo Fublicalions -hee u
 ..
R DigtaLic &
coA (OSeSp
Advantageo oegentation
int the phy sical aldrses (for all memory ceses of the a10.7.3 Segmentation fre fres out of the five to prceu A hs
TNaMgas an
Memey Niamajenend.
or the dntal in aled s vlrtua --.-- gneutatwn n e mone stnactuned

Ua.10.7.S VBeno EAtIOn in

al kdrrsss
spe ed in dfkeou MIner i Th
Explainhow address
10.7.2 Virtual to Physlcal Address atieon allows the uer program to e abstrcted frt Man Menory Man M
trans lation* Pnos* n
irtual hehysical whih y. this makes the
Translation : Address Translation mermory
prgras a" * a any deired
Mechanism ewy
MU-O. ue y s space. Pg T

46. Dec. 10, 10 Marks oint

segmentaln w

:* Eplan 4ta irual meMOry

u 10.7.4 What is Segmentation y
U

-
Smale
54antationand pagig A-0.10.May174Mara e nhby sical memory space.
Segnentation is a virtal memury managemient toctnique
NDRAA: i The points, above naNe
ing ah ulbuer
F
ynage nemt s nvesay for the OS kemel to
whuct hc me u
The agical alkxation s pertord on the busis on
logically.
contral
eined
5
cnvinmment wi
Segnentatu paovus o
c grenl
tul cotTTA of
easible.
memry
24

N Cer o of program code and data.

pg e a Su data, stack
alaln a manage en.. ao allows OSo corirel

DAtfeent tchimques
cess o ia memm
itual
merteyhanageme Such allated memory blocks are called s egments to ams te m

s u two comonents
Segins
y
e 0 vanaee
e neeeu to contan.
g
on de progran code
allcate
inalverte ntly
te another prmgrait, eiter alveriemly or

Indea pounts to the have address of the allocaiel memory

*Segment address ransiation
Page Piacement and
ig. 1073:hgng ndhg nme Alaiam
10.7.4 Paging,
n is done uhrugh
sualy ydhe e ur prugTn yxulis ne artual aldress tie form of
in Page Address
0Skecpng rikk ol all base adlieswes of the loaled niemy
Oocns naniy ne egment ndex or lDD und an
LOcaton 1t o--** e
*gmt auge as descnhed in latet setins) ue ounpuier sysieth uuaily:Q 10.7.7 Bplan t pag arss a*
he main neeory' avalahie ih
a segmem lae
axkdel to it to generate the physical addres Tis pmwo
o
calicu asaddres tanslation. Fig 10.7.1 shows the Virtual the
lusdod serments "eses prograns.
e uh cas, te semory ********
e divded ad u gnga
E Te, ne nakt provwded in the virfual address, seleets ams needs to
tress urthe
Vetual A

e*gnens is
se aldress
in he
obtained.
segmient tabie and the egnent divided to ensure that simultanevus urlel Lsks cah a
#teren
onset traaabua The pagg a can
index Then to this egment buse Aess, cs a
ertomed y
ea
the offset provided in tiee

Teuting these
uhe
dov iskns with
a fhved
*srecan
can kal
lo wase ofmcham a
(Adrs) This address
points to the aut ing unequal div single Level Paging
Segmient that is being aoessed. Fig. 10.7.2 shows the
ney s actss kcatioes since u
ldresses won't be detenminsuc the F

rual Ace er lo avoid these isues, * omy Vivak Aaesa

Physical Address Segment ld ofset Pg n of rraessprogrwn

lodule
PEtomd. g
fuod ire called s ra
or data into much su
Fig. 10.7.1: Virtual to Physical Address Transatlon tino euual sred chu
or Franaes 1he pagr*
e
i
There are two virtual mem
ely.
becks
pplcallon.
menwy

iom
uch

management
The allkocatioe can
as the
Sucn
akaD
mgram

iechnuque
s caied
can be caried cut by physa
ce
Cam

callel as
is
or data of a specifie
asa *Emei,
virtual
Ald

Memory
ihe
gmen

(SBA)
- Physical
page frames. This envures un
the vnly fraie that wi
CTy
nn require cae
Fig 10.7.
ng

s
last pu

nle of paging
ess
kxatioms
N
a
d will be th
that let page des

o fised
Page
urTual as ell as the physical memary space is
divided into egment
BA
puge 0, 1, 2 and The . e s franes buve
n sie
e
tTY DNAS
aesPpages nd he itua
can
al e allbcaied. They are
nemay managenent
ual suthliv Iswis s hae
S
free frank

S4CHIN
techaique Is callkd as pagng Ng. 10.72 t Segment Addrss SHH eeter
Tnna
Ceupies. when pmaess
Teeh-Neo Publicatioas-Wberr Autbes inpur a tine
an yer
inan al

-ASIN SIHAN Veature

Publieatioas
-Neo
 -Som.3Co
Digital Logic & COA (MU-Sem. 3-Comp)
(10-12) Mend Dg
zeon
Therefore, as a
e uN mechanism

Pr
eable
dss s having wo components, an index to the
and an offset within the page frame. The table 10.7.5 Page Fauts, TLB In Address
hle to hande e
ads te desired paprs
,the word is ransfemed from cache 1o CPU.

E su to select an enuy onc oul o une enunes ransato n, cE cdle is takea from man meno wi
llows the programs havine and
epae abic.

gne
Page tahie

n
slores o ennes, cs
number

uhc physical memory space.

The virtua memoy spae
to ied Sane sizePages uirements to share the physical memory
sn
eisiciendy
memoey
nfece e o ne
and the phyical u7 P** lo mutualy excusively. rom sane oemory bkck is more.
t is called as
sized Page
fixedM
nd E
Base Address (PFBA) 0cE diagrm of Read Operation shown in
*ne MEMORY is

pe cnuy seleeied by he iboex and 1 prov1des e age muh biegcr in

r ofaspages in virtu the
number compared to pae ar 10.8 CACHE
CONCEPTS AND NEED
ne bae
e onset sadea o e frames in he physical memory space and therefoe.

p
Address

CO
lo generale
Or data 15
he Physical
accessed
address where few pages can be accommodalica in the available page frame
in the physical memory space.
. 10.8. at
e. the ecessrty *-**.
what tache ic E of
ds
wo-Level Pging Tberefore, wo issues are coatronted in loading and unloading
"
pang ysen, ue ge address tansuabod
e Ould
be loaded in he page 1Fames . *
y 10,3 Marks
med oul as shown in the Fig. 107.5.
physical me mory space, ie. Page Allocation.
ia the rocessnr or
r d r es o be

Dimdov d ns, al 1ndex me memoy lires ar hlcs then

he Page
PSo e or unleaded when a he
w e puge irame. The Directory index new page s De
is used to selec need laaded and there is no page ccessed from the main memory. I s aho copied ino the
rame empy in ue pinysicau menmory space. ie. Page Ls or blocEs
"
O E Cnes stored in the page directory cache memory in e or sa Felch word ro
Virual A0dress Therefore, some memany auess cuners at avilabe in be U
Dir Ioexable hoex se *Page Fauits cache ney es r oioCAS Ut O the total largF anoust o

contenis a
When the Proceisor or CPu demands an element of program e Dis e ONE
code or
daa and 1t s cunenuy dalaDIe n he pages basic operating principle ot cacbe meino sysir

PoE PrE
transtion ng the
cache pnngies caln e r ubales nemory s
PTBA-O PFBA process of page
ACepluon is caled
address
as Page Faull
10.9 CACHE MEMORY
he rage
PRINCIPLES / PRINCIPLES
rut ne
PTBA y Fcesr
nacales
ar LFo
at
curentiy
daa or

not avaiaDie
code elemen neede
ue OF LOCALITT
memory ocaica is returned to the
C.u
Page b in pnysica
DUEcOy nouer words, the page containi Si
*
g 10.7.5 Two Level agg
i in the physical memory space. The nane
n order to increase computaional sped,
time of Main Memory (MM) sbould be E
e . Dur g
is adres is laded into Cathe
Niemy.
the memoy

reS
ne vanualnemory space memory increases Ue cosOr uE
locazion
age (wluch is on the secondary memory peed
irtely siores Dunbcr or enirnes, cach ponung o te
Seture.
Pe ae
pysea eKy pace. it
5 caled as Pg*
as Hard disk)
EnCe, a oore economacal soubon s o cu Fg 1095 hows the Cxe and Main Metbry

speca memory cro

tr orovides rhe
PDEL l contains the Page Table Base
uy ecied by cemed
el paging the pge fault
nes
E
is generatod wile
indicating that lo pon
in betwee
into
B
this small
igh-speed
and it concemes Lhih speed mencory is cau Lwords)
tOr Acceing the selected page table. In Two-level paging. he page fa while memory. The Fig. 10.9.1 idustrales e sn Module_
ne ne aex s ued to elect n enty one ESng Uner tie Page Direciory Enury (PDE) or wi rs) 5
out
of the
ennes eOreu in page tahie. Page tabie slores number of
the xcessng age 1able Enuy (PTE). I1 andicates that eitnet
Entries, cach poinung to the page frame in the physical conceea Fuge tabie or the concened Page is Do avaa Main
Cache Menony
onains the Page Frame Base
Address (IEL (PHRA y Fault is
y pace.
page faade h away similar
nE pape entry seilected by the index and it provides the Page an lntemupt. The
&109.Ceche Niemog -1 word)n

Framc Hae Address. Then Uie ftset is adoca to Uhe Page

rame Base Address 10 gcnerale he Poysica aaress where s mec harnism of loading the pages in he puge
frames
A biock of Main Memory 5
aslered is
wite
slow ss nemery
y
rs
pryrm code or dala is accessed. Page Direcilory POysical memory pace when he page o ns mcmony aite high. Whereas.
a sery be wngis 0Ln uieib*
age, the Page conlains al the offvet, the roied frnd i
payica
rgam codeldata reference and it
memory space;
s
as Dermand
is
transferred from cache to CPO ortion of uin arth () Tu (T)
prograrm dala or code at the compuled Physical address. Paglog
is called
" e when ne cat
a sord from
*

echeck
ry p
is maidc to dre
ie whecher the wo 1SICH.SHuH leature

Treh-Neo Pablications Vhere duthon íapire inaoratioo

MSACHIN SHUI Vetu ed-Neo Pulblieation. bere tD
 igital Logic a
Digital Logic & COA (MU-Sem
3em. 3-Comy
(10-14) Son Cnall amount o aDOUt
1 of the tots Memory Orgjanezauo

For Main Memory. assurning 'a' number of addressing lines, Therefore,h le mentauon *** "" y populated
m
N,N =1-m
as
ct Lne Sue
unerent memary iocabons avalabie.
De tnory kOcaUOn can store a woru or ieng c Loo up penally is defined as the time reo
quired for
nemoiy.
Techniques
As stated
is
eax
sually by
bre h Popuiated byie by byie but it

Memony. a block of "L word size is transfered. The data the cache controlier ogC o acenan the cache mem Pping s well as mloading (writing back) is always

lone
with .T
pau n uhe Cche memoy
The rule Uha

y
c n or block
in te
and at what block position inf he
Cacbe
locaion of main memory. Hence, the length of each line of
H 10.11 ELEMENTS OF CACHE oacbe hne specifies tha oe
data umib, ie. Byles ar Words. Thee
mem Wmany
E LEngth ot 1ag (T) * Word Length (W). DESIGN ralled as the Mapping Function of the Cacte
O10.9.1 Write short note on Principle of
UQ. 10.111
--
What are the atures af
of the Cache memones are mapped asing eithe
fost
Associali we 0r aye ASsociative (where k can be a
SDarial
a e yiem m enplovong he

ocality of refertnca y Namber of Cachbes

memory design? power of 2) 0r uaey e Et Enapped

----Princdples
.@, May 18 10 Marks
o loeality: Cache memones are sUKCESSsTul duE 0 .
MU-O. 3a),May
5a)
May16.10
15arks 4 Repiacement Algorithm D 00 the sysiem conhgurnbon,opy
owing two principles of locality of reference. specifying be acbe
UQ. 10.132 What are tiemeEns or cache
Replacene Agonn ne or bloc mplemented in the sysierm
pe of Spatial ocality : This principle state that if the design? that wou n whea he dEVes o ae
eres e
---
Explain in detail. cutet
then there isa very high probability that the ng function) to load a new block or line in to
the
xe their coafígurations.
to a ncarby address in space, in the near
y 14,8 Marks
LrEercnce The processor or CPU generates akdress for access to the
nory and TEpiacemeutnecessary s cuTenty te Address
Tuture specitiedcaMcne 1s u en,
Ue eplacement in such case is u..1 Cache
e already in
(u)rncpie or Temporal Localty : his principe staie that
he proces5or or ro s reierencing a parucur
memory then there is a very high probability that the ess e
nne
f
accessed from the main memory, it is also copied into
Cacne nemoNy in one or 1ts cache lines or blocks. Various
caried out as per tne eparenet agnn
Most commony use Tepiacement agorithms
(LeASt Ceuy useoy 0r FiO (Fist la First Out)
LRU
- Addressing/Pos tioning of the Cache Memory
Virtual Memory is the iem ued o
rom

e woud relerence the same address location Tatos coe mo pa Poes anng Ue
5. Write Policy memery
actually available. This copcept o Virtaal
eu0
Cache memory. Tbe Cace memory organiza0on Tactors are
Write pobcy determines the bebaviour of
Cache Memory and is used in almost all oo-embedded appbcanos
0
10.10 CACHE MEMORY
important in the design

Few basic design elements

ot Cache
whch
memory syste ms.
are considered to classuly cons by the Cache system in case of te ucos. orr plemeirta
TERMINOLOGY
PERFORMANCE METRICS
and dierenbale dullercnt cache architecture are as follows:
or or CPU Write cycles. When the processor or
performsa Write cycle, there 15 aways ca c
r In order
nest Ueit (MMU) s
ual physical

eui
memory wouid en coL
AND IMPROVEMENTs
integrity as The Cache and Main
e wo ways in which Cache Addresimg
can ae
Cace Size
ifferent dala. place in order to implemest the
coocept af vurual
pPping 1cchniques pouaes ae lormed and 1ouwa
ssue,
wih respect to cache memories, following teminology is
Neplacement Algonthm
oesolve s Write using MMU.
CP and MMU
used: most or he cases, WI (Wnte Throgh) * w5
ed by the By eoenec my m between

e Policy Back) are the two write policaies

nat ae roud
o Cache hit : The processor or CPU demands an address . Cache coberency Cache sy n thus casc, the CHO treses the Cxbe Memory directy
NNU by geeraing Virtaa Ad
and the address is found in one of the cache lines or
biockS. 1hs event is calcd as ue e Lne 6. Cache cohereney
without
s e Memory is si
inl ache
o
ne miss ne processor or CPO demands an address wnen a specific element is
cached m te caxie ddress, bence cache
memory Is aso caa

ess uo Tu O0e 0r une cane ines or

blocks. This event is called as the cache miss.
Cache Addresses here exist two copies of the informabog.
maun ne
t
or irtual e
The addresses of the cache meoy ocation and second one in its parent
Hit Ratio (h): n is the ratio ofaceesses made by hy hiock or
or u ue po* MMU
Copying in to the faster memory) is done blork CAchea location gets modiheu
processor or CPU to the cache memory to he total o
line by line. Ik is called as ecache bloek or cache line. performs wnte opera0n can get
emory and etenl
Cache mem
he addresses in the main memory that are to be cached or On the other hand, main
to syslem bus ase
u the DMA conrolkr or

Let, N, be the number of accesses to cache memory and N, be

e eEses 0 main memory the hit ratio is defined as,
nat are cached, termed as cache addresses. These addresses
epCacie
rack of what part of main memory is actually Iying 1a
ue
yOuner bus masier. coatauns of cete
Uhe
the
E When such events occu,I, on would be ditet Data Bus
N,+N 2 Cache Size sparent maun
incoherent. Such sit
c i desirgble
et
Mis Ratio (m) : t is the ratio of accesses made by d maintain
tDE
iv and

processor or CPU to the main memory to the total e

suZe ot the Cache memory. Generally, cace
memones occupy higher
must always De co
of lechni
maintaln the ai
number of accesses made to the maun memory and
e. their packine cOgtents SHAB Veature
cache memory together. g Implementations ofC
p s low) and therefore,
ial ys are called as
cacbe .berec
coak
SACHEY

e memoy e noe pae nemor

Tech-Nee Publications Wbere Aothors iaspire innovation

d-Neo Publieations berAU
SACMLN SHN e
 By connecting8 Memory in berween MMU and A. Diret sappg
Physical Memory as showa in Fig. 10.12 This is the plest ye ot mapping function. As
sho
n this ase, cacbe memory s connected in berween Fig 10.11.3, this techique
tmaps each block of mainmo enoryA
Address
temoy. Hence, te meogy inlo only one possibe cacne he. g Une Wond
Main memO
e more a T 1iee the
ayical addeez, the cache mernory can be accesseod.

D bs d
ddress
MMU

Tmatch
Ceche

Pg. 1a112 : Physical eache

u
ho me
Hh
First m blocks
à 10.11.2 Cache Sz
discussed n section 106, if the size of cache memory g 1011i Direet iapped Cache Memory match
The mapping function for direct
mupping Can be givenas
ame increa
reduciog the sed of t i jmodulo m Ass n caa
sae trade-of berwsen smed
ue othor factos while n
Where, i cache line number
Pg. 10.114: Diret mapplog cacbe
organaton
nain iemory block number
ees, thenumber of transistors
nnumber of lines in the cache FAdvantages or direct mapping9
gue cabe also ICTEAeS, increasing the complexity Hg 10.113 shows bow thirt n biocAs Ot main memory are
e inhung and low memory ocCupancy. he nat rad

ae ppeu into o Simple to impiemen

This
making the cacbe
*S ited
meme

by the size
speod ol

of available o
memo Tess
or
bence
ache
ihe memory contains m different
cache
contains b t bs. he main memory
lines, and each liae
can be sepanted into
ess cne ne.
anount o0f tag memory to be implemented per
ample
GQ 10114 Draw
of direct mapped
ore
cache
oard. duect blocks of length m. I equires Oniy one companson to delermine wbether the
a 10.11.3 Cache Mapping cache is a hat or a miss. 1herefore, look up penaty
S

Techniques kbation of mapping between e is low. cacW pechcations

UQ. 10.31 Eplain eo
asoctiVecache
*
13, ie B,
mem
n cache as sh
he Disadvantages of direct mapping bytes cacha a or 8lock. 32 KB
tecniques aPping dngets mapped with L
Thrashing : any given block,
cacha amorg 20 Bit Addresses
U-o.6al. Dec. 15,5 MarksEor accessing cache helds, refer t proeesor
cach main memoty
auo efers ted
e
*

Mapping functlon or mapping

nlo
achines. theeast
different fields. In
most of ent existing block from cache has to be thrasbed every direct mapped cache, the cacbe
geant ume. by same nuTnbered block
pae techniques bytes represent addresses. OpuareuuEpopuialed of any tag
pones aihca che memory may not be ful 00C n etnory
byte within block of main Ochuty a unique word or
Ihe cacbe memory iemory.
ey. ue
cees s emony ines
an ma
The remajaina
Dee naney baxis ae bcied lo be
Cache logic ideahi
ide DockS of main memory. The odule
he * uese 01s as lags ot s -r bits NOTES
Aba. an Tr
brts. and line o
will occupy lines in cac deckde which memory Addiress lkngth
c ofganuzaon block (6+ w) bits
s decided by the type of cache
Demory Number of sddressable
of mapping function units = 2
implemenied. words or byies
SRe E
ine size = 2 words or
tct
B.
mapping
AssoCative maPping
Numberofblocks in
main memory-
bys

L
(fully asociative
mapping) Number of lines -2
essocaile mapping in cache = m=?
ecb-Neo Publirationa
e of cache 2fr
words or
ere Aatherspr anovatis Size of tag
-r) bits
bytes

S4CHLY SHUH Ventaore

e Neo inonaie
ASACHIN SHAH Ventare
ablieations ere Aotbor gwire
 d Logic& AMU-Sem 3-Come)
Dtal Logic& COA (MU-Sem. 5com (10-18) anizat
32kB D Memory Organlzaton
TagzosMain men
h 16 Btes BioCK Z047
Memory Address
Tag kain men
Eeck 0

BiOCk 2U
16 BytesBlock 2
16 ByesBlock 1
ByesBlock
16
2047
AOOres T matcn
1 14 3
rno match Ceche

g 10.1S: Direct MapPped Cache-Example

B. Associative Mapping (or Fully Cche
Assocative2 cache memory 3 usualyruuy
occuped as the first
match
apping) replacement occurs onily wbEn all cacbe blocks are full.
MIss
O' f no match
n cacre
ihe dsadvantage of direct mapping Due to very hugh occupancy and no uhrashing, this mapping
ovEreome Dy
ASsocLatve Mapping. As5ocai ve MaPpng gue
ows cen has hughest ht ratio FHg 10.116: Fuly asociatve ache orpanizaten
block to be moved into any lioe
of cahe
meiay
control block takes memony kress Disadvantages of fully associative mapping Main emoy
as Gache
combiaation of Tag and Word field.
Uysouve mappling 50CKM 16 BytesBiock 204AT
technique requires more amount of
g 1s ued to etchusively identity a block of
main memor g ery lo e impicmenled
cou ge gocs trough lags of cach line to fnd
out2 t requirtsn companisons where n is
number of cache blocks
whether a block is present in cache memory
or not. in the cache memory. 1herefore,
look up penalty is hugn.
As hown in the Hg 1011.6, the line number is not
orermined by any hekd in the addres. Example of fully associative cache
Adiess Lengh (4*w) bts
Draw BIo
Number ot addressable uaits .5 organization of hdly
=
2words or bytes Block 1
Associative cache with speciications Modale
Block size Byte Cc
Namber of blocks in main
lipe sizE onds
r ys 16 Bytes/cache line or block, 32 R5
16
5
memory2 cache memOry. 20 Bit Address 6
Number of lines in cache = processor.
undetermined
9 the Block 2 Wond
Size of tag sbits Ta
n Tuly asocialijve cache, any block in cache can
Block 1 -4B
Advantages of fully associatye mapping Populaicvae-ppulated by any block in the muin menoy
Block 0
L. Many cacbe block can be occupied
dhrshng never oce
from any memory blkock,
Fuly Amocade
Cce Sapp-p
Hg 10.11.7:

SMUA Vonture
1SORIY

ASACHIY SHM Veatere

D-Nee Publicationa Dere a
 aDigital Logie & COA(MU.Sem. S-compl 020)
weo anizaton
mole of 2-way Set Bssoclative cache
-....
c Set-Associative Mapping The cacbe control iog eory akress
0.11-7 Draw ogAOR Oof
2-way set associati -
wrEN Spcficationg 16 Bytes/cacha lind
0 10.116 Bplain set associative cac
--*
three fheids

Henebit
will
be
snerified h
any.
i or Biock o
****************
cRche (16 KB/way), 20
. Bit . ENerdta
of the Tag and Set field is used to select
by
tPceso.....
mapping the 2 blocks of main euny Main miemoy
ress****
e-associative
MU-0. 4a). Dec. 175 Marks mapping. tne tag im a elnoy 1s smalkr.
Tag z0nes ey eassoaatve
bits
Addres lunes
(*w Block 1023

Number of addlessabie units 2

set 1023

e
aVemPping.BY
or bodn
doung 0,

direct and aisociai ve mapping are

une
BIE SIZE
os or bytes 5lock 1
Number or Diocks n man neory= 2
For this iechnique, the cache is divided into oumber of sets
Number of lines in set
and cach set consists of number of lines. This can be
Number ot sets
V 2
maihenmabcally representpd as follows
Number of lines in cache m =kv =kx2" Block 023 1

w+k
Size of cache kx2 worusOE Dyies
Suze of tag - s
where, cache set nuaber J= main mey Di Advantage oft set associative mapping
mnumber of lines in cache
Set-asociate mapping is the combination of direct nappns
1023

VDumber af sels as well as associaive mapping. Therefore, it eliminates u

Address
number of lines in each set disadvantages of both the mapping techniques,
pung ln tas Word
tyoe.
block B can e ma FDisadvantage of set associative mapping 6B4**10 BT* BI
referred sn
direct mapped cache is
Nh
lines. The first v lines of main memory are copied
ines
s

of cache memony. The next v lines are further mapped

into
first The only disavantage of tis technique is that t
cmplex lo 1nplement as compared to carlier two methods
is relatively
In
we
2-way set assocLati cache, cach
Fig. 10.11.3:Two-Way Set Asocadve Cacbe Mapping-
set has 2 Blocks (Le. set 0 as
a
Block 0 ia way 0 and Block 0 in way
1
Any (block o) given set

Mapped, Set Assoclative and Fuly Associative

Cache
& 10.11.3(a) comparison of Direct
Memory Mapping
Memoy MAdde
Cache
Man memory Fully
et oc
TagS wo
Bo
ecnnique he look up Penauly s us omparisons(4
1 on
is peeded to high as Ncompus way set associative) and
therefore, look
wbether cache is a hit or miss. rnae cene 1s t OE

enaly s 1
much Ln this tecthnrque, uE e
this technique, tag field is small
e fo it mguires high than fully associanve but biger nan u
In memoygs
leneth and therefore.. s noutal ue
required isess.
remainingChatkes oroE g es enanng enmpy
ag lines
of some LAg iDes
emaunung
Chs r
Chances
Emalch
no Cply are very gn.
enply sioclaae

.
match
in cache
POes ht aion better
ower This echague po g* " mt ap Du er an y
memory
This technique provides rea io cache
aiw
macn Fralo as cuche
memory is

very low.
Chances
1if no match
Fig.10.11.3: K-way set assocatve S4CHY MMAN Veature
cache organization y high
E1Chances of trishung ae
Tech-Nee ublicatioua ere Autbers inpire ianovation
Aothas ny
eeh-Neo Publications bee
 O-Sem.
Digital Logic&COA (MU-Sem. Memony D S 10223
3-Comp) anzae Man Memort Memory Organizabon
15
a 10.11.3(b) Problems based on Cache However, Address field (A) Tag Fiekd () Word
d field
(w) for AssociBtVE LE. Fuy nsoiaueane Mapping.
ppingMann Techniques Therefore, 1ag heid is A-W=5-2=6 Bits,
U
1011.8 Condider a cace MEO The Main menoy wou De mo 4 Blocks
ofve 256
wonds EACh
worns Each block consists oof
block conssts os cacn
each. Any Cache block can e
anae woepopualeo
gao as 4 Blocks of4
ords
4

.
hno any block in the
words Sie of the main memory is Main memo
bytes DraW associative memory.
1011 Abock set asociative tache consists
Pad
wORDsie.
calculate TAG and:Q ot iocS anaea in block sets
MU- blocks, each
12 4096
0. 5B, May 19, 10 Marks. O. 5b locks, each 23 Woras or 16 bit
Dec, 18. 10 Marks length

e50) these eamples ae identical with same

Fiow ang hits are there in
dinMemory address?
ne et o values 2 how Mang. brts are thereinc
Cache meMo9 drEss iFedFekd i Fd
The Data from the example is (tag,
yis15 of
W
and word helds?
EDoY
Words.
cof 10
16 Words -
Each Block is consisting of - .
D S Fig. 10.11.11
The Data from the example is
heretore. the Cache memory organzed
4 Blocks of 4 Words each. Cache Memory is comsisting ot 64 BIOckS divided Misses and e t
ih thus methoa, the upcaie s maie oniy lu
into 4 10.11.3C) Handling cache bexk
axhe menory. There is an akhional rag bet calcus
Tberefore, ord held (w) of the 5ystem Writes
47 Bis in widn
Aain Memory
Therefore,
Assaociati
are, Therefore 64+4= l6Se
Uus Cache Memory 1s

ng
organized as 4-Way Set
4 blocks, These
CPU generaies an adoress wen tines
to wmie some daia
DIRTY b or USE bt
memory, the tag ne bne
. Wen a o replaced he chaages
TagEuAs No. of Sets cinoy. r naemoy olocE containing that
addressis
16. o main memory cnly if the UsE bit *
n cache, it modihes cacie or ce
Therefore, Set Field (S) is of 2 l69 the ine is set Also, if LO es cess
4 Bits in width
s first brought into c
A data
ache
wor ha
first the USE bit of the coTEspondhng
No. of ahe
Ways4 (No. of Blocks in cach set4 needs to be updaled

No. of Words/Block = 128 and each word is of 16 Bits

memory
eu s any other VO device might need
memory will
eed
ie.2 Bytes If at least one memory wrnte operaon
memony sxu
5 en used else he prevus ey
Therefore, Each Block is consisting of 128 x
2= 256 Bytes on a word hne of cache, the main be
ry
Therefore, Word ficld (W) of the system is of wn ie updated data before bnnging in
*w biock o main drawbuck ow This increases the
u
Bits in width.
hApes
wiv a0d reults into bolesieck
Toal Main memory
2256>8 DEre are two main Situations ieeuco
circuil compies
adresability is
FUst, one io device along wiun ro nas Replaacement Algorinm
U96 X 128
x2 Byes 1048576 Bytes =2
= ache, then
the
10.11.4
bas to be Modale
Bck elore, Tta Main Memory Address Field is
20 Bils (3)
nepoidung meioy *
d O, if vo drve
is mv
n order lo briag
new back unto
ble in cache
memory
cate aN there
he cahe tey s n, 5

word Oever, Address field (A) = Tag Field (T)-

Word field (W) for Associative Associatie altered mialn
d in cache
one memory
naa opa Dw
Bock O ie. Fully ace hen
n 00e ne block of Caxfe tosy
Address Fw Mapping attached to a sane
multiple orocessors ossib
Therefore, 1ag Field (1) is
w =A- (S+W) = 20-(4+8)=8 Bits processor has its own local cace
to aouHESS Ue aoE partcula
-.(4) nere are two techniques ncs ae possible fur any
bx

.
Hence, the uns wer a
Fleid problem. slocithem neeed for erficieat
2 Bit
un Mem0ry Address is of 20 Bits-
As per calculations in
L.Write Through : This s . h Cache
is
impkemented in hard ae
ust be useu gns E A s
this technique a wriie opr
ahe and main
four of
aos ommony
Fig. 0.11.10
Field and 8ss Ou
Lontans 8
edAS
Bils Tag Field, 4 Bits Set
per the
and main memory
sunng
hmniged, There is a

L Lest R
RO)
eram conLained in main memory
is more

Calculations in k c effecbe
The Main memory is of 236 Bytes -1olal
Address field (A) 2) and (4) above. memory are bon Thi, technique i istutions or kops. **
conc
S or 8 Bits. The Fig. 10.11.1| shows disadvantage of thus e fic resulring
organization of sach cacthe memoy ASACHIYSMUI Venture
ech-Neo amount ot meN
Tech-Neo Publieations here Autbos inspere iaooration
- S4CHIYSMAH Veature
OLuenec
ec-Neo Publieations bere
-
A
e oorai
 Digtal Digit
&COA MU.Sem.;
Logic & COA (MUSem 3-Comp)
(10-24) Meio oanizabio
SugESest, this algonthm replaces the block which is not CPU
used rec
increases. i he SkAMs gn such that it can
sLaie, ne enormance
by CPU. In order implcment thi si oode nuch of Register alty efen to the tendency of the processor
rd ne e
em wil not des te
Fil
n n cache
memory is added with a flag bit. This
system designs do not use system bus for cently. Iemivn wCh were cceRsed veiy
it 15 Called
USE bt. any olUhe ane troa
If Dio berween CPU and L2 caches. Imstead they
dala transfer
Microprocess
ndtionaly. eumpe
dee ncenthy ot tempor
y CPU, the UsE bit sed data and instruc
hlock of all the lanes om a oN data traser. s reuces burden on system rie bus
bus
cachey innplemented
memory
value of USE bit, w
find out which block is

wtose value of USE bit

va 8Onsity
processor components, ne a NIE Ae
and shrinkape o
"
included on-chip One Level Cache
iehng echanis.
by using large cacthe
sim

CA is 0, gets r
mproving performance.
: L esy to npiement
for a tully
"
nue of fwo- kvd Memory
associati'vw
e. LRO B e moNt POpular
alEonm &s nned caches mcans tri
onal wo Level Cache

N
ts

Algonthms
ie sinpiest

are:
algornthm to implement.
cache memory. Nowadays, there an oe in single
Fig 10.11.12: One and Two level Cacbe
bcaliy
ger ng
property can be sed ia te formaton o
evel memory (L) be refermod
Ga and instnuctions. This dedicatod d
rst n Flrst Out (PIPO): This algorithm replaces e
0
Dedicarcd instniction cacne eoy
snal size, fster txecubn and cosuy. Ao
bouh act as level 1 eache
Performance Characteristies of Two Level Cache e the lower level 1)
time
Thie aene memory for ne
longest When processor tnies to retch inStrc hon ThOm memory,
LI Locality and Operatlon EXCUlon
menery having
ad less conuty as compared. M1 is used to
b
s implcmented as Round Robin instruction cache is referred finL And when processor
technique. E tries purtialy and tempor
3.Least Frrqueatly Used (LFU) : This algorithm u l d caene referred fir
IS
Lecality Whenever a e
yse te contcmts of menory M2
is o ni acbe system are as folkows Es mae. n iemgt s made to fiad that
E L. L2 cache memory

.
Ogram contained in the eference
non
As data an LIMemand e Miisbe ea avalable, can be
ie hit rati ik
Ouns n0n epeabvE, quedal evee twn
et or Oons. incTEases. This is because. if memony and the CPU forming a cesed quickly. It
places ue DNOCK roih cacne which as of data fetch, the Carhe ES nemory. This cwo-ieve achtecture uses the pr
ewer references. number
upatco wh more dala from main memory andi locality known as ocaluly or relerenee, to improve
Ted
hoe a block is
from M2 to MI aend then daa

4. its moved in M1. due to locality, there will be

doml nane suggests, Execuuon pallem performance over one evel cacbe. Locality
andom

esnew line from main mema

and strucoons 1elcn, he
volvesa
cae
memory.
wn
Eearer numiber of
8et upated wIn nore onks on ue pncpie a he memory referace es hich msults ia siet
hat ill
caecuo
happen in MI for dhat bloc

an clusier. When memores tor a long peniod of time,

simuialed resuls snowing random
thod beingsliphtly 2.
" e design.
cessed
Rs the ht raie for MI thea (1 -H) will be tde hit rate for
he ci
tend be cioseranaered
nreror oener atbove-mienuoDed methods.
The main advanfsn vtead
to uhe
CPscd usually e tmes for memores MI and
e ystem are as fol Ee accesS

e
a 10.11.5 Number of Caches aThe conlention a cluster. M2 mspeci'vely. Then the avenge access time, Ts can
and execution unit is eliminated
Occode unit
The principle of localhty 1s based on the following
iniualy, 5yiem designing was done using singie cache b.This he lps in the design where ppelining of instruction observadions TsHxTI+(1-H)x(TI T2)
KECenuy. due o aovancement n designing ana
tncte 1 Except the branching and intemupt iastructioes, most of Hrl+1+12-RTl -Hi2
anes n 5ysiem den nas E combinauon or unitied and split cacbe is
ue nstrucuons
D ie e *Htl-R)xz
Le. Multilevel caches and
nee
c1 egnng the syste mpiemented ih curtett 5ysiens. ne spint cces ae Sequne ene usuly. e ext mstructan D be t an be observod that for a high percenage of hit, the tal
d implemented as levelI cache
and unified cache are executed follows immediately ater the ome last felched.
Cacbes : The increasc in lnoia is mach closer to Ti than T:
evel ory,
This
A. eehed as level 2 cache. tis very uncommon to have continuous uDction Calls
corss time

One Level
ess ulizauon of sy'stcm
vanages uke taster dala uranster rate, Cache me
and Two Levelacne
USed for temporary
an retus. insi
ea
exteral s bus. wneneveta storage by the processor
proces
S
spans before memory fetches return to he
ma o evauale the performae or e o
e ca co K
equest is made by CPU, 1t 1s 1ound n e o-cnip
*
All the uctive data, information, ow. abo importan permnee. Lt e the avernge coNt per Module
available for other transfer Hence the bus is
y slornge. Mostly the processors reuiring small Looping functions Us ave mber bit is

ysiem s performance. ns ncteaEs OvErall o

esset
uieircomplexity use LI cache. LI cache is
3.
ucuons rEpeaied seveul nuzber
imes
orunet. This bo bar
bt ir i &MI
g
ad NM: Ggrtr,

AlOng with
oo-chip
Du in Emporay TasL, COse iemory present ou e ntineent 0 menoySS
cache, most contemporary desigr
EOprocessor chip itself.
includes otf-chip erlemal cache. 1his olf-chip
s also called as Level 2 (2) cacoe, LEve
external cache s s called s ue one level cacthe, data e the avere coper bit for C
Stnce oniy one 9pe n some cases, compu
This
chip cache. There are Some novanages or oE processors tuys,
eads to
S1 be the sie of MI and
meng k.6CE. performing coMnplex tasks rea nvoved.ew ucures ke D
f processor makes a request to memory
locaion which is not
t 1s satisfied by using L2 Cache l
This uccessive nemory ae ity references,
sp
Setese
Then,
nas lo Literature suggests two types or
DRAM and ROM brine
cache, he perforn
e

of system decreases, Instead

be accessed.
aaccessea
Since
ad
cnE Present as an external memory chip but
S

addicssea as ir t were a purt ot internal cax

ral. spatial localhty eiers o
emary locabo0s C
aS13 ad Sl S2, then C5 wuld be equal to C2.
bodh LI and L2 are Cxecule instructions tnvOYg
involved, it is termed as two-Ievel
aof 5 used as L2 cache, the peobability
AM CAche trom clustered. It can also mcan tes
dency to eaecuie
missing nfomaion cane L Tounu
L cache ations. SACHEV.SHAM Venture
BCcSsing sequential duta Kxauo A
Tech-Neo Publicationa ere duthars inpire innoration A S4CHUN SILAH Veoture
dutbors inpire
ublications hee
 COA (MU.Se
Dioptal Logic&COA(MUSem.
3-Comg
Memon
DIa oga ,S0mp)
Using
Using
adc parlely te for the 2 27
10.11.6 Cache Coherency lii) Non-cacheable Memory : In his
approach, if
nemot conecung
ecting the
the remainine of

UQ. 10.1110 Eplain

uQ. 10.1110 Eplai ** O1 neory 1s required by multiple caches
at s
a lock dhe o the memo eice ued in
thasi Eg A
lam considert a two bit
in brief cach cohereny E
ime,
bc P ing or s ng HOl meor) ystem

o TY
w not 2-bit ddrese for a CPU
eDy be shared with any
T

Probe csns. 1hat memory block is the

called as non-cacheal Sch technnique using a0ress
ines n he addrevs
s for HOT 086)
from the MSB side
Such sysieins

MU-O 6b), Dec. 17.1O Marks nenoy. ally for seleeung memoy bus DEryblock is addres (A-A a
10.111 Write short notes on Cache 10.11.7 LIne size
accessing ne emoty block, is Calle ially for ide of the adress h ng 18 bits on
A
Cohereney. nterleaving an metony devices confimdemory edo,be sysiem dvides
he lotal of
MU-0.6b). Dec. 16. 10 Marks Line size isa crical desugn
eieinent Memor System.
te in Interieaved processor d to oy space into
1 MB (1024 KB)
rom ma menouy opied o
when a block of data
cacneE,
CPU
Let or have adress bus
aving Deory blocks of 236 KB
UQ. 10.1L112 Eplain in detais cache equired wru, aaent
along with of K
address lines are numbered ie
consecuive address
rnnge. The blocks
cohertncy wors ae aso noved into
cache, Therelo from 0 led wi de help of decoder asing
1F the lo K-I the HOl address
MU-0. 1C) Dec 14.3 Marks size of block incrcases, the
psiDiuty the next word o A lines be for
used th
A d
A ines,

******* -- -- SS
ined in the same block also increases.
Hence the hit ratio
i
selecton
or addressing each
me es Kj ies for 10.122 Lower Order
ider a system in
their owr
10.11.13.
which
ga
two or more processors, having
single memor ,having
Shown
else two effect
comes i block should increase beyond a imit
er sing
hej lines used forr the
the seleri
s ased on
Memory
Interleaved (LO
ae from the MSH aside or LSB side, ther
1b Fig If block size increases, the
lotal number ot blocks that fit ieto
memory interieaving. Mainly, Higher Order 1n of
f data word in any of
the ci eeases. Each block fet the Lower Onder lnterle

ane block of memory i

memor
e
1) is modified,

plc cache small

overwe
number of blocks results in
ng
Lower Order 1nilerkaved.
nterlaved
LSH
ved o
side are used for
me
ESS
2, 39, that data word in
main Snouy. get Kj ddress lines for memory block
O0her cache
becomes invalid, even if wote through
umpiemented. 1his probiem is policy is
As block s1Ze
incrtases, the distance cutent
requested word increases, hence t s ess
word and
a 10.12.1Igner order Interleaved (HO)
emory
nes romDtA
lermed as Cache Loncreney nkely to be needed akress DeS
In the Higher Order Inteteaved memory system, j address
K-1
eecton.
(A..
Y DeDy biocE

CPU1 CPU2CPUu 10.12 INTERLEAVED MEMORY ines from the MSB Side are used 1or Demory block
selecton, |
leaving the lower KeJ adress unes Tor memary block access.
SYSTEM In this situation, address unes from to Memory Bark
Cache1 Cache 2 K-FIAL+A
Cache
UQ 10.121 Eplain

Techniques.
Mensom
ereavin
MU-O. 10. May 19.5 Marks
ae kept

-
0r u EEDOy oick are
xy
e
accESs and addreSs lines froa
tot emory bilock
kept
nenop mto equal sizd
blocks with eacbh block having the cosccutive xiress range.
adiress rngs
H

eNE Fig 10123 : Lower Order Inierleaved (LOD ienon

UQ. 10.122 Explain the Interleaved memorg Hkj-1
MU-O.26). May 16,10 Marks Blork Selet Memory Block Address
LOl syntem divides be memery u
cach block having the noa-cot
sa o
uQ 10.12.3 Explain various kigh speed memories address in coaecuive blocks ae comecutive but akdree
Plg, 10.11.13: Cache Coberence
Such as interteaved memones HOT Addr. ia the same block are interieaved. Thas nethod is suitable for
Dilferent approaches to prevent cache ana ividng te memary intb meming banks requned to be used
coberency are g. 10.12.1 : Higher Order Interleaved (HOJ Memo
W Bus Wwatching with Wrile Through: In this
case, each. he
**
-
memory addiess space processor
ot
OSQ:Dec 14,10 Marks[
or CP0is very
hus method is suitable for dividing the memory nlo e
memory areas using these HOI memory blocks.
tar byie-aldiressable sysie ms having data bus width of 16 or

64 bis
one-bit Lol memory sysem for a CPU Module
aCOrouer kceps a walch on address bus. If there 512e Or vidualrmnemoy deICes s
ian2e. Eg Lt us comsider a

smaller T s 6,
wnie operaluon performed on main memory block,
by tetauy Dwcoder
having 20 bit aktress bus (such Such sysiens
5
soe cacne, which is also shared wIth
other cache, the partitioned or see emory ddress space 1s
provide oe bit for LOi trom e Ls s
cache conroier will invalidate that entry on main technigues
Oyblocks or units aesseu Dy e retaaing 19 buts on the
memory. The policy has ressing C cd as
penory bank8
to be decided by all cache uboning or Memory Segmentatio higher side af dhe sauirts bus lAA.
controllers in advance. sai or IB (I024 KB)
Aportant herefore, tbe system avides e
I
echnque by which the memory spce can be
ed s Memory Interleaving.
) Haraware ransparency memany banks or Si2 KB
n this case, an exira emory adtress space ino ao
hard ware is Used to update all the caches and main DD IEy nave Don
memory any change appening
mereaving and nter leaved memor L siued calked
as EvEN N
k addiresses in Bank
I

in he snared daa cooc. oem 19/1817 coesecive alidreis

rnge wIn all oud
Dunks ure selected with
Hcnce, any cache in BaE 0. e
il updalcs a word, it is immediately
e cmory ddress spuce is determined by the Mar d l even akrtiwes
updated n main Detmoly. AIso, evey cne s r ress unes provided by the CPU or processor ou he eip 0r oarr ang u
upoalcd with the same
uress calions.
unes provide the memory address
blockedHOTO A SACHY SMAN Venture
Teeh-Neo Publications. 2here Aulbos inpire ooova lion Fig. 10.12.2 : Four
SACIIY SHAH Veature
eb-Neo Publicatiens.
bere
 aDigtal Logic &COA (MU-Sem. 3.Comg 0-2
.
remaining
location,
pouu
the dala 15
"

traned u
Memory oganizalion

Bler.
en into the

Logic
Therefore, total data width
i* se 0t which k bits
are used To0 of
Select d gemaining n bits arc ctual stored in the
Selec
ain
On the other hand, when the word is to be read from a
ive memory. the revese process is carmed ou. The
contents addessable porion or pcd and memory
ULL accesses that specitic locanonruevng dada and
Ds Fig.
1
1 19
total dala output or
hows organizauon o ne ASaE
the
k
n Ds e
einoy.
suppued. 10.13.1

AAo From the block diagram, we can say

Memory Bank
LOI nemory consists of a memory amy ano1oge
an associative
lor m words
at
LAress 3ddress
with n bits per word.
Fig. 10.12.4 : Odd and Even Banked LOol memory
Apument register (A)
H 10.13 ASSOCIATIVE MEMORY
UQ. 1013.1 What is Associative
memory ?
MU-0.1e. May 15,4 Marks yesier I)
-An associative memory is the memory unit or device whose
SAored dala can be idenufied for access by the content of the
kBts 1register

a Eser mther thanby providing any address or Input

naos
SO eiCrea
Or
to as
he nenory ocanon. Assocatve memoy 15
ontent Addressabie Memory (CAN).
Read (m2)
Bcn a nie operaon 1s pertormed on this associanve Wite m words
memory, no address or specifications of the memory locaion
15 gven to the wprd. The memory itself can find the location
KnEits
utput
arepose, Irom the conients ot tne data to be
k DIS 01
written
a
register which is used as Key of the finding one of the m Fig 10.13.1 : ASSociative Memory organization
0auons O he memory unit and it is relerTed by Key
tgister.
AS m locations are addressed by k bits, they are related as
m2Nowas one of the possible m locations is chosen, ..Chapter Ends
 Logic & A MU-Sem.3Comp)
1 Advance
al Advanced Processor ani
and of
E
noples
Digial Logic & COA (MU-Som 3-Conp BAsC PIPELINED DATA
pesdup and Amdan
.
********
15
11
11.1
PATH AND CONTRODL perA
ddress
ad store the component needed for
B
for te memory elerence a per the
rne
a
. ML-Q. 6c) May 18, 10
Fyms classilicabon
11.5
ion 11-15 EIng
ua. 11.5.1
a.
Write shon o lon In detail MU O. 10 May 14. 5 MarAS, DDEG
311 Epaun instruction pipatine ran trectos
y 16, 10 Marks, 0. 11d), Dec 16,b N e av 1S 2M -15
11-15
with suitable dingram Reguer A Restes R521
Du. 1183 Lsi the Fynn's class itication of paralel
processing 5yens Y Regster B Regiser uRD2164J
1-17 AU-O. 30), Dec. E, O. Sla, Dec 17 10
costents ae loaied in lo mgslerA J
pered
arget (he address to whch the brane a

11.7 Concepts of Superscalar architecture.

. aaesaasese**s*raas

ana *as 11-18

a8cs
five
he
in the MIPS pupeluned architechure are shows in
1.1
we
gE
be taken) brah addes of te Instraction.

Da.11.7.1 Eplain SuperscaiarAennecur Dec. Ex MEM Sags3-X:Exerste Stag

11.7.1 Sup
Te). 18. 10 Marks. 0. 1el. May
* msssamems**armssnaea*******
E.S
***********re
11-18
18 Ex MEM W a tis sage te instructioesae execsed

Superscalar Processors or Superscalar Architecture.. 1-18 | F1D EX MEM WB

.
11.7.2 Register
MEM we
A Regster A AL
* essmsamuwmor*******sssak smesmsemm***** aaanssmesann******
msmsnersesnsa ****am*
****** -18
17-200 F1DEX pered anhnetic ar ogical operaion isperforned o
EUUa
11.10 Imtroducton to Multicore processor architecture.
11.10.1 Mutticore Processor Architecture. u
**
*
20
17-20
FD BX
ee d e is ready a te ALU outp
11.10.2 Hardware and Software Issues in Mulbcore Organzauon as******* -21 Fig. 11.1.1:S Slage MIS Mpeline Load-Store lastroctions
set is
high ALUouT Regisser A + SigaExieni[IR[IS:0]
The Mi
11.11
1

nsuru
aified into R-type instructioes, Load-Saae he 16 bits valiue s
5
dd to tecoatens
O 1144 Differantiate between RiSC
and CISC processor Instrucuons and Branch
instructioo5. a the ALU output. 11has

May, 17, 10 arithmetic and logical physical address grneraied lor the memory efeenee.
4pl,M-O. Marks. O.5DIO, Dec.1S DAS
Ua. 11.112 What are the diferences between RiSC and CISC processors [email protected] 14
11-23 R-Type instructions are used for the be
operations and are on KKegsier) operands caly. Brasch

ongare
A3y 15,5 Marks O. 26, Dec. 15, 10 MarkS10, De
SD
HiS and Cisc processors. MY 16,3 dO O
.63 S 11-23
11-23
LOad
Branct
Stor insirucaons camy out
instructions facilitale program coatrol
memory relerences and
traasfers
Target-Ada ac Sig-ExudRID
is
compuaed he ened
Da. 1.114 Explain foatres
.
of RISC and CISC processors. MU-0. 46). Dec. 14. 10 Marks 11-23
unt of the sign exuension aided lo
u.2ntroducion to Buses sua 11-23 IF lnstruction Fetch a
existing conents of PC. Therefore, MPS banches
1
** Stage :

12 plan Bus Contenion and diferent method to resove t. MU- O, 4a). Dec. 18, 10 Marks 11-23
this stage ror aree pe o cuon, K<y* elhive brapcbes
1.13 BU in
nsurucaons, Load-store istrucooas and Branch 18suctons,
Cwodein ** * 24
UO. 11.13.1 What is busAhitrntion? tech
surucuon coies pone Dy tage4- MENM :Memory Acees
AMU-O. 6a), Dec. 14. 0. 6(b), Dec. 15. 0. 4(a) May . 11-24 ue emoy calon out and thec
16. 0. 6). May 18. 10 Marks ue txtetnal usSes a hus sage the
memony eferences a caed
Over 4
a.11.13.2 Explain Bus contention and diferent mathod to resolve it eved
eguster (uk). F B intnauy e tad by mcmory is es
Oa,or GUs Dec. 18, O. 4A), May 19. 10 Marks are 32 bits or

11.14
d.eods
11.13.2 Multple
SA, PA

11.14.3 Universal
BuS

andUSB stanoaros .
y Standard
ustry

Se
Iniversal Senai
Arbitraion

Bus (USB)
a
ypes ol Bus Arbitraton/ Techniques of Bus Arbitration.
(Wuiious) ierareny

Architecture (ISA).
anoard Archtecture (SA)......
u ma aua**
a
us e

s
-24 **

.
u
11-25
11-2
point to the next instructuon. As
4 bytes wide).
Instruction etcn stage s
1e
k
Instr-Mem[PC]
PC+4
epresentadian of Kpe structos
No operaion

Lend-ore
akes place

Load Iastructions
NOP
in us agE

a Slage 2-1D: Instructios Derode

Mem-Data Dats-Mem[ALUour
and fetsting ALU
the instruction Data Memory location poisted by
is used for decoding ofthe
O Chapter EndsS. s sage
perands Outut
OUpur is loaded into
the MPS processe S

R-type instructions
Keglster A

Register A and
Kegister Be
Register |URIB2
Register |uKZU: 10J
contaia 2 sour operan
Store Instrucuas
Data-MemALUoun

the Daa specilhed

Memory locabon
y O
..
gsir
pointeu by the ALU Ouiput.
ue Data Modnle

eceived from MIPS egslet.

Tech-Neo Publiratiens ere

Load-Store
ESICr A +
s
Register (|R[252eisct
[IR(52I|)
Authors iaspire naoa te Register UKaUrioJ
A5MCHIY SAU Yenture
4CHIY SLAI Veature Kegister B-
ayT
Tech-Nea
et-hee
p.AE.
F'ubi ten ere dutbor
 gial Logic & COA MUSam 3Com
115 cgles ofAdwanced Processor and US
Diotal Logic & COA (MUSem.5comp (11-4 ples of AbENCE d Buses
The single data path diagram is trplained by the following
ae 11.1.1 iALU funetion Control nes
Branch instructioas Store Instructions ctional blocks:
Instructionetching logie ALUFmction inplemenird
NOP f consistis of PC, Instruction ALU Control Llhes

ee
TFALUZ): PC Trget-Address memory an0 Lonicats of PC are supplied to
ng napeis u on prce. owever, the Data
he instrictieOn e memony accesses the
put (4) is sserted, indicating the Zero c Data Un
resulk or equalaty. then the Target address computed in the
sent ou y ed location. uction thal 1s to De eteeuied. generales
he comtio
signals 1or the source and dESunation register operands, ALU
previous stage is writea in the PC. Hence efectively, the gn nOns, KeR And wnie signals
Braneh instructions operation runcion,
branch or ump taken as Dext instruction would fetched from for Ihe
NOP It consists of 32 General
this changed PC address contents ALU and Execution Logie :

No operation 1s done 10r brincri instruetion in WB (Write ose registers of 32-Bits and ALU. The egister data padh Nor
Sage 5-WB: Write Beck rce eer opernas
Back) stage. connects o epu AL
he conlol
ontrol logic is tor
e Enaue operins are wnen back. provide o o
e u
nsurucuoCsor AL E of jestructices Obe

Rype instructions
a11.1.1 Data Path for Pipeline (R°1Ype un sncdcns
ana an opuonaly muliplened input
from Sign Exiend logiC ucd Tor branch instnicucn. 1be AL
en e aded in the similar fashucon.

Creating and building a single da held will also have to be orcooeu pre
Register [UR[IS:11]}]- ALUOuT pai 0 utput can be teo ) physical address
archulecture, omsist of the logic circuit building blocks and or as his
ana ue ALU co
TALesult is stored to the register designaied for the
connecting the m togetaer into the compiete uncional block
or the
data memery(for Load Store instraeo Pprocn
coo5ignais s main
Logic t comsss or
Data Memory and Sign Extend man controler.
:
suze of dhe
diagram. The data connections and multiplexes are added in vge s n redueing the
Load-Store Instructions
the design where ever required.
Dala memOy and oE ue io Sg a
Load Iastructioas
memory comlains can e
Ker
1or wucn
The Set of contro Sgnas

he singe daa pauh lor Mis achtecture comssis of in cuse o Lod Slore instrucu0ns ndoa sigmals rquired o control he Datapatn ae e
ol the Ihe
B Mem-Dala struction edchung logic, ALU and Exccu on log, Data muuplexer I5 UNed at the output
ders art used o following
heMem-Data rrceived 1s sored inue KEgIsier Mcmory and Sign erlend opic, discrete components like Adders and Mulgext
B. IDe Lu
ins by 4 (for every instructDoa)
ano
o Jumpset to for a jump instrustoi
1

trom mem localion transfer operalion 1s compieted incren

ne the beanch rget duress DrI Branch-set to for a branch ust
I

instructions) Muliplexers are used. o Memto Rrg- set o1 for

a
a s
Data Path with Controls

.
11.1.2
on the delals or the devIGeS i ne
The control logic depends lor YPe iastructions, and 0 for
contrul path, and on the
individual bits In ue g co KegDst set io
immediate ins
nsirue uols.
annneue a
1ne a
load instruction.
upena o MemRead et o forI

Ype insinctions also

a

used MemW rile-set to for a store instraction.

insinuctuon. The data puth eiemens o
PCSrc an output indicaing it
the result 1
for any nstnueuonHng o
RegWrte A S2-bit ALU wih

Kedntnucion
address
Read
ser dala 1
Read - Memwnts MemoReg
zero.
Adders MUX's (2 line to 1-Jine) ALDOp
pe opraos,
k bis) encE
wnca at eneourd by e
AL
rut ne

ntrucuon
20-16)
Lo
, Read .Zero
Read
address data
Read
L
O A32 register x 32
32-bil egisicn
bits/register -Register hie

Aoaly, e conerl uals at peneraked for the

eer
mgister

Odividual
(1511)
data
RegDst
M write e
ALUOp
ddress
Wte
Memke
Data

o Duta Memory
The Control
on Memory

signals and control logic

is Jed
n-Source
ion
astruc .
Regisier

ce Regiser Operand
Operaad I
- Bis [25-21]
2-Bits j20- 16
of

o
the

he

ALUSe or u or
Sign Simple implemenlaton rd-Destination Regisler Opennd- Bibs [ls-]
tna
processor is
he
cormplete
o
the Instroo Module
Mgnals are generca n
ALU COntrois The control Bits (31

For
generaung A contr g put e 9Une signals requied for
e
BPgre decode ne H
erforms the opera The Fig. 1I.L3
show3
Flg11.1.2: Singde data path for MiS architeclure operao
MUX, labelcd lines areEAS Linpiene
FuncTRon Cconfruis
ana suberakt ALU ASACNIW SLAH Keatare
nd, 0r, d,
follows
TAm duthe
Teeb-Neoablialions. Pere Authorw iapwre innoao
M SACIY SHAH Venure Tech-Nre PuMieatiwna.um
 MU-Sem.
pigital Logic& COA (
Diotal LogicA COA(MIU-Som.
3.Comp) nsideration or conurol
iples of Advanced
RegDs
rcsopo Buses FO
et ot Mi
signal
insiructions, is laken.
implementalien
ies ol Aovanced Processor and BUSE

Regw rhe insu g are

ase ider a e
pipelined pm
f a non-pipelined proCessor
asa
l1.21. We consider
(0 sdd a c
nnimetic Instructione wo functional
orei
They e instruc tions (P) and
under uneg elype instructions Th eexon o he instraction
inatructon Re d2operands and Rei o-pipelined processor case, it is seen that instracticns
destinanion operand as
clearly seen
fom e wo time slots each wo complete its fetching and
1.1.2.
ASD, ALDOp function 010
and
110 ae s Econ
for add ana Sat OperbOns, respectively.
Selectedd
aE "u eher hand, in the case of pipelined procesor, N
Fig. 11.13; Generation of MIlS Centrol Sas poduble to fetch the next instrucbon
() and, or and st are Logical Insiruction he wh
DE CouD Sgnal 1abie for simple Arithmetic,
Logical, Load & Store and Branch instructions is s per the
able 11.1.2.
uCTe caiegory of R-Type instratin
lal
SDCBO bemg txeculed.
aows a
Tabie 11.1.2: Coatrol signal generation for
sample set of MIls nstructions
Register Sourceand 2 operands and Regisser
xCess 002verlap
same
graliet e
destinalion operanacieaiy sen frem the Table number of instr Executed in the ime frane (the
S Eected woukbe one ess than
Control Signals 11.1.2. Also, ALUOp function 000,001 and 1 ouble).
RegDit RegWrlie ALUSe ALDOp MemWrite MemRead MemfoReg respecuvely *iet anu, or and set kst than Non Pipeined processor or CPU
(st) ALU
operaions.
0
10 (i) lw and sw ae Load-Store Instructions-
h
hey ne
0 000 0 registeraswE
w
yaes sset tro
0 001 0 the Table 11.1.2. loads the Data
pelined processor or CPU
oae eer opend aod sw stoes the Rep

010 operand conlens to Daia

e miny. 1-

iv) beq instruction is a Bribch type instruction-

branches 11 equal lt is not needing any egis
t means E
nemory uceess and so no control signal is oeeded. The Pg I121:Pipeline Hazards
Table 11.1.2 clearly ipdicates this set
g Bddress|d 1-0) Implementing the above -
said control signals an the Dula
o mcreave the pertormance
f the processoe nstrucbons a
palung u is ecm and showng te ieEung wnile ceruBIng 5 Caled as mstrurtion PIPe bnung
PC431-28
memony acces and ALU funcbons are as shown in the 11.21 Plpelining Strategy
RegDsl Fig. 11.14.

and
PCSe Every msrucbioa 1n procesir 5 ovcu
H 11.2 INSTRUCTION PIPELINE
If the processor is performing anthnetc og
anu
sS1-2
MemWria
what
uQ. 11.2.1 What ic
instruction pipelining?
is instruction pipelining?
Fr E.

with negister operands, then tbe buses are ree elch o e

May 14, 0.5o) May15,6 Marks
MU-0.5c.
PCLRead asr
Inst [20-16)
Reed
a
----
sruction
--
cycle ot the peoces50r ar cro cc
Is wil euuce ue
conpletely n the sane
wung me
CIOck cyce wucs
so fwo asks
il
ae
reuce e
Is functonal unsts.
required
ameD
31 OnS d is operationally divied 0
al a tneB an r imh sumulaneusly is called as
processung
ecnie
RasBus ALU in the processor life syck is
cton
32 Read
inctuon
ineflicienl proeea pipelioe in which there 15 a etcb
tUs comsider a two-stage
pecilic instnucthon compkles 15 w0 ouup cyck and eccute cycle. ee e y n n
un u
Inst [15-0) uit and goes lo the nekt unng eecuaoa ew y
s 0or being

n Sign2 memory Ol
anu can ploen*
uonial unit S Tree,
Ins(5 unc Therefore, he execuo0 5ck d etch cyek wort
ALU ASncto in he saE
cioas arc in le
eretore, at any given instune, aw muhuneousily.
6
C dilferent stages of
advancementat ue s
execued in the same
o be
32 elcr number of insnucuos
Fig. 11.14 i Smple Mls as
implementation with control signals n. Ihis leature is called insu ASACHIY SUI Ventae

Tech-Neo ublieatioas. beAuthors inpure aaoathoa Fenati

Authon ap
A MCHIY SLuI Vooiure -Nee P'ublieations her
 Digtal Logic & COA (MU-Sem. 3-Como)
(MU-Sen

& 11.2.2
o and Buses Dgta A
Pipelined Performance nstnucbons in an instucton pipelined processor. HOwee in the pa
***************- we knOw tha, o compiete ue execution of n instructio many reure otle necks and oneSod the case.
Thee
q4. 122 Eplain the
Performance metncs for u eguues tk ak ANemaety.t
te curre
that doesn icultes
n
* -
1) clock Ods, t allow he pepeline to operale ide imtrtien that i under evecubon
--- --- ihstruction p'pelines. Therelore
perir

All such practical issues and resource he

in
Nio,
s eaplained ahove, the instnue *****- CPIAn= the
instructuon pipeline to deviate make etching te
net
mproves the fr gm.
ce of the system as i
n>»k then quantites
Econs ns gnincant
charactenstucs are cailed as Hazards hus case
bh frtch stagr d euecne ar *
uOn

instructions
uon
cd
and thereby increasine th
pet me
Onparcd to n and therefore.
Them as Hazardsinrbuee neCncy
executionne o mstnuctions
and, therefo
e
ference

ne processor.
unit a against any
CP
in certain
DuBes
me.
can e pven to omly one et them a
hazards " eneral degrade the in eefor,
i s O ppelioe art detenmined by
Uon pipeline uniy Le. one insunueuon
seuon L Yalue is nea perfomae
hazards can oe
the two operabins to he perfomoed ane er the

having k sapes in h cople every clock The ciasSne inio hrte types as followy
Pipeline be P penne 8 thar the imsman etecruion takes
o CXCcution of a seaence nazards d eline bieger bo

"uuons uien,
"

we can
deuce una Throughput: Instructions Per Second
A non-pipelined processor woukd require clock Millon
(PS) and 00te structurn Razrds
k periods each Instructions Per Seconds (MIPS) (or He*
eaecute one enture Imtriction ancd
theretore lo ekeue Number of iastructions completed n one Control
second provides
On asuruchons would require EXn bumier o OU 0r
an cwaluating uhe pen
hazaros aards E
eppeline deeper ie the pipeine shoukd have 4

An equivalent k stage piementing the instraction pipelines. Resou denoes nstrucban

nuneer ot stags Tis reucs the pro yo
peniods to exe
processor woukd require k
e most o e proceEsor operales in frequency range
hazards escrTe boteneck ind the pipeline als andherete
OC
uructions Moult
wever the above megahertz, a more convenient unit B the mulion Fig. 11.22 :
Ppelipe hazardsb Dr ginve impact of sraural harards.

o execute. Therefore, total number of clock of MIPS indicates a better perd PS). A highe.
valie e ide the CP This makes the
umbet
PEnd reuired o eNeCute arek*n
s compared to (k
which is much
-

LatEney
a 11.2.3(A)Structural Hazards (or
nesource azards) urce borte neck
revurte botk neck on the bucs
on te ucs and
d
g
x n) This clearly indicates that the performance
o E Wl De improved.
DE ency s ane Ocluy. n e or esoue
EY Speed Up fs)
pipene,
coniexr
aeney is denned as uE une del4y
o lnstruction Structurards hazars ane te hazands To have dual cache. A dual cehe impiementabom ee
n
Iis defined as the amouat of üme taken by a DO
etw ee uhe tame ntroducedan
nton ppeune y witue ot sGrucuirnd

pipelined procesuro of the instruction is fetched and loaded in the processor

or problerms or resourte bottle necks.

cqui va Ppelined prorsse en by an

uc sanE pecific instruction d a tere hey ar ruled o the dta cae
completes its cxecution on
--FE
r

execution Dm the cuber hand. pre-fetuh or feth stage mnemory eferences

A progra bequence of n instructions.
En sec. (or more approprialely in Micro-seconds
or |E mram
NOw we have ime taken by non pipelune
POEsor
and-seconds 2 memoy
*

n-
n ano ume taken
Therelore, Speed Up
by k SLage pipeline processor lo b
Issue Lalency is

instruction for execution.

he lalency or ume delay In ssuing the
Execution unit
eeee
mea mouce the bak neci

.
sy aem bus and therefore structurnl hazards ae alo educad
the execution of an
Iy ue dcuy in completüng t's a stall
ata
Er ue prucesor. Data Hazards (or Dependencies)
Speed up is an important metric 12J8)
Ponnance of instruction pipeline
for cvaluating o
a 11.2.3 Pipeline Hazards
uQ.
uQ 1124 List and plain vanions data
n >>k then quantties & and becomes insignificant
comparcd to n and therefores
1

as UQ. 11.23 Explain different type of pipeline i apenderoes, nd . branch

k hazards FIg 1.23: Structural or resource hazards aZAris tat occur wn ta coPutdr
Therelore, ak sage pipeline in its best case provides
a speed MU-O.18). Dec. 14,3 Marks, O.11a). May 16
faster.
aULgE
*

programs ieariy k times

O.16 Dec. 16.5 Marks, O. 6(a), May 17 PIpeune are or dssimuar

n he Fig. Il23,
our
as the instruction l, feth sage
-- ---- 0rs;
CO, Dec: 17 OGB), May 18 ** d to the execute *
E Clocks per Instruction (CP) -- ------------i0SDNE0arks Equires more ume lo compeie
is ideal as l has
oa unit
s oner ponnt pertarnance malrnt o pipe
lie. I
Pven s nuining absolulely seoth and
ch
sLage ot
areauy co
insucuon
ion of iastruction
. he rao cesuu
s

ordestinanon
uE d 1o

operana
be depennt
H
it

ives an indication that ow m not yct eint co nimaions ons are cemmun Tbee ae
Tunctional suge of the pipeline and Uherefore L. which is dhree
9 Dlodule
o complete an instnuctuon on an avenge
nsuuetuon, every instnction is compleling its exccuuon n n da naards
dpenkncin ohenad
defined as the number of clock penod required per eXacuy one cIxA perno.
is called as
pipeline st we
nsin
N er e sequenice of n Such situation
Aing intrucons o ake kge
a A SCNEY SZUY Venlure
Teeh-Neo P'ublications ere Autho npure inN LG execute and therefore degraidung
ir natiat
erc-Neo P'ulilicativns- hee u
 MUSem. 3-

A
D
Dijital Lgjc & COA (MSem.scom and Buses -stage pipeline
dor consider 8
nn
niples
elayed Branch Technique
of Advanced Processor and buS
Data azards or Dependencies Solution to Dat azards
wa instucion : n thi of the

he srt Period
FOFEX nched
Siicims hefore the hranc
icty cubvequeet lo he keanch srac tie.
oAs

RAW WAR AW technique that is called as data forwarding aor

operand
,hen te emdatbonal ranch 1s takem, the ang

edepenoeny
ater oad Write ater wriie forwaning
**

NF I1o ycd making this specific inruction sueu

epenoer
in tis echinue, oupt o s ed back at ly n
be
ton to be executed in any case befor

ASO called
the input ot tie ezecule stage. bereore, the destination
Pipeine i TElore, ubbzng yome n

pEn A0-Dpendeny
denende e ndy available
oressor fresh and therefore a
the ame »xted
due to pupeline fushing Ths instrction
in

hich
the

Fig. T1224 : Dats before it gets actually wrilten into the destination register or plpeline Is a waste Sro0Uced
hazards or dependencies i5 hushed
locatic. no ppeu pendent iainac tion that does nod affect te
Resd arter Write (RAW) dependency or flow Therefore, the delay caused due to walbng tor tie destination Fig. 11.2.5:Onru or Instruction lHazards ne
UEx. 11.21
ranch directly or indirecly

operand of previous instruction is avoided.

As a result of this, there is no stall observed on the instruction Solutions to control hazards LMU-0. 21a). Dec. 18. 0. 218), May 19 10 Marks
*
." euc naard, the dcsbnauon

c o Ue minimized
pact ou c uaus art (KAW or Branch
redc es way to miligate de gan having 1oiastruetions (without Branch and Call

.
perands in the sh wAW) is
conprol

There fore, it is temed as ead aficr wnie haa oeram. Unconditional hranctes halcan be predictes s art occuming no0pipeune Pi n
Al instructions are of same length am having
cAeuled oO and

dependency alwuys leads to the data hazard

in
'.6:3{) Control Hazards (Instruction aecurately as the branch always taken. is i On.
PIpe ine stages and time required to each stage I asec. is
nstnuctaon Pipeline. OSDEaung wtn Branches This allows the brach prediction logic to start fetching
s Cauculate ume required to exccule the program on un-
ucuent instruction cannot fetch
Go.11.2si subseg nched locion
rnnds
instncic
uniess the previous instrurtion
has stored
one clock
** a vanous ways in
piain
which an Mstruction Pipeline can
(arget adoress). As
correctly, thc penalty
ne
in
eways predicted
terms of stalls is nearly reduxed to )Calculate Spedup
processor.
be
.enod stall as a subsequent
MOV HX, DX
deal wth conditional branch
zero.

The more chalenging task is to predict condiiocal branches

ADD AX, BA --------------------- The number ot isiructuons etecuted ae 0.
The conditona Drancn predkcuon may no aways be comct Therelore

e
zas
Write after Read (WAR) dependency or Ant
r ntrucu0n ttaards ae calused due la the a*
Dependency or may not take the bra
r ppeline stuges at gven as4. Theretioe *
the system acuvity
may
In this type of data dependency hazard,
or eEvenis. Lontrol trsteh at Feery condition code in advance while decoding the beranch
Now the ume equired for Non- ppelined processor Is ven
the one of the source Causco by the cunditionial and uncondiional branch
aperands of the previc instruction is not possible.
tie user progrums.
sequent instruction. Therefore, it is tiermed as Write cais in

events such as intem

There are two different lechniques of branch prediction
Lceptions and s iem
This type of dependency does not lead to the
) Static branch prediction lopie : lo thus kge. te
data hazard in When the control transfer, say typically branch predietons are performed by a fised stane rule S, l = 10
+4-1 = I3 aS
a branch instruction
P nE, usUaly WAR dependency is
Ppcarn in the user pro which predicLs all unconditional banches lo e c, arther uhe peed-up s gvens KabDO of ames for Noe-
3 ion s gPpcined and hpeuneu pror
g Mov DX. BX PIpeline stall takes place as shown in the Fig. all forward branches (where the target addres
* (n *k-) =S,'S,= 40M3
ADD BX. AX De branch msinucuon comes for execution, next few

Write ater wrtie wAW) dependency or ouput stcuo

e
s o
aready
be
in the pipe
exCculed tron the
line but, since the next
branch aduress (larget
ae
Cs
predicted hot to he takesn and all backwau
(arget address smaller
than sourte addes)
Derefae, peelup S= J08

pendy address). all Uie to be taken. This branch prediction

ae predhcted logic 11.3 BRANCH PREDICTIONS
insiructaons
in
his yp dala dependency Samalarly. nce he pipeline is
he
now buill
pipeine ae
a
sone cioc chough but no very eiciend
E
hazard, uhe destunuluon alresh,
11.3.1 Bplain Branch Prediction Logie and
p "eprevius insinction are sarme as destination aPain fdh une the pipeline is fully built Dynamic branch prediction loge Tis is i
meUO. delayed brarch
lermed peu
s Wite after Write dependenrv
OE, It is
ore n
Tereloe, OC angle of the Fig 11.25).
piex 1ogIC where brancth
MU0.20Dec 1404AS E 10Marks
ns ype o
taal heavY penalty in lerms ar
ppei s oyamcally on the basis o hranx
dependency uNMally does not and delay is required
lead to the dala paa. slory are the hesd way w mitugae the control
nzau tur Singre scalar mstructuorm pipeline. However, it may
to be
Control hazards ure the he
For this pupose, the CPU atais brand
BTB)
Bru
s to predict in advance the braaches that are accuming
lead a data hazard Lable (BHT) or a Branch Taget u
to in supencalar excculuon as muluple uhe pipeline Malling coninbule makimum to
the brunh his in the uver prugn Module
s ue execuied simultancously. performmance.
alion o the system The branch arget bu
s
Rased on the stus L'nvndinomal rans van s Pukiru *uraey as the
6
g MOV DA, BX for the mosl receuy s ay
ADD DX. A2 history, the dynartic cbanh
bancn
p
prda branch

Teeh-Nee Publicaliens
anch
eAuibwrs pu inoalio 4CHI SCUW Veaue
A S4CHINSAMAN Venture
eeh-Neo Publications Autbars inpire inavnau
Au
here
 DigtalLogc& COA Sem.omp)
b (11-13)
rincip d Buses
ADigtal Logic & COA (MUSem. sCONO Advancd e Duses COMPUTER PERFORMANCE
4.4 t ths proiem deuzners o pra
his allows the branch prediction logic to sart etching Let us consider the Dynanic branh prediction logic of
MEASUREMENT Op ed hardwae mechaniim pa ach

subequent addresses fom the branched lkcabcm (arget

Penbum processor rom Iniei
BENCHMARKS (SPEC)FOR rgt address »eil in dvance o that the
1arget Buner (Bl6) s ued EVALUATION
As the hrans

erms of tallss
Deardy ectly, the penmalty in Branch
Architecure to store the adkdiresies (Sourte
in Pentum
as well as
herefeehrach pred
PIpeut ad e
wnte Short note on Performe
prodio
branches.
The more challenpog task is to predict conditional branches.
mal Target) of the most irquenuy and recenuy Branch 0.141 DnanCe Supercalar enecutw
cdibonal hranch he comect statements and reler to these addreses
measures.
when branch
cde a evaluated while executing the MU-060Dec. ** ance af the procer an e hurther imre
nrucuoo may or ma nor ase ue branch ana knowng e
Suruction 1s eneouniered.
i *** *****
extensively t
1810s
many comple ciock cycke.
couon c0de n advance whule decoding the branch E Aadress *
unss a wnictn the branch Comul
instructioa is aot poxsible.
insuncudPp le dat
of processing large amcunt dala it
can beaxheved by incorporating mutipe parnie
here are two different techaiques ot branch predictom.
munimal nne
1et adaress ine adress o which the branch is eitcr performance.
Satic branch prediction logic adc
above requirement imposes redesigning af coeputoe
*
uatre eecution
The
this logic, the branch predictions a
n Statie Bats- 2 Bt Brnch State field 00,01,10,11( aST, nachines. But exacuy which paruneies io be edesigned a a cas e procesor ahers the kow of program
formed by a ixed
satic nule which predicts all unconditonal branches to be taken, all WT, WNT and SNT ) big question. pculatively
Torward
SOute
branches (where uhe aget aaliess
adrtss where branch insruchion apras)
S DEYe

are
the
a Pentium Maintaims 2 Pre-fctch buffers of 2 Cache Lines
lo his >eeu eran 1acton to dsign for E ow prxET a *o on
a
no
prc performance
to be taken and all backw ard branches (arget adkdress smalicr nan UE Bes x ) Le. Having total ot 128 Byies of Pre
to
Metrics such as CPU Tme, a11.4.2 Aspects and Factors Affecting
prrdictcd
legic is good enough ur noy
be taken. This branch prediction felch Bufler Memoy
11.4.1 Througnput, etc.
Computer Performance
" the Branch 1s predice not o e taE, ED The
Te
Dynamic branch predicion logic tetcting cotumues in Cutent Buier scqucntially. EED gs e peed o e prE teed
speed of the processer can be incTEased by imprvving
The the

more complex logic where branch predictions are thie Branch is predicted to be taken, then The Pre mechanism in which the data and unstrctions art led to t.
nput ouput devikes have nct kept with speed ihereloe tere

mauntans a branch history Lable

tetch bufter is swtehed and Pre-fetching is caried out here are arnous aneur EEDLS Eporeu ch
ganuy
is a need lo ked o
5H
Pupoe the
P
or a Branch Target Buffer (BTB).
trom branch target address im the switched Buffer. has increased the perfomance ot proE
Duuw ing ae ew cdnous
neEthe
The branch target buffer is a caching address buffer maintains the branch prediction is corect, the instruction
ening menm prc
this pume y branches. For pipeline contnues snoy Le firsi comsder the musmaach
Merfaee. This inerface affects he spead dprc
the branch mis-prediction occurs, then instruction eaEC UOn
which the branch instruction appears), urget addresses Superscalar drasbcally at lekcbes dta and instrue ths ttm tmly

aaress Pipeline stalls for 3 Clocks in U-Pipeline /4 Clocks in peculatve execuioa he operabm sge
to wnich uhe branch s lo e akca) ana hisoy sae V. Pipeline.
4 whach s compaably slow and behee

branch in the past.

Based on uhe stafus .ipelining
of branch history, the dynamic brnch
Taken instnuction is executed in mulbpke phais a opera (u) ore e bieteeulae A e
NOt 1N An
the instruction,

ure Addresagrt Address Sate Bits

for eg fetching u rssina.
.ec.
Fig 1132:Dynamie Branch Prediction loge fetching the G
Usang ppe procesor can work with malbpe (u) Reducing theana lo u e
Prediction Logic (Applied at Di Pipeline stage) ohases In this *ay d
Branch is Predicted to be Taken if Stae is ST or wT instnactions are executed simula y
Branch is Predicted Not to be Taken if sate is WNT or SNT cycle. are
hprem
ou u PTpocrals. Ie suraiegues overeodee
berefore the overall speed
Slaic Chaunge Applied t EX Hpeline suage) nJ urternng
increased.
Initdally, sT slaie 1s always allocaled tar each branch 4) Hgber pred etcoe u
2. Brunch Prediction Module
Slaie allered nghtward if the Branch
is
is Actually not Taken. tall of pea
n oranching instruction can cause ennplete 6
State is aliered lefiward if the Branch is Actuully Taken
cchnique.

SMW Tewture
Fig. 113.1 : Branch Target BufTer (FTB)
SCNIY
matee
Terh-Nee 'ublicatanms.. er Authars impure MnovaLo - SACHIY SLW Veoture Tech-Neo Publications Dert
 &11.4.3 Comparing 1-14) FrocessoresOrand
Computer Performances Buses
GQ. 11+2
State the evolution
cessosofprocesso
er I Addressable mem T
Wdth C SpeI
..
**** 114.
The sp
peedup and Amdah's
Law
1971
L800S O
*Dyes
DS 0Hz
ache MMemory
stem isthis system pa
system parametet of the
compe UG.
LYNN'S CLASSIFICATION

8 bits 108 KHz

proposed y ysiem designers various
sobce s15 e
194 Parallel PTocessing-By increasing ertnots on
Fns
F's
0 1978
ARB
oDs 2 Mlz processing Cietnent handling
the eec
mumbet
of panllel e lessifeatien
MS
16 bits SMHz,8MHz,10 MHz
trying or eecule
in panalel andUQ sk du 11
11 -0 Se May
0 5i). May 18 10 Marks
code. ethe Epain
o 1982
8 bits S MHZ,
SMHZ
Cehe
Cache Memory hierarchy-By
a by-By mplementing
R's dessification in detail
LM-O10 May
TGB such that the faster 14.3Mar
o Dis moy ccess
80386DX 1985
average in
wait stales cycle time is
mdace
o 21a
creasing the system terf ire mduced 1id) Dec. 15. 5 Marks
DIs 6-35MHZ Uereoy
formace
S6DX1989 32 bits Faster memory and D0 cycles earks
um 1993 wnee
By
as well as LO data nroducing iectsgaes
e ay. quicker Lst Fs cdassihcatien o

.
GB
Dits 66MHz araster
be the aCea med in Parilal process
Penuun Po 1995 *UD compes er he
is
ystS
completion of their
Pentuum-u
4 Dis TS0-200MHZ 1EKB Li and
IstB L2 improvemeu peotace n ue and T****-. LPU has pnmary 9 53Marks
9I DGB
Dits UOMHz But incTease in any ot the above
Is Kheved T functenaity of processing
Pentium-ITI 1999 eN L echniqpes does
not incr ntw pms. rogram is euence of

enurn 200
1GB
b6UMHz T2KB L2
niting factor on speedupia memory, When
Bedd o
t e
fesch imstruc tions
program
mored in e

The Amdahl's law pr in the

Core-20 4GB program running on mutiprocessor
the
mpurison o
4 bits T06-120HZ Sngie pTDCESor.
Core 2013 Let us consider there are N
p
the in d
y
wle eeng ***

aon ngprgain
N t siores outp
1SMB L21SMB
L3
wilh comp ur
5 given as:
01
1hen the speedap
0a data operands to de memory
10a De ow or movemeoi of msurutions rom memory 1o e
11.4.4 Marketing Metrics- MIPS&
Speedup

MFLOPS
Mlion instruction Per Second (MIPS) Time D
exScuGrn srge processor Time to exac.tearogann
he CPU and he
wmemory
of nput aod ourpu daa operancs berwees
called as data
It a perfomance parameter pars el processors is stream
tor the processor which indicates
Base etne: 1ese are requirco
bave stict uidelines a pond re
tor
number suuetions
of Million Instructions executcd
àre
exCCuled. MlPsi Specdup
T(1-9+8 (TIN)
nstructon
1or compliaton.
ssen rate is computed
mpuled by
by the formula:
the formula
:
Per Second. The MIP'S
Where

e elault
estto achieve comparal
settings should be
1s Uhe total
rEsults. MIPS execuluOn ime proren sng unge
Peak letr5

system performance
s enables sers to attempt
to optimize eTx10 CMx 10 proCessor
of he

1s nstrecien and Data stre

yopu ng ue connpier output.
Mllons (of) floating point operations per
t s the fraction of the code which is paralelizable with no
Speed Metrie: This i Spiy a measure ment ot the ume second cheduing Tberefore, there e wo pes of streas oboervet
akes to execute a compile
it (MFLOPS) Instraction stream aod Duta sreams shown in the

or comparing the ability ne speed metric is

t
s ao
and (1-) is the fractioa of code which eecuies squentaily
Fg. 13

Kate
gle lasks.

metnie
oPe 0 COmpiete
hdicates the floating-point
inet

as Uhe number of Floating-Point

r B
or the processor which FFom above equation we can copchude tal for espkotang e
ompicie parnle lism of procesor, the progran
mu have the compuien
ns Cadicthe
This is a measurement of how many tasks edetined Operalions compleicd or
a hugh paralel execution capabilities.
compuler Can accomplish in a certain aunt
throuphnut cana
called as hrougnpul,
alsocallea
of time; this is rer Second, It is given as
gea
a Taonomy. The four types ae
LDe overall specdup of the sysiem Smge Lasruto Sreum Sunge Dala SteAm
Commercially,
capacity or rate measurc. MiOPS rale
floatin
SSD:
following metnes exectured 1loating-point
Number ol excctured
benchmark
Enchmark and and compare hethe nerfon
arket to O operatuons in a pro Speedup
penomances or uhe computer Seream
Execution ime x 10
lnstra tom Suam, Sunge Daa
systems (un MSD
1
Nhulmpe

wlhere SU is the enhancenest tactor Module

wn no Maltiple Data 6
which is parallelizabie MIMD : lulniple Iastracbon Stream,
the fraction of the code
Saream
heduling
aa (1-1) is the fraction of
code whkh ekecuesyay Veature
SACRIY SUH
Teeh-Neo Publicalions-Wbere Authors inspire innovation
A SACHIN SLLH Yeoture
Teh-Neo Publicatien "**
 Diita aCOA (MUSem.: (11-17
Digital Logic & COA (MU-Sem. 3-Como)
1-1 Buses hese type or compaet ysiems are widely in s of Advanced
pipelined processors which are also ed the dat
ce call Systolic
() Single Instruction Stream, The CU receives instrcOns rom ue memony over a single anap when a specific instruction completes
Single Data Stream its work o
te sp
(SISD) nsur u
decoded 1nstruction 0 uerent DrO
u
And
basis of
cach DPU
ltiple Instruction Stream, Maltiple
Stream (MIMD)
Data
conl unst is
fire, and t can proxesa >u
nit then the
auy
organizalion, there is only one instruction stream and Proceses dinerent data clement.
ne tis to be made uppof t type ot compuer
parts namely BuZed The data element is accessed from the memory over different byues ere at muhiple comtrol 0y gven instance, different instructions are im

-Data processing unit (DPU) and control unit (CU). The

DPU deals with data and c s of ALU and the data nath
heretore, PU acceses the daa stream from the memory
Diirectionaly.
data surtams
Therefore, SIMD pro ae capable
processor are capabke or

The Pig. 11.3.9 shows organizanon or DI

processor
of executing the

their applications
cOmpulers.
units and moup
different d
Each D
cach
.
tions is fetched frem ue memor
uns. Each DPU

r
SUEamis.

eent
processes

t
CU and
these
iees
ater
Be
oumber of iine
This feature is caled as instruction Pipeline

Consida cae of aa non-pipelined processor

peBedprDCEscY a8 sown in the
E 0 Ne
g
tetchang of the insaruetbons (F)
ne ume aulows a

in mulimedia
De conr0 unit deals wilh
incbon he
strem as and sienal operabons, ad
and find eAECuGDa of the instructioo (E
receives insnicions memory aNa decudes
Tom he
processing Therefore, these kinds o processors ae capable of haadling
Subsequently, the CU gets these instructions executed from -ppeined processor case, it is seen that instructons
multiple independent instructions on multiple difem
()Multiple Instruction Stream, Single Data SDs ea wo compe s Teg
elements Simultaneously. execution.
E al or
or DiD conpuet is as shown in the Stream (MIIsD)
Insu
Main On oher hand, in the case of pipehned process,
the
ana one instruction suream. This is the most widely used In the organi zation o1 this ype ot computer sysiem, there are posible to fech the sext instruction ar the same time while
computer DEEvo nsrk o00 lB ing eNecu
he daa processing are arraingeu in a sequental manner
uniEs
CU his functonal overlap allows a
aier nue
ume iramE
in such a way that output of onc DPU is input of the next msirucbons tp be execuied in the same
Control Is DPU in order.
tC Instruction Unt Memory drhiei
stream DFO
heretore, all DrUs ogenet nanoie oy one data ekment, Non Pipelined procassor r CPU
15 accesgeu
ach D CU and
s nstrucion stream each CU processes it's different instruction. Each of these
nstructnons is reichea trom Uhe memory over diferent FODEFO
instrue uon
Fg 11.5.2:Single Instruction Stream, Single Data Stream Plpeined procssor or CPU
(SISD)
s peproesso
Eelements scqucntualy by mluple
processes ne same aala
instructioms. Organization
FE
() Single Instrpction Stream, Muliple Data of MISD is as shown in the Fig. 11.5.4. 2 E
Stream(SIMD) 3
*-*
Pg l1a.l :
lnstrctdon pelibe
Mulkiple Data
Fig. 11.5.5: Multiple Instruction Stream,
the processor instre uoos
muluple processing elements or Dala processing units are
Stream (MINMD) To incrtase the penfomaunce of
(DPUs) in the computer architecture.
1dcly Used
ir SimMIkMEDUSy ecne ckerus
hey are controlcd by a single control unit. Ihese type o compaEr ys feaching whik eeubng caEd
PP
supercompu anced GPGPU (Geoeral
csing Unit)
Processing Un PIpeline 5tages
Main rphic & 11.6.2
Tory
caecuted ia a ppeline
INSTRUCTION PIPELINE jn a mtion pipeline is a multüistage pupeun
H 11.6
suages. h
fe fmlal daers The pipehie suages ae cop
cubenn
paralkl processing is caTedvine ppeone
paralk ism or
of para cases. u all
by
esto insmu ar
The finest ievel
way
level of inelining concepts areingle clock period in majonity ot
execuioo and out of crrcomplete in aBe cbe a d speed tberefore maximizing the
furtier advaDced by way ss proxe manoer m
secuons these parallel he given clock
cecuuion. Following ystem pe
pproachies
OF EXWB
Module
Plpellne Concepto
a 11.6.1 may O
CPU consists o
Ssor or
Instruction inally divided into 1s me is an
s ns functions and is op procestor hie e SACHEN SHAM Yentare
ig. 1.53: Single Instruction Strearn, Multiple Data Stream Fig. 1.54: Multiple Instruction Stream, Single Data Stream A
in the
eient neocess.

Autbars aperr
SACHIY SHuI Veoture
Teb-Nro rubliatwnsam her Authors anyune maora A feh-Nee Publicatiena-*
 Digital Loc sOA MU-Sem. 34
Pinciples of Advanced Processor end Bus
Scheduling
Dital Logc& COA (MU.Sem. 3-Comp 1-18) nci OA n Buses nstruction prog m
order, and dhen evaluate which instrucuos

A DA0FA EWe standar pipeine, the instructionsa operands ar

(1e.
eady w
etecuted.he decode stage is the se
The five pipeline stages are
In ched, decor im
in the progran
ecuios Rar.
neiructioe Felch (UF) :
la this stage the processor fetches oro data, and control nazs Ie
EE NMetifies the
proceswor
hardware
wEVEr,subjea to the fact that it is not dependest any of the
nsructions and loas them into an instraction egister for
FAA AA itectural feauresy o
impat E Um 0nat have
ot yet completed their execio
hazards. The compuer can also make use of d
these
decodang
tnstruction Decode (1D) : ln this stage te processor decodes
F10FEXW
A1DA EXwBA OFA gvailable about the hard ware to minimize the hazoed
OTE, In Out-of-Order execution. the instructions

grim order and received, decoded but hey e ekGEu

tn ue

scheduling the dcpencnt useructions away from each othet order (L4. Even prior o ne ns
the instructions and the control umit of the procesor generates
the necessary intermal and extenal control signals for the Also, complucr ue pung
logether instructios that
neprogram order, sabyect io the coo
outrol FA 1DAOFA BWEA complete
nazaru. ou
But there are
yslem
imit avoida be ady.data operands needed to execute the iostrucbos,ae
structural nazau
strdetural
perand rech (O) :
in tns sage ue processor iecnes the
EX
B
Lo oFe OFEX, taken al compier end. in certain sequ
aD b these effors
ne iasiruction is not dependent on preceding ay
tor nstructon executon rom eiter
w nazarus become unavoidable
Tctions,
dala operands requied
he regsters or memory locauons. AAA hereloe,
Out-of-Order execuuon o 0
e concept of
nuction whose eecution is not yet compiried.

caryingOutol-order Executon Implementatons

Execute (2) : ln tis stage. the processor execuies the e Instructon eneuungtne processor hardware
nstructiom. F 11.7.l Superscer Execuuon wun 2 calar Instructlon architecture level rather that geting pertormedte 1o approprialely implememt the Oo0 processor, the pupehne
e Bac wB) : In is sage. ue Procesor slores or pipelines complc evel.
eerd to be modified to keep of the
ct
comleiy eta eaturts
writes back the results of the executed instruction to registers
a 11.7.2 Superscalar Processors or out-of-order Executlon and
functioeal uis
or memory kocations.
Superscalar Architecture Regster renaming : Registers that are the destinations of
The pipelines stu catcr nas ne nstructons staically instruction results are renamed to avoid unnecessany
H 11.7 CONCEPTS OF SUPERSCALAR
ARCHITECTURE
Supercaar processing
ru eecuOB the schedulca ana neteto,
in thesc PIpenes
n
tat ,
ekeeuuo s caniecd out in-order
nsuctos ae etecuied in
acpendency casbes. therefore more than ome venioa o

a hazAru causes stall cycks in the processor,

*** 11.7.s
uQ. Explain Superscalar Architectur
Scaa pipeune ekst in ne processor aee, cach scalar

pipeline equivalent to a simple muli-stag pipeline,

program order. it
then all instrucluons susequent o ne tnsuruction cusing
raoes
instances of logical renamed regsen
puysCal
usingg
tegisu
a Repisier ABAS
stall, are also stalled untl he hazard esoved and te Table. It also keeps track of free available physical regsier
May 18. 0. 1e). Dec. 18. 10 Marks The processOr that usc and implement the necessary resources
A-0.50). 19,51Marks nsur rescurces.
- 0ay for such Superscalar exeCution arc callcd as Superscalar dition
and
other tochniques misimize
su e sue
**

orwaring Modiñed Instructos

ese sometimes a stall is unavoidable. For instance consider of oer
a11.7.1 Superscalar Concept their
ta Supercalar procesor 15 having scalar pipelines, then it he following code: eadiness to execute ie. in Daa or
& a 5ueSupercalar processor. Sumilardy niber than Progam order.
The instruction pipelines usually implemented are essentiay calca ld rl,(r)// load rl from memory location pointed by ró
Ssinge pupelines operating on single set of function units in rs neno Reservation Statkons
:
Each fumenonal unt has a et of
processor providing functional overlap. paralel scalar msuruction pipeines5. SuEn proessos AoW
add r,tl, esrv
E
3 0r4msrcaons simutaneousty They provide gher
"
tmeans that mutöple instructions are handled inside the r3 are already availabie in snoas can also be
NOw the register contents r2 and
processor or CPU in different functional stages. However, in orr peronances. neirspeeo-up valuEs and MiPs value instruct ld that waD OEeuy to ssuc. IDe rEervanoo
renamung
the register tie. Now co ng ie gisuet
nsrucuo0 hroughput arc also much hugber that the
cc runcional stage there is only one instruction. 0
Simple singe muli-stage pipelined processors. Under ideal causes the menoy s Li data cache mis,
O

rding: These are algorithms thai keeps incE O ne

Mcaning. 5uppose we consider Eecule (EA) stage, any condition, a 2-issue superscalur processor provides CP value s0 the lodd unt ber of clock cycles to retnev
details of the ppeu.
nstance, there is only one instruction executis data rom the L2 cache or main
memory wili e available from
of 0.5 and a 3-issue superscalur provides CPL value of 0.35. The eo
processor. is worting oa this nene shea dependent instruactioas
the ume the load unit
Such single set of resource is Caled as a ingie scalar
HoweVr, Incrcaved compieity ol simuitarneous insireuon unnE stalled. Notce, bowever, tte execuied, and wben they can wmie their iesus
Ppe ine. we visualize that he processor possesses such
1
execution Superscalar processing poses vanous
in
issues and operaling constrau ntis. 1hese 55ues are
eg sub is actualy aot depeodenl on the a desinaion mgisters. It
easures that ao dpe
instrction on
anoru s esuus Prcr o tne
mpie units of scalar pipelines, then such implementation is
be tackled in order to make superscalar
it can be execu
structioa uniess in-or s Cxcuiru 0a anies
nunaning he Tlow and logic of
processing 0 u is CpeiEnc, as
caled as upercalar execution of Instructions in the Pipcline is not capable of executing thas insuos whuch

processor. Processing in such CPU is called as Superscalar

smoothly and provide the desired performance improvements.
the previous instructioas in
the program oroet
s it s the aluditbonal logc bDceded 1o collect the
processing The function unit (ypicaly dy whee Retirtng Uait: ujon. Sice te
Meaning, suppose we consider Execute (EX) stage, processor
H 11.8 OUT-OF-ORDER EXECUTION
subtracting 2 from r3, 1s cureny
sdle. Inas is
exauy
esuls
esecue
or a e uuos
. the results are also received Oul-
proviOes Suaient resources to actualy execute 2 or more nderrstand Out-of-Order (Oo0) eaecution, it is requirtd he OoO becomes usetu
schedukng. is reiring unit collects and aranges uem o C
dynamic plete or
instructions simujaneousiy. topipeuned
understand the concept
ot lnstruct norma Ou-of-order ezecunon
ns
non
oecessarily in tem in-order. Therefore, insNu
progra order.
The Fig. 1.7.1 shows superscalar execution schematie, with archilecture Uhat 15 nol supporting o. technique used to exCcue in which they
etire in the original
2-issue Super-Scalar pipelines A and B. program-order (Le. ue wih out of-order execuuo
SACHIN SBAW Vnture
appear in the uset POB
o0), the processor would
ch e
of the instructo

lech-Neo Publcat ons.

bere Authos mpa
DE Auhors nput maoYalhon
A SACHIY SHAH Veature
eeh-N
o Publications
 COA MU-Sem comp)
Digta
Digal Loga cOA MUSem 3.Comp) ti-core processor consists c Advanced Processor ero
(11-201 Principles o AGVenceolESO andBuses A tYpical
u of
two or more
ang with a split
(wa les
sae eing facod in the desigs a
11.9 SPECULATIVE EXECUTiON execution alomg the other path is needed to be taken
shown
tparc nstrction cache alledt yeenns
up LI Cache ndsepaae ot ihe maih-core pae
However, since only one instruction t tighelv
The Speculaive eAubos In caied LI-D) and a
ma oes m muo co
eltes to the exeuiono eLecuuon, this method doesn't equire higher a Data cache local unified
nt of
eysually sually a
On-board ighdy ed ey ot comprncnts and higher witchng eds
pe
processor resources. 2 cxhe coupled
DOGs may may ot
e eleud n we program unified L.3 cane s aiNo implemented. ake he procer chip to heal ecesmvely puting
n on the trogpency of operaion.
inth
ibnabanches srctures appearing 11.10 INTRODUCTION TO comcept o noogy is mainly
t is te to ths s sed along-with Out-of Order execution
MULTICORE PROCESSOR
The
round the coepoPare computing. which can
revolving
Ing
Ypicauly
igher mimber of eoes allows
e es competan on heavy ane
eey
ARCHITECTURE significantlyDoOx Coput speed and efficiency by Can e lewered wduce te neng or a
te. Dyar stracton cheduling) and Satüic/Dynamic r
bench including two or more central processing units (CPUS) in a
predieion lopc, to miaimize te pipeline hazards and ne or
te aCs in paraliet prucesing is providing single chip. This recduces he system's heat and power
econecton betwork rebated imes: Botenecks
Mulupe cores ar tne procesgor ina singie FU package. Muli- consumption. 1his means mucn beuiet perfarmance with less he multi-
ht e sc 0 ieierconnecn n
ection discusses Mutticoreng
ethet te er Dyamic brunea o logic
gnamic bnanch pPprediction Neeasingiy popular. Following
or the same amount
or energy. i oth
or
y
r comditonal branch and koop insunuctions to
processor architectures.
The architecture of
a mulicore processor enables heen grocessor cores, loca
exalernive tsruon equeces tnat wola e sye
11.10.1 Multicore Processor nication between all available cores to ensure that the cache memories, main memoryand other
Archftecture cO
processing lasks ae aPpropmialely distnbuted and assigned components
ouc e speculatire execuion runs procesor archliecture refers to an architecture in
tkcore among the cores, accurately.
yNewer
ypes and design of buses such as in fib and are
o coetrl tis issua.
P Hene o ecn, oecoue and execute he wcn & Blngie

D more han
payae proxessur ncopoes he core
one Processor.nese proessor cores
logic
At the time of task complction,
the processed data from each
pgrin oruer speculatively, either are
in
paageu a core is delivereu bak to e sysiem bus by means of single
a
Eects of parallellm-Mul-core allows mulbple
nanve as. Ths ut lizes the
in0 Singie iniegraled Circuit.
These single integraicd Cireuits are khOwn as a dic. shared gateway.
l 0abos on de proceso
PRce nrdwre reources and minimizes penalties due Multicore
execunes dáifferent threads of a processor or copey
to stalls cread by data and covetrol (4. Instruction) hazards. nmpe processor cores
processor.
This lechniqae sigany enneS PomncE Comgareu
differeat proce
Fy, ae e 6yaca to singie-core processoOE ne equivaient ciock spe
a
a
Ehae of deOrder eecatlon reduces the The oh This makes handling of instructons sireaums
tho
Sas and tume wasuge by executung insinuctuons
by data exploiting paralklism at
the pe cores is that of Multicore ectinoiogy is Vey usehu n compuialoa
beavy O

the paralel prcEssing cairamen, caEnging a

a

et an be used pplcauons,
Ana Sun as decoding/encoding. J-D
Mulb-coe po
rehaiques mulúthreading and muli. Cache and memory ssue
ogether provide optimized tASKS
results tasking, u
video ediung. o
OEvEr high perfomance of the proceuor and system. and thereby achieve gaming. multumedia strtaming and L a
overall grealer sysicm pertokance. have privately held or oghaty coupled
p E Eecuon, therefore, uses system resources lssues In emories. mult-leve ANe
ey
meaon equence in predicted (speculathvely) a 11.10.2 Hardware and Software
eEE Muticore organization
CPU Core
1CPU Core n
1
pulh or all atemate pas.
u e Ve prediction i
Tect. reuls geered by
CoTect, ethe rEuis
geerai wwdely in the current proiocois or ubsapual cmpiekuly
a BESsly
oE eEuon Mulu Core Architectures
are used moet
e e
e committed. I the prediction goes
ra Dack and penalty due to
wrong.
atcd processors.
Cary our etnenE Cene
cuEeDt maeL

stallss is
growth and treguery
incured.. saturation reaching in the organzations
The Speculave eecution is of two ditferent ypes
LLZcache 2cache
With
a makamurn lor inge aip
r esgi&11.10.3 Muticore u
hng implementations or muld-coes,
Mucofe orgLaa leave od
.
folows:
Eager Esecutiom : In this type of speculative
ecuon,
ufactures are putung up
mn
cacth much smaller
core 1s
und reluave
gncr Differeat
on the basis of folw ng chcna
ncoeeTxEASOr
dtiomal branch is enconte
eecuton. *Ce
Tunctionan
then a CPU.
t a betir
Number oores e
d
rcton E
sequrnces (one when the condition
aer ome when main memory nEe Cores work
together for processing
4
d NuraDet or ievels of
cacte meones in the Molticore

I anner and with improved pertoric

is no) The O

prOces eurese uawancn etecue cores allows lor

the treey u
ae e cahe nEINCS
insirueuo wnen
pahs. uE
uo a
ko,
ip I1.10.1 : Multi-core Architecture ue ot mulaiple
thus reducing
the
iemperature Cupung or
opes a Multicore Processor
pn reuls re committed. This technology s Ess
1O be reduced,

iasre
re alloweu The Fg 11.10
showy diferene
cashe kves.
most commonly used in multicore cores, wiuh diffrerear meDory
amount of oroes E to stalls but
Equires lar
ceswors, wtiere two or more yem and with mulu ganizatlons

pocesOr reource requircment

e or Nuch

CTeaes
simullancously and concurrenlly-in-ume, a
Multicore-bauscd processors
as a single
syie
run
res On ndiwidual cores iTL
aUnt of paralelism. Modale
when multiple branches are considered. hnd
Predietlve Execution
pplcaos in
In this tyr .EVery o ditior
peculatively and instnuction workstalions and server.
Predcled
wucn
ype or execunon ere
y
e prcdicted path, is exccuted. In this
in no penaity t pedictuon geN
The Fig I1.10.1 shows
archilecture,
a typical Mulli-core processo
A SACHIN SEHH Veeture
coTect. herwie, penaliy due o slall is incurred and
a

TerhNee Publiestionanmau Wbe Avthors npire mnoplioa pie

ACMW S72AN Veature Teedh-Neo Publiratiens
 oigtal Loges cOA MUSem.3come
Diotal LogcaASem.3-Comp)
PaneiesO eo no Buses
11.11 RISC AGAINST CISC OVanced Processor and Bus
CPU Core 1 CPU Coe n CPU Core 1 CPU Core n 41s rentiate bethw
DitereAtidta berweGn ** N Se Comgles atrucdion Set
RISC and CISC
25 roceso
No KEserSmal
ofCPU
sze ot Kegsirr n
AUOa. May 17. 10 Marks gi
L 2cache 2cache Dec Marks 17.5 a 34

01111.2 What are the differences between otthe instructions nsuos

RISC and cisc 0) execute e Anounl o

.
procesors? SIngie e ckoct
RAU-O.3a.May 14. O.301, Aay
15 SMarks 1ALU Instructions
wortALUs
() Dedicated LI cache (6) Dedicated L2 cache 1arks. 0ly with Register| with all types (Register,

o
perands. Oly memory. LO) of operands.
UQ. 11..s Compare RIsC and
CPU Core 1 CPU Core n Core Processors ADe surueoCsA suuo
LCPU
L e 1

1Pu Core n ANO 1d), May 16.5 IMarks

UQ 11-13* ain reatures of RISC and CISC
processors. Usually implemented by iceneu
d (.
by

cootrol unit
2cache ache
****
H0LDec4101M
argwired

Reduced Instruction Set Computing (RISC) M 11.12 INTRODUCTION TO BUSES

main memory
Reduced nstructon
simplification of architecture
opnE
Dy reducing e
c oe Single Bus CPO
number
main memony *** 5plan **
Contention and
(C) Shared Lz cachee
instructions in the instruction set 22 Bus iierent
(d) Shared L3 eache
Complex Instruction Set Ccomputing (Csc)
ethodto resolve it
11.10.2: Mals-core Organizatios

Mutdcore processor organization with

Complex InstructionSet Compuang ( o Compooents of a CFU ud
ache
dedicated L1
core processor organizaton with Shared 2
architecture hat is capable of executing complicalod or complex
and large number of instructions in the instrucuon set CPU are connected to a single intera.al bus thas makes the
This type of organizatios intercoanecon Suue
with
provides muiple processor cores npe o organi2ation provides multiple processOr cores Comparlson of RISC and CISC ing the CPU to the memory
splt dedcaied loosely coupicd Ll cache memory wul splnt aealcaicd oxoely
O
"
ycpleo uninea Lz cache memory.
and
iniermal tughuy coupied shared
copica LI cache memory and
Instruction Set Comples nstrucion Se
ics is coanetnd to the CPU via Memory Data
his orga
unuied
cache memory.
Lz Sr.Reduced Register (MDR) and the memoy ares egsier (NMLAR).
comnony
architectures having
prevalent in ocessor Lnis organuzADO commonly prevalent n processo mpuuing tlklbJ e abvantages of using iairmal is arrangeens are
2-evel cache sysiem. naving 4-evel cactie systetns navng
EAnpie. improve
Peatum Processor performance c essors menaoned in a) above.
The
1Limited or Reduced Comple
ot strcuons 1
) Simple structure achilecture allows sumple controls.
Example: Core Duo
Processors DEEOr instruchoas inumber (u) Ease dt Inier-reguster oganzabon Cu space
(Muucore proceseor organlzation with
dedlcated L2
ucore processor organization with Shared L3
Ucuon set Ess|E u " minimizanon IS t
cache cache
This type of organizaion provides multiple his ype o org
processor o
Limited number
GESAdulessing Moues
riallyContro
(usually CPU
dedicated loosely o
pruDCessor cores widh dedicaled looe
split dedicaled
wdh splat
loosely coupicd LI
iuple 1ddresing Memal bus
emory and ache memony aa
intermal loosely coupled
dT
dedicated unified L2 cache memoy. aniemal loosely coupled un
e memory. mber
This organization is commonly added with external tightly c LAmited oumber of Lage
prevalent in processor 5
ec
performance
navng
over
*-evel
cache syMens having
processors mentioaed
improved
mcmory
pertormance.
for additional f
Snared unified L3
mprovement in the system instructio orn Lnsiracd a
in a) above. sUly Iess tan S
Example: Xoon and i-Core Processors. This organizauon ts
architectures ang
commonly prevalent
in processor
Fued Instrnuctiod iot
Yanabic
formaInsur
su o
Bus Modnle
ievel cache systems hav Om m
O e over processors mentioned (a),
an in (a), b)d All instnicuons e varie
in
d (6) with Da
he Ample: Zcon
Processo Example:
Zeon
and i-Core-3,5, 7
(i3, i5, i7) e S1z Ana correlation
11.121:Slnge Bus CPU Arehltecture
Tech-Neo Publicatioas ee Authors inrpire innorativa
A SHCHIN SiAH Featare
*****
A SACHN SHAN Venta
Ubere Autbery pure
ech-Neo Publications
In this organizabon
Buses Poling or kOg
rority method
The Bus Arblter decides who would become cument
bus les ctvanced Processor eno
are Lenena upose regsiers. In this method, e devces art assigned uniqu
-I m CDinler s Regster
mastet.
There are two approaches to bus arbitration: omplete to access une tbus, but the prionities nd
wAdVatages
that keeps track
of changed to gVe evey dcvice an his method generates
o Centralized bus, arbitranon A Single bus arbiter opportunity to fastesponse
nstruction peromns nie requircd arbitration.
bus. *Ces te mONt
Kegster Regisier that slores hexible method It can implement
Instruction Opcode eceived tom uE tbe masking and
o Distributed bus arbitratlon : Al
- Memorn Address KegisterE
devices participate in
o MAR
KEgser e selecuon ot the next bus master, Bue BusyY Disadvantages
y Auress to be accessed, can be se

* e Extemal Address Bus. a 11.13.1 Methods of Bus Arbitration ware cost is high s large
aumber ot coarol unes a
o MDR Memory Dala Regtster : quin
Kegisier a suor TYpesof Bus Arbltration
the Memory
the memory). can be soen
as to
oen as Front end of the Externa wen Tecnniques or Bus Arbltratlon
1.13.2 Multiple Bus (Multibus) Hierarchy
Data Bus There are thiree bus arbitration methods :
Uenerally, single bus architecture
Two lemporay registersY (ALU Input Temporary Register) has processr * cho
() Daisy Chaining method h nd bo devCEs ovEr
cmporry KEgiser) are ded to the ngieh syse
put bus which has
bus and conrol
a
ALD. In
heu abence, the outpait ot ALU wouk be shonie It is a ceniralized bus arbstraion method. Daring cOnsbitaent
with its input, which is to any bus
be avoided in order to keep the cycle, une bus tmaster may e any ueve e procesAor or
Data Iniegnty over the
single bus system. any DLA controler Ut or anyDus s
11.13.2 I order to improve the performance of
the system

11.13 BUS ARBITRATION AND

bus. The bus mastening device checks for
Coneeica to the
whether the When Buas busy signasoc seeu,
0e or more devices
aveeraircny
multiple buses forming the malib
in onder to have all higher speed

MULTIPLE BUS HIERARCHY Bus busy line, If

the y sampling the may requesE 0 ue os
e a ga ine
dcvices coneciedooe bus a wer
iei
or u guence (it is coanter), the connecied n daffereat bus. 1hererCre along
y devices may ask for the buses by
chance lo occupy on one bus aDa ow
UQ 1113.1 What is bus arbitration2 Explain ang ue e
bus arbiter, in response the
generaies Bus Gra Ue
the bus. Therefore. polling pplies rolating prlority. anoherbus, serd comsICOn O

racion?
two
AU-O.Ca.
tachniques of bus arbitration eyuestng
y-cnauned
E ges
devices.
through
ue Ds urun signal
The first
gets the
Advantages There are bwO widely used mulbbas hierarchy archutectures.

Dec. 14,0.Sb. Dec Ths euod doeES not Tavour any particular device and
GIC 1O
May 1a 10 darks procesxor
Arcniecnure with local bus and system brs
n this architecture the processor or CPU with its
UQ. 11.15.2 Explain Bus contention and dilferent 2 The method is also quite simple.
. one device tails, Uhen enare system will not sop working
L Cne enOY es
the proxesso

Pethod to esove it. Disadvanag L cacbe me mory through the backside bus( BS8). The
A.0.40Dec 18.0.4A. May19.101aks E||Ba BUs
-

A 008 relers to the process by which the curent

A

ca
Masterina
Device N
Adoing bus masters 1s dirterent as increases the mumber of xO Dus s hgh speed us and t connects to
address lines of the circult
cn ieaves the comtrol of the bus and the system
passes it to another bus m ( FExed priority or independent Kequest meth
The sysuem bus (i4. RCl bus) is operaing at relarively
an The
controller that has access to abes ina
at an instance is known as
bus at
In this method, the bus control passes from one device o
Ds master C Cy hrougn e cenurallZed bus arbiiet. Each devce through the norh brnugee yem bu mietaxes
nOcpenoent Kequest and Gran ines and they sge devces, networTing device, combunication
A con/bct may arise il the number of DMA controllers or any
omunicute with the bus arbiter through these pair od une
uer conrouers or processors (Tn fact any Bus m Advanages
comon bus at the same time, but access can be
ven to Ony one or thase. Only one processor or controller
It is simple to use and casy 10 scale. No.
ways low and equals 3.
of lines required are
Bus req 1
us Mastering
L
an enus masicr at ne same point ot urme. if there
C
e The user can add more devices anywbere
along the chain, upP
mupic Dus masies A55gnied to the bus simAilkaneously, O a cern maimum value. Bus Gnt 1
Video and
muluple signals woulld be mixed on ie buses. 1ns wo
Disedvantages Bus reaE Memoy
lead to noiSe and hardware damage.
Bus Contention.
Ihis situaton 1s calcaas
. e vauue ot pronity signca lo a device
To resolve these confucts, Bus Arbilration procedure is posion ot aster bus. 1e. Devices closer
is depe naling on
o Bus arouct
u Bus ArbilerBus Gnt #2
on ud
e S devices
master
r
pony and hog the bus, on he odhe
ed 0r the bus.
Module
must take into account the needs of Propagation delay arises across Bu Ne Bus N
the daisy chaan, n Dew ystem bus
establishing a prioty * r Aaing access to the bus. method. ArchileturE e DIS ADd
.1.13.4
2

3. If one device fails, then entire 3us Gnt "

system stops working
Teeh-Neo Publicatio as.. here Authors inpire inoovatioa Flg. 11.13.3 MERY3RA" Venun
-ASACHIN SHAI Venture
eo r'ublieations bere Autbury pe
 Logis COA(MU.Sem.
340
Digtl
Digtal Logic & COA (MU.Sem. 3 Co (11-26) Pincples c AGanco0 lcessot and Bus8 aced the artier 16-Biu bus standards voch
ea
as 16-BiISA
ples ot Advenced Processor end BU
(6) Three bus architecture (Thre bas hierareny The ISA bus was designed to operale at system speed of ended 1SA (EISA) buses. Ithad many wnigue features
33.39 MHa
x32 bits (4 Bytes) -133 Moy
This architecture has intertaces oue poe 4.77 MHz and was later om upgried to 88.35 MHz wadesigned to be peen, evrorment s
Ddge connecting the
and triendiy bus A a 18% pin capable of transfering data
133 MIB/S
asct
to hre lo tben standardized 5 MB/% ot 1SA D

connecied o e mg rcesor local bus th ocoefiguraion capabilioes inchless

explained above.
ce component called as th ougha for
nuga North Bridge and it perpheral
eT sahurd bus added which is a low speed bus it *e
cos e uo usteE
eavely 0w speed
tns ous ceonneea
BA DUS)

uevoes suchas nuran uecuoa

Pig 11.14.11&-Bin 1SA Bus -52 Pn IaterAe
coCDected
operaing
to egcy
on uen
odevices and slower
ISA bUs architecture through anodr
cpabites take care of al
yCl ype o peripoer
skhreses, DQ ad DMA

devces and senal and paralel parts.

gvesa
-The ISA Bus was originaly designed for 8-Bit architectares called as e
llows it to be
s aetlecture of PCI Bas SUppos iner bunts ype of dia transfer wncs
Dtore 5ysiem structurod appearance with
Ahiterues Therefoe
the hus is wvsilahle in 2
s 16-Bit
ven ienae eesiy win aimost all types of eurEs thal data bus is cottnuaily hued wu

medium speed devices connerted

to system devi 1e l us Biehiiectut connecting different TDasbus supports bus mastering. thertby
g
bit version and 16-bit version ypcan a sn0WD m Ue hg I1.143.
system dee uamber of ime li gent penphe
ae o bus

.
speed devices connected to 10 bus.
Rafures ofB Bh iSA Bus
aekae hgh throoghput, high ponily tas
Festure of PCl
concueney echmology tnc
Enght data lines icure supports

Eight iotemupt roquest levels PCI bus adds anouner Der 1o the tradiuonal inlerface between
CPU and V devices.
at mcroprocesso penies smuacotsy

20 ddess ines
Enables to handle 1 MB of memory This tier bypasses ue staard O bus by inserting ancthe

bus berween CrO and O oevices. The lier is termed as PCI

Norma e aher

Feature of 16 Bit ISA bus.

P ments to the+5 vot d
BA This bus was developed for PC-AT Ype ot motherboard in
The PCI bus is driven using a special componert caled as
coonector. A +3.3 volt counector adds a key in 1213 positon
CIbndge.
prevent accideotal insertiocn of +5 vot dc R board o
O A
(a 5A Bua
wo card edge
s
e
coanectors
l A bord
widh b4 pin and
consisis of
S0 pin each. The
Due to ue aubove
oaN pssg
system bus i5 used to increase bus clocE speed and makes
+3.3 volt dc sio
Siamilarty, the +5 volt de slot is keyed in 5osl positoe to

terncion DeMc Panial Ports r pn compatible and ffñcient use of CPu's data bus. preveat placiag +33 vot dc board into +5 vok de slot.
o Standard bandwidth of PCI bus al clock speed of 3SI 66
lg Al-A31 (for Side A) and B1-B31 (for Side B). The
l1.13S:Bus system architecture (S-Bus hierarchy
36 coanections are availsble as Side C and Side D having Pin MHz and 2-61 pa
W 11.14 ISA, PCI AND uSB oeons i8 tor Side C) and Di-D18 (for Side D)
t sugpors o Dr aata ana A Dit BAdrEses. It hias nddressing
STANDARDs apacily at 16 Mb. Conbole

Ik bas hve adduonal

a 11.14.1 Industry Standard Architecture independcnt deVce inicnuge teuesu
(RQ9, IRQIL-12, IRQ1415) and 4more DMA
(ISA) cqucsu Acknowlcdge channels (DRQ4-DRQT). Procesor Lot B

ndusty Saard Arecture I uc rarnie (SA) so Provided in addition to

on AT
bus to 8/8.33 MHz"
bpeea is increased
standadid provding inteaationally
nuned as Motherboas) fe em boards (usually
resona
A31 Bue
C1 18 Pa
Computers (PCR). The us is based on 8-bit architecture and otlers
folowing fealnures

iSA us usedin PC/ PC-XT motherboand consists

Hg 11.142 : 16-Bit 1SA Bus - 52+36 Pin Interface
2-sIdes or edges to nc conacer Ana e Ca oe^ a
Side B. The Pins are standardized to have nomenclature as

.
9.2
Fenpheral Component
AlASI (for šide A) andBl-831 (for Side B). Interconnect (PC)
h provdes 8 data lines and 20 address lines. Thus
bus *y orMB. Periphenl Component laterconnect (PC)
was designed by
Modnle

ns I
E COMntee ot computer scientists set up
by BM. her
six 0ependent device com uter
intem international
39.Bis
for 32-Bit interface
for iversal
for 32-Bit System Architecture.
standard
Reques/Acknowledge Channels (DRQ0,2.3) channels.
143: PCIBas Arcaie SACETN SMAH Vesture
Tecb-Nee PublicationsWhere Authorr inspire innoratin
AALCHLN SHAH Feanure
rublication ere Aotdus s
 && COAMSem.scomo)
LogC
DIital Pdnciples ol Advanced Procassor and Buses
Transfer:
LDrerrupt Tr
This uranicr
Snaacket size and two wires foa power (+5 vohs and ground) asteu
(11-28) Principles O1 ACVENGeoesS0r and Buse Uransfer rate. t is suntabie
of m input device
aDigital Logic & COA (MU-Sem. 3-Comp 0 wS to camy te data On the power wies, the conpu
or a keyboar., whch will be sending ery
AAS e an interrupt to arn processor s bention suply up o 500 mulliamps of powerv
ceds
volt w EEES (such as mce) can draw
he p
62B63
For+5
hee evice activity) would
choose the intemuet

packet size and very

E DU. n
eimal gower from
ers) have

A94 Balk Trans bus. Hebs

cas h o
A62AB3 transt Or large data
.nrinter ofr external Hard cUmneted to be hh
0 cea
For +3.3 volt bigh o
runsfe tane
in one big the bulk
packet, uses the Hot phagzabilhty USB device can be conoee
BS4
eoeves packet. bulk transfer mode. : A
ece
block o
" data is sent and verifñed to make sure it is
coect
pow ring offa PC. The phlug and play' feare un

es
ue DU
Pig. 11.14.4 : 185 12in FUi BUS cne o

auto-detects it and asks for the device driver. If the

A

Isochronous
s transf has large pack ue gocn
neugence in the UsB
and handimg
oYEs

e
-01
raasfer
Us wdth.
rale of 133 MB/S for 32-Bit and 266 MB/s for n
device has already been installed or in the system datahase of andvery
Multi-meola oe
A
ivochoec Sh
the
as
O Swappable
be:
: USB devices are hot swappabie;
USB devices meas you
drives, the computer auto-defects and starts the host in real- time, apd
can
Each PI
work with 32-bif or 64-bit bus width.

bus have 256 devices and maKimum of 230 P

communicating to It. USB devices can be connected and
disconnccted at any hme.
etween
e
emor correcuon,
oevce and
us anEving the highest data transfer raies. Hab architerture: The devices are
Connected o an USB bub. he
bot dausy chaineu
UsB ub s a
USB has two ypes of connectors, nameily ype A and 1ype Ports
E E nerang o the r on one side aDd
t uses 3.3 V or 2.2 V 1or operaions and consumes less Features of USB on oer saiEs.
B conneciors. ype A Conneetois ilEtaee 1o uE 5ystem side OD penpieral dEvxes
the host adapter. every asacDo
and are called as Upsream connector. 1ype B connectors e computer has centne the CrU/software imtars
t
:

PCI bus is device independent which means it can be used to : Up to 127 devIces can counect
to the gn the Ru
interface on the device side and are called as Downstrearn Number of devices 0 e UsB bus. Hence, the overhead
coanect different types of devices such as hard disk opepuers that too,
controllers, sound cards, multimedia controllers, LAN cards
connector. eTases when rge Dunr
of transactions,
conaected
Many USB devices come with their own builh-in cable, and caDies can run as lmg nvovIng the ge number
Maximum distance indual b pu to sieep by the
devices can be up to 30 meter (i USB devices can be
SuPP echniques such as Grecn Machine concept, melers, with hubs, oer arng: Mlany
woro ue cepae e es a powet-sav
wave switching and Faimess algonthm for Bus
has a socket on it that accepis a USB B connector. cascaed) away
trom the host. host compuler
Relecied cables bus has
With USB 20, the
Speed of data transfer:
mastenng mode.
and USB 3.0
480 megabits per second
nudinurn data rate of
11.14.3 Universal Serial Bus (USB) 3 allows marimum data
rales up 10 gtps.
i

rEquirement and types of :

cable A LSB cable has apter Erds
-Universal Serial Bus (USB) is the international universal ower
bus/port inerface standard for connectung penptberals and v Yp
w tne conpuler sysiem and works on the
0eces Pig. 11.145: USB Type A and Type B Connections
syncnronous era
ala comiuinmcatbon prolocols& The USB standard uses "A" and "B" connectors
techniques. Simple design with only 4-wire interface and its

sear
n 0and ot o
A connectos head "upstream" toward the computer.
port Curendy, it has become the de-facto interface standand Bconnectors head "dowastream'" and connect to individual
acvices.
or allmodem penpherais and Do devic
Ompuicr coes with one or. more Uaiversal Serial Bus yPo do aata rahsrera
connectons on the back. A operngy e
USB so that the installalon or the device dnveS USB works on sychronous etial Daua Commun
15
uck techoique with default
y pauou g transfer protocol and therefore has different types of data transfers
compuler (including parallel ports, Senal pots
a
for lacilitating diferent class ot dala.
cards), UsB devices are very simple to interface. The

ue way to conpect u to 121d

casy-lo- , n up. t queries all of the USB devic

connected to the bus through the USB Root Hub and assigns each
oe an ress. process s Caled as USB enumeration.
I is capable of interfacing to slow and high-speed it is

devices as well as output devices at the same time with oe. 0Eces ae said to be enumerated when they connect to
Extemalmas5 storage devices and streaming Multi-media ost pter aso finds out from each device Modnle
(Audio & Video) devices. u ransier t wises o perform. 1Tbere are Four
ditterenl Dala Transiers supportcd by USB Standard
USB Cables and Connectors Ccontrol ranster : lhis transter has small packet size and
Connecting a USB device to a computer is Simple you 1ind ower data rasier rdes. lt 15 used for sending and receiving
the USB connector on the back of your machine and plug the Control and Status Data packets respecuvely.

US5
Tecb-Neo
connecor no u
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