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Advanced Computer Architecture

This document is the exam for an Advanced Computer Architecture course taken in the fall semester of 2009 at Pokhara University. The exam contains 7 questions testing knowledge of computer organization, generations of computers, VLSI technologies, memory access techniques, pipelining hazards, virtual memory, cache memory, RISC architecture, vector/array processing, and multiprocessor systems. Candidates are required to answer all questions in their own words and the exam is worth a total of 100 marks over a 3 hour period.

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Adhikari Sushil
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46 views1 page

Advanced Computer Architecture

This document is the exam for an Advanced Computer Architecture course taken in the fall semester of 2009 at Pokhara University. The exam contains 7 questions testing knowledge of computer organization, generations of computers, VLSI technologies, memory access techniques, pipelining hazards, virtual memory, cache memory, RISC architecture, vector/array processing, and multiprocessor systems. Candidates are required to answer all questions in their own words and the exam is worth a total of 100 marks over a 3 hour period.

Uploaded by

Adhikari Sushil
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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POKHARA UNIVERSITY

Level: Bachelor Semester – Fall Year : 2009


Programme: BE Full Marks : 100
Course: Advanced Computer Architecture Time : 3hrs.
Candidates are required to give their answers in their own words as far
as practicable.
The figures in the margin indicate full marks.
Attempt all the questions.

1. a. Describe the structure of a computer system. How does computer 8


organization differ from that of computer architecture?
b. Describe the various generations of computer. 7
2. a. Explain the major VLSI technologies and advantage of VLSI in 8
computer architecture.
b. What are the techniques applied to accelerate the memory access and 7
transfer?
3. a. Explain the data dependencies ad branch penalty piplining hazards. 8
b. Discuss the address translation technique in virtual memory.
7
4. a. Describe page segmentation in virtual memory. 8
b. Explain how cache read operation take place. 7
5. a. What are the issues in the design of a cache memory? Describe. 7
b. Explain RISC pipelining with suitable example. 8
6. a. What is vector processing and array processing? Explain with a 8
suitable diagram.
b. Explain about multiprocessor system organization. 7
7. Write short notes on (Any Two) 5×2
a. Update policies in cache
b. Translation Look – Aside Buffer
c. RISC instruction

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