AD9371/AD9375 System Development User Guide

UG-992
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com

System Development User Guide for the AD9371 and AD9375 Integrated Dual-
Channel RF Transceivers
INTRODUCTION
This user guide is the main source of information for systems are interchangeable unless otherwise stated. The sections in this
engineers and software developers using the AD9371 family of user guide are organized to simplify navigation for users to find
software defined radio transceivers. This family includes the the information pertinent to their area of interest.
AD9371 and the AD9375. For this the user guide, these devices

PLEASE SEE THE LAST PAGE FOR AN IMPORTANT

WARNING AND LEGAL TERMS AND CONDITIONS. Rev. B | Page 1 of 360
UG-992 AD9371/AD9375 System Development User Guide

TABLE OF CONTENTS
Introduction ...................................................................................... 1 Reading the ARM Version ........................................................ 99
Revision History ............................................................................... 4 Performing an ARM Memory Dump ...................................... 99
User Guide Section Description ..................................................... 7 System Control.............................................................................. 102
System Overview .............................................................................. 8 Control of Signal Chains (Tx/Rx) .......................................... 102
System Architecture Description.................................................. 11 ORx Path Control ..................................................................... 104
Software Architecture ................................................................ 11 ARM GPIO Operation ............................................................ 107
Folder Structure .......................................................................... 12 Tx Power Control ......................................................................... 108
Software Integration ....................................................................... 13 Power Amplifier (PA) Protection ............................................... 109
Modifying common.c ................................................................ 13 PA Error Flag ............................................................................ 109
Developing the Application ...................................................... 14 Protection Algorithm............................................................... 109
Serial Peripheral Interface (SPI) ................................................... 17 API Commands for PA Protection ........................................ 111
SPI Configuration Using API Function .................................. 17 Reference Clock and SYSREF Connections .............................. 113
SPI Bus Signals ............................................................................ 17 Connections for External Clock (DEV_CLK_IN)............... 113
SPI Data Transfer Protocol ........................................................ 18 DEV_CLK Phase Noise Requirements.................................. 113
Timing Diagrams........................................................................ 19 SYSREF Requirements ............................................................. 114
JESD204B Interface ........................................................................ 21 Synthesizer Configuration........................................................... 116
Receivers (ADC) Datapath........................................................ 22 Connections for External LO ................................................. 117
Transmitters (DAC) Datapath .................................................. 41 Software Configuration ........................................................... 119
Link Establishment..................................................................... 55 RF PLL Frequency Change Procedure .................................. 122
Hardware Considerations for SYNC Signals .............................. 56 RF PLL Resolution Limitations .............................................. 126
Compatibility with Xilinx JESD204B FPGA IP ..................... 56 Gain Control ................................................................................. 127
Multichip Synchronization........................................................ 56 Variable Gain Elements in the Receiver Datapaths.................. 127
Multichip API Function Description....................................... 58 Gain Table Format .................................................................... 129
System Initialization ....................................................................... 59 Gain Table Programming Description .................................. 132
Modification of common.c for User Code Integration ......... 59 Rx Gain Delay ........................................................................... 132
Data Structure Member Initialization ..................................... 59 Manual Gain Control, Hybrid Mode, and Automatic Gain
Initialization Sequence............................................................... 61 Control Overview..................................................................... 134

Example Code ............................................................................. 61 Manual Gain Control ............................................................... 135

Source Code Examples .............................................................. 62 Hybrid Gain Control................................................................ 136

Quadrature Error Correction, Calibration, and ARM Automatic Gain Control (AGC) ............................................. 137
Configuration .................................................................................. 83 AGC API Commands .............................................................. 143
ARM State Machine Overview ................................................. 83 Application Programming Interface (API) Programming
Loading the ARM ....................................................................... 83 Summary ................................................................................... 144

Initial ARM Calibrations ........................................................... 84 Summary of the AGC Parameters.......................................... 154

Tracking Calibrations................................................................. 85 Digital Gain Compensation, Slicer, and Floating Point

Formatter ................................................................................... 155
Tracking Calibration Scheduler ................................................ 85
Slicer API Commands and GPIO Information .................... 159
System Considerations for ARM Calibrations ....................... 88
Floating Point API Commands .............................................. 161
ARM GPIOs ................................................................................ 96
Filter Configuration ..................................................................... 163
Initial Calibration Errors ........................................................... 97
Receiver Signal Path ................................................................. 163
Tracking Calibration Errors ...................................................... 99
Rx Signal Path Example ........................................................... 165
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AD9371/AD9375 System Development User Guide UG-992
Transmitter Signal Path ........................................................... 166 Isolation Techniques Used on the ADRV9371-N/PCBZ
Tx Signal Path Example ........................................................... 167 Evaluation Board .......................................................................273

Observation Receivers Signal Path ........................................ 168 Unused Balls ..............................................................................276

Observation Receiver Signal Path Example.......................... 169 Power Management Considerations ...........................................277

Application Programming Interface (API) Data Structures Power Supply Sequence ............................................................277
and API Commands ................................................................ 170 Power Distribution for Different Power Supply Domains ..277
Observation Receiver (ORx)....................................................... 172 ADRV9371-N/PCBZ Evaluation Board Power Supply Block
Observation System Receiver Details .................................... 173 Diagram ......................................................................................279

ORx AGC, Hybrid, and MGC ................................................ 175 RF and Clock Synthesizer Supplies.........................................280

Observation System Receiver Front-End Programming .... 176 Demonstration System Overview ...............................................281

TDD Configuration and Setup ................................................... 178 Initial Setup ................................................................................281

TDD in the Mykonos Evaluation System ............................. 178 Hardware and Software Requirements ..................................281

API/DLL Commands for TDD Configuration .................... 190 Hardware Setup for External Tx LO Leakage Calibration ..285

General-Purpose Input/Output (GPIO) Configuration ......... 195 Hardware Operation .................................................................286

GPIO Operation ....................................................................... 196 Transceiver Evaluation Software .................................................287

GPIO Manual Mode ................................................................ 201 Installation .................................................................................287

Monitor Output ........................................................................ 202 Starting the Transceiver Evaluation Software (TES) ............287

ARM GPIO Interface ............................................................... 209 Normal Operation ....................................................................289

Tx Attenuation Control ........................................................... 213 Configuring the AD9371 .........................................................290

Secondary Serial Peripheral Interface (SPI2) ....................... 216 Programming the Evaluation System .....................................301

Rx Manual Gain Control ......................................................... 218 Other TES Features ...................................................................302

3.3 V General-Purpose Input/Output Overview ..................... 221 Receiver Setup ...........................................................................305

3.3 V General-Purpose Input/Output control ..................... 223 Transmitter Setup ......................................................................308

General-Purpose Interrupt Overview ....................................... 225 TDD Mode .................................................................................310

Auxiliary Converters—AUXDAC_x, AUXADC_x, and Scripting .....................................................................................315

Temperature Sensor ..................................................................... 227 DPD, CLGC, and VSWR Measurement (AD9375 Only) ........319
Auxiliary DACs ........................................................................ 227 DPD Overview ..........................................................................319
Auxiliary ADC .......................................................................... 230 CLGC Overview ........................................................................323
Temperature Sensor ................................................................. 232 Voltage Standing Wave Ratio Measurement Overview .......323
RF Port Interface .......................................................................... 236 DPD GUI........................................................................................324
Series and Parallel Impedance Models .................................. 236 Waveform Setup ........................................................................325
RF Port Impedance Data ......................................................... 237 DPD Setup .................................................................................327
Transmitter Bias and Port Interface ....................................... 245 PA Calibration Configuration .................................................329
General Receiver Path Interface ............................................. 246 Error Messages and Debug Information................................331
Impedance Matching Network ............................................... 249 DPD API ........................................................................................332
Board Layout Design Recommendations ............................. 255 ARM Setup Commands ...........................................................332
Printed Circuit Board Layout Guidelines ................................. 256 DPD API Data Structures ........................................................334
PCB Material and Stack Up Selection ................................... 256 DPD Functionality API Functions .........................................339
Fanout and Trace Space Guidelines ....................................... 258 CLGC Tracking Calibration.........................................................341
Component Placement and Routing Priorities .................... 259 CLGC Configuration ................................................................341
RF and JESD204B Transmission Line Layout ...................... 264 CLGC API ......................................................................................342
CLGC API Data Structures......................................................342
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UG-992 AD9371/AD9375 System Development User Guide
CLGC Functionality API Functions ...................................... 345  Guidelines for Developing and Troubleshooting a DPD
VSWR Tracking Calibration ....................................................... 346  System ........................................................................................ 352 

VSWR Monitoring ................................................................... 346  Designing a System for a TDD Application.......................... 353 

VSWR API ..................................................................................... 347  External Loopback Flatness Requirements ........................... 354 

VSWR API Data Structures .................................................... 347  CLGC Convergence Time ....................................................... 356 

VSWR Functionality API Functions...................................... 350  DPD Limitations ...................................................................... 356 

Systems Design Considerations .................................................. 351  Other Considerations .............................................................. 356 

DPD Tuning Procedure ........................................................... 351  Typical Test Setup And DPD Performance ............................... 357 

DPD Model Save/Restore Functionality ............................... 351  TDD Setup Instructions .............................................................. 359 

REVISION HISTORY
5/2017—Rev. A to Rev. B Changes to Table 155 ................................................................... 207
Added AD9375 .............................................................. Throughout Changes to MYKONOS_getGpioMonitorOut Section..................209
Updated Layout ................................................................... Universal Deleted Figure 112; Renumbered Sequentially ................................224
Changes to Title and Introduction ................................................. 1 Changes to MYKONOS_getGpio3v3PinLevel Section ........... 224
Added User Guide Section Description Section .......................... 7 Changes to Table 163 ................................................................... 226
Changes to Overview Section ......................................................... 8 Added Auxiliary DAC Control Software Control Procedure
Added Figure 2; Renumbered Sequentially ................................ 10 Section............................................................................................ 227
Changes to Table 5 .......................................................................... 22 Added Auxiliary (AUX) ADC Readback Software Control
Changes to MYKONOS_setupDeserializers(…) Section ......... 46 Procedure Section......................................................................... 230
Changes to External Tx LO Leakage Initial Calibration Section .... 90 Changes to Example 1: SEDZ to PEDZ Conversion Section ........236
Changes to System Considerations for Tracking Calibrations Changes to Example 2: PEDZ to SEDZ Conversion Section ........237
Section .............................................................................................. 91 Changes to Impedance Matching Network Section........................249
Changes to External Channel Section ......................................... 96 Changes to Figure 151 ...........................................................................252
Changes to ORx Path Control Section ...................................... 104 Changes to Table 170 to Table 172 ......................................................253
Added Power Amplifier (PA) Protection Section and Table 92; Changes to Table 173 to Table 176 ......................................................254
Renumbered Sequentially............................................................ 109 Added Mykonos Tx1 and Tx2 Port Impedance Section.......... 255
Add Figure 48 ................................................................................ 110 Changes to Figure 159 Caption .................................................. 262
Changes to MYKONOS_setupPaProtection(…) Section ....... 111 Changes to Figure 161 Caption .................................................. 263
Changes to MYKONOS_getPaProtectErrorFlagStatus(…) Changes to Line Design Examples Section ............................... 264
Section ............................................................................................ 112 Changed Transmitter Bias and Port Interface Section to
Changes to Table 95 Caption ...................................................... 117 Transmitter Bias Design Considerations Section..................... 268
Changes to RF PLL Frequency Change Procedure .................. 122 Changes to Isolation Techniques Used on the ADRV9371-N/PCBZ
Changes to RF PLL Resolution Limitations Section ................ 126 Evaluation Board Section ............................................................ 273
Changes to Gain Control Section .......................................................127 Changed AD9371 Demonstration System Overview Section to
Changed Receiver Datapath—Variable Gain Elements Section to Demonstration System Overview Section ................................ 281
Variable Gain Elements in the Receiver Datapath Section ............127 Changes to Hardware Setup Section .......................................... 281
Changes to Figure 59 and Figure 60 ........................................... 132 Changed AD9371 Transceiver Evaluation Software (TES)
Changes to PMD Measurement Duration Section and PMD Section to Transceiver Evaluation Software (TES) Section and
Measurement Configuration Section......................................... 153 AD9371 Starting the Transceiver Evaluation Software Section to
Changes to Real IF Section .......................................................... 164 Starting the Transceiver Evaluation Software Section ............. 287
Changes to Rx Signal Path Example Section, Figure 77, and Changes to Installation Section and Figure 183 Caption ........ 287
Figure 78 ........................................................................................ 165 Changes to Figure 184 ................................................................. 288
Changes to THB2 Section and THB1 Section .......................... 166 Changes to GPIO Configuration Tab Section .......................... 293
Changes to Figure 85 .................................................................... 169 Changes to Figure 207 ...........................................................................301
Changes to Figure 87 .................................................................... 170 Changes to File Dropdown Menu Section, Figure 209 Caption,
Changed Programming Filter Settings to the AD9371 via API Figure 210 Caption, ..................................................................... 302
Section to Programming Filter Settings via API Section ........ 171 Changes to Tools Dropdown Menu Section, Figure 212
Changes to Datapath Trigger Modes Section and Table 138 .. 183 Caption, Figure 213 Caption, and Table 188 ............................ 303
Changes to Table 139.................................................................... 184
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AD9371/AD9375 System Development User Guide UG-992
Changes to Help Dropdown Menu, Figure 214 Caption, System, Added Figure 260 .......................................................................... 260
System Status Bar Section, Figure 215 Caption, and Figure 217
Caption ...........................................................................................304 1/2017—Rev. 0 to Rev. A
Changes to Rx Signal Chain Section...........................................306 Changes to Introduction Section .................................................... 1
Added DPD, CLGC, and VSWR Measurement (AD9375 Only) Deleted /src/example Section .......................................................... 7
Section, DPD Overview Section, and Figure 229 .....................319 Changes to Figure 3 .......................................................................... 8
Added Figure 230 ..........................................................................320 Changes to Developing the Application Section ........................ 10
Added Figure 231 to Figure 233 ..................................................321 Changes to API Sequence Section ................................................ 11
Added Figure 234 and Equation 57; Renumbered Sequentially...322 Changes to Figure 4 and Figure 5 ................................................. 15
Added CLGC Overview Section, Voltage Standing Wave Ratio Change to tCO Parameter, Table 4 and Figure 6 ........................... 16
Measurement Overview Section, Equation 58, and Figure 235 ...323 Changes to Table 38 ........................................................................ 38
Added DPD GUI Section amd Figure 236.................................324 Added Hardware Considerations for Sync Signals Section ....... 53
Added Figure 237, Waveform Setup Section, and Figure 238.......325 Changes to Data Structure Member Initialization Section ....... 56
Added DPD Setup Section, Figure 239, and Figure 240 ..........327 Deleted Folder Location Section and Figure 28;
Added Figure 241 ..........................................................................328 Renumbered Sequentially .............................................................. 58
Added PA Calibration Configuration Section and Figure 242 .....329 Changes to headless.c Section ....................................................... 58
Added Error Messages and Debug Information Section and Added Reference Clock and SYSREF Connections Section,
Figure 243 .......................................................................................331 Connections for External Clock (DEV_CLK_IN) Section,
Added DPD API Section, ARM Setup Commands Section, and Figure 47, DEV_CLK Phase Noise Requirements Section,
Table 190 .........................................................................................332 Table 92, and Table 93; Renumbered Sequentially ................... 104
Added Table 191 ............................................................................333 Added SYSREF Requirements Section and Figure 48 .............. 105
Added DPD API Data Structures Section, Figure 244, and Added Minimum Delay Requirements Between SYSREF Pulses
Table 192 .........................................................................................334 Section, Timing of SYSREF Compared to DEV_CLK Section,
Added Figure 245 ..........................................................................335 Figure 50, and Figure 51 ............................................................... 106
Added Table 193 ............................................................................336 Added Connections for External LO Section, Figure 52, and
Added Figure 246 and Table 194 .................................................338 Table 94 ........................................................................................... 107
Added DPD Functionality API Functions Section ...................339 Added Performance Limitations Section and Figure 53 .......... 109
Added CLGC Tracking Calibration Section, CLGC Changes to Example 1 Section, Example 2 Section, and
Configurations Section, Figure 247, and Figure 248 ................341 Example 3 Section ......................................................................... 118
Added CLGC API Section, CLGC API Data Structures Section, Deleted DEV_CLK, SYSREF, and External LO Section,
Figure 249, and Table 195.............................................................342 Overview Section, Connections for the External Clock
Added Figure 250 and Table 196 .................................................344 (DEV_CLK_IN) Section, Figure 51, and Figure 52;................. 120
CLGC Functionality API Functions ...........................................345 Deleted DEV_CLK Phase Noise Requirements Section,
Added VSWR Tracking Calibration Section, VSWR Monitoring Figure 53, Table 94, and Table 95; Renumbered Sequentially .......121
Section, and Figure 251 ................................................................346 Deleted Figure 54 and Figure 55 ................................................. 122
Added VSWR API Section, VSWR API Data Structures Section, Deleted Multichip Synchronization (JESD204B Mode) Section
Figure 252, and Table 197.............................................................347 and Figure 56 ................................................................................. 123
Added Figure 243 and Table 198 .................................................349 Deleted Connections for External LO Section, Figure 57, and
Added VSWR Functionality API Functions Section................350 Table 96 ........................................................................................... 124
Added Systems Design Considerations Section, DPD Tuning Changes to Analog Peak Detector (APD) Basics Section........ 127
Procedure Section, and DPD Model Save/Restore Functionality Changes to Half-Band 2 (HB2) Overload Detector
Section ............................................................................................351 Basics Section ................................................................................ 129
Added Guidelines for Developing and Troubleshooting a DPD Added TDD Configuration and Setup Section, TDD in the
System Section ...............................................................................352 Mykonos Evaluation System Section, ARM Input and Output
Added Designing a System for a TDD Application Section and Signals Section, and ARM Pin Mode Configurations Section......168
Table 199 .........................................................................................353 Added Figure 88 ............................................................................ 169
Added External Loopback Flatness Requirements and Added ARM Acknowledge Signals Section, Table 133, and
Figure 254 .......................................................................................354 Figure 89 ......................................................................................... 170
Added Figure 255 ..........................................................................355 Added Table 134 and Table 135................................................... 171
Added CLGC Convergence Time Section, Figure 256, DPD Added Figure 90 and Table 136 ................................................... 172
Limitations Section, and Other Considerations Section .........356 Added FPGA Output Signals Section, Data Path Trigger
Added Typical Test Setup and DPD Performance Section and Modes Section, and Table 137 ..................................................... 173
Figure 257 .......................................................................................357 Added Table 138 ............................................................................ 174
Added Figure 258 ..........................................................................358 Added TDD Finite State Machine Class Section, Quick Help for
Added TDD Setup Instructions Section and Figure 259 .........359 Programming FPGA/Mykonos Section, and Table 139........... 175
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UG-992 AD9371/AD9375 System Development User Guide
Added ORX_MODE[2:0] and ORX_TRIGGER, as Seen by Added Signals with Lowest Routing Priority and Figure 160 ....... 251
the FPGA Section and Example TDD Script in IronPython Added RF and JESD204B Transmission Line Layout Section ...... 252
Section ............................................................................................ 176 Changes to Table 178 to Table 181 ............................................. 253
Added API/DLL Commands for TDD Configuration Section.... 180 Changes to Example 5 Section, Table 182, and RF Line Design
Added Secondary Serial Peripheral Interface (SPI2) Section, Summary Section ......................................................................... 254
Figure 97, and Figure 98 .............................................................. 204 Added Figure 161 and Figure 162 .............................................. 254
Added Table 160, SPI2 Register Map Section, API Description Added Transmitter Bias and Port Interface Section, Figure 163,
Section, and Table 161 ................................................................. 205 Figure 164, and Tx Balun DC Supply Options Section ........... 255
Moved Impedance Matching Network Section ........................ 237 Added Figure 165, DC Balun Section, and Chokes Section ... 256
Moved Figure 144 to Figure 146 ................................................. 238 Added Figure 166 ......................................................................... 257
Moved Figure 147 to Figure 149 ................................................. 239 Added Figure 167, Figure 168, JESD204B Trace Routing
Moved Figure 150 ......................................................................... 240 Recommendations Section, and Routing Recommendations
Moved Selected Balun and Component Values Section, and Section ............................................................................................ 258
Table 169 to Table 172 .................................................................. 241 Added Stripline vs. Microstrip Section, Isolation Techniques
Moved Table 173 to Table 176 and Mykonos Tx1 and TX2 Port Used on the ADRV9371-N/PCBZ Evaluation Card Section, and
Impedance Section ....................................................................... 242 Figure 169 ...................................................................................... 259
Moved Figure 151 and Figure 152 .............................................. 243 Added Figure 170 ......................................................................... 260
Added Board Layout Design Recommendations Section ....... 243 Added Isolation Between JESD204B Lines Section and
Added Printed Circuit Board Layout Guidelines Section and Figure 171 ...................................................................................... 261
PCB Material and Stack Up Selection Section .......................... 244 Added Unused Pins Section and Table 183 .............................. 262
Added Figure 153 and Table 177 ................................................ 245 Added Power Management Considerations Section and
Added Fanout and Trace Space Guidelines Section and Table 184 ........................................................................................ 263
Figure 154 ...................................................................................... 246 Added ADRV9371-N/PCBZ Evaluation Card Power Supply
Added Component Placement and Routing Priorities Section, Block Diagram Section and Figure 173 ..................................... 265
Signals with Highest Routing Priority Section, and Figure 155 .. 247 Added RF and Clock Synthesizer Supplies Section ................. 266
Added Figure 156 ......................................................................... 248 Changes to Figure 202 and AD9528 Description Section ...... 286
Added Signals with Second Routing Priority Section and Changes to Figure 213 ................................................................. 291
Figure 157 ...................................................................................... 249
Added Figure 158 and Figure 159 .............................................. 250 7/2016—Revision 0: Initial Version

Rev. B | Page 6 of 360

AD9371/AD9375 System Development User Guide UG-992

USER GUIDE SECTION DESCRIPTION

For simplified navigation of this user guide, an overview of each  Gain Control. This section describes the options for
section follows: controlling receiver gain settings, including manual gain
 System Overview. This section explains the capability of control (MGC) provided by the BBP and automatic gain
the device and serves as an introduction to all the subsystems control (AGC) provided by the integrated transceiver.
and functions, including the block diagrams and interfaces.  Filter Configuration. This section describes all the digital
 System Architecture Description. This section explains the filter blocks in the receivers and transmitters, and explains the
software design approach using the application programmable FIR filters and how to set their coefficients.
programming interface (API) and all details required to  Observation Receiver. This section describes the ORx inputs
develop code on the device. and the sniffer receiver (SnRx) inputs, including system
 Software Integration. This section describes the process for implementation and setup APIs.
developing code using the APIs. This section lists common  TDD Configuration and Setup. This section describes
API functions for user integration into the code base. software configuration for operating in a time division
 Serial Peripheral Interface (SPI). The SPI is the main duplexed (TDD) system.
control interface between the baseband processor (BBP)  General-Purpose Input/Output (GPIO) Configuration.
and the integrated transceiver. This section describes the options for configuring standard
 JESD204B Interface. This section provides a description of digital GPIO pins.
the JESD204B digital interface, setup, and configuration  3.3 V General-Purpose Input/Output Overview. This
options. section describes the options for configuring the 3.3 V
 System Initialization. This section provides the sequence of supplied GPIO pins.
steps required at startup.  General-Purpose Interrupt Overview. This section describes
 Quadrature Error Correction, Calibration, and ARM setup and operation of the general-purpose interrupt pin.
Configuration. This section describes the calibration and  Auxiliary Converters—AUXDAC_x, AUXADC. This
error correction functions and setup guidelines for section describes the capability of the AUXADC_x inputs,
configuring the ARM processor to perform scheduled the AUXDAC_x outputs, and how to properly configure
adjustments. the inputs and outputs for various applications.
 System Control. This section describes the commands and  RF Port Interface. This section explains all the details
sequences for setting up the different radio channels. necessary to properly match the RF impedances of each
 Tx Power Control. This section explains the commands differential input and output port.
and procedures for adjusting Tx power control during  Printed Circuit Board Layout Guidelines. This section
normal operation. describes the printed circuit board (PCB) construction,
 Power Amplifier (PA) Protection. This section describes layout, routing, and isolation techniques necessary to
how to setup the PA protection features to help prevent the optimize device performance.
power amplifier from being overdriven. The transmitter  Power Management Considerations. This section describes
channels features a protection mechanism that can help the power supply design and all the considerations needed
prevent damage to the PA connected to either of the to optimize device performance.
transmitter outputs. When the full-scale output power of  Demonstration System Overview. This section describes
the device exceeds the maximum input to the PA, it can the demonstration system, including the evaluation board,
damage the PA. The PA protection feature implements motherboard, and hardware integration setup needed to
feedback in the system to prevent an overload by properly evaluate device performance.
measuring the signal level and by comparing it to the user-  Transceiver Evaluation Software. This section describes the
programmable threshold. This information can reduce the transceiver evaluation software (TES) that provides a
transmit output level on the flagged channel and eliminate graphical user interface that controls the evaluation system.
the damage threat. This section describes how to set up the  DPD, CLGC, and VSWR Measurement (AD9375 Only).
reference clocks needed for the internal clock and for This section describes operation of the closed-loop transmitter
signal generation as well as data synchronization. control functions available only in the AD9375 device.
 Synthesizer Configuration. This section describes how to
configure the synthesizers for different modes of operation.
This section includes details for receiver (Rx), transmitter
(Tx), observation receiver (ORx), and clock phase-locked
loop (PLL) setup, as well as the calibration PLL setup.

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UG-992 AD9371/AD9375 System Development User Guide

SYSTEM OVERVIEW
Analog Devices, Inc., provides a variety of highly integrated RF All signal data transfers are accomplished using a JESD204B
agile transceivers, including the AD9371 and AD9375. This high speed serial interface with eight separate lanes. Four lanes
transceiver family provides dual-channel receivers, dual-channel are dedicated as inputs to the transmitter system and four lanes
transmitters, integrated synthesizers, digital signal processing are configurable to serve as outputs for the receiver system.
functions, and a high speed serial interface. The AD9375 provides When one or two main signal chain receivers are active and an
the added capability or integrated digital predistortion (DPD) observation/sniffer receiver is active, the main signal chain
for the transmitter channels to improve linearity and decrease receivers can be assigned one or two receiver lanes, and the
power consumption. The devices operate over the wide frequency observation/sniffer receiver can also be assigned only one or
range of 300 MHz to 6 GHz and can support a transmit synthesis two lanes. Note that only one observation receiver or sniffer
bandwidth up to 250 MHz, as well as a receiver bandwidth up receiver can be operational at any given time, but all four lanes
to 100 MHz. The information in this document applies equally can be assigned to that channel or shared between this channel
to the AD9371 and the AD9375, except for the section that and the active signal chain receivers.
describes DPD operation for the AD9375. To avoid confusion, A serial peripheral interface (SPI) transmits and receives control
the term device is used throughout the user guide to refer to information between the device and a baseband processor. All
both devices interchangeably. In sections that refer to only one software control is communicated via this interface. There is
device, the part number referenced to clearly delineate which also a control interface that utilizes GPIO lines to provide
device is being described. Note that references in the diagrams hardware control to and from the device. These pins can be
and the application programming interface (API) code examples configured to provide dedicated sets of functions for different
keep the text that appears in the code, even when it applies to application scenarios. Some GPIOs are intended for digital
both devices. control, while others are supplied by a 3.3 V analog supply for
The device provides three receiver inputs with limited bandwidth use in controlling external analog components. There are also
(20 MHz) to monitor signals on other channels of interest. These ten auxiliary digital to analog converters (DACs), known as
receivers, commonly referred to as sniffer receivers (SnRxs), can auxiliary DACs, that can be muxed with 3.3 V GPIO pins to be
be matched to different frequency range antennae to monitor a used as control voltage sources for other devices requiring variable
wider spectrum during normal operation in a more narrow band. control voltages. Included in this block is a set of three low
The independent synthesizer associated with these receivers allows speed auxiliary analog to digital converters (ADCs) that
the receivers to operate on different frequency channels during monitor external voltages of interest to system operation.
normal transmit/receive operation. Figure 1 and Figure 2 show block diagrams for the AD9371
An additional pair of receiver channels can be used as dedicated and the AD9375, respectively. Software control of each block is
observation receivers used to monitor the transmitter channels. described in the following sections of this user guide. Note that
These receivers provide the same bandwidth and gain capability all software code is taken from the API that is supplied with the
as the main signal channel receivers, but are dedicated for use as device. References to Mykonos in the API refer to the Analog
monitors for transmitter performance. These receivers provide Devices development name for the device family.
a feedback path to implement calibration and error correction
algorithms on the transmit data.

Rev. B | Page 8 of 360

AD9371/AD9375 System Development User Guide UG-992
Rx1
RX1+
TIA ADC DECIMATION,
pFIR,
AGC,
DC OFFSET,
QEC,
TUNING,
RSSI, JESD204B
TIA ADC OVERLOAD
RX1–

2
SERDOUT0±
RX_EXTLO+ Rx
LO
GENERATOR SYNTHESIZER
RX_EXTLO– 2
SERDOUT1±
Rx2
RX2+ 2
TIA ADC DECIMATION, FRAMER SERIALIZER SERDOUT2±
pFIR,
AGC,
DC OFFSET,
QEC,
TUNING, 2
RSSI, SERDOUT3±
TIA ADC OVERLOAD
RX2–
4 SYNCINB1±
SYNCINB0±
ORx
ORX1+
ORX1–

ORX2+ CONTROL
INTERFACE
ORX2– (GPIO)
MICRO-
CONTROLLER

SPI PORT
SnRx
SNRXA+
TIA ADC DECIMATION, CLOCK
SNRXA– pFIR, GENERATION AuxADC,
AGC,
SNRXB+ DC-OFFSET, ANALOG
SNRXB– QEC, GPIO
TUNING,
SNRXC+ RSSI,
TIA ADC OVERLOAD
SNRXC–

Tx POWER MANAGEMENT
SYNTHESIZER LO ORx
GENERATOR SYNTHESIZER
TX_EXTLO+ LO
GENERATOR
TX_EXTLO–
JESD204B
Tx1
DAC
TX1+ LPF 2
SERDIN0±
INTERPOLATE,
pFIR, QEC
TX1– 2
DAC SERDIN1±
LPF
JESD204B 2
DEFRAMER DESERIALIZER SERDIN2±
Tx2
DAC 2
TX2+ LPF
SERDIN3±
INTERPOLATE,
pFIR, QEC
TX2– 2
DAC SYNCOUTB0±
LPF
14652-001

Figure 1. AD9371 Functional Block Diagram

Rev. B | Page 9 of 360

UG-992 AD9371/AD9375 System Development User Guide
Rx1
RX1+
TIA ADC DECIMATION,
pFIR,
DC OFFSET,
QEC,
TUNING,
RSSI,
OVERLOAD JESD204B
TIA ADC
RX1–

2
SERDOUT0±
RX_EXTLO+ Rx
LO
GENERATOR SYNTHESIZER
RX_EXTLO– 2
SERDOUT1±
Rx2
RX2+ 2
TIA ADC DECIMATION, FRAMER SERIALIZER SERDOUT2±
pFIR,
DC OFFSET,
QEC,
TUNING,
RSSI, 2
OVERLOAD SERDOUT3±
TIA ADC
RX2–
4 SYNCINB1±
SYNCINB0±
ORx
ORX1+
ORX1–

ORX2+ CONTROL
INTERFACE
ORX2– (GPIO)
MICRO-
CONTROLLER

SPI PORT
SnRx
SNRXA+
TIA ADC DECIMATION, CLOCK
SNRXA– pFIR, GENERATION AuxADC,
AGC,
SNRXB+ DC OFFSET, ANALOG
SNRXB– QEC, GPIO
TUNING,
SNRXC+ RSSI,
TIA ADC OVERLOAD
SNRXC–

Tx POWER MANAGEMENT
SYNTHESIZER LO ORx
GENERATOR SYNTHESIZER
TX_EXTLO+ LO
GENERATOR
TX_EXTLO–
JESD204B
Tx1
DAC
TX1+ LPF INTERPOLATE, 2
pFIR, SERDIN0±
DPD

DC OFFSET,
QEC,
TX1– TUNING 2
DAC SERDIN1±
LPF
JESD204B 2
DEFRAMER DESERIALIZER SERDIN2±
Tx2
DAC 2
TX2+ LPF SERDIN3±
DPD

INTERPOLATE,
pFIR, QEC
TX2– 2
SYNCOUTB0±
DAC
LPF
14652-101

Figure 2. AD9375 Functional Block Diagram

Rev. B | Page 10 of 360

AD9371/AD9375 System Development User Guide UG-992

SYSTEM ARCHITECTURE DESCRIPTION

This user guide provides information about the API software the /src/doc file in the software package directory structure.
developed by Analog Devices for the AD9371 transceiver This file can also be viewed in the Help tab on the transceiver
family. This user guide outlines the overall architecture, folder evaluation software (TES) used for controlling the evaluation
structure, and methods for using the application programming platform.
interface software on any platform. This user guide does not
SOFTWARE ARCHITECTURE
describe the API library functions. Detailed information regarding
the application programming interface functions is located in Figure 3 shows the software architecture.

USER APPLICATION
DEFINED (/src/example/headless.*)

/src/api/ad9528 /src/api/mykonos

API

/src/api/common.*

USER HARDWARE
DEFINED PLATFORM DRIVERS

14652-002

USER HARDWARE PLATFORM

DEFINED

Figure 3. API Software Architecture

Rev. B | Page 11 of 360

UG-992 AD9371/AD9375 System Development User Guide
FOLDER STRUCTURE Devices AD9528 clock chip. The application programming
The source files are located in the folder structure shown in interface (API) is composed of all files located in the /mykonos
Figure 4. Each branch is explained in the following sections. folder, as well as the common.h file and common.c file. The
/mykonos folder contains the high level function prototypes,
/src
data types, macros, and source code used to build the final user
software system. The user is strictly forbidden to modify the
/api files contained in the /mykonos folder and the /ad9528 folder.
/ad9528 Analog Devices maintains this code as intellectual property and
/mykonos all changes are at their sole discretion. The common.h and
common.h common.c files provide the means for a user to insert their
common.c hardware driver code for system integration with the AD9371
/doc API. A description regarding the use of common.c is contained
14652-003

mykonos.chm in the Software Integration section.

Figure 4. API Folder Structure /src/doc
/src/api This folder contains the API doxygen (mykonos.chm) file for
This folder includes the main application programming interface user reference. It is in compressed HTML format.
code for the AD9371 transceiver family, as well as the Analog

Rev. B | Page 12 of 360

AD9371/AD9375 System Development User Guide UG-992

SOFTWARE INTEGRATION
The current application programming interface (API) package The API is designed with the intent that developers may use any
was developed on a Xilinx® ZC706 reference platform using a driver of their choice for their platform requirements. Users are
dual-core ARM A9 processor running a Linux® variant. Users are permitted to substitute their driver code within the function
required to integrate the API with their platform specific code bodies located in common.c file in the /mykonos_api directory
base. This is readily accomplished because the API abides by for their platform requirements. However, users may not modify
ANSI C constructs while maintaining Linux system call the parameter declarations for these functions or any other code
transparency. The ANSI C standard was followed to ensure because doing so breaks the API. Analog Devices does not support
agnostic processor and operating system integration with the any user application containing unauthorized API code. The
API code. functions in the common.c file for which a developer can
substitute their own hardware specific information are
MODIFYING COMMON.C
described in Table 1.
Users develop code on their own hardware specific platforms.
Therefore, users maintain different drivers for the peripherals,
such as the SPI and GPIO, than what is included in the API.
Users can use their own drivers for these peripherals, or they
may use standard drivers if they use an operating system, such
as Linux.

Table 1. Common API Functions for User Integration

Function Description
void CMB_hardReset(uint8_t spiChipSelectIndex) This function performs the required platform dependent resets.
void CMB_setGPIO(uint32_t GPIO) This function sets the GPIOs based on the platform requirement.
void CMB_setSPIOptions(spiSettings_t *spiSettings) The device and the clock chip use the same SPI settings, but different
chip selects. This function assigns SPI settings to each SPI enabled
device on the board.
void CMB_setSPIChannel(uint16_t chipSelectIndex ) This function assigns the chip select to the device on the board. Users
know the chip select assigned to each device on their platform.
CMB_SPIWriteByte(spiSettings_t *spiSettings, uint16_t addr, Use this function to write a byte to an SPI register.
uint8_t data)
CMB_SPIReadByte (spiSettings_t *spiSettings, uint16_t addr, Use this function to read a 1-byte SPI register.
uint8_t *readdata)
CMB_SPIWriteField(spiSettings_t *spiSettings, uint16_t addr, This function writes a bit field to an SPI register.
uint8_t field_val, uint8_t mask, uint8_t start_bit)
CMB_SPIReadField (spiSettings_t *spiSettings, uint16_t addr, This function reads a bit field from an SPI register.
uint8_t *field_val, uint8_t mask, uint8_t start_bit)
CMB_wait_ms(uint32_t time_ms) This function instructs the API to wait for units of ms.
CMB_wait_us(uint32_t time_us) This function instructs the API to wait for units of µs.
CMB_setTimeout_ms(uint32_t timeOut_ms) This function sets the timeout in ms.
CMB_setTimeout_us(uint32_t timeOut_us) This function sets the timeout in µs.
BOOL CMB_hasTimeoutExpired() This function shows if timeout happened based on the timeout
already set in the system.

Rev. B | Page 13 of 360

UG-992 AD9371/AD9375 System Development User Guide
DEVELOPING THE APPLICATION structures. All application programming interface functions use
The headless.c file provides a user example for top level a pointer to a device data structure to convey configuration and
configuration and control. Users can reference this to develop control settings. It is imperative that structure initialization is
their application. However, the initialization sequence is unique complete before attempting system operation. Table 2 contains a
and includes the assignment of data structure values. Data list of these structures.
structures containing device configuration and operation The headless.c file illustrates the structure initialization
variables are throughout the application programming interface. sequence at the beginning of the file. Explanations for each data
A headless.c file incorporating user selected settings can be structure are contained in the mykonos.chm document.
obtained by creating a C script using transceiver evaluation Note that all unchanged JESD204B parameters must use the
software (TES) as described in the Other TES Features section. default JESD204B parameters in the application programming
Data Structures interface. Failure to do so results in erroneous link operation.
The application programming interface functions use a specific
set of data structures. The application code initializes these data

Table 2. List of Data Structures Used in Application Programming Interface

Data Structure Location Description
spiSettings_t /src/api/common.h This data structure contains the SPI settings for all system
device types.
mykonosFir_t /src/api/mykonos/t_mykonos.h This data structure contains the FIR filter gain, the number
of coefficients, and a pointer to a filter coefficient array.
mykonosJesd204bFramerConfig_t /src/api/mykonos/t_mykonos.h This data structure contains the JESD204B framer
configuration parameters.
mykonosJesd204bDeframerConfig_t /src/api/mykonos/t_mykonos.h This data structure contains the JESD204B deframer
configuration parameters.
mykonosRxProfile_t /src/api/mykonos/t_mykonos.h This data structure contains the Rx profile information.
mykonosTxProfile_t /src/api/mykonos/t_mykonos.h This data structure contains the Tx profile information.
mykonosSnifferGainControl_t /src/api/mykonos/t_mykonos.h This data structure contains the sniffer Rx manual gain
control information.
mykonosORxGainControl_t /src/api/mykonos/t_mykonos.h This data structure contains the observation Rx manual
gain control information.
mykonosRxGainControl_t /src/api/mykonos/t_mykonos.h This data structure contains the Rx manual gain control
information.
mykonosAgcCfg_t /src/api/mykonos/t_mykonos.h This data structure contains the automatic gain control (AGC)
information.
mykonosTxSettings_t /src/api/mykonos/t_mykonos.h This data structure contains the Tx setting information.
mykonosRxSettings_t /src/api/mykonos/t_mykonos.h This data structure contains the Rx setting information.
mykonosObsRxSettings_t /src/api/mykonos/t_mykonos.h This data structure contains the observation Rx setting
information.
mykonosGpio3v3_t /src/api/mykonos/t_mykonos.h This data structure contains the 3.3 V dc GPIO setting
information.
mykonosGpio1v8_t /src/api/mykonos/t_mykonos.h This data structure contains the 1.8 V dc GPIO setting
information.
mykonosAuxIo_t /src/api/mykonos/t_mykonos.h This data structure contains the auxiliary ADC, DAC, and
pointers to the GPIO setting information.
mykonosDigClocks_t /src/api/mykonos/t_mykonos.h This data structure contains the digital clock parameters.
mykonosDevice_t /src/api/mykonos/t_mykonos.h This data structure is inclusive of all previous data types,
which are instantiated as pointers. The PROFILESVALID bit
field identifies which profile is valid. This data type is used
to instantiate one device for configuration and control
after member structure initialization.
mykonosArmGpioConfig_t /src/api/mykonos/t_mykonos.h This data structure holds the ARM GPIO pin assignments
for each ARM input/output pin.
mykonosPeakDetAgcCfg_t /src/api/mykonos/t_mykonos.h This data structure holds the peak detector settings for the
AGC.
mykonosPowerMeasAgcCfg_t /src/api/mykonos/t_mykonos.h This data structure holds the power measurement settings
for the AGC.
Rev. B | Page 14 of 360
AD9371/AD9375 System Development User Guide UG-992
Data Structure Location Description
mykonosInitCalStatus_t /src/api/mykonos/t_mykonos.h This data structure reads back the initialization calibration
status.
mykonosTxLolStatus_t /src/api/mykonos/t_mykonos.h This data structure holds the Tx local oscillator leakage
(LOL) status.
mykonosTxQecStatus_t /src/api/mykonos/t_mykonos.h This data structure holds the Tx quadrature error
correction (QEC) status.
mykonosRxQecStatus_t /src/api/mykonos/t_mykonos.h This data structure holds the Rx QEC status.
mykonosOrxQecStatus_t /src/api/mykonos/t_mykonos.h This data structure holds the Orx QEC status.
mykonosGainComp_t /src/api/mykonos/t_mykonos_gpio.h This data structure holds the gain compensation settings
for the main receive channels.
mykonosObsRxGainComp_t /src/api/mykonos/t_mykonos_gpio.h This data structure holds the gain compensation settings
for the observation channel.
mykonosFloatPntFrmt_t /src/api/mykonos/t_mykonos_gpio.h This data structure holds the floating point formatter
settings for the floating point number generation
mykonosTempSensorConfig_t /src/api/mykonos/t_mykonos_gpio.h This data structure configures the on die temperature
sensor.
mykonosTempSensorStatus_t /src/api/mykonos/t_mykonos_gpio.h This data structure stores the temperature sensor related
values.
mykonosLaneErr_t /src/api/mykonos/mykonos_debug/ This data structure holds the error counters per a given lane.
t_mykonos_dbgjesd.h
mykonosDeframerStatus_t /src/api/mykonos/mykonos_debug/ This data structure holds the deframer status.
t_mykonos_dbgjesd.h

Using API Functions API Sequence

Direct SPI read/write operation is not permitted when The outline of the correct API initialization sequence illustrated
configuring the device or the Analog Devices clock chip device. in headless.c is as follows:
Only use the high level API functions defined in the 1. Instantiate all data structures and load their members
/src/api/mykonos/mykonos.h, /src/api/mykonos/mykonos_ required by the user application (myk_init.c contents).
gpio.h, /src/api/mykonos/mykonos_debug/mykonos_ 2. Initialize and set up all clocks (the platform clock source
dbgjesd.h, or /src/api/ad9528/ad9528.h files. Users must not and the JESD204B SYSREF signals are set up).
directly use any SPI read/write function located in common.c 3. Initialize the hardware platform (hardware dependent
in their application code for device configuration or control. devices such as FPGA/ASIC/BBP interfaces are initialized).
Analog Devices does not support any user code containing SPI 4. Reset the device (call MYKONOS_resetDevice for the reset
writes reverse engineered from the original API. of the transceiver device in preparation for initialization).
Adding Gain Tables and Device Profiles 5. Initialize the device (call MYKONOS_initialize function
The /src/api/mykonos/mykonos_user.h and /src/api/mykonos/ for configuration of the device).
mykonos_user.c files provide setup information for the gain 6. Check CLKPLL status for lock (call MYKONOS_
tables. The default gain table settings for the Rx, the ORx, and checkPllLockStatus and perform check with user defined
the sniffer Rx are located in mykonos_profiles.c. Each gain table code).
is organized according to a descending gain index normalized 7. Perform multichip synchronization (all JESD204B lanes are
to a maximum gain for each respective API calling function. synchronized together for deterministic latency
The tables consist of a two-dimensional array construct where the requirements).
subarray order for each gain table type is a code comment at the 8. Initialize the ARM processor (call MYKONOS_initArm).
beginning of the declaration. Users can modify these gain tables 9. Load the ARM binary file (call MYKONOS_
to include their own custom configurations. Users must submit loadArmFromBinary with user defined binary array
their custom gain settings to Analog Devices for approval. pointer).
Analog Devices does not support any custom gain tables not 10. Set the RF PLL frequencies (call MYKONOS_
submitted for approval prior to user use. Details of these files setRfPllFrequency for each channel used by the
are available in the device /src/doc file in the software package application).
directory structure 11. Perform the RF PLL lock check (call MYKONOS_
checkPllLockStatus and perform the check with user-
defined code).
12. Set the GPIO functions with the desired configuration
(check headless.c for API calls to be made).
Rev. B | Page 15 of 360
UG-992 AD9371/AD9375 System Development User Guide
13. Run the initialization calibrations (call MYKONOS_ Note that hardware designs with multiple AD9371 or AD9375
runInitCals and MYKONOS_waitInitCals with user devices require each device to have its own unique
defined code). configuration data initialized for all data structures.
14. Enable the SYSREF for the Rx and ORx deframer (call Restrictions
MYKONOS_enableSysrefTo … functions).
Do not modify any code located in the /src/api/* folder, other
15. Send the SYSREF signal to bring up the JESD204B
than changing the common.c code bodies for hardware driver
interface.
insertion and gain table and profile changes in mykonos_
16. Check deframer and framer status (call MYKONOS_
profiles.c, as previously discussed. Analog Devices maintains
readDeframerStatus and
the code in the /src/api/mykonos and /src/api/ad9528 folders
MYKONOS_readRxFramerStatus).
as intellectual property and all changes are at their sole
17. Verify the sync and link status for the hardware platform.
discretion. Analog Devices provides new releases to fix any
18. Enable tracking calibrations (call MYKONOS_
code bugs in these folders. Verification of all code bugs is
enableTrackingCals).
independent of any user code.
19. Turn the radio on for all transmitters and receivers that
were previously set up (call MYKONOS_radioOn).

Rev. B | Page 16 of 360

AD9371/AD9375 System Development User Guide UG-992

SERIAL PERIPHERAL INTERFACE (SPI)

The SPI bus provides the mechanism for all digital control of SPI BUS SIGNALS
the device by a baseband processor (BBP). Each SPI register is The SPI bus consists of the signals described in the following
8 bits wide, and each register contains control bits, status monitors, sections.
or other settings that control all functions of the device. This
section is mainly an informational section meant to give the CSB
user an understanding of the interface used by the BBP for CSB is the active low chip select that functions as the bus enable
digital control. All control functions are implemented using the signal driven from the baseband processor to the device. CSB is
API detailed within this user guide. The following sections driven low before the first SCLK rising edge and is normally
explain the specifics of this interface. driven high again after the last SCLK falling edge. The device
ignores the clock and data signals while CSB is high. CSB also
SPI CONFIGURATION USING API FUNCTION
frames communication to and from the device and returns the
The SPI bus is configured by the MYKONOS_setSpiSettings device to the ready state when it is driven high.
(mykonosDevice_t *device) function. Users can configure SPI
Forcing CSB high in the middle of a transaction aborts part or
settings for the device for use in different configurations by
all of the transaction. If the transaction is aborted before the
calling the MYKONOS_setSpiSettings function with the
instruction is complete or in the middle of the first data word,
following parameters.
the transaction is aborted and the state machine returns to the
• To use the SPI as a 4-wire interface, ready state. Any complete data byte transfers prior to CSB
MYKONOS_setSpiSettings (device-> deasserting are valid, but all subsequent transfers in a
spiSettings->fourWireMode = 1); continuous SPI transaction are aborted.
• To use the SPI as a 3-wire interface (default configuration), SCLK
MYKONOS_setSpiSettings (device-> SCLK is the serial interface reference clock driven by the BBP to
spiSettings->fourWireMode = 0); the device. It is only active while CSB is low. The maximum
• To use the SPI in LSB first mode, SCLK frequency is 50 MHz.
SDIO and SDO
MYKONOS_setSpiSettings (device->
spiSettings->MSBFirst = 0); When configured as a 4-wire bus, the SPI uses two data signals:
• To use the SPI in MSB first mode (default configuration), SDIO and SDO. SDIO is the data input line driven from the
baseband processor to the device, and SDO is the data output
MYKONOS_setSpiSettings (device-> from the AD9371 to the baseband processor in this configuration.
spiSettings->MSBFirst = 1);
When configured as a 3-wire bus, SDIO is used as a bidirectional
• To enable single instruction SPI data transfer mode, data signal that both receives and transmits serial data. In this
MYKONOS_setSpiSettings (device-> mode, the SDO port is disabled.
spiSettings->enSpiStreaming = 0); The data signals are launched on the falling edge of SCLK and
• To enable SPI streaming mode, sampled on the rising edge of SCLK by both the baseband
processor and the device. SDIO carries the control field from
MYKONOS_setSpiSettings (device->
spiSettings->enSpiStreaming = 1);
the baseband processor to the AD9371 during all transactions,
and it carries the write data fields during a write transaction. In
SPI streaming allows the device to automatically change the a 3-wire SPI configuration, SDIO carries the returning read data
register address after each operation. Users can select an fields from the device to the BBP during a read transaction. In a
autoincrement or autodecrement SPI address with the following 4-wire SPI configuration, SDO carries the returning data fields to
parameters: the baseband processor.
• For an autoincrement SPI address, where next addr = addr + The SDO and SDIO pins transition to a high impedance state
1, program the following: when the CSB input is high. The device does not provide any
MYKONOS_setSpiSettings (device-> weak pull-up or pull-down on these pins. When SDO is inactive, it
spiSettings->autoIncAddrUp = 1); is floated in a high impedance state. If a valid logic state on SDO is
• For an utodecrement SPI address, where next addr = addr − 1, required at all times, add an external, weak pull-up/pull-down
program the following: on the printed circuit board (PCB).

MYKONOS_setSpiSettings (device->
spiSettings->autoIncAddrUp = 0);

Rev. B | Page 17 of 360

UG-992 AD9371/AD9375 System Development User Guide
SPI DATA TRANSFER PROTOCOL In MSB mode, the first bit transmitted is the R/W bit that
The device SPI is a flexible, synchronous serial communications determines if the operation is a read (set) or a write (clear). The
bus allowing seamless interfacing to many industry-standard MSB of the address is the next bit transmitted from the baseband
microcontrollers and microprocessors. The serial input/output processor, followed by the remaining 14 bits in order from next
(I/O) is compatible with most synchronous transfer formats, MSB to LSB. If the operation is a write, the baseband processor
including both the Motorola, Inc., SPI and Intel® SSR protocols. transmits the next 8 bits MSB to LSB. If the operation is a read, the
The control field width is limited to 16 bits, and multibyte I/O device transmits the next 8 bits MSB to LSB. After the final bit is
operation is allowed. The device cannot be used to control other transferred, the data lines return to their idle state and the CSB line
devices on the bus; it only operates as a slave. must be driven high to end the communication session.

There are two phases to a communication cycle. Phase 1 is the Multibyte Data Transfer
control cycle, which is the writing of a control word into the When enSpiStreaming = 1, a multibyte data transfer is allowed. In
device. The control word provides the serial port controller with this mode, data transfers across the bus as long as the CSB pin is
information regarding the data field transfer cycle, which is Phase 2 low. The autoIncAddrUp controls how the address changes for
of the communication cycle. The Phase 1 control field defines subsequent writes or reads. When autoIncAddrUp = 1, the address
whether the upcoming data transfer is a read or a write. It also increments from the starting address for each subsequent data
defines the register address being accessed. transfer until CSB is driven high. If the last register address is
Phase 1 Instruction Format reached, the next address accessed is 0x000. When this bit is
clear, the address decrements from the starting address for each
The 16-bit control field contains information shown in Table 3. subsequent data transfer. If this bit is clear and Address 0x000
Table 3. Phase 1 16-Bit Control Field is reached, the next address to be accessed is the last register
MSB [D14:D0] location defined in the register map. It is strongly recommended
R/W A[14:0]
that any data transfer be controlled so that Address 0x000 is
only written once at startup.
R/W For multibyte data transfers in LSB mode, the LSB of the
Bit 15 of the instruction word determines whether a read or write address is the first bit transmitted from the baseband processor,
data transfer occurs after the instruction byte write. Logic high followed by the next 14 bits in order from next LSB to MSB. The
indicates a read operation; Logic 0 indicates a write operation. next bit signifies if the operation is a read (set) or a write (clear).
If the operation is a write, the baseband processor transmits the
[D14:D0] next 8 bits LSB to MSB. After the MSB is received, the address
Bits A[14:0] specify the starting byte address for the data increments or decrements based on the autoIncAddrUp
transfer during Phase 2 of the input/output operation. parameter. The baseband processor then continues to transfer
All byte addresses, both starting and internally generated addresses, data in 8-bit words, LSB to MSB, until the operation is
are assumed to be valid. That is, if an invalid address (undefined terminated by CSB being driven high. If the operation is a read,
register) is accessed, the input/output operation continues as if the the device transmits the next 8 bits LSB to MSB. The device
address space is valid. For write operations, the written bits are then changes the address and continues to transfer data in 8-bit
discarded, and the read operations result in Logic 0s at the words, LSB to MSB, until the operation is terminated by CSB
output being driven high.

Single-Byte Data Transfer For multibyte data transfers in MSB mode, the same process is
followed, except the first bit transferred indicates if the operation is
When enSpiStreaming = 0, a single-byte data transfer is chosen.
a read (set) or a write (clear). The starting address is then trans-
In this mode, CSB goes active low, the SCLK signal activates,
mitted by the baseband processor, MSB to LSB, followed by the
and the address is transferred from the baseband processor to
data transfer, MSB to LSB. Address increment or decrement is
the device.
still controlled by the autoIncAddrUp parameter.
In LSB mode, the LSB of the address is the first bit transmitted
from the baseband processor, followed by the next 14 bits in
order from the next LSB to MSB. The next bit signifies if the
operation is a read (set) or a write (clear). If the operation is a
write, the baseband processor transmits the next 8 bits LSB to
MSB. If the operation is a read, the device transmits the next 8
bits LSB to MSB. After the final bit is transferred, the data lines
return to their idle state and the CSB line must be driven high
to end the communication session.

Rev. B | Page 18 of 360

AD9371/AD9375 System Development User Guide UG-992
Example: LSB First Multibyte Transfer, Autoincrementing  Make sure that fourWireMode = 1 (the device is
Address configured to work with the 4-wire interface).
To complete a 4-byte write starting at Register 0x02A and  Make sure that MSBFirst = 1 (the SPI works in MSB first
ending with Register 0x02D in LSB first format, follow these mode).
instructions when programming the master:  Make sure that autoIncAddrUp = 0 (the address pointer
automatically decrements).
 Ensure that fourWireMode = 1 (the device is configured to
 Make sure that enSpiStreaming = 1 (a multibyte data
work with the 4-wire interface).
transfer is allowed).
 Ensure that MSBFirst = 0 (the SPI works in LSB first mode).
 Force the CSB line low and keep it low until the last byte is
 Ensure that autoIncAddrUp = 1 (the address pointer transferred.
automatically increments).
 Send the instruction word 0_000 0000 0010 1010 (the first
 Ensure that enSpiStreaming = 1 (a multibyte data transfer 0 indicates a write operation) to select Register 0x02A as
is allowed). the starting address.
 Force the CSB line low and keep it low until the last byte is  Use the next 32 clock cycles to send the data to be written
transferred. to the registers, MSB to LSB for each 8-bit word.
 Send the instruction word 0101 0100 0000 000_0 (the last 0  Make sure the CSB line is driven high after the last bit has
indicates a write operation) to select Register 0x02A as the been sent to Register 0x027 to end the data transfer.
starting address.
 Use the next 32 clock cycles to send the data to be written TIMING DIAGRAMS
to the registers, LSB to MSB for each 8-bit word. The diagrams in Figure 5 and Figure 6 show the SPI bus
 Ensure the CSB line is driven high after the last bit is sent waveforms for a single register write operation and a single
to Register 0x02D to end the data transfer register read operation, respectively. In Figure 5, the value 0x55
is written to Register 0x00A. In Figure 6, Register 0x00A is read
Example: MSB First Multibyte Transfer,
and the value returned by the device is 0x55. If the same operations
Autodecrementing Address
are performed with a 3-wire bus, the SDO line in Figure 5 is
To complete a 4-byte write starting at Register 0x02A and eliminated, and the SDIO and SDO lines in Figure 6 are combined
ending with Register 0x027 in LSB first format, follow these on the SDIO line. Note that both operations use MSB first mode
instructions when programming the master: and all data is latched on the rising edge of the SCLK signal.

CSB

SCLK

SDIO

14652-004

SDO

WRITE TO REGISTER 0x00A – VALUE = 0x55

Figure 5. Nominal Timing Diagram, SPI Write Operation

CSB

SCLK

SDIO

SDO
14652-005

READ REGISTER 0x00A – VALUE = 0x55

Figure 6. Nominal Timing Diagram, SPI Read Operation

Rev. B | Page 19 of 360

UG-992 AD9371/AD9375 System Development User Guide
Table 4 lists the timing specifications for the SPI bus. The timing parameters are marked. Note that this is a single-read
relationship between these parameters is shown in Figure 7. operation; therefore, the bus ready parameter after the data is
This diagram shows a 3-wire SPI bus timing diagram with the driven from the device (tHZS) is not shown in the diagram.
device returning a value of 0xD4 from Register 0x00A; the

Table 4. SPI Bus Timing Constraint Values

Parameter Min Typ Max Description
tCP 20 ns SCLK cycle time (clock period)
tMP 10 ns SCLK pulse width
tSC 3 ns CSB setup time to first SCLK rising edge
tHC 0 ns Last SCLK falling edge to CSB hold
tS 3 ns SDIO data input setup time to SCLK
tH 0 ns SDIO data input hold time to SCLK
tCO 3 ns 8 ns SCLK falling edge to output data delay (3-wire or 4-wire mode)
tHZM tH tCO Bus turnaround time after baseband processor drives the last address bit
tHZS 3 ns tCO Bus turnaround time after the device drives the last data bit (not shown in Figure 7)

tSC tMP tCP tHZM tCO tHC

tH
CSB tS

SCLK DON’T CARE DON’T CARE

14652-006
SDIO DON’T CARE R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 DON’T CARE

Figure 7. 3-Wire SPI Timing with Parameter Labels, SPI Read Operation

Rev. B | Page 20 of 360

AD9371/AD9375 System Development User Guide UG-992

JESD204B INTERFACE
The device employs the JESD204B Subclass 1 standard to solution provides a device clock and a SYSREF to both the
transfer ADC and DAC samples between the device and a device and the baseband processor. The SYSREF signal ensures
baseband processor. JESD204B Subclass 1 devices use a system deterministic latency between the transceiver and the baseband
reference (SYSREF) signal to synchronize the establishment of processor. This signal is also used to provide digital synchronization
the links to provide deterministic latency through the link. For when more than one device is used; it is also required to
details on deterministic latency, refer to Section 6 of the JEDEC maintain data timing synchronization among the devices. The
Standard No. 204B. Multichip Synchronization section describes the setup required
The device supports high speed serial lane rates from to achieve the desired results.
614.4 Mbps to 6144 Mbps. An external clock distribution

AD9371
SYNCINB0±
SYNCB
CROSSBAR SYNCINB1±

FRAMER
ADC
ADC
ADC 8-BIT/ LANE
MAIN RECEIVERS CROSSBAR LANES TO 10-BIT CROSSBAR
SAMPLES DECODE
ADC
ADC
SERDOUT0±
SERDOUT1±
MUX SERIALIZERS SERDOUT2±
FRAMER SERDOUT3±

ADC 8-BIT/ LANE

SnRx/ORx RECEIVER ADC
ADC CROSSBAR LANES TO 10-BIT CROSSBAR
SAMPLES DECODE

DEVICE CLOCK
CLOCK
GENERATION
AND SYSREF SYSREF
RETIMING

DEFRAMER
DAC
ADC
SERDIN0±
DAC 8-BIT/ LANE
TRANSMITTERS CROSSBAR LANES TO 10-BIT CROSSBAR SERDIN1±
SAMPLES DECODE DESERIALIZERS SERDIN2±
DAC
ADC SERDIN3±

SYNCOUTB0±
14652-007

Figure 8. High Level JESD204B Interface Block Diagram

Rev. B | Page 21 of 360

UG-992 AD9371/AD9375 System Development User Guide
RECEIVERS (ADC) DATAPATH combine for no more than 4 lanes. If one framer uses all 4 lanes,
The transport and link layers for JESD204B are performed in the then the other framer cannot be used.
framers. The device has two JESD204B framers that multiplex into Each framer has an ADC crossbar that can connect any ADC
four serial lanes. Samples from the main receivers are sent to the to any framer input. The ADC crossbar for the main receiver
first framer. Samples from the sniffer/observation receiver are sent framer has an optional automatic channel selection feature to
to the second framer. Each framer has its own SYNCB signal. automatically shift the Rx2 ADCs to Framer 0 and Framer 1. If
This allows the sniffer/observation JESD204B lanes to be the framer is configured for only two inputs (M = 2), Rx1 is
brought down for reconfiguration without interrupting the disabled, and Rx2 is enabled, the ADCs for Rx2 must be connected
main receiver lanes. to the Framer 0 and Framer 1 inputs. The automatic channel
The two framers are capable of operating at different sample selection feature allows this shift without reconfiguring the
rates. The higher sample rate must be a power of two multiples ADC crossbar.
of the lower sample rate (for example, 2×, 4×, or 8×). For example, Each framer is capable of generating a pseudorandom bit
the two main receivers can be configured for a 122.88 MHz sequence (PRBS) on the enabled lanes. After the PRBS is
sample rate into the framer, and a sniffer with a sample rate of enabled, errors can be injected. Enabling the PRBS generator
30.72 MHz can be connected to the second framer. There are disables the normal JESD204B framing, and may cause the
two options to make this work: oversample at the framer input SYNCB signal to deassert.
or bit repeat at the serializer output. Oversample mode repeats The serializers can be configured to adjust the amplitude and
sample values at the framer input of the slower rate, allowing all preemphasis of the physical signal to help combat bit errors due
the serializers to run at the same bit rate. Bit repeat mode repeats to various PCB trace lengths.
each bit in the lane or lanes that carry the slower data as it exits
the serializer. Because this is after the 8-bit/10-bit encoding, it Supported Framer Link Parameters
appears as if the lane is running at a slower data rate than the The device supports a subset of possible JESD204B link
other lanes. configurations. The number of ADCs and the number of
JESD204B lanes implemented in the silicon limit these
Both framers must share the four serializers. Each framer must
configurations.
be configured for 0, 1, 2, or 4 lanes such that the two framers

Table 5. Static JESD204B Parameters

JESD204B Parameter AD9371/AD9375 Value Description
S 1 Samples transmitted/single converter/frame cycle
N 14 Converter resolution
N’ 16 Total number of bits per sample
CF 0 Number of control words/frame clock cycle/converter device
CS 2 Number of control bits/conversion sample
HD 0…1 High density mode (only M2L4 uses HD = 1)
K Variable, suggested: 32 Number of frames in 1 multiframe, (20 ≤ F × K ≤ 256), F × K must be a multiple of 4, K ≤ 32

Table 6. JESD204B Parameters Dependent on Number of Lanes and Number of ADCs

Number of ADCs (M) Number of Lanes (L) Number of Bytes in 1 Frame (F) (F = 2 × M/L)
2 1 4
2 2 2
2 4 1
4 1 8
4 2 4
4 4 2

Rev. B | Page 22 of 360

AD9371/AD9375 System Development User Guide UG-992
For a particular converter sample rate, not all combinations Table 8. Preemphasis Amplitude Settings
listed in Table 6 are valid. For the JESD204B configuration Emphasis (Decimal) Differential Amplitude (mV p-p)
mode to be valid, the lane rate for that mode must be within the 0 0
614.4 Mbps to 6144 Mbps range. The lane rate is the serial bit 1 40
rate for one lane of the JESD204B link. Calculate the lane rate 2 80
using Equation 1. 3 120
Lane Rate = IQ Sample Rate × M × 16 bits × (10 ÷ 8) ÷ L (1) 4 160
5 200
Serializer Configuration
6 240
A 5-bit number that is not linearly weighted represents the 7 280
amplitude of the serializer. Not all settings are unique, and not
500
all settings meet the JESD204B transmitter mask. The JESD204B EMPHASIS = 7
EMPHASIS = 3
transmitter mask requires a differential amplitude greater than EMPHASIS = 0

DIFFERENTIAL AMPLITUDE (mV)

360 mV and less than 770 mV. To meet the JESD204B transmitter 300

mask, it is recommended to set the serializer amplitude to a

decimal value between 18 to 26. The default amplitude is 100
22 mV p-p.

Table 7. Serializer Amplitude Settings That Meet the –100

JESD204B Transmitter Mask

Serializer Amplitude –300
(Decimal) Differential Amplitude (mV p-p)
18 400

14652-008
–500
19 440 TIME
20 480 Figure 9. Serializer Preemphasis Measured on 3 Gbps Serial Data, Serializer
21 520
Another metric for the effect of the serializer preemphasis is
22 (default) 560
how much insertion loss each preemphasis setting can overcome.
23 600
Different PCBs have different insertion loss due to factors such
24 640
as different materials, stackups, and trace geometry. However,
25 680
the insertion loss can be measured with a network analyzer or
26 720
simulated to estimate how much loss a particular PCB has. Note
The values shown in Table 7 are calculated values based on the that the preemphasis gain has some dependency on the main
design. Measured values are slightly lower than the calculated serializer amplitude setting.
values. It is always recommended to verify the eye diagram in 16
PREEMPHASIS = 0
PREEMPHASIS = 1
the system after building a PCB to verify any layout related 14 PREEMPHASIS = 2
PREEMPHASIS = 3
performance differences. PREEMPHASIS = 4
12 PREEMPHASIS = 5
PREEMPHASIS GAIN (dB)

The serializer preemphasis allows boosting the amplitude any PREEMPHASIS = 6

PREEMPHASIS = 7
time the serial bit changes state. If bit transition does not occur, 10

the amplitude is deemphasized. Preemphasis helps open the eye

8
diagram for longer PCB traces or when the parasitic loading of
connectors has a noticeable effect. In most cases, to find the 6

best setting, a simulation or measuring the eye diagram with a

4
high speed scope at the receiver is recommended. A 3-bit
number represents the serializer preemphasis. The range in 2

differential amplitude can be seen in Table 8, and its effects are

0
14652-009

shown in Figure 9. 18 19 20 21 22 23 24 25 26
SERIALIZER AMPLITUDE (Decimal)

Figure 10. Gain (in dB) of Each Preemphasis and Amplitude Setting

Rev. B | Page 23 of 360

UG-992 AD9371/AD9375 System Development User Guide
Framer
0.385
The framer receives 16-bit ADC samples and maps them to
high speed serial lanes. The mapping changes depending on the
DIFFERENTIAL VOLTAGE (V)

0.180 JESD204B configuration chosen, specifically the number of

lanes and the number of converters. Table 6 summarizes the
0
valid framer configurations for the device.
The responsibilities of the framer include the following:
–0.180  JESD204B link initialization—state machine to progress
link from code group synchronization (CGS) to initial lane
–0.385 assignment sequence (ILAS), then to user data.
 Character replacement. This allows frame and multiframe

14652-600
0 0.15 0.40 0.60 0.85 1.00 synchronization during user data.
NORMALIZED BIT TIME (UI)  Map ADC samples to JESD204B lanes.
Figure 11. Serializer Eye Diagram Requirements Mask  Perform 8-bit/10-bit encoding.
400
The ADC sample inputs into the framer pass through a sample
300 crossbar, allowing the framer to map any ADC input to any
200
framed sample location during the framing process. For example,
this can be used to swap I and Q samples. The framer lane data
100 outputs also pass through a lane crossbar, allowing mapping any
VOLTAGE (V)

0
framer output lane (internal to the silicon) to any physical
JESD204B lane at the package pin. The framer packs the ADC
–100 samples into lane data following the JESD204B specification.
–200

–300

–400
14652-010

–150 –100 –50 0 50 100 150

TIME (ps)

Figure 12. Example 6.144 Gbps Eye Diagram at the Serializer Output with
Specifications Mask Superimposed
SAMPLE FRAMER LANE
CROSSBAR CROSSBAR
Rx1 Q[15:0]
ADC0[15:0]
Rx1 I[15:0] 1 FRAME (M = 2, L = 1, F = 4) FIRST BYTE
ADC1[15:0]
Rx2 Q[15:0] ADC1 ADC1 ADC0 ADC0 TO SERIALIZER 8-BIT/ LANE 0
Rx2 I[15:0] [7:0] [15:8] [7:0] [15:8] 10-BIT LANE 1
ENCODE

14652-011

Figure 13. Framer Data Packing for M = 2, L = 1

SAMPLE FRAMER LANE
CROSSBAR CROSSBAR
Rx1 Q[15:0] 1 FRAME
ADC0[15:0] (M = 2, L = 2, F = 2)
Rx1 I[15:0]
ADC1[15:0] ADC0 ADC0
Rx2 Q[15:0] 8-BIT/10-BIT LANE 0
[7:0] [15:8]
Rx2 I[15:0] FIRST BYTE ENCODE LANE 1
ADC1 ADC1
14652-012

[7:0] [15:8] TO SERIALIZER 8-BIT/10-BIT

ENCODE

Figure 14. Framer Data Packing for M = 2, L = 2

SAMPLE FRAMER 1 FRAME LANE

CROSSBAR (M = 2, L = 4, F = 1) FIRST BYTE CROSSBAR
Rx1 Q[15:0]
ADC0[15:0] ADC0 TO SERIALIZER
Rx1 I[15:0] 8-BIT/10-BIT
ADC1[15:0] [15:8] ENCODE
Rx2 Q[15:0] LANE 0
ADC0 8-BIT/10-BIT
Rx2 I[15:0] [7:0] LANE 1
ENCODE
LANE 2
ADC1 8-BIT/10-BIT
[15:8] LANE 3
ENCODE
ADC1 8-BIT/10-BIT
[7:0] ENCODE
14652-013

NOTES
1. HD = 1 (1 SAMPLE SPLIT ACROSS MULTIPLE LANES).
Figure 15. Framer Data Packing for M = 2, L = 4

Rev. B | Page 24 of 360

AD9371/AD9375 System Development User Guide UG-992

SAMPLE FRAMER LANE

CROSSBAR CROSSBAR
Rx1 Q[15:0]
ADC0[15:0]
Rx1 I[15:0] 1 FRAME (M = 4, L = 1, F = 8)
ADC1[15:0] 8-BIT/
Rx2 Q[15:0] ADC3 ADC3 ADC2 ADC2 ADC1 ADC1 ADC0 ADC0 LANE 0
Rx2 I[15:0] ADC2[15:0] 10-BIT
[7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] ENCODE LANE 1
ADC3[15:0]

14652-014
FIRST BYTE
TO SERIALIZER

Figure 16. Framer Data Packing for M = 4, L = 1

SAMPLE FRAMER ONLY IN THIS CASE, LANE
CROSSBAR FRAMER OUTPUT PORTS CROSSBAR
Rx1 Q[15:0]
ADC0[15:0] 0 AND 2 ARE USED
Rx1 I[15:0] 1 FRAME (M = 4, L = 2, F = 4)
ADC1[15:0]
Rx2 Q[15:0] ADC1 ADC1 ADC0 ADC0 8-BIT/10-BIT LANE 0
ADC2[15:0]
Rx2 I[15:0] [7:0] [15:8] [7:0] [15:8] FIRST BYTE ENCODE LANE 1
ADC3[15:0]

14652-015
ADC3 ADC3 ADC2 ADC2 TO SERIALIZER 8-BIT/10-BIT
[7:0] [15:8] [7:0] [15:8] ENCODE

Figure 17. Framer Data Packing for M = 4, L = 2

SAMPLE FRAMER 1 FRAME LANE
CROSSBAR (M = 4, L = 4, F = 2) FIRST BYTE CROSSBAR
Rx1 Q[15:0]
ADC0[15:0] ADC0 ADC0 TO SERIALIZER
Rx1 I[15:0] 8-BIT/10-BIT
ADC1[15:0] [7:0] [15:8] ENCODE
Rx2 Q[15:0] LANE 0
ADC2[15:0] ADC1 ADC1
Rx2 I[15:0] 8-BIT/10-BIT LANE 1
ADC3[15:0] [7:0] [15:8] ENCODE
LANE 2
ADC2 ADC2 8-BIT/10-BIT LANE 3
[7:0] [15:8] ENCODE

14652-016
ADC3 ADC3 8-BIT/10-BIT
[7:0] [15:8] ENCODE

Figure 18. Framer Data Packing for M = 4, L = 4

ADC/SAMPLE CROSSBAR LANE CROSSBAR
FRAMER
11 11 LANE 3
FRAMER INPUT 3[15:0] FRAMER OUTPUT 3[15:0]
10 10 LANE 2
Rx2 I M3 FRAMER INPUT 2[15:0] FRAMER OUTPUT 2[15:0]
ADC3 01 01 LANE 1
FRAMER INPUT 1[15:0] FRAMER OUTPUT 1[15:0]
00 00 LANE 0
FRAMER INPUT 0[15:0] FRAMER OUTPUT 0[15:0]

11 11
10 10
Rx2 Q M2
ADC2 01 01
00 00
SINGLE CH
AUTO SELECT

11 11
1 10 10
M1
Rx1 I 01 01
ADC1 0
00 00

11 11
1 10 10
M0
Rx1 Q 01 01
ADC0 0
14652-017

00 00

Figure 19. Framer Crossbar Detail

Rev. B | Page 25 of 360

UG-992 AD9371/AD9375 System Development User Guide
Other Useful Framer IP Features JESD204B Framer API Data Structures
Serializer PRBS mykonosJesd204bFramerConfig_t
The serializer has a built in pseudorandom bit sequence (PRBS) The mykonosJesd204bFramerConfig_t data structure contains
test pattern it can output to aid in debugging the JESD204B the information required to properly configure each framer.
serial link. If errors caused by signal integrity exist, it may be Details of each member can be found in Table 9. The transceiver
difficult to get the JESD204B framer/deframer to work properly. evaluation software (TES) has the option to output example
The PRBS generator built into the serializer allows the device to data structures with values chosen from the configuration tab of
output serial data, even when the link may be causing bit errors. the software.
The PRBS generator can be configured to transmit PRBS7, typedef struct
PRBS15, or PRBS31 sequences. With this mode enabled, the {
serializer amplitude and emphasis can be adjusted to find the uint8_t bankId;
best setting to minimize bit errors on the serial link. For this uint8_t deviceId;
uint8_t lane0Id;
mode to be fully utilized, the baseband processor must have a
uint8_t M;
PRBS checker to check the PRBS sequence for errors. uint8_t K;
The typical usage sequence is as follows: uint8_t scramble;
uint8_t externalSysref;
1. Initialize the device as outlined in the Link Establishment uint8_t serializerLanesEnabled;
section. uint8_t serializerLaneCrossbar;
2. Run the MYKONOS_enableRxFramerPrbs(…) with the uint8_t serializerAmplitude;
required PRBS order and set it to enable = 1. uint8_t preEmphasis;
uint8_t invertLanePolarity;
3. Enable the PRBS checker on the baseband processor and uint8_t lmfcOffset;
reset its error count. uint8_t newSysrefOnRelink;
4. Wait a specific amount of time to allow a good number of uint8_t enableAutoChanXbar;
samples to be transmitted, and then check the PRBS error uint8_t ObsRxSyncbSelect;
count of the baseband processor.
uint8_t overSample;
API Software Integration } mykonosJesd204bFramerConfig_t;
The MYKONOS_initialize(…) API function handles the
configuration of the serializer, Rx1/Rx2 framer, and ORx framer.
Set any JESD204B link options in the mykonosDevice_t data
structure before calling MYKONOS_initialize(…). After
initialization, there are some other API functions to aid in
debugging and monitoring the status of the JESD204B link.

Table 9. JESD204B Framer Configuration Structure Member Description

Structure Member Valid Values Description
bankId 0 … 15 JESD204B configuration bank ID—extension to device ID.
deviceId 0 … 255 JESD204B configuration device ID—link identification number.
lane0Id 0 … 31 JESD204B configuration lane ID—if more than one lane is used, each subsequent lane
increments from this number.
M 0, 2, 4 Number of ADC converters—two converters per receive chain.
K 1 … 32 Number of frames in a multiframe; the default value is 32.
F × K must be a multiple of 4.
scramble 0.. … Scrambling enabled.
If scramble = 0, then scrambling is disabled.
If scramble > 0, then scrambling is enabled.
externalSysref 0 … 255 External SYSREF enabled.
If externalSysref = 0, then use internal SYSREF.
If externalSysref > 0, then use external SYSREF.
serializerLanesEnabled 0x0 … 0xF Serializer lane enabled—one bit per lane.
If Bit 0 = 0, then Lane 0 is disabled; if Bit 0 = 1, then Lane 0 is enabled.
If Bit 1 = 0, then Lane 1 is disabled; if Bit 1 = 1, then Lane 1 is enabled.
If Bit 2 = 0, then Lane 2 is disabled; if Bit 2 = 1, then Lane 2 is enabled.
If Bit 3 = 0, then Lane 3 is disabled; if Bit 3 = 1, then Lane 3 is enabled.

Rev. B | Page 26 of 360

AD9371/AD9375 System Development User Guide UG-992
Structure Member Valid Values Description
serializerLaneCrossbar 0x0 … 0xFF Serializer lane crossbar—two bits per lane.
Bits[1:0] identify the framer lane that connects to Serializer Lane 0.
Bits[3:2] identify the framer lane that connects to Serializer Lane 1.
Bits[5:4] identify the framer lane that connects to Serializer Lane 2.
Bits[7:6] identify the framer lane that connects to Serializer Lane 3.
serializerAmplitude 0 … 31 Serializer amplitude—default is 22.
preEmphasis 0…7 Serializer preemphasis—default is 4.
invertLanePolarity 0x0 … 0xF Serializer lane polarity inversion.
If Bit 0 = 0, then Lane 0 is unaffected; if Bit 0 = 1, then Lane 0 is inverted.
If Bit 1 = 0, then Lane 1 is unaffected; if Bit 1 = 1, then Lane 1 is inverted.
If Bit 2 = 0, then Lane 2 is unaffected; if Bit 2 = 1, then Lane 2 is inverted.
If Bit 3 = 0, then Lane 3 is unaffected; if Bit 3 = 1, then Lane 3 is inverted.
lmfcOffset 0 … 31 Local multiframe counter (LMFC) offset—local multi frame counter offset value for deterministic
latency setting, set this such that 0 ≤ lmfcOffset ≤ (K − 1).
newSysrefOnRelink 0 … 255 New SYSREF on relink—flag to indicate that a SYSREF is required to reestablish the link.
If newSysrefOnRelink = 0, then no SYSREF is required.
If newSysrefOnRelink > 0, then SYSREF is required.
enableAutoChanXbar 0 … 255 Enable automatic channel select for the ADC crossbar.
If enableAutoChanXbar = 0, then the auto channel selection is disabled.
If enableAutoChanXbar > 0, then the auto channel selection is enabled.
obsRxSyncbSelect 0…1 SYNCB selection—selects which SYNCINB input is connected to the framer.
If obsRxSyncbSelect = 0, then SYNCINB0 is connected to the framer.
If obsRxSyncbSelect = 1, then SYNCINB1 is connected to the framer.
overSample 0…1 Oversample mode—selects which method is chosen when oversample or bit repeat is required.
If overSample = 0, then bit repeat mode is selected.
If overSample = 1, then oversample is selected.

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UG-992 AD9371/AD9375 System Development User Guide
API Functions DEPENDENCIES
MYKONOS_setupJesd204bFramer(…) The dependencies for the MYKONOS_
mykonosErr_t setupJesd204bFramer(…) function are as follows:
MYKONOS_setupJesd204bFramer(mykonosDevice
_t *device);
• device → spiSettings
• device → spiSettings → chipSelectIndex
This function is called directly from MYKONOS_Intialize(). It
• device → rx → framer → M
is not necessary to call this function if MYKONOS_Intialize() is
• device → rx → realIfData
used. This function sets up the JESD204B Rx framer.
• device → rx → framer → bankId
• device → rx → framer → lane0Id
• device → rx → framer → serializerLanesEnabled
• device → rx → framer → obsRxSyncbSelect
• device → rx → framer → K
• device → rx → framer → externalSysref
• device → rx → rxChannels
• device → rx → framer → newSysrefOnRelink
• device → rx → framer → enableAutoChanXbar
• device → rx → framer → lmfcOffset
• device → rx → framer → scramble

Table 10. MYKONOS_setupJesd204bFramer(…) Parameters

Parameter Description
device Pointer to the device settings structure

Table 11. MYKONOS_setupJesd204bFramer(…) Return Values

Return Value Description
MYKONOS_ERR_OK Function completed successfully
MYKONOS_ERR_FRAMER_INV_REAL_IF_DATA_PARM Invalid framer M, M can only = 1 in real IF mode
MYKONOS_ERR_FRAMER_INV_M_PARM Invalid framer M (valid 1, 2, 4)
MYKONOS_ERR_FRAMER_INV_BANKID_PARM Invalid BankId (valid 0 to 15)
MYKONOS_ERR_FRAMER_INV_LANEID_PARM Invalid Lane0Id (valid 0 to 31)
MYKONOS_ERR_RXFRAMER_INV_FK_PARAM Invalid F × K value (F × K must be >20 and divisible by 4)
MYKONOS_ERR_FRAMER_INV_K_OFFSET_PARAM Invalid K offset, must be less than K

Rev. B | Page 28 of 360

AD9371/AD9375 System Development User Guide UG-992
MYKONOS_setupJesd204bObsRxFramer(…) DEPENDENCIES
mykonosErr_t The dependencies for the MYKONOS_
MYKONOS_setupJesd204bObsRxFramer(mykonosD setupJesd204bObsRxFramer(…) function are as follows:
evice_t *device);
• device → spiSettings
This function is called directly from
• device → spiSettings → chipSelectIndex
MYKONOS_Intialize(). It is not necessary to call this
function if MYKONOS_Intialize() is used. This function • device → rx → framer → M
sets up the JESD204B OBSRX framer. • device → rx → realIfData
• device → rx → framer → bankId
• device → rx → framer → lane0Id
• device → rx → framer → serializerLanesEnabled
• device → rx → framer → obsRxSyncbSelect
• device → rx → framer → K
• device → rx → framer → externalSysref
• device → rx → rxChannels
• device → rx → framer → newSysrefOnRelink
• device → rx → framer → lmfcOffset
• device → rx → framer → scramble

Table 12. MYKONOS_setupJesd204bObsRxFramer(…) Parameters

Parameter Description
device Pointer to the device settings structure

Table 13. MYKONOS_setupJesd204bObsRxFramer(…) Return Values

Return Value Description
MYKONOS_ERR_OK Function completed successfully
MYKONOS_ERR_OBSRX_FRAMER_INV_REAL_IF_DATA_PARM Invalid framer M, M can only = 1 in real IF mode
MYKONOS_ERR_OBSRX_FRAMER_INV_M_PARM Invalid framer M (valid 1, 2, 4)
MYKONOS_ERR_OBSRX_FRAMER_INV_BANKID_PARM Invalid BankId (valid 0 to 15)
MYKONOS_ERR_OBSRX_FRAMER_INV_LANEID_PARM Invalid Lane0Id (valid 0 to 31)
MYKONOS_ERR_OBSRX_RXFRAMER_INV_FK_PARAM Invalid F × K value (F × K must be >20 and divisible by 4)
MYKONOS_ERR_OBSRXFRAMER_INV_K_OFFSET_PARAM Invalid K offset, must be less than K

Rev. B | Page 29 of 360

UG-992 AD9371/AD9375 System Development User Guide
MYKONOS_setupSerializers(…) DEPENDENCIES
mykonosErr_t The dependencies for the MYKONOS_setupSerializers(…)
MYKONOS_setupSerializers(mykonosDevice_t function are as follows:
*device);
• device → spiSettings
This function is called directly from MYKONOS_Intialize(). It
• device → spiSettings → chipSelectIndex
is not necessary to call this function if MYKONOS_Intialize() is
used. This function sets up the JESD204B serializers. This • device → rx → framer → M
function uses the Rx framer and ObsRx framer structures to • device → rx → framer → serializerAmplitude
setup the four serializer lanes that are shared between the two • device → rx → framer → preEmphasis
framers. If the Rx profile is valid, the serializer amplitude and • device → rx → framer → serializerLanesEnabled
preemphasis are used from the Rx framer. If only the ObsRx • device → rx → framer → invertLanePolarity
profile is valid, the obsRx framer settings are used. • device → obsrx → framer → M
• device → obsrx → framer → serializerAmplitude
• device → obsrx → framer → preEmphasis
• device → obsrx → framer → serializerLanesEnabled
• device → obsrx → framer → invertLanePolarity

Table 14. MYKONOS_setupSerializers(…) Parameters

Parameter Description
device Pointer to the device settings structure

Table 15. MYKONOS_setupSerializers(…) Return Values

Return Value Description
MYKONOS_ERR_OK Function completed successfully
MYKONOS_ERR_INITSER_INV_VCODIV_PARM CLKPLL has invalid VCO divider, verify CLKPLL configuration
MYKONOS_ERR_SER_LANE_CONFLICT_PARM When both Rx and ObsRx framers are enabled, framers must not share the
same physical lane
MYKONOS_ERR_SER_INV_REAL_IF_DATA_PARM Rx Framer M can only = 1 when real IF mode is enabled
MYKONOS_ERR_SER_INV_M_PARM Invalid Rx Framer M (valid 1, 2, 4)
MYKONOS_ERR_SER_INV_LANEEN_PARM Invalid Rx framer serializerLanesEnabled (valid 0 to 15)
MYKONOS_ERR_SER_INV_AMP_PARM Invalid Rx serializer amplitude (valid 0 to 31)
MYKONOS_ERR_SER_INV_PREEMP_PARM Invalid Rx serializer preemphesis (valid 0 to 7)
MYKONOS_ERR_SER_INV_LANEPN_PARM Invalid Rx serializer pseudonoise (PN) invert setting (valid 0 to 15)
MYKONOS_ERR_SER_INV_L_PARM Invalid Rx serializer lanes enabled (must use 1, 2, or 4 lanes)
MYKONOS_ERR_SER_INV_LANERATE_PARM Invalid Rx serializer lane rate (valid 614.4 Mbps to 6144 Mbps)
MYKONOS_ERR_SER_LANE_RATE_CONFLICT_PARM Necessary lane rates for Rx and ObsRx framer cannot be obtained with
possible divider settings
MYKONOS_ERR_SER_INV_HSCLK_PARM Invalid HSCLK frequency (check CLKPLL config, HSCLK must be ≤ 6144 GHz)
MYKONOS_ERR_HS_AND_LANE_RATE_NOT_INTEGER_MULT HSCLK is not an integer multiple of the lane clock rate
MYKONOS_ERR_SER_INV_TXSER_DIV_PARM No valid Tx serializer divider to obtain desired lane rates
MYKONOS_ERR_INITSER_INV_PROFILE Rx/ObsRx and sniffer profiles are not valid, cannot configuration serializers
MYKONOS_ERR_INV_RXFRAMER_PCLKDIV_PARM Invalid Rx framer PCLK divider
MYKONOS_ERR_INV_OBSRXFRAMER_PCLKDIV_PARM Invalid ORx/sniffer framer PCLK divider

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AD9371/AD9375 System Development User Guide UG-992
MYKONOS_enableSysrefToRxFramer(…) processor (BBP) is ready to bring up the JESD204B link, call this
mykonosErr_t function with enable = 1 to allow the device Rx framer to retime
MYKONOS_enableSysrefToRxFramer(mykonosDev the local multiframe counter (LMFC) to the SYSREF.
ice_t *device, uint8_t enable);
DEPENDENCIES
This function can gate or allow the SYSREF at the outside of the
The dependencies for the MYKONOS_
device to reach the SYSREF input in the Rx framer IP in the
enableSysrefToRxFramer(…) function are as follows:
device. Typically, the framers ignore SYSREF (enable = 0) until
after multichip sync is completed. When the baseband • device → spiSettings

Table 16. MYKONOS_enableSysrefToRxFramer(…) Parameters

Parameter Description
device Pointer to the device settings structure
enable 1 enables SYSREF to the Rx framer, 0 disables SYSREF to the Rx framer

Table 17. MYKONOS_enableSysrefToRxFramer(…) Return Values

Return Value Description
MYKONOS_ERR_OK Function completed successfully

Rev. B | Page 31 of 360

UG-992 AD9371/AD9375 System Development User Guide
MYKONOS_enableSysrefToObsRxFramer(…) bring up the JESD204B link, call this function with enable = 1
mykonosErr_t to allow the ORx framer to retime the local multiframe counter
MYKONOS_enableSysrefToObsRxFramer(mykonos to the SYSREF.
Device_t *device, uint8_t enable);
DEPENDENCIES
This function gates or allows the SYSREF at the outside of the
The dependencies for the MYKONOS_enableSysrefToObsRx-
device to reach the SYSREF input in the ORx framer IP in the
Framer(…) function are as follows:
device. Typically, the framers ignore SYSREF (enable = 0) until
after multichip sync. When the baseband processor is ready to • device → spiSettings

Table 18. MYKONOS_enableSysrefToObsRxFramer(…) Parameters

Parameter Description
device Pointer to the device settings structure
enable 1 enables the SYSREF to the ORx framer, 0 disables the SYSREF to the ORx framer

Table 19. MYKONOS_enableSysrefToObsRxFramer(…) Return Values

Return Value Description
MYKONOS_ERR_OK Function completed successfully

Rev. B | Page 32 of 360

AD9371/AD9375 System Development User Guide UG-992
MYKONOS_enableRxFramerLink(…) DEPENDENCIES
mykonosErr_t The dependencies for the MYKONOS_
MYKONOS_enableRxFramerLink(mykonosDevice_ enableRxFramerLink(…) function are as follows:
t *device, uint8_t enable);
• device → spiSettings
This function is normally not necessary. In the event that the
• device → rx → framer → serializerLanesEnabled
link must be reset, this function allows the Rx framer to be
disabled and reenabled.

Table 20. MYKONOS_enableRxFramerLink(…) Parameters

Parameter Description
device Pointer to the device settings structure
enable 1 enables the Rx framer, 0 disables the Rx framer

Table 21. MYKONOS_enableRxFramerLink(…) Return Values

Return Value Description
MYKONOS_ERR_OK Function completed successfully
MYKONOS_ERR_ENFRAMERLINK_INV_LANESEN_PARAM Invalid serializerLanesEnabled parameter in the device data structure (valid 0 to 15)

Rev. B | Page 33 of 360

UG-992 AD9371/AD9375 System Development User Guide
MYKONOS_enableObsRxFramerLink(…) DEPENDENCIES
mykonosErr_t The dependencies for the MYKONOS_
MYKONOS_enableObsRxFramerLink(mykonosDevi enableObsRxFramerLink(…) function are as follows:
ce_t *device, uint8_t enable);
• device → spiSettings
This function is normally not necessary. In the event that the
• device → obsRx → framer → serializerLanesEnabled
link must be reset, this function allows the ORx framer to be
disabled and reenabled.

Table 22. MYKONOS_enableObsRxFramerLink(…) Parameters

Parameter Description
device Pointer to the device settings structure
enable 1 enables the ORx framer, 0 disables the ORx framer

Table 23. MYKONOS_enableObsRxFramerLink(…) Return Values

Return Value Description
MYKONOS_ERR_OK Function completed successfully
MYKONOS_ERR_ENFRAMERLINK_INV_LANESEN_PARAM Invalid serializerLanesEnabled parameter in the device data structure (valid 0 to 15)

Rev. B | Page 34 of 360

AD9371/AD9375 System Development User Guide UG-992
MYKONOS_readRxFramerStatus (…) DEPENDENCIES
mykonosErr_t The dependencies for the MYKONOS_readRxFramerStatus (…)
MYKONOS_readRxFramerStatus(mykonosDevice_ function are as follows:
t *device, uint8_t *framerStatus);
• device → spiSettings
This function reads back the Rx framer status to determine the
state of the JESD204B Rx framer link. The framerStatus return
value returns an 8-bit status word.

Table 24. MYKONOS_readRxFramerStatus (…) Parameters

Parameter Description
device Pointer to the device settings structure
framerStatus Rx framer status byte as described in Table 25

Table 25. Rx Framer Status Byte

framerStatus Description
7 SYSREF phase error—a new SYSREF has different timing than the first that set the local multiframe counter (LMFC) timing.
6 Framer lane first in, first out (FIFO) read/write pointer delta has changed. Can help debug issues with deterministic
latency.
5 Framer has received the SYSREF and has retimed its LMFC.
[4:2] Framer initial lane assignment sequence (ILAS) state.
0 = code group synchronization (CGS).
1 = 1st multframe.
2 = 2nd multiframe.
3 = 3rd multiframe.
4 = 4th multiframe.
5 = last multiframe.
6 = invalid.
7 = ILAS complete.
[1:0] Framer Tx state.
0 = CGS.
1 = ILAS.
2 = ADC data.

Table 26. MYKONOS_readRxFramerStatus (…) Return Values

Return Value Description
MYKONOS_ERR_OK Function completed successfully
MYKONOS_ERR_READ_RXFRAMERSTATUS_NULL_PARAM Function parameter framerStatus has null pointer

Rev. B | Page 35 of 360

UG-992 AD9371/AD9375 System Development User Guide
MYKONOS_readObsRxFramerStatus (…) DEPENDENCIES
mykonosErr_t The dependencies for the MYKONOS_readObsRxFramerStatus
MYKONOS_readObsRxFramerStatus(mykonosDevi (…) function are as follows:
ce_t *device, uint8_t *framerStatus);
• device → spiSettings
This function read back the observation Rx framer status to
determine the state of the JESD204B ORx framer link. The
framerStatus return value returns an 8-bit status word.

Table 27. MYKONOS_readObsRxFramerStatus (…) Parameters

Parameter Description
device Pointer to the device settings structure
obsFramerStatus ORx framer status byte as described in Table 28

Table 28. ORx Framer Status Byte

obsFramerStatus Description
7 SYSREF phase error—a new SYSREF had different timing than the first that set the local multiframe counter timing.
6 Framer lane FIFO read/write pointer delta has changed. Can help debug issues with deterministic latency.
5 Framer has received the SYSREF and has retimed its local multiframe counter.
[4:2] Framer initial lane assignment sequence (ILAS) state.
0 = code group synchronization (CGS).
1 = 1st multframe.
2 = 2nd multiframe.
3 = 3rd multiframe.
4 = 4th multiframe.
5 = last multiframe.
6 = invalid.
7 = ILAS complete.
[1:0] Framer Tx state.
0 = CGS.
1 = ILAS.
2 = ADC data.

Table 29. MYKONOS_readObsRxFramerStatus (…) Return Values

Return Value Description
MYKONOS_ERR_OK Function completed successfully
MYKONOS_ERR_READ_ORXFRAMERSTATUS_NULL_PARAM Function parameter obsFramerStatus has null pointer

Rev. B | Page 36 of 360

AD9371/AD9375 System Development User Guide UG-992
MYKONOS_enableRxFramerPrbs (…) The PRBS order can be set to MYK_PRBS7, MYK_PRBS15,
mykonosErr_t or MYK_PRBS31 by the enumerated list value passed into the
MYKONOS_enableRxFramerPrbs(mykonosDevice_ polyOrder parameter. The PRBS generator can be enabled (1)
t *device, mykonosPrbsOrder_t polyOrder, or disabled (0) by the enable parameter.
uint8_t enable);
Note that if both the Rx framer and ORx framer crossbar
After the serializer and framer are configured with settings overlap and use the same lanes, the data from the two
MYKONOS_initialize(…), this function can be called to enable framers is logically OR’ed together. This results in unexpected
the Rx framer to output a pseudorandom bit sequence (PRBS) data being output from the serializer lanes.
pattern on the serializer lanes. Only the serializer lanes connected
to the Rx framer are output. Review the lane crossbar settings DEPENDENCIES
configured in the Rx framer data structure to verify which lanes The dependencies for the MYKONOS_enableRxFramerPrbs (…)
are affected. function are as follows:
• device → spiSettings

Table 30. MYKONOS_enableRxFramerPrbs (…) Parameters

Parameter Description
device Pointer to the device settings structure
polyOrder Selects the pseudorandom bit sequence (PRBS) type based on enumeration value: MYK_PRBS7, MYK_PRBS15, MYK_PRBS31
enable 1 enables PRBS generator in the Rx framer, 0 disables the PRBS generator

Table 31. MYKONOS_enableRxFramerPrbs (…) Return Values

Return Value Description
MYKONOS_ERR_OK Function completed successfully
MYKONOS_ERR_RX_FRAMER_INV_PRBS_POLYORDER_PARAM Invalid polyOrder parameter, use proper enumerator

Rev. B | Page 37 of 360

UG-992 AD9371/AD9375 System Development User Guide
MYKONOS_enableObsRxFramerPrbs (…) The PRBS order can be set to MYK_PRBS7, MYK_PRBS15, or
mykonosErr_t MYK_PRBS31 by the enumeration value passed into the
MYKONOS_enableObsRxFramerPrbs(mykonosDevi polyOrder parameter. The PRBS generator can be enabled (1)
ce_t *device, mykonosPrbsOrder_t or disabled (0) by the enable parameter.
polyOrder, uint8_t enable);
Note that if both the Rx framer and the ORx framer crossbar
After the serializer and framer are configured with settings overlap and use the same lanes, the data from the two
MYKONOS_initialize(…), this function can be called to enable framers is logically OR’ed together. This results in unexpected
the ORx framer to output a pseudorandom bit sequence (PRBS) data being output from the serializer lanes.
pattern on the serializer lanes. Only the serializer lanes connected
to the ORx framer are output. Review the lane crossbar settings DEPENDENCIES
configured in the ORx framer data structure to verify which The dependencies for the MYKONOS_enableObsRxFramerPrbs
lanes are affected. (…) function are as follows:
• device → spiSettings

Table 32. MYKONOS_enableObsRxFramerPrbs(…) Parameters

Parameter Description
device Pointer to the device settings structure
polyOrder Selects the pseudorandom bit sequence (PRBS) type based on enumeration value: MYK_PRBS7, MYK_PRBS15, MYK_PRBS31
enable 1 enables the PRBS generator in the ORx framer, 0 disables the PRBS generator

Table 33. MYKONOS_enableObsRxFramerPrbs(…) Return Values

Return Value Description
MYKONOS_ERR_OK Function completed successfully
MYKONOS_ERR_OBSRX_FRAMER_INV_PRBS_POLYORDER_PARAM Invalid polyOrder parameter, use proper enumerator

Rev. B | Page 38 of 360

AD9371/AD9375 System Development User Guide UG-992
MYKONOS_rxInjectPrbsError PRBS checker to increment. Calling this function injects one to
mykonosErr_t three errors into the framer PRBS generation.
MYKONOS_rxInjectPrbsError(mykonosDevice_t DEPENDENCIES
*device);
The dependencies for the MYKONOS_rxInjectPrbsError
To verify pseudorandom bit sequence (PRBS) is working
function are as follows:
correctly on a good link, errors can be injected to force the
• device → spiSettings

Table 34. MYKONOS_rxInjectPrbsError Parameters

Parameter Description
device Pointer to the device settings structure

Table 35. MYKONOS_rxInjectPrbsError Return Values

Return Value Description
MYKONOS_ERR_OK Function completed successfully

Rev. B | Page 39 of 360

UG-992 AD9371/AD9375 System Development User Guide
MYKONOS_obsRxInjectPrbsError DEPENDENCIES
mykonosErr_t The dependencies for the MYKONOS_obsRxInjectPrbsError
MYKONOS_obsRxInjectPrbsError(mykonosDevic function are as follows:
e_t *device);
• device → spiSettings
To verify PRBS is working correctly on a good link, errors can
be injected to force the PRBS checker to increment. Calling this
function injects one to three errors into the ORx framer PRBS
generation.

Table 36. MYKONOS_obsRxInjectPrbsError Parameters

Parameter Description
device Pointer to the device settings structure

Table 37. MYKONOS_obsRxInjectPrbsError Return Values

Return Value Description
MYKONOS_ERR_OK Function completed successfully

Rev. B | Page 40 of 360

AD9371/AD9375 System Development User Guide UG-992
TRANSMITTERS (DAC) DATAPATH Deserializer Configuration
The device has one JESD204B deframer configurable for up to The deserializer includes an equalizer that can be set to a fixed
four lanes and four DAC converters. All converters must run at setting. Table 40 summarizes the amount of insertion loss each
the same sample rate. Likewise, all lanes must run at the same equalizer setting can overcome. Note that the measured length
data rate. The deframer is capable of receiving a pseudorandom is the value at which the eye diagram is nearly failing the receive
bit sequence (PRBS) sequence and accumulating error counts. mask for each equalizer setting.
The deserializers have adjustable equalization circuits (fixed Deframer
setting, not adaptive) to counteract the insertion loss due to
The deframer receives 8-bit/10-bit encoded data from the
various PCB trace lengths and materials.
deserializer and decodes the data into 16-bit DAC samples.
Supported Deframer Link Parameters Because the DAC samples are only 14-bit, the device uses the
The device supports a subset of possible JESD204B link upper 14-bits of the 16-bit word DAC samples by default. The
configurations. The modes are limited by the number of DACs deserializer to DAC sample mapping changes depending on the
and the number of JESD204B lanes implemented in the silicon. JESD204B link configuration setting. The responsibilities of the
deframer are as follows:
For a particular converter sample rate, not all combinations
listed in Table 39 are valid. For the JESD204B configuration • Monitor the JESD204B link for running disparity errors
mode to be valid, the lane rate for that mode must be within the (controls the SYNCOUT_B signal to reset the link or
614.4 Mbps to 6144 Mbps range. The lane rate is the serial bit report errors).
rate for one lane of the JESD204B link. Calculate the lane rate • Control the JESD204B interrupt signal (can output on
using Equation 1. general-purpose interrupt pin) to signal baseband processor
The deserializer link is allowed to run at a different lane rate when certain JESD204B error conditions arise.
than the serializer link, under the condition that both lane • Remove character replacement.
rates are possible with respect to the clock divider settings. • Perform 8-bit/10-bit decoding.
Both the deserializer and serializer link rates are derived from • Map JESD204B lane data to DAC samples.
the same clock PLL, but there are separate dividers to generate
A lane crossbar provides the ability to reorder the lanes into the
the deserializer clock data recovery (CDR) clock and the
deframer input. A sample crossbar provides the ability to reorder
serializer clock.
the DAC samples at the output of the deframer. The lane and
sample crossbars enable flexiblity on which physical lanes are
used and what data is on each lane. Figure 20 to Figure 25
demonstrate the valid deframer configurations.

Table 38. Static JESD204B Parameters

JESD204B Parameter AD9371/AD9375 Value Description
S 1 Samples transmitted/single converter/frame cycle
N 16 Converter resolution
N’ 16 Total number of bits per sample
CF 0 Number of control words/frame clock cycle/converter device
CS 0 Number of control bits/conversion sample
HD 0 or 1 High density mode (only M = 2, L = 4 uses HD = 1)
K Variable, suggested: 32 Number of frames in 1 multiframe, (20 ≤ F × K ≤ 256), F × K must be a multiple of 4, K ≤ 32

Table 39. JESD204B Parameters Dependent on Number of Lanes and Number of DACs
Number of DACs (M) Number of Lanes (L) Number of Bytes in 1 Frame (F) (F = 2 × M/L)
2 1 4
2 2 2
2 4 1
4 1 8
4 2 4
4 4 2

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UG-992 AD9371/AD9375 System Development User Guide
Table 40. Measured Deserializer Equalizer Correction (Nomimal 1.3 V, 25°C)
Equalizer (EQ) Setting 3 GHz Loss (dB) 6 GHz Loss (dB) FR408HR Length (Inches) FR4 Length (Inches)
0 6.5 14 20 12
1 11.5 21 30 20
2 18 31 46 32
3 21.5 38 56 40
4 22 39 60 43

SAMPLE DEFRAMER LANE

CROSSBAR CROSSBAR
Tx1 Q[15:0]
DAC0[15:0]
Tx1 I[15:0] 1 FRAME (M = 2, L = 1, F = 4)
DAC1[15:0]
Tx2 Q[15:0] DAC0 DAC0 DAC1 DAC1 8-BIT/10-BIT LANE 0
Tx2 I[15:0] [15:8] [7:0] [15:8] [7:0] DECODE LANE 1

14652-018
LANE 2
FIRST BYTE LANE 3
FROM DESERIALIZER

Figure 20. M2L1 Lane to DAC Byte Order

SAMPLE DEFRAMER LANE

CROSSBAR 1 FRAME CROSSBAR
Tx1 Q[15:0]
DAC0[15:0] (M = 2, L = 2, F = 2)
Tx1 I[15:0]
DAC1[15:0] DAC0 DAC0
Tx2 Q[15:0] 8-BIT/10-BIT LANE 0
[15:8] [7:0]
Tx2 I[15:0] FIRST BYTE DECODE LANE 1
DAC1 DAC1

14652-019
FROM 8-BIT/10-BIT LANE 2
DESERIALIZER [15:8] [7:0]
DECODE LANE 3

Figure 21. M2L2 Lane to DAC Byte Order

SAMPLE DEFRAMER 1 FRAME LANE

CROSSBAR (M = 2, L = 4, F = 1) CROSSBAR
Tx1 Q[15:0]
DAC0[15:0] DAC0
Tx1 I[15:0] 8-BIT/10-BIT
DAC1[15:0] [15:8] DECODE
Tx2 Q[15:0] LANE 0
Tx2 I[15:0] DAC0 8-BIT/10-BIT
[7:0] LANE 1
DECODE LANE 2
DAC1 8-BIT/10-BIT LANE 3
[15:8] DECODE
DAC1 8-BIT/10-BIT
[7:0] DECODE

14652-020
NOTES
1. HD = 1 (1 SAMPLE SPLIT ACROSS MULTIPLE LANES).

Figure 22. M2L4 Lane to DAC Byte Order

SAMPLE DEFRAMER LANE

CROSSBAR CROSSBAR
Tx1 Q[15:0]
DAC0[15:0]
Tx1 I[15:0] 1 FRAME (M = 4, L = 1, F = 8)
DAC1[15:0]
Tx2 Q[15:0] DAC0 DAC0 DAC1 DAC1 DAC2 DAC2 DAC3 DAC3 8-BIT/10-BIT LANE 0
DAC2[15:0]
Tx2 I[15:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] ENCODE LANE 1
DAC3[15:0]
14652-021

LANE 2
FIRST BYTE
FROM DESERIALIZER LANE 3

Figure 23. M4L1 Lane to DAC Byte Order

SAMPLE DEFRAMER ONLY IN THIS CASE, LANE

CROSSBAR DEFRAMER INPUT PORTS CROSSBAR
Tx1 Q[15:0]
DAC0[15:0] 0 AND 2 ARE USED
Tx1 I[15:0] 1 FRAME (M = 4, L = 2, F = 4)
DAC1[15:0]
Tx2 Q[15:0] DAC2[15:0] DAC0 DAC0 DAC1 DAC1 8-BIT/10-BIT LANE 0
Tx2 I[15:0] [15:8] [7:0] [15:8] [7:0] ENCODE LANE 1
DAC3[15:0] FIRST BYTE
14652-022

DAC2 DAC2 DAC3 DAC3 8-BIT/10-BIT LANE 2

FROM [15:8] [7:0] [15:8] [7:0]
DESERIALIZER ENCODE LANE 3

Figure 24. M4L2 Lane to DAC Byte Order

Rev. B | Page 42 of 360

AD9371/AD9375 System Development User Guide UG-992
SAMPLE DEFRAMER 1 FRAME LANE
CROSSBAR (M = 4, L = 4, F = 2) CROSSBAR
Tx1 Q[15:0]
DAC0[15:0] DAC0 DAC0
Tx1 I[15:0] 8-BIT/10-BIT
DAC1[15:0] [15:8] [7:0] DECODE
Tx2 Q[15:0] DAC2[15:0] LANE 0
Tx2 I[15:0] DAC1 DAC1 8-BIT/10-BIT LANE 1
DAC3[15:0] FIRST BYTE [15:8] [7:0] DECODE
FROM LANE 2
DAC2 DAC2 8-BIT/10-BIT LANE 3
DESERIALIZER [15:8] [7:0] DECODE

14652-023
DAC3 DAC3 8-BIT/10-BIT
[15:8] [7:0] DECODE

Figure 25. M4L4 Lane to DAC Byte Order

SINGLE CHANNEL
AUTO SELECT DAC/SAMPLE CROSSBAR LANE CROSSBAR
DEFRAMER
11 11 LANE 3
DEFRAMER OUTPUT 3[15:0] DEFRAMER INPUT 3[15:0]
0 M3 10 10 LANE 2
Tx2 I DEFRAMER OUTPUT 2[15:0] DEFRAMER INPUT 2[15:0]
DAC3 01 01 LANE 1
1 DEFRAMER OUTPUT 1[15:0] DEFRAMER INPUT 1[15:0]
00 00 LANE0
DEFRAMER OUTPUT 0[15:0] DEFRAMER INPUT 0[15:0]

11
11
10
0 M2 10
Tx2 Q 01
DAC2 01
1 00
00

11
11
10
Tx1 I M1 10
DAC1 01
01
00
00

11
11
M0 10
Tx1 Q 10
DAC0 01
01
00

14652-024
00

Figure 26. Deframer Lane Mux and Sample Mux Details

Other Useful Deframer IP Features 4. After some amount of time, call the API function to check
Deserializer PRBS the PRBS errors. This can be done by calling the API
function MYKONOS_readDeframerPrbsCounters(…)
The deserializer has a built in pseudorandom bit sequence
passing the actual device being evaluated, the counter
(PRBS) checker. The PRBS checker can self synchronize and
selection lane to be read and the error count are returned
check for PRBS errors on a PRBS7, PRBS15, or PRBS31 sequence.
in the third parameter passed.
Because this mode works even in the midst of potential bit errors
on each lane, the physical link can be debugged even when the To prove an error count of 0 is valid, the baseband processor
deframer is unable to work properly. This mode can be used to may have a PRBS error inject feature. Alternatively, the
check the robustness of the physical link during initial testing baseband processor amplitude and emphasis settings can be
and/or factory test. For this mode to be fully utilized, the BPP set to a setting where errors occur. To reset the error count,
must have a PRBS generator capable of creating PRBS7, call the API function that clears the counters (MYKONOS_
PRBS15, or PRBS31 data. clearDeframerPrbsCounters(…)).
A typical usage sequence is as follows: API Software Integration
1. Initialize the device as outlined in the Link Establishment the MYKONOS_initialize(…) API function handles the
section. configuration of the deserializer and Tx1/Tx2 deframer. Set any
2. Enable the PRBS generator on the baseband processor with JESD204B link options in the mykonosDevice_t data structure
the same PRBS sequence required. before calling MYKONOS_initialize(…). After initialization,
3. Call the application programming interface (API) there are some other API functions to aid in debugging and
MYKONOS_enableDeframerPrbsChecker(…) passing monitoring the status of the JESD204B link.
the actual device being evaluated, the PRBS sequence to
check and enable bit set to 1.

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UG-992 AD9371/AD9375 System Development User Guide
JESD204B Deframer API Data Structures uint8_t externalSysref;
mykonosJesd204bDeframerConfig_t uint8_t deserializerLanesEnabled;
typedef struct uint8_t deserializerLaneCrossbar;
{ uint8_t EQSetting;
uint8_t bankId; uint8_t invertLanePolarity;
uint8_t deviceId; uint8_t lmfcOffset;
uint8_t lane0Id; uint8_t newSysrefOnRelink;
uint8_t M; uint8_t enableAutoChanXbar;
uint8_t K; } mykonosJesd204bDeframerConfig_t;
uint8_t scramble;

Table 41. Deframer Structure Member Description

Structure Member Valid Values Description
bankID 0 … 15 JESD204B configuration bank ID—extension to device ID.
deviceID 0 … 255 JESD204B configuration device ID—link identification number.
lane0ID 0 … 31 JESD204B configuration lane ID—if more than one lane is used, each subsequent lane
increments from this number.
M 0, 2, 4 Number of DAC converters—2 converters per receive chain.
K 1 … 32 Number of frames in a multiframe—default is 32.
F × K must be a multiple of 4.
scramble 0 … 255 Scrambling enabled.
If scramble = 0, then scrambling is disabled.
If scramble > 0, then scrambling is enabled.
externalSysref 0 … 255 External SYSREF enabled.
If externalSysref = 0, then use internal SYSREF.
If externalSysref > 0, then use external SYSREF.
deserializerLanesEnabled 0x0 … 0xF Deserializer lane enabled—one bit per lane.
If Bit 0 = 0, then Lane 0 is disabled; if Bit 0 = 1, then Lane 0 is enabled.
If Bit 1 = 0, then Lane 1 is disabled; if Bit 1 = 1, then Lane 1 is enabled.
If Bit 2 = 0, then Lane 2 is disabled; if Bit 2 = 1, then Lane 2 is enabled.
If Bit 3 = 0, then Lane 3 is disabled; if Bit 3 = 1, then Lane 3 is enabled.
deserializerLaneCrossbar 0x0 … 0xFF Deserializer lane crossbar—two bits per lane.
Bits[1:0] identify the deserializer lane that connects to Deframer Lane 0.
Bits[3:2] identify the deserializer lane that connects to Deframer Lane 1.
Bits[5:4] identify the deserializer lane that connects to Deframer Lane 2.
Bits[7:6] identify the deserializer lane that connects to Deframer Lane 3.
EQSetting 0…4 Equalizer setting, see Table 40 for details.
invertLanePolarity 0x0 … 0xF Deserializer lane polarity inversion.
If Bit 0 = 0, then Lane 0 is unaffected; if Bit 0 = 1, then Lane 0 is inverted.
If Bit 1 = 0, then Lane 1 is unaffected; if Bit 1 = 1, then Lane 1 is inverted.
If Bit 2 = 0, then Lane 2 is unaffected; if Bit 2 = 1, then Lane 2 is inverted.
If Bit 3 = 0, then Lane 3 is unaffected; if Bit 3 = 1, then Lane 3 is inverted.
lmfcOffset 0 … 31 Local multiframe counter (LMFC) offset—local multiframe counter offset value for deterministic
latency setting, set this such that 0 ≤ lmfcOffset ≤ (K − 1).
newSysrefOnRelink 0 … 255 New SYSREF on Relink—flag to indicate that a SYSREF is required to reestablish the link.
If newSysrefOnRelink = 0, then no SYSREF is required.
If newSysrefOnRelink > 0, then SYSREF is required.
enableAutoChanXbar 0 … 255 Enable automatic channel select for the ADC crossbar.
If enableAutoChanXbar = 0, then the auto channel selection is disabled.
If enableAutoChanXbar > 0, then the auto channel selection is enabled.

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AD9371/AD9375 System Development User Guide UG-992
API Functions DEPENDENCIES
MYKONOS_setupJesd204bDeframer(…) The dependencies for the MYKONOS_
mykonosErr_t setupJesd204bDeframer(…) function are as follows:
MYKONOS_setupJesd204bDeframer(mykonosDevi • device → spiSettings
ce_t *device);
• device → spiSettings → chipSelectIndex
This function is called directly from MYKONOS_Intialize(). It • device → tx → deframer → M
is not necessary to call this function if MYKONOS_Intialize() is • device → tx → deframer → bankId
used. This function sets up the JESD204B deframer. • device → tx → deframer → lane0Id
• device → tx → deframer → deserializerLanesEnabled
• device → tx → deframer → K
• device → tx → deframer → externalSysref
• device → tx → deframer → newSysrefOnRelink
• device → tx → deframer → enableAutoChanXbar
• device → tx → deframer → lmfcOffset
• device → tx → deframer → scramble

Table 42. MYKONOS_setupJesd204bDeframer(…) Parameters

Parameter Description
device Pointer to the device settings structure

Table 43. MYKONOS_setupJesd204bDeframer(…) Return Values

Return Value Description
MYKONOS_ERR_OK Function completed successfully
MYKONOS_ERR_DEFRAMER_INV_M_PARM Invalid framer M (valid 1, 2, 4)
MYKONOS_ERR_DEFRAMER_INV_BANKID_PARM Invalid bankId (valid 0 to 15)
MYKONOS_ERR_DEFRAMER_INV_LANEID_PARM Invalid lane0Id (valid 0 to 31)
MYKONOS_ERR_DEFRAMER_INV_K_PARAM Invalid K parameter in deframer structure (valid 1 to 32 with other constraints)
MYKONOS_ERR_DEFRAMER_INV_FK_PARAM Invalid F × K value (F × K must be >20 and divisible by 4)
MYKONOS_ERR_DEFRAMER_INV_K_OFFSET_PARAM Invalid K offset, must be less than K

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UG-992 AD9371/AD9375 System Development User Guide
MYKONOS_setupDeserializers(…) DEPENDENCIES
mykonosErr_t The dependencies for the MYKONOS_setupDeserializers(…)
MYKONOS_setupDeserializers(mykonosDevice_ function are as follows:
t *device);
• device → spiSettings
This function is called directly from MYKONOS_Intialize().
• device → spiSettings → chipSelectIndex
It is not necessary to call this function if MYKONOS_Intialize()
is used. This function sets up the JESD204B deserializers. This • device → tx → txProfile → clkPllVcoDiv
function enables the necessary deserializer lanes, sets the • device → tx → txProfile → vcoFreq_kHz
deserializer clocks polarity inversion settings, and determines • device → tx → txProfile → txIqRate_kHz
equalizer settings based on the information found in the device • device → tx → deframer → M
data structure. • device → tx → deframer → deserializerLanesEnabled
• device → tx → deframer → invertLanePolarity
• device → tx → deframer → EQSetting

Table 44. MYKONOS_setupDeserializers(…) Parameters

Parameter Description
device Pointer to the device settings structure

Table 45. MYKONOS_setupDeserializers(…) Return Values

Return Value Description
MYKONOS_ERR_OK Function completed successfully
MYKONOS_ERR_INITDES_INV_TXPROFILE Tx profile is not valid in data structure; cannot setup deserializer
MYKONOS_ERR_INITDES_INV_VCODIV_PARM CLKPLL VCO divider is invalid
MYKONOS_ERR_DESER_INV_M_PARM Invalid M (valid 2 or 4)
MYKONOS_ERR_DESER_INV_L_PARM Invalid L (valid 1, 2, 4)
MYKONOS_ERR_DESER_INV_HSCLK_PARM Invalid HSCLK, must be 6.144 G or less after CLKPLL VCO divider; verify
CLKPLL configuration
MYKONOS_ERR_DESER_INV_LANERATE_PARM Invalid lane rate, must be between 614.4 Mbps to 6144 Mbps
MYKONOS_ERR_DESER_INV_LANEEN_PARM Invalid deserializerLanesEnabled (valid 0 to 15 in 1, 2, and 4 lane
combinations)
MYKONOS_ERR_DESER_INV_EQ_PARM Invalid equalizer parameter (valid 0 to 4)
MYKONOS_ERR_DESER_INV_LANEPN_PARM Invalid pseudonoise (PN) invert setting, (valid 0 to 15, invert bit per lane)
MYKONOS_ERR_DES_HS_AND_LANE_RATE_NOT_INTEGER_MULT Invalid clock settings, HSCLK is not an integer multiple of lane rate

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AD9371/AD9375 System Development User Guide UG-992
MYKONOS_resetDeframer(…) lost. This can lead the lane FIFO to have underflow/overflow
mykonosErr_t errors. This function resets the lane FIFOs and deframer IP.
MYKONOS_resetDeframer(mykonosDevice_t This also resets the SYSREF received internal signal. Therefore,
*device); send a SYSREF after this reset to properly retime the deframers
It is important to reset the deframer after the baseband local multiframe counter (LMFC).
processor (BBP) begins outputting code group synchronization DEPENDENCIES
(CGS) characters on the JESD204B link. The lane FIFOs in the
The dependencies for the MYKONOS_resetDeframer(…)
deframer path use the clock data recovery (CDR), recovered,
function are as follows:
clock. If the BBP ever resets the PLLs or clocking that drive the
BBP serializer data, the recovered CDR clock in the device is • device → spiSettings

Table 46. MYKONOS_resetDeframer(…) Parameters

Parameter Description
device Pointer to the device settings structure

Table 47. MYKONOS_resetDeframer(…) Return Values

Return Value Description
MYKONOS_ERR_OK Function completed successfully

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UG-992 AD9371/AD9375 System Development User Guide
MYKONOS_enableSysrefToDeframer(…) is ready to bring up the JESD204B link, call this function with
mykonosErr_t enable = 1 to allow the deframer to retime its local multiframe
MYKONOS_enableSysrefToDeframer(mykonosDev counter (LMFC) to the SYSREF.
ice_t *device, uint8_t enable);
DEPENDENCIES
This function can gate or allow the SYSREF at the outside of the
The dependencies for the MYKONOS_
device to reach the SYSREF input in the deframer IP in the
enableSysrefToDeframer(…) function are as follows:
device. Typically, the deframer ignores SYSREF (enable = 0)
until after multichip sync. When the baseband processor (BBP) • device → spiSettings

Table 48. MYKONOS_enableSysrefToDeframer(…) Parameters

Parameter Description
device Pointer to the device settings structure
enable 1 enables SYSREF to deframer, 0 disables SYSREF to deframer

Table 49. MYKONOS_enableSysrefToDeframer(…) Return Values

Return Value Description
MYKONOS_ERR_OK Function completed successfully

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AD9371/AD9375 System Development User Guide UG-992
MYKONOS_getDeframerFifoDepth(…) power-up, deterministic latency may not be met. If an underflow
mykonosErr_t or overflow occurs, the data may still be correct, but it might
MYKONOS_enableSysrefToDeframer(mykonosDev slip by one multiframe (losing deterministic latency). To correct
ice_t *device, uint8_t *fifoDepth, an overflow/underflow, the baseband processor must add delay
uint8_t *readEnLmfcCount); from SYSREF until the first symbol in a multiframe.
This function reads the JESD204B deframer deterministic FIFO DEPENDENCIES
depth. To verify that the deterministic latency FIFO is not close
to a underflow or overflow condition, it is recommended to The dependencies for the MYKONOS_
check the FIFO depth. If the FIFO is close to an overflow or getDeframerFifoDepth(…) function are as follows:
underflow condition, it is possible that, from power-up to • device → spiSettings

Table 50. MYKONOS_getDeframerFifoDepth(…) Parameters

Parameter Description
device Pointer to the device settings structure
fifoDepth Returns the depth of the deframer deterministic latency FIFO
readEnLmfcCount Returns the local multiframe counter (LMFC) count value when the deterministic latency FIFO read enable was
asserted; counts are at the internal deframer PCLK frequency

Table 51. MYKONOS_getDeframerFifoDepth(…) Return Values

Return Value Description
MYKONOS_ERR_OK Function completed successfully
MYKONOS_ERR_READ_DEFFIFODEPTH_NULL_PARAM Function parameter fifoDepth is a null pointer
MYKONOS_ERR_READ_DEFFIFODEPTH_LMFCCOUNT_NULL_PARAM Function parameter readEnLmfcCount is a null pointer

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UG-992 AD9371/AD9375 System Development User Guide
MYKONOS_readDeframerStatus(…) DEPENDENCIES
mykonosErr_t The dependencies for the MYKONOS_readDeframerStatus(…)
MYKONOS_readDeframerStatus(mykonosDevice_ function are as follows:
t *device, uint8_t *deframerStatus);
• device → spiSettings
After bringing up the deframer JESD204B link, the baseband
processor (BBP) checks the status of the deframer.

Table 52. MYKONOS_readDeframerStatus(…) Parameters

Parameter Description
device Pointer to the device settings structure
deframerStatus Deframer status byte as described in Table 53

Table 53. deframerStatus Byte

deframerStatus Bit Name Description
7 Unused Unused.
6 Deframer IRQ This bit indicates that the IRQ interrupt is asserted.
5 Deframer SYSREF received When this bit is set, it indicates that the SYSREF pulse is received by the deframer IP.
4 Deframer receiver error This bit is set when pseudorandom bit sequence (PRBS) receives an error.
u Valid checksum This bit is set when the received initial lane assignment sequence (ILAS) checksum is valid.
2 EOF event This bit captures the internal status of the framer end of frame (EOF) event. Value = 1 if
framing error during ILAS.
1 EOMF event This bit captures the internal status of the framer end of multiframe (EOMF) event. Value =
1 if framing error during ILAS.
0 FS lost This bit captures the internal status of the framer frame symbol (FS) event. Value = 1 if
framing error during ILAS or user data (invalid replacement characters).

Table 54. MYKONOS_readDeframerStatus(…) Return Values

Return Value Description
MYKONOS_ERR_OK Function completed successfully
MYKONOS_ERR_READ_DEFRAMERSTATUS_NULL_PARAMETER Function parameter deframerStatus has a null pointer

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AD9371/AD9375 System Development User Guide UG-992
MYKONOS_jesd204bIlasCheck(…) DEPENDENCIES
mykonosErr_t The dependencies for the MYKONOS_jesd204bIlasCheck(…)
MYKONOS_jesd204bIlasCheck(mykonosDevice_t function are as follows:
*device, uint16_t *mismatch);
• device → spiSettings
This function allows the baseband processor (BBP) to verify
that the initial lane assignment sequence (ILAS) configuration
sent by the BBP to the deframer matches the configuration
programmed during MYKONOS_initialize(). The mismatch
parameter is a bit field that alerts the BBP of exactly which field
has a mismatch.

Table 55. MYKONOS_jesd204bIlasCheck(…) Parameters

Parameter Description
device Pointer to the device settings structure
mismatch Bit encoded word to indicate mismatch as described in Table 56

Table 56. mismatch Parameter Descriptions

mismatch Bit Description
15 Mismatch detected bit: Bits[0:14] are OR’ed together to set this bit.
14 JESD204B FCHK0: configuration checksum OK bit, where 0 = fail and 1 = pass.
13 JESD204B HD: high density bit, where 0 = samples are contained with single lane and 1 = samples are divided over more
than one lane.
12 JESD204B CF: 0 = control bits appended to each sample, 1 = control bits appended to end of frame.
11 JESD204B S: number of samples per converter per frame.
10 JESD204B NP: JESD204B word size based on the highest data converter resolution.
9 JESD204B CS: number of control bits transferred per sample per frame.
8 JESD204B N: data converter sample resolution.
7 JESD204B M: number of data converters.
6 JESD204B K: frames per multiframe.
5 JESD204B F: octets per frame.
4 JESD204B SCR: scramble setting.
3 JESD204B L: lanes per data converter.
2 JESD204B LID0: lane ID.
1 JESD204B BID: bank ID.
0 JESD204B DID: device ID.

Table 57. MYKONOS_jesd204bIlasCheck(…) Return Values

Return Value Description
MYKONOS_ERR_OK Function completed successfully
MYKONOS_ERR_JESD204B_ILAS_MISMATCH_NULLPARAM Function parameter mismatch has a null pointer

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UG-992 AD9371/AD9375 System Development User Guide
MYKONOS_enableDeframerPrbsChecker(…) The lanes parameter is a bit mask (bit per lane), allowing the
mykonosErr_t checker to be enabled for a particular JESD204B deserializer
MYKONOS_enableDeframerPrbsChecker(mykonos lane. The polyOrder enumeration can be set to MYK_PRBS7,
Device_t *device, uint8_t lanes, MYK_PRBS15, or MYK_PRBS31. The prbsOrder applies to all
mykonosPrbsOrder_t polyOrder, uint8_t
enable); enable lanes. The enable parameter allows turning on and off
the PRBS checker function.
This function enables the pseudorandom bit sequence (PRBS)
checker in the deframer IP. When enabled, the JESD204B DEPENDENCIES
deframer is disabled and PRBS data is expected on the link The dependencies for the MYKONOS_
instead of framed JESD204B data. The checker is a self enableDeframerPrbsChecker(…) function are as follows:
synchronizing PRBS checker, as specified in the JESD204B
• device → spiSettings
specification. It is capable of checking PRBS7, PRBS15, and
PRBS31 sequences.

Table 58. MYKONOS_enableDeframerPrbsChecker(…) Parameters

Parameter Description
device Pointer to the device settings structure
lanes Selects the lane for pseudorandom bit sequence (PRBS) checking based on a 4-bit mask, where each bit selects a different
lane: 1 = Lane 0, 2 = Lane 1, 4 = Lane 2, 8 = Lane 3
polyOrder Selects the PRBS type based on enumerator values: MYK_PRBS7, MYK_PRBS15, MYK_PRBS31
enable 1 enables checking, 0 disables checking

Table 59. MYKONOS_enableDeframerPrbsChecker(…) Return Values

Return Value Description
MYKONOS_ERR_OK Function completed successfully
MYKONOS_ERR_DEFRAMER_INV_PRBS_POLYORDER_PARAM Invalid polyOrder parameter, use proper enumeration
MYKONOS_ERR_DEFRAMER_INV_PRBS_ENABLE_PARAM Invalid enable (valid 0 to 1) or lanes (valid 0 to 15) parameter

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AD9371/AD9375 System Development User Guide UG-992
MYKONOS_clearDeframerPrbsCounters(…) DEPENDENCIES
mykonosErr_t
The dependencies for the MYKONOS_
MYKONOS_clearDeframerPrbsCounters(mykonos
Device_t *device); clearDeframerPrbsCounters(…) function are as follows:
This function allows the baseband processor to clear the deframer • device → spiSettings
pseudorandom bit sequence (PRBS) counters. It resets the PRBS
error counters for all lanes. It is recommended to clear the error
counters after enabling the deframer PRBS checker.

Table 60. MYKONOS_clearDeframerPrbsCounters(…) Parameters

Parameter Description
device Pointer to the device settings structure

Table 61. MYKONOS_clearDeframerPrbsCounters(…) Return Values

Return Value Description
MYKONOS_ERR_OK Function completed successfully

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UG-992 AD9371/AD9375 System Development User Guide
MYKONOS_readDeframerPrbsCounters(…) function four times. Note that the counterSelect parameter selects
mykonosErr_t the deframer input, not the physical lane at the outside of the
MYKONOS_readDeframerPrbsCounters(mykonosD chip. The counterSelect value required to read a particular lane
evice_t *device, uint8_t counterSelect, depends on the lane crossbar of the deframer.
uint32_t *prbsErrorCount);
The 24-bit PRBS error count is returned in the prbsErrorCount
After enabling the deframer pseudorandom bit sequence (PRBS) parameter.
checker and clearing the PRBS error counters, use this function
to read back the PRBS error counters. The counterSelect parameter DEPENDENCIES
allows the baseband processor (BBP) to select which lane error The dependencies for the MYKONOS_
counter to read. Only one lane error counter can be read at a readDeframerPrbsCounters(…) function are as follows:
time. To read error counters for all four lanes, the BBP calls this • device → spiSettings

Table 62. MYKONOS_readDeframerPrbsCounters(…) Parameters

Parameter Description
device Pointer to the device settings structure
counterSelect Selects the pseudorandom bit sequence (PRBS) error counter to be read based on values 0 to 3
prbsErrorCount Number of errors detected in the PRBS pattern

Table 63. MYKONOS_readDeframerPrbsCounters(…) Return Values

Return Value Description
MYKONOS_ERR_OK Function completed successfully
MYKONOS_ERR_READ_DEFRAMERPRBS_NULL_PARAM Function parameter prbsErrorCount has a null pointer
MYKONOS_ERR_DEFRAMER_INV_PRBS_CNTR_SEL_PARAM Invalid counterSelect parameter (valid from 0 to 3)

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AD9371/AD9375 System Development User Guide UG-992
LINK ESTABLISHMENT mykError =
MYKONOS_enableMultichipSync(pthe
After applying power to the device, the serializers, framers, AD9371Device, 0, &mcsStatus);
deserializer, deframer, and the rest of the JESD204B circuits are if (mykError != MYKONOS_ERR_OK)
powered down. Several steps are required to successfully power {
up the JESD204B link. //function threw error code
}
Suggested JESD204B API Initialization Sequence
5. Complete the normal sequence to load the ARM processor
The steps required to initialize the device JESD204B links (both and to run initialization calibrations. The JESD204B link
ADCs and DACs datapaths) are as follows: initialization is usually performed at the very end of
1. Initialize the mykonosDevice_t application programming initialization. The ARM loading and calibrations have no
interface (API) data structure and substructures with the impact on the JESD204B link.
desired settings. The transceiver evaluation software (TES) 6. If the baseband processor (BBP) requires the DAC transmit
can output a .c/.h file with the data structures initialized to datapath, instruct the BBP to run the required initialization
the values from the configuration tab. for the baseband processor. Enable the JESD204B serializer
2. Call the MYKONOS_initialize(…) API command to in the BBP to the state in which it outputs code group
configure the device. This sets up the device to use the synchronization (CGS) K characters.
chosen Rx/Tx/ORx/sniffer profiles, program the clock PLL 7. Perform a reset to the deframer to clear any disparity bit
and digital clocks, set up the serializer, framer, deserializer, errors previously detected. Also, if the SERDES PLL inside
deframer, and so on, for the Rx/Tx/ORx/sniffer profiles the FPGA resets, it can cause the lane FIFOs to overflow/
that are valid. underflow, requiring a deframer reset.
3. Perform multichip synchronization. Send at least two initial MYKONOS_resetDeframer(pthe
SYSREF rising edges for multichip sync between multiple AD9371Device);
devices. For proper synchronization, the same SYSREF
8. Enable the JESD204B IP blocks to accept a SYSREF signal
pulses must be seen at each device during the same device
for internal local multiframe counter (LMFC) timing reset.
clock cycle. If only a single device is used, this step is still
Only the calls to the desired framers/deframers are necessary.
required to ensure JESD204B deterministic latency. For
Send a third SYSREF pulse to the device and BBP to reset
proper operation, it is recommended to disable the
the JESD204B LMFC timing locally in each device to
SYSREF, enable multichip synchronization, then reenable
guarantee deterministic latency. The device does not reset
SYSREF. SYSREF may either be a single pulse or free
its LMFC timing on any future SYSREF pulses unless the
running. If a periodic pulse is used, the phase must not
newSysrefOnRelink option is enabled in the framer/deframer
change between rising edges. Single-pulse mode can be
data structures.
implemented by gating a free running SYSREF after the
falling edge occurs, allowing a single pulse to output. MYKONOS_enableSysrefToRxFramer(pthe
AD9371Device, 1);
//Disable SYSREF from clock device MYKONOS_enableSysrefToObsRxFramer(pt
if free running he AD9371Device, 1);
MYKONOS_enableSysrefToDeframer(pthe
uint8_t mcsStatus = 0; AD9371Device, 1);
mykonosErr_t mykError =
MYKONOS_ERR_OK; //default to no error //Request a SYSREF pulse or several
from clock device
//Enable MCS in the AD9371. Ad9528.requestSysref(true);
mykError =
MYKONOS_enableMultichipSync(pthe
Framers
AD9371Device, 1, &mcsStatus); When the baseband processor (BBP) asserts the SYNCIN_B signal
if (mykError != MYKONOS_ERR_OK) (low), the framer transmits the code group synchronization (CGS)
{ K characters. The framer continues to transmit the CGS until the
//function threw error code
} SYSREF is received. After the framer receives the SYSREF pulse, the
//Request at least 2 SYSREF pulses framer resets the local multiframe counter (LMFC) counter and
from clock device waits for the deassertion of SYNCIN_B. After the BBP deasserts
Ad9528.requestSysref(true); the SYNCIN_B signal (high), the framer transmits the initial lane
Ad9528.requestSysref(true); assignment sequence (ILAS) at the beginning of the subsequent
//Disable MCS in the AD9371 and LMFC boundary. After the ILAS sequence is complete, the framer
readback MCS status begins transmitting the ADC data. Details on the initial lane
synchronization can be found in Section 5.3.3.5 of the

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UG-992 AD9371/AD9375 System Development User Guide
JEDEC Standard No. 204B. Refer to Figure 35 in the JEDEC • To set LVDS or CMOS mode for the Tx signals
Standard No 204B for details on the ILAS. SYNCOUTB0±, refer to the device data structure member
Deframer located at: device > tx > deframer > txSyncbMode.
Out of reset, the deframer asserts the SYNCOUT_B signal For the parameters previously mentioned, if the txSyncbMode
(low). With the SYNCOUT_B signal asserted, the baseband or rxSyncbMode parameter is set to 0, this corresponds to
processor (BBP) transmits the code group synchronization LVDS operation. If the parameter is set greater than 0, CMOS
(CGS) K characters. When the deframer receives the SYSREF operation is enabled.
pulse, the deframer resets the local multiframe counter (LMFC) COMPATIBILITY WITH XILINX JESD204B FPGA IP
counter. After the deframer synchronizes to the received data
Analog Devices uses the Xilinx JESD204B IP bundled with the
stream and properly decodes the K characters, it deasserts the
XC7Z045 FFG900 for demonstration with the provided Analog
SYNCOUT_B signal (high) on the subsequent LMFC boundary.
Devices evaluation platform.
The deassertion of the SYNCOUT_B signal prompts the BBP to
begin the ILAS. If the link is established over multiple lanes, the Some versions of the Xilinx JESD204B IP include a watchdog
ILAS may arrive at the device skewed in time across the lanes. timer that resets the high speed serial PLLs if SYNCOUT_B is
The lane FIFOs buffer the data in each lane until the next held low for more than 10 ms. This feature causes the lane
LMFC boundary, at which time it releases all lanes aligned in FIFOs in the deserializers to overflow/underflow because the
time. After the lanes are aligned and the configuration data in lane FIFOs derive the write clock from the recovered clock data
the ILAS is verified, the user data following the ILAS is sent to recovery (CDR) clock. When the field programmable gate array
the DACs. For more details, refer to Section 6.3 of the JEDEC (FPGA) resets its SERDES PLLs, the CDR clock in the device
Standard No. 204B. Refer to Figure 36 of the JEDEC Standard unlocks and causes the lane FIFO to underflow/overflow.
No.204B for details on establishing a link with deterministic Typically, this is not a problem because SYNCOUT_B is not
latency. held low for longer than 10 ms in normal use. In debug mode,
however, a user may choose to hold SYNCOUT_B low to test
Ensure that the scrambling setting matches in the BBP and the
the link. It is recommended to disable the 10 ms watchdog reset
device. It is possible for the JESD204B link to successfully link
in the Xilinx IP wrapper to prevent unnecessary issues caused
and the data to appear corrupt because only the data is
by randomly resetting PLLs in the system.
scrambled, not the ILAS. This can result in a transmit spectrum
that looks like noise. MULTICHIP SYNCHRONIZATION
HARDWARE CONSIDERATIONS FOR SYNC SIGNALS For multiple input, multiple output (MIMO) systems requiring
more than two input or two output channels, multiple devices
The device features pins digital input/outputs pins designated
and a common reference oscillator are required. The device
SYNCOUTB0+, SYNCOUTB0−, SYNCINB0+, SYNCINB0−,
provides the capability to accept an external reference clock
SYNCINB1+, and SYNCINB1−. In general, each SYNC pin
and synchronize operation with other devices. Each device
allows the JESD204B receiver to communicate with the
includes its own baseband PLL that generates sampling and
JESD204B transmitter. The SYNC pins can be configured as
data clocks from the reference clock input, so an additional
LVDS differential pairs or as a single ended CMOS pin. In
control mechanism is required to synchronize multiple devices.
LVDS mode for the SYNCINB0± and SYNCINB1±, a 100 Ω
A set of logical pulses on the SYSREF_IN input is required to
on-chip termination is enabled.
align the data clock on each device with a common reference.
When configured in CMOS mode, only the positive polarity pin This user guide describes the hardware connections necessary
is used. If CMOS mode is used for the SYNCINB0 signal or the to synchronize two devices. This user guide also provides detailed
SYNCINB1 signal, the negative polarity pin should be information about timing requirement for SYSREF pulse in
connected to ground through a pull down resistor. If CMOS reference to DEV_CLK signal clock. Figure 27 shows the hardware
mode is used for the SYNCOUTB0 signal, the negative polarity connections required to perform this synchronization.
pin should not be connected.
When working with multiple transceivers, or even a single
API Configuration transceiver that requires deterministic latency between the Tx
To configure the device SYNC pins for either CMOS or LVDS and observation and or main Rx JESD204B datapath, multichip
mode, there are three device data structure members to consider: sync is necessary. The series of three (or more) SYSREF pulses
must be synchronous to the device clock. Typically, this is an
• To set LVDS or CMOS mode for ObsRx signal(s)
output from the same clock generation IC that generates the
SYNCINB1±, refer to the device data structure member
device clock, allowing the setup and hold times to be guaranteed.
located at: device > obsRx > framer > rxSyncbMode.
The device evaluation system hardware uses the AD9528 for
• To set LVDS or CMOS mode for Rx signals SYNCINB0±,
clock and SYSREF generation and distribution.
refer to the device data structure member located at: device
> rx > framer > rxSyncbMode.

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AD9371/AD9375 System Development User Guide UG-992
The frequency of the SYSREF pulse train must be a submultiple Figure 28 shows where each SYSREF pulse is applied inside the
of the JESD204B local multiframe counter (LMFC) rate. The device. The pulses reset the chip in the following order:
first two pulses synchronize the digital circuits and the third 1. Reset the device clock input scaler.
and following pulses are passed along to the JESD204B 2. Reset the digital core clock generation dividers. These
interface. It is possible for more than three pulses to be required dividers generate the ADC/DAC and digital clocks.
if their frequency occurs faster than the JESD204B interface 3. Reset provides JESD204B lane alignment and deterministic
PLL can lock and synchronize. For detailed recommendations lane synchronization.
regarding establishing deterministic latency on the JESD204B
interface, refer to the Link Establishment section. Note that the multichip synchronization (MCS) function does not
include RF synchronization. The ability to synchronize RF local
oscillators (LOs) is not available in devices. The only alignment
among multiple chips that is possible using this feature is digital
timing alignment.

AD9371 AD9371
Rx/Tx Rx/Tx
DEVICE 1 DEVICE 2
DEV_CLK
SYSREF

DEV_CLK
SYSREF

DEV_CLK
SYSREF
CLOCK AND SYSREF
GENERATION BBP
AD9528
SPI

14652-025
CLK CONTOL

Figure 27. Multichip Connectivity—DEV_CLK Clock and SYSREF Signal Connections from the Clock Generation

SERDES PHY
CLOCK SYNTHESIZER PLL RX_CDR_CLK
K = 0.5, 1, 2, 4 TX_SERDES_CLK MEET SKEW BUDGET
VCO 6GHz (RESET, CLK SKEW)
DEV_CLK_IN TO 12.3GHz
PFD
/K CP LPF HS_DIVIDERS

HS_DIGCLK

PFD_FB_CLK
DIVIDER DIGITAL CLOCK
CLK_PLL_SYNC_CLK (6 TO 255) GENERATOR

SDM_CLK ADC CLOCK

GENERATOR
Σ-∆ ×1, /2
MODULATOR
DAC CLOCK
(NOTE: Σ-∆ GENERATOR
MODULATOR TYPICALLY DISABLED) /2, /2.5 /4
CLK_PLL_SYNC_CLK

TO ADCs
DIVK_RESET

SDM_RESET

ADC_CLK
HS_DIGCLK

ADC/DAC
DEVICE CLOCK

REFCLK

RETIMING DAC_CLK
TO DACs CIRCUITS

1 DIGITAL CORE
2

DIGITAL DIVIDER RESET PULSE

DIGITAL DIVIDER RESET
MULTICHIP SYNCHRONIZATION AND JESD204B
PULSE GENERATION JESD204B LMFC RESET PULSE
SYSREF SYSREF LOGIC
SYSREF PULSE
14652-026

Figure 28. Clocking Architecture Indicating SYSREF Reset Sequence

Rev. B | Page 57 of 360
UG-992 AD9371/AD9375 System Development User Guide
MULTICHIP API FUNCTION DESCRIPTION The typical sequence for multichip synchronization is as follows:
The application programming interface (API) package provided 1. Initialize all devices in system using MYKONOS_initialize().
with the device contains the MYKONOS_enableMultichipSync 2. Run MYKONOS_enableMultichipSync with enableMcs = 1
function. This function sets up the device to route SYSREF 3. Send at least three SYSREF pulses.
pulses through the chip to reset the clock synthesizer, all digital 4. Run MYKONOS_enableMultichipSync with enableMcs = 0.
clocks, and the JESD204B interface. Run this function after a 5. Load ARM, run ARM cals and continue to active transmit/
single transceiver is initialized (or all transceivers, if more than receive/.
one is used).
An example sequence of multichip sync sequence copied from
mykonosErr_t an IronPython script generated by the transceiver evaluation
MYKONOS_enableMultichipSync(mykonosDevice
software (TES) is as follows:
_t *device, uint8_t enableMcs, uint8_t
*mcsStatus) :
The function parameters are as follows: Link.the AD9371.resetDevice()
enableMcs Link.the AD9371.initialize()

When set to = 1, enable the multichip synchronization (MCS) pllStatus = Link.the

AD9371.checkPllsLockStatus()
state machine. When set to = 0, allow reading back MCS status.
mcsStatus = 0
mcsStatus
Link.the AD9371.enableMultichipSync(1,
If pointer is not null, then this parameter returns the MCS mcsStatus)
status word. Each bit of this status word represents the following Link.Ad9528.requestSysref(True)
functions:
Link.Ad9528.requestSysref(True)
• Bit 0, MCS JESD204B SYSREF status (1 = sync occurred). Link.Ad9528.requestSysref(True)
This bit indicates that the clock synthesizer input divider
Link.the AD9371.enableMultichipSync(0,
scaler has been reset. mcsStatus)
• Bit 1, MCS digital clocks sync status (1 = sync occurred).
:
This bit indicates that the clock synthesizer sigma delta
modulator has been synchronized. This feature is disabled. The key to successful synchronization is to disable external
The PLL operates in integer mode only for JESD204B SYSREF pulses before configuring the clock synth in all devices
support. in the system (while the SYSREF is disabled, it must be held in a
• Bit 2, MCS clock PLL Σ-Δ modulator sync status (1 = sync low state). With SYSREF still disabled, use MYKONOS_
occurred). This bit indicates that the digital dividers after enableMultichipSync as described previously. After three pulses
the clock synth are synchronized. are applied, all the devices sync at the same time with the SYSREF
pulses. Exact details regarding SYSREF pulse timing relative to
• Bit 3, MCS device clock divider sync status (1 = sync
DEV_CLK are described in this user guide.
occurred). This bit indicates that MCS for the JESD204B
framer/deframer required for deterministic latency has The device only synchronizes on the first three applied SYSREF
been performed. pulses. More than three pulses may be supplied, but they do not
have any further effect on synchronization (additional pulses are
After the SYSREF pulses are sent, call the MYKONOS_ passed to the JESD204B interface). To resync, it is necessary to
enableMultichipSync() function again with the enableMcs
reset the device with a hard reset (applied to the RESET pin).
parameter set to 0. When enableMcs = 0, the MCS status is
returned in the multichip sync status parameters.

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AD9371/AD9375 System Development User Guide UG-992

SYSTEM INITIALIZATION
This section provides information about the initialization DATA STRUCTURE MEMBER INITIALIZATION
process for the transceiver device using the application The application programming interface (API) functions use
programming interface (API) developed by Analog Devices. sets of data structures to convey configuration and control
The following sections describe the developer preparation data. These structures must be instantiated and their members
requirements, initialization sequence, and example code for loaded (initialized) with valid settings in the user code before
using the API software on any platform. This section does not the initialization sequence can take place. The transceiver
explain the API library functions. Detailed information regarding evaluation software (TES) can generate valid data structure
the API functions can be found in the device API doxygen member values based on user settings. The TES generates the
document, located in the /src/doc file in the software package myk_init.c and myk_init.h files for direct porting to the user
directory structure code or can be cut and pasted as required. The myk_init.* files
MODIFICATION OF COMMON.C FOR USER CODE contain the preloaded data structures and accompanying header
INTEGRATION file, respectively. The data structures that must be instantiated
The user is required to integrate their platform level drivers into and loaded are contained in Table 64.
common.c before using any application programming interface Note that hardware designs with multiple devices require each
(API) function calls. Details regarding this are contained in the device to have its own unique configuration data initialized for
Software Integration section. The API used in the initialization all data structures; headless.c illustrates the structure initialization
process does not execute properly on the user hardware sequence at the beginning of the file. Explanations for each data
platform if this step is ignored. structure are contained in the mykonos.chm document.

Table 64. Data Structures Requiring Initialization

Data Structure Location Description
spiSettings_t /src/api/common.h This contains the SPI settings for all system device types.
mykonosFir_t /src/api/mykonos/t_mykonos.h This contains the finite impulse response (FIR) filter gain,
number of coefficients, and a pointer to a filter coefficient array.
mykonosJesd204bFramerConfig_t /src/api/mykonos/t_mykonos.h This contains the JESD204B framer configuration parameters.
mykonosJesd204bDeframerConfig_t /src/api/mykonos/t_mykonos.h This contains the JESD204B deframer configuration
parameters.
mykonosRxProfile_t /src/api/mykonos/t_mykonos.h This contains the Rx profile information.
mykonosTxProfile_t /src/api/mykonos/t_mykonos.h This contains the Tx profile information
mykonosSnifferGainControl_t /src/api/mykonos/t_mykonos.h This contains the sniffer Rx manual gain control information.
mykonosORxGainControl_t /src/api/mykonos/t_mykonos.h This contains the observation Rx manual gain control
information.
mykonosRxGainControl_t /src/api/mykonos/t_mykonos.h This contains the Rx manual gain control information.
mykonosAgcCfg_t /src/api/mykonos/t_mykonos.h This contains the automatic gain control (AGC) information.
mykonosTxSettings_t /src/api/mykonos/t_mykonos.h This contains the Tx setting information.
mykonosRxSettings_t /src/api/mykonos/t_mykonos.h This contains the Rx setting information.
mykonosObsRxSettings_t /src/api/mykonos/t_mykonos.h This contains the observation Rx setting information.
mykonosGpio3v3_t /src/api/mykonos/t_mykonos.h This contains the 3.3 V dc GPIO setting information.
mykonosGpio1v8_t /src/api/mykonos/t_mykonos.h This contains the 1.8 V dc GPIO setting information.
mykonosAuxIo_t /src/api/mykonos/t_mykonos.h This contains the auxiliary ADC, DAC, and pointers to the
GPIO setting information.
mykonosDigClocks_t /src/api/mykonos/t_mykonos.h This contains the digital clock parameters.
mykonosDevice_t /src/api/mykonos/t_mykonos.h This data structure is inclusive of all previous data types,
which are instantiated as pointers. The profilesValid bit field
identifies which profile is valid. This data type is used to
instantiate one device for configuration and control after
member structure initialization.
mykonosArmGpioConfig_t /src/api/mykonos/t_mykonos.h Data structure to hold ARM GPIO pin assignments for each
ARM input/output pin.
mykonosPeakDetAgcCfg_t /src/api/mykonos/t_mykonos.h Data structure to hold peak detector settings for the AGC.
mykonosPowerMeasAgcCfg_t /src/api/mykonos/t_mykonos.h Data structure to hold power measurement settings for the
AGC.

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UG-992 AD9371/AD9375 System Development User Guide
Data Structure Location Description
mykonosInitCalStatus_t /src/api/mykonos/t_mykonos.h Data structure used to read back the initialization
calibration status.
mykonosTxLolStatus_t /src/api/mykonos/t_mykonos.h Data structure to hold Tx local oscillator leakage (LOL) status.
mykonosTxQecStatus_t /src/api/mykonos/t_mykonos.h Data structure to hold Tx quadrature error correction (QEC)
status.
mykonosRxQecStatus_t /src/api/mykonos/t_mykonos.h Data structure to hold Rx QEC status.
mykonosOrxQecStatus_t /src/api/mykonos/t_mykonos.h Data structure to hold Orx QEC status.
mykonosGainComp_t /src/api/mykonos/t_mykonos_gpio.h Data structure to hold gain compensation settings for the
main receive channels.
mykonosObsRxGainComp_t /src/api/mykonos/t_mykonos_gpio.h Data structure to hold gain compensation settings for the
observation channel.
mykonosFloatPntFrmt_t /src/api/mykonos/t_mykonos_gpio.h Data structure to hold floating point formatter settings for
the floating point number generation.
mykonosTempSensorConfig_t /src/api/mykonos/t_mykonos_gpio.h Data structure used to configure the on die temperature
sensor.
mykonosTempSensorStatus_t /src/api/mykonos/t_mykonos_gpio.h Data structure used to store temperature sensor related values.

Rev. B | Page 60 of 360

AD9371/AD9375 System Development User Guide UG-992
INITIALIZATION SEQUENCE 13. Run the initialization calibrations (call MYKONOS_
The initialization sequence is comprised of application runInitCals and MYKONOS_waitInitCals with user
programming interface (API) calls mixed with user defined defined code).
function calls specific to the hardware platform. The API 14. Enable the SYSREF for Rx and ORx deframer (call
functions perform all of the necessary tasks for transceiver MYKONOS_enableSysrefTo… functions).
configuration, calibration, and control. The user is required to 15. Send the SYSREF signal to bring up the JESD204B interface.
insert their code into the initialization sequence specific to the 16. Check deframer and framer status (call MYKONOS_
hardware platform requirements. These platform requirements readDeframerStatus and
include, but are not limited to, user clock device, user field MYKONOS_readRxFramerStatus).
programmable gate array (FPGA)\application specific IC 17. User verifies sync and link status for hardware platform.
(ASIC)\baseband processor (BBP) JESD204B interface, 18. Enable tracking calibrations (call MYKONOS_
datapath control, and various system checks governed by the enableTrackingCals).
application. The source code contained in headless.c provides a 19. Turn the radio on for all transmitters and receivers that
basic initialization sequence with code comments to help guide were set up previously (call MYKONOS_radioOn).
the user with the insertion of their application specific code. EXAMPLE CODE
Sequence Order headless.c
The initialization sequence order follows these steps: The headless.c file contains the initialization sequence example
1. Instantiate all data structures and load their members code. The sequence of the code written in this file matches the
required by the user application (myk_init.c contents). aforementioned initialization order. The headless.c file works
2. Initialize and setup of all clocks (platform clock source and with myk_init.c and myk_init.h. These source code files are
JESD204B SYSREF signals are set up). generated by the TES based on user settings, as previously
3. Initialize hardware platform (hardware dependent devices mentioned. The comment header at the top of headless.c
such as FPGA/ASIC/BBP interfaces are initialized). describes the default TES user settings used to generate
4. Reset the device (call MYKONOS_resetDevice for reset of myk_init.c and myk_init.h. The data structures and their
transceiver device in preparation for initialization). generated values in these files are subject to change based on
5. Initialize the device (call MYKONOS_initialize function TES revision. The headless.c file was written with the intent to be
for configuration of the device). used as a template by the user when developing their application.
6. Check CLKPLL status for lock (call MYKONOS_ Specially formatted code comments are placed throughout file,
checkPllLockStatus and perform check with user defined such as Action (which are user needed actions) and Info to help
code). the user properly identify where they can insert their
7. Multichip synchronization (all the JESD204B lanes are application specific code.
synchronized together for deterministic latency headless.h
requirements). The accompanying header file for headless.c is headless.h. It
8. Initialize the ARM processor (call MYKONOS_initArm). contains no code and is provided as a convenience to the user.
9. Load the ARM binary file (call MYKONOS_
loadArmFromBinary with user defined binary array Disclaimer
pointer). Users may not modify any code located in the /src/api folder
10. Set the RF PLL frequencies (call MYKONOS_ other than changing the common.c code bodies for hardware
setRfPllFrequency for each channel used by the application). driver insertion and gain table changes in mykonos_user.c.
11. Perform RF PLL lock check (call MYKONOS_ Analog Devices maintains the code in /src/api/mykonos and
checkPllLockStatus and perform check with user defined /src/api/ad9528 as intellectual property and all changes are at
code). their sole discretion. Analog Devices provides new releases to
12. Set GPIO functions with the desired configuration (check fix any code bugs in these folders. Verification of all code bugs
headless.c for API calls to be made). is independent of any user code.

Rev. B | Page 61 of 360

UG-992 AD9371/AD9375 System Development User Guide
SOURCE CODE EXAMPLES
myk_init.h
/**
* \file myk_init.h
*
* \brief Contains structure definitions for myk_init.c
*
* The top level structure mykonosDevice_t mykDevice uses keyword
* extern to allow the application layer main() to have visibility
* to these settings.
*/

#ifndef MYK_INIT_H_
#define MYK_INIT_H_

#ifdef __cplusplus
extern "C" {
#endif

extern mykonosDevice_t mykDevice;

#ifdef __cplusplus
}
#endif

#endif

myk_init.c
/**
* \brief Contains init setting structure declarations for the _instance API
*
* The top level structure mykonosDevice_t mykDevice uses keyword
* extern to allow the application layer main() to have visibility
* to these settings.
*
* All data structures required for operation have been initialized with values which
reflect these settings:
*
* Device Clock:
* 122.88MHz
*
* Profiles:
* Rx 20MHz, IQrate 30.72MSPS, Dec5
* Tx 20/100MHz, IQrate 122.88MSPS, Dec5
* ORX 100MHz, IQrate 122.88MSPS, Dec5
* SRx 20MHz, IQrate 30.72MSPS, Dec5
*
*/

#include <stddef.h>
#include "t_mykonos.h"
#include "t_mykonos_gpio.h"
#include "myk_init.h "

static int16_t txFirCoefs[] = {-94,-26,282,177,-438,-368,756,732,-1170,-1337,1758,2479,-

2648,-5088,4064,16760,16759,4110,-4881,-2247,2888,1917,-1440,-1296,745,828,-358,-
474,164,298,-16,-94};

static mykonosFir_t txFir =

{
6, /* Filter gain in dB*/
Rev. B | Page 62 of 360
AD9371/AD9375 System Development User Guide UG-992
32, /* Number of coefficients in the FIR filter*/
&txFirCoefs[0] /* A pointer to an array of filter coefficients*/
};

static int16_t rxFirCoefs[] = {-13,-53,-50,-20,88,197,231,80,-239,-576,-654,-

268,538,1359,1585,749,-1060,-3028,-3847,-2340,1835,7799,13660,17289,17289,13660,7799,1835,-
2340,-3847,-3028,-1060,749,1585,1359,538,-268,-654,-576,-239,80,231,197,88,-20,-50,-53,-
13};

static mykonosFir_t rxFir =

{
-6, /* Filter gain in dB*/
48, /* Number of coefficients in the FIR filter*/
&rxFirCoefs[0] /* A pointer to an array of filter coefficients*/
};

static int16_t obsrxFirCoefs[] = {-14,-19,44,41,-89,-95,175,178,-303,-317,499,527,-779,-

843,1184,1317,-1781,-2059,2760,3350,-4962,-7433,9822,32154,32154,9822,-7433,-
4962,3350,2760,-2059,-1781,1317,1184,-843,-779,527,499,-317,-303,178,175,-95,-89,41,44,-
19,-14};
static mykonosFir_t obsrxFir =
{
-6, /* Filter gain in dB*/
48, /* Number of coefficients in the FIR filter*/
&obsrxFirCoefs[0]/* A pointer to an array of filter coefficients*/
};

static int16_t snifferFirCoefs[] = {-1,-5,-14,-23,-16,24,92,137,80,-120,-378,-471,-

174,507,1174,1183,98,-1771,-3216,-2641,942,7027,13533,17738,17738,13533,7027,942,-2641,-
3216,-1771,98,1183,1174,507,-174,-471,-378,-120,80,137,92,24,-16,-23,-14,-5,-1};
static mykonosFir_t snifferRxFir=
{
-6, /* Filter gain in dB*/
48, /* Number of coefficients in the FIR filter*/
&snifferFirCoefs[0]/* A pointer to an array of filter coefficients*/
};

static mykonosJesd204bFramerConfig_t rxFramer =

{
0, /* JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15)*/
0, /* JESD204B Configuration Device ID - link identification number. (Valid
0..255)*/
0, /* JESD204B Configuration starting Lane ID. If more than one lane used,
each lane will increment from the Lane0 ID. (Valid 0..31)*/
4, /* number of ADCs (0, 2, or 4) - 2 ADCs per receive chain*/
32, /* number of frames in a multiframe (default=32), F*K must be a multiple of
4. (F=2*M/numberOfLanes)*/
1, /* scrambling off if framerScramble= 0, if framerScramble>0 scramble is
enabled.*/
1, /* 0=use internal SYSREF, 1= use external SYSREF*/
0x00, /* serializerLanesEnabled - bit per lane, [0] = Lane0 enabled, [1] = Lane1
enabled*/
0xE4, /* serializerLaneCrossbar*/
22, /* serializerAmplitude - default 22 (valid (0-31)*/
4, /* preEmphasis - < default 4 (valid 0 - 7)*/
0, /* invertLanePolarity - default 0 ([0] will invert lane [0], bit1 will
invert lane1)*/
0, /* lmfcOffset - LMFC_Offset offset value for deterministic latency
setting*/
0, /* Flag for determining if SYSREF on relink should be set. Where, if > 0 =
set, 0 = not set*/

Rev. B | Page 63 of 360

UG-992 AD9371/AD9375 System Development User Guide
0, /* Flag for determining if auto channel select for the xbar should be set.
Where, if > 0 = set, '0' = not set*/
0, /* Selects SYNCb input source. Where, 0 = use RXSYNCB for this framer, 1 =
use OBSRX_SYNCB for this framer*/
0, /* Flag for determining if CMOS mode for RX Sync signal is used. Where, if
> 0 = CMOS, '0' = LVDS*/
0 /* Selects framer bit repeat or oversampling mode for lane rate matching.
Where, 0 = bitRepeat mode (changes effective lanerate), 1 = overSample (maintains same lane
rate between ObsRx framer and Rx framer and oversamples the ADC samples)*/
};

static mykonosJesd204bFramerConfig_t obsRxFramer =

{
0, /* JESD204B Configuration Bank ID -extension to Device ID (Valid 0..15)*/
0, /* JESD204B Configuration Device ID - link identification number. (Valid
0..255)*/
0, /* JESD204B Configuration starting Lane ID. If more than one lane used, each
lane will increment from the Lane0 ID. (Valid 0..31)*/
2, /* number of ADCs (0, 2, or 4) - 2 ADCs per receive chain*/
32, /* number of frames in a multiframe (default=32), F*K must be a multiple of 4.
(F=2*M/numberOfLanes)*/
1, /* scrambling off if framerScramble= 0, if framerScramble>0 scramble is
enabled.*/
1, /* 0=use internal SYSREF, 1= use external SYSREF*/
0x00, /* serializerLanesEnabled - bit per lane, [0] = Lane0 enabled, [1] = Lane1
enabled*/
0xE4, /* Lane crossbar to map framer lane outputs to physical lanes*/
22, /* serializerAmplitude - default 22 (valid (0-31)*/
4, /* preEmphasis - < default 4 (valid 0 - 7)*/
0, /* invertLanePolarity - default 0 ([0] will invert lane [0], bit1 will invert
lane1)*/
0, /* lmfcOffset - LMFC_Offset offset value for deterministic latency setting*/
0, /* Flag for determining if SYSREF on relink should be set. Where, if > 0 = set,
0 = not set*/
0, /* Flag for determining if auto channel select for the xbar should be set.
Where, if > 0 = set, '0' = not set*/
1, /* Selects SYNCb input source. Where, 0 = use RXSYNCB for this framer, 1 = use
OBSRX_SYNCB for this framer*/
0, /* Flag for determining if CMOS mode for RX Sync signal is used. Where, if > 0
= CMOS, '0' = LVDS*/
1 /* Selects framer bit repeat or oversampling mode for lane rate matching.
Where, 0 = bitRepeat mode (changes effective lanerate), 1 = overSample (maintains same lane
rate between ObsRx framer and Rx framer and oversamples the ADC samples)*/
};

static mykonosJesd204bDeframerConfig_t deframer =

{
0, /* bankId extension to Device ID (Valid 0..15)*/
0, /* deviceId link identification number. (Valid 0..255)*/
0, /* lane0Id Lane0 ID. (Valid 0..31)*/
4, /* M number of DACss (0, 2, or 4) - 2 DACs per transmit chain */
32, /* K #frames in a multiframe (default=32), F*K=multiple of 4.
(F=2*M/numberOfLanes)*/
1, /* scramble scrambling off if scramble= 0.*/
1, /* External SYSREF select. 0 = use internal SYSREF, 1 = external SYSREF*/
0x00, /* Deserializer lane select bit field. Where, [0] = Lane0 enabled, [1] = Lane1
enabled, etc */
0xE4, /* Lane crossbar to map physical lanes to deframer lane inputs [1:0] = Deframer
Input 0 Lane section, [3:2] = Deframer Input 1 lane select, etc */
1, /* Equalizer setting. Applied to all deserializer lanes. Range is 0..4*/
0, /* PN inversion per each lane. bit[0] = 1 Invert PN of Lane 0, bit[1] = Invert
PN of Lane 1, etc).*/
Rev. B | Page 64 of 360
AD9371/AD9375 System Development User Guide UG-992
0, /* LMFC_Offset offset value to adjust deterministic latency. Range is 0..31*/
0, /* Flag for determining if SYSREF on relink should be set. Where, if > 0 = set,
'0' = not set*/
0, /* Flag for determining if auto channel select for the xbar should be set.
Where, if > 0 = set, '0' = not set*/
0 /* Flag for determining if CMOS mode for TX Sync signal is used. Where, if > 0 =
CMOS, '0' = LVDS*/
};

static mykonosRxGainControl_t rxGainControl =

{
MGC, /* Current Rx gain control mode setting*/
255, /* Rx1 Gain Index, can be used in different ways for manual and AGC
gain control*/
255, /* Rx2 Gain Index, can be used in different ways for manual and AGC
gain control*/
255, /* Max gain index for the currently loaded Rx1 Gain table*/
195, /* Min gain index for the currently loaded Rx1 Gain table*/
255, /* Max gain index for the currently loaded Rx2 Gain table*/
195, /* Min gain index for the currently loaded Rx2 Gain table*/
0, /* Stores Rx1 RSSI value read back from the AD9371*/
0 /* Stores Rx2 RSSI value read back from the AD9371*/
};

static mykonosORxGainControl_t orxGainControl =

{
MGC, /* Current ORx gain control mode setting*/
255, /* ORx1 Gain Index, can be used in different ways for manual and AGC
gain control*/
255, /* ORx2 Gain Index, can be used in different ways for manual and AGC
gain control*/
255, /* Max gain index for the currently loaded ORx Gain table*/
237 /* Min gain index for the currently loaded ORx Gain table*/
};

static mykonosSnifferGainControl_t snifferGainControl =

{
MGC, /* Current Sniffer gain control mode setting*/
255, /* Current Sniffer gain index. Can be used differently for Manual Gain
control/AGC*/
255, /* Max gain index for the currently loaded Sniffer Gain table*/
203 /* Min gain index for the currently loaded Sniffer Gain table*/
};

static mykonosPeakDetAgcCfg_t rxPeakAgc =

{
0x1F, /* apdHighThresh: */
0x16, /* apdLowThresh */
0xB5, /* hb2HighThresh */
0x80, /* hb2LowThresh */
0x40, /* hb2VeryLowThresh */
0x06, /* apdHighThreshExceededCnt */
0x04, /* apdLowThreshExceededCnt */
0x06, /* hb2HighThreshExceededCnt */
0x04, /* hb2LowThreshExceededCnt */
0x04, /* hb2VeryLowThreshExceededCnt */
0x4, /* apdHighGainStepAttack */
0x2, /* apdLowGainStepRecovery */
0x4, /* hb2HighGainStepAttack */
0x2, /* hb2LowGainStepRecovery */
0x4, /* hb2VeryLowGainStepRecovery */
0x1, /* apdFastAttack */
Rev. B | Page 65 of 360
UG-992 AD9371/AD9375 System Development User Guide
0x1, /* hb2FastAttack */
0x1, /* hb2OverloadDetectEnable */
0x1, /* hb2OverloadDurationCnt */
0x1 /* hb2OverloadThreshCnt */
};

static mykonosPowerMeasAgcCfg_t rxPwrAgc =

{
0x01, /* pmdUpperHighThresh */
0x03, /* pmdUpperLowThresh */
0x0C, /* pmdLowerHighThresh */
0x04, /* pmdLowerLowThresh */
0x4, /* pmdUpperHighGainStepAttack */
0x2, /* pmdUpperLowGainStepAttack */
0x2, /* pmdLowerHighGainStepRecovery */
0x4, /* pmdLowerLowGainStepRecovery */
0x08, /* pmdMeasDuration */
0x02 /* pmdMeasConfig */
};

static mykonosAgcCfg_t rxAgcConfig =

{
255, /* AGC peak wait time */
195, /* agcRx1MinGainIndex */
255, /* agcRx2MaxGainIndex */
195, /* agcRx2MinGainIndex: */
255, /* agcObsRxMaxGainIndex */
203, /* agcObsRxMinGainIndex */
1, /* agcObsRxSelect */
1, /* agcPeakThresholdMode */
1, /* agcLowThsPreventGainIncrease */
30720, /* agcGainUpdateCounter */
3, /* agcSlowLoopSettlingDelay */
2, /* agcPeakWaitTime */
0, /* agcResetOnRxEnable */
0, /* agcEnableSyncPulseForGainCounter */
&rxPeakAgc,
&rxPwrAgc
};

static mykonosPeakDetAgcCfg_t obsRxPeakAgc =

{
0x1F, /* apdHighThresh: */
0x16, /* apdLowThresh */
0xB5, /* hb2HighThresh */
0x80, /* hb2LowThresh */
0x40, /* hb2VeryLowThresh */
0x06, /* apdHighThreshExceededCnt */
0x04, /* apdLowThreshExceededCnt */
0x06, /* hb2HighThreshExceededCnt */
0x04, /* hb2LowThreshExceededCnt */
0x04, /* hb2VeryLowThreshExceededCnt */
0x4, /* apdHighGainStepAttack */
0x2, /* apdLowGainStepRecovery */
0x4, /* hb2HighGainStepAttack */
0x2, /* hb2LowGainStepRecovery */
0x4, /* hb2VeryLowGainStepRecovery */
0x1, /* apdFastAttack */
0x1, /* hb2FastAttack */
0x1, /* hb2OverloadDetectEnable */
0x1, /* hb2OverloadDurationCnt */
0x1 /* hb2OverloadThreshCnt */
Rev. B | Page 66 of 360
AD9371/AD9375 System Development User Guide UG-992
};

static mykonosPowerMeasAgcCfg_t obsRxPwrAgc =

{
0x01, /* pmdUpperHighThresh */
0x03, /* pmdUpperLowThresh */
0x0C, /* pmdLowerHighThresh */
0x04, /* pmdLowerLowThresh */
0x4, /* pmdUpperHighGainStepAttack */
0x2, /* pmdUpperLowGainStepAttack */
0x2, /* pmdLowerHighGainStepRecovery */
0x4, /* pmdLowerLowGainStepRecovery */
0x08, /* pmdMeasDuration */
0x02 /* pmdMeasConfig */
};

static mykonosAgcCfg_t obsRxAgcConfig =

{
255, /* agcRx1MaxGainIndex */
195, /* agcRx1MinGainIndex */
255, /* agcRx2MaxGainIndex */
195, /* agcRx2MinGainIndex: */
255, /* agcObsRxMaxGainIndex */
203, /* agcObsRxMinGainIndex */
1, /* agcObsRxSelect */
1, /* agcPeakThresholdMode */
1, /* agcLowThsPreventGainIncrease */
30720, /* agcGainUpdateCounter */
3, /* agcSlowLoopSettlingDelay */
2, /* agcPeakWaitTime */
0, /* agcResetOnRxEnable */
0, /* agcEnableSyncPulseForGainCounter */
&obsRxPeakAgc,
&obsRxPwrAgc
};

static mykonosRxProfile_t rxProfile =

{/* Rx 20MHz, IQrate 30.72MSPS, Dec5 */
1, /* The divider used to generate the ADC clock*/
&rxFir, /* Pointer to Rx FIR filter structure*/
4, /* Rx FIR decimation (1,2,4)*/
5, /* Decimation of Dec5 or Dec4 filter (5,4)*/
1, /* If set, and DEC5 filter used, will use a higher rejection DEC5 FIR
filter (1=Enabled, 0=Disabled)*/
2, /* RX Half band 1 decimation (1 or 2)*/
30720, /* Rx IQ data rate in kHz*/
20000000, /* The Rx RF passband bandwidth for the profile*/
20000, /* Rx BBF 3dB corner in kHz*/
NULL /* pointer to custom ADC profile*/
};

static mykonosRxProfile_t orxProfile =

{/* ORX 100MHz, IQrate 122.88MSPS, Dec5 */
1, /* The divider used to generate the ADC clock*/
&obsrxFir, /* Pointer to Rx FIR filter structure or NULL*/
2, /* Rx FIR decimation (1,2,4)*/
5, /* Decimation of Dec5 or Dec4 filter (5,4)*/
0, /* If set, and DEC5 filter used, will use a higher rejection DEC5 FIR
filter (1=Enabled, 0=Disabled)*/
1, /* RX Half band 1 decimation (1 or 2)*/
122880, /* Rx IQ data rate in kHz*/
Rev. B | Page 67 of 360
UG-992 AD9371/AD9375 System Development User Guide
100000000, /* The Rx RF passband bandwidth for the profile*/
100000, /* Rx BBF 3dB corner in kHz*/
NULL /* Pointer to custom ADC profile*/
};

static mykonosRxProfile_t snifferProfile =

{ /* SRx 20MHz, IQrate 30.72MSPS, Dec5 */
1, /* The divider used to generate the ADC clock*/
&snifferRxFir, /* Pointer to Rx FIR filter structure or NULL*/
4, /* Rx FIR decimation (1,2,4)*/
5, /* Decimation of Dec5 or Dec4 filter (5,4)*/
0, /* If set, and DEC5 filter used, will use a higher rejection DEC5 FIR
filter (1=Enabled, 0=Disabled)*/
2, /* RX Half band 1 decimation (1 or 2)*/
30720, /* Rx IQ data rate in kHz*/
20000000, /* The Rx RF passband bandwidth for the profile*/
100000, /* Rx BBF 3dB corner in kHz*/
NULL /* pointer to custom ADC profile*/
};

static mykonosTxProfile_t txProfile =

{ /* Tx 20/100MHz, IQrate 122.88MSPS, Dec5 */
DACDIV_2p5, /* The divider used to generate the DAC clock*/
&txFir, /* Pointer to Tx FIR filter structure*/
2, /* The Tx digital FIR filter interpolation (1,2,4)*/
2, /* Tx Halfband1 filter interpolation (1,2)*/
1, /* Tx Halfband2 filter interpolation (1,2)*/
1, /* TxInputHbInterpolation (1,2)*/
122880, /* Tx IQ data rate in kHz*/
20000000, /* Primary Signal BW*/
100000000, /* The Tx RF passband bandwidth for the profile*/
710539, /* The DAC filter 3dB corner in kHz*/
50000, /* Tx BBF 3dB corner in kHz*/
0 /* Enable DPD, only valid for AD9373*/
};

static mykonosDigClocks_t mykonosClocks =

{
122880, /* CLKPLL and device reference clock frequency in kHz*/
9830400, /* CLKPLL VCO frequency in kHz*/
VCODIV_2, /* CLKPLL VCO divider*/
4 /* CLKPLL high speed clock divider*/
};

static mykonosRxSettings_t rxSettings =

{
&rxProfile, /* Rx datapath profile, 3dB corner frequencies, and digital filter
enables*/
&rxFramer, /* Rx JESD204b framer configuration structure*/
&rxGainControl, /* Rx Gain control settings structure*/
&rxAgcConfig, /* Rx AGC control settings structure*/
3, /* The desired Rx Channels to enable during initialization*/
0, /* Internal LO = 0, external LO*2 = 1*/
2490000000U, /* Rx PLL LO Frequency (internal or external LO)*/
0 /* Flag to choose if complex baseband or real IF data are selected for
Rx and ObsRx paths. Where, if > 0 = real IF data, '0' = zero IF (IQ) data*/
};

static mykonosDpdConfig_t dpdConfig =

{
Rev. B | Page 68 of 360
AD9371/AD9375 System Development User Guide UG-992
5, /* 1/2^(damping + 8) fraction of power `forgotten' per sample (default:
`1/8192' = 5, valid 0 to 15), 0 = infinite damping*/
1, /* number of weights to use for int8_cpx weights weights member of this
structure (default = 1)*/
2, /* DPD model version: one of four different generalized polynomial
models: 0 = same as R0 silicon, 1-3 are new and the best one depends on the PA (default:
2)*/
1, /* 1 = Update saved model whenever peak Tx digital RMS is within 1dB of
historical peak Tx RMS*/
20, /* Determines how much weight the loaded prior model has on DPD
modeling (Valid 0 - 32, default 20)*/
0, /* Default off = 0, 1=enables automatic outlier removal during DPD
modeling */
512, /* Number of samples to capture (default: 512, valid 64-32768)*/
4096, /* threshold for sample in AM-AM plot outside of 1:1 line to be thrown
out. (default: 50% = 8192/2, valid 8192 to 1)*/
0, /* 16th of an ORx sample (16=1sample), (default 0, valid -64 to 64)*/
255, /* Default 255 (-30dBFs=(20Log10(value/8192)), (valid range 1 to
8191)*/
{{64,0},{0,0},{0,0}}/* DPD model error weighting (real/imag valid from -128 to 127)*/
};

static mykonosClgcConfig_t clgcConfig =

{
-2000, /* (value = 100 * dB (valid range -32768 to 32767) - total gain and
attenuation from the AD9371 Tx1 output to ORx1 input in (dB * 100)*/
-2000, /* (value = 100 * dB (valid range -32768 to 32767) - total gain and
attenuation from the AD9371 Tx2 output to ORx2 input in (dB * 100)*/
0, /* (valid range 0 - 40dB), no default, depends on PA, Protects PA by
making sure Tx1Atten is not reduced below the limit*/
0, /* (valid range 0 - 40dB), no default, depends on PA, Protects PA by
making sure Tx2Atten is not reduced below the limit*/
75, /* valid range 1-100, default 75*/
75, /* valid range 1-100, default 45*/
0, /* 0= allow CLGC to run, but Tx1Atten will not be updated. User can
still read back power measurements. 1=CLGC runs, and Tx1Atten automatically updated*/
0, /* 0= allow CLGC to run, but Tx2Atten will not be updated. User can
still read back power measurements. 1=CLGC runs, and Tx2Atten automatically updated*/
0, /* 16th of an ORx sample (16=1sample), (default 0, valid -64 to 64)*/
255 /* Default 255 (-30dBFs=(20Log10(value/8192)), (valid range 1 to
8191)*/
};

static mykonosVswrConfig_t vswrConfig =

{
0, /* 16th of an ORx sample (16=1sample), (default 0, valid -64 to 64)*/
255, /* Default 255 (-30dBFs=(20Log10(value/8192)), (valid range 1 to
8191)*/
0, /* 3p3V GPIO pin to use to control VSWR switch for Tx1 (valid 0-11)
(output from the AD9371)*/
1, /* 3p3V GPIO pin to use to control VSWR switch for Tx2 (valid 0-11)
(output from the AD9371)*/
0, /* 3p3v GPIO pin polarity for forward path of Tx1, opposite used for
reflection path (1 = high level, 0 = low level)*/
0, /* 3p3v GPIO pin polarity for forward path of Tx2, opposite used for
reflection path (1 = high level, 0 = low level)*/
1, /* Delay for Tx1 after flipping the VSWR switch until measurement is
made. In ms resolution*/
1 /* Delay for Tx2 after flipping the VSWR switch until measurement is
made. In ms resolution*/
};

Rev. B | Page 69 of 360

UG-992 AD9371/AD9375 System Development User Guide
static mykonosTxSettings_t txSettings =
{
&txProfile, /* Tx datapath profile, 3dB corner frequencies, and digital filter
enables*/
&deframer, /* the AD9371 JESD204b deframer config for the Tx data path*/
TX1_TX2, /* The desired Tx channels to enable during initialization*/
0, /* Internal LO=0, external LO*2 if =1*/
2503000000U, /* Tx PLL LO frequency (internal or external LO)*/
TXATTEN_0P05_DB,/* Initial and current Tx1 Attenuation*/
10000, /* Initial and current Tx1 Attenuation mdB*/
10000, /* Initial and current Tx2 Attenuation mdB*/
NULL, /* DPD,CLGC,VSWR settings. Only valid for AD9373 device, set pointer to
NULL otherwise*/
NULL, /* CLGC Config Structure. Only valid for AD9373 device, set pointer to
NULL otherwise*/
NULL /* VSWR Config Structure. Only valid for AD9373 device, set pointer to
NULL otherwise*/
};

static mykonosObsRxSettings_t obsRxSettings =

{
&orxProfile, /* ORx datapath profile, 3dB corner frequencies, and digital filter
enables*/
&orxGainControl,/* ObsRx gain control settings structure*/
&obsRxAgcConfig,/* ORx AGC control settings structure*/
&snifferProfile,/* Sniffer datapath profile, 3dB corner frequencies, and digital filter
enables*/
&snifferGainControl,/* SnRx gain control settings structure*/
&obsRxFramer, /* ObsRx JESD204b framer configuration structure */
(MYK_ORX1_ORX2 | MYK_SNRXA_B_C),/* obsRxChannel */
OBSLO_TX_PLL, /* (obsRxLoSource) The Obs Rx mixer can use the Tx Synth(TX_PLL) or
Sniffer Synth (SNIFFER_PLL) */
2600000000U, /* SnRx PLL LO frequency in Hz */
0, /* Flag to choose if complex baseband or real IF data are selected for
Rx and ObsRx paths. Where if > 0 = real IF data, '0' = complex data*/
NULL, /* Custom Loopback ADC profile to set the bandwidth of the ADC response
*/
OBS_RXOFF /* Default ObsRx channel to enter when radioOn called */
};

static mykonosArmGpioConfig_t armGpio =

{
0, // useRx2EnablePin; /*!< 0= RX1_ENABLE controls RX1 and RX2, 1 = separate
RX1_ENABLE/RX2_ENABLE pins */
0, // useTx2EnablePin; /*!< 0= TX1_ENABLE controls TX1 and TX2, 1 = separate
TX1_ENABLE/TX2_ENABLE pins */
0, // txRxPinMode; /*!< 0= ARM command mode, 1 = Pin mode to power up Tx/Rx chains
*/
0, // orxPinMode; /*!< 0= ARM command mode, 1 = Pin mode to power up ObsRx
receiver*/

/*the AD9371 ARM input GPIO pins -- Only valid if orxPinMode = 1 */

0, // orxTriggerPin; /*!< Select desired GPIO pin (valid 4-15) */
0, // orxMode2Pin; /*!< Select desired GPIO pin (valid 0-18) */
0, // orxMode1Pin; /*!< Select desired GPIO pin (valid 0-18) */
0, // orxMode0Pin; /*!< Select desired GPIO pin (valid 0-18) */

/* the AD9371 ARM output GPIO pins -- always available, even when pin mode not
enabled*/
0, // rx1EnableAck; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
0, // rx2EnableAck; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
0, // tx1EnableAck; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
Rev. B | Page 70 of 360
AD9371/AD9375 System Development User Guide UG-992
0, // tx2EnableAck; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
0, // orx1EnableAck; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
0, // orx2EnableAck; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
0, // srxEnableAck; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
0 // txObsSelect; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
/* When 2Tx are used with only 1 ORx input, this GPIO tells the BBP which Tx channel is
*/
/* active for calibrations, so BBP can route correct RF Tx path into the single ORx
input*/
};

static mykonosGpio3v3_t gpio3v3 =

{
0, /*!< Oe per pin, 1=output, 0 = input */
GPIO3V3_BITBANG_MODE, /*!< Mode for GPIO3V3[3:0] */
GPIO3V3_BITBANG_MODE, /*!< Mode for GPIO3V3[7:4] */
GPIO3V3_BITBANG_MODE, /*!< Mode for GPIO3V3[11:8] */
};

static mykonosGpioLowVoltage_t gpio =

{
0,/* Oe per pin, 1=output, 0 = input */
GPIO_MONITOR_MODE,/* Mode for GPIO[3:0] */
GPIO_MONITOR_MODE,/* Mode for GPIO[7:4] */
GPIO_MONITOR_MODE,/* Mode for GPIO[11:8] */
GPIO_MONITOR_MODE,/* Mode for GPIO[15:12] */
GPIO_MONITOR_MODE,/* Mode for GPIO[18:16] */
};

static mykonosAuxIo_t mykonosAuxIo =

{
0, //auxDacEnableMask uint16_t
{0,0,0,0,0,0,0,0,0,0}, //AuxDacValue uint16[10]
{0,0,0,0,0,0,0,0,0,0}, //AuxDacSlope uint8[10]
{0,0,0,0,0,0,0,0,0,0}, //AuxDacVref uint8[10]
&gpio3v3, //pointer to gpio3v3 struct
&gpio, //pointer to gpio1v8 struct
&armGpio
};

static spiSettings_t mykSpiSettings =

{
1, /* chip select index - valid 1~8 */
0, /* the level of the write bit of a SPI write instruction word, value is inverted for
SPI read operation */
1, /* 1 = 16-bit instruction word, 0 = 8-bit instruction word */
1, /* 1 = MSBFirst, 0 = LSBFirst */
0, /* clock phase, sets which clock edge the data updates (valid 0 or 1) */
0, /* clock polarity 0 = clock starts low, 1 = clock starts high */
0, /* Not implemented in ADIs platform layer. SW feature to improve SPI throughput */
1, /* Not implemented in ADIs platform layer. For SPI Streaming, set address increment
direction. 1= next addr = addr+1, 0:addr=addr-1 */
1 /* 1: Use 4-wire SPI, 0: 3-wire SPI (SDIO pin is bidirectional). NOTE: ADI's FPGA
platform always uses 4-wire mode */
};

static mykonosTempSensorConfig_t tempSensor =

{
7, /* 3-bit value that controls the AuxADC decimation factor when used for
temp sensor calculations; AuxADC_decimation = 256 * 2^tempDecimation*/
67, /* 8-bit offset that gets added to temp sensor code internally*/

Rev. B | Page 71 of 360

UG-992 AD9371/AD9375 System Development User Guide
1, /* this bit overrides the factory-calibrated fuse offset and uses the
value stored in the offset member*/
15, /* 4-bit code with a resolution of 1°C/LSB, each time a temperature
measurement is performed, the device compares the current temperature against the previous
value.*/
};

static mykonosTempSensorStatus_t tempStatus =

{
0, /* 16-bit signed temperature value (in deg C) that is read back*/
0, /* If the absolute value of the difference is greater than the value in
temperature configuration tempWindow, the windowExceeded flag is set.*/
0, /* when windowExceeded member gets set, this bit is set to 1 if current
value is greater than previous value, else reset*/
0, /* when the reading is complete and a valid temperature value stored in
tempCode.*/
};

mykonosDevice_t mykDevice =
{
&mykSpiSettings, /* SPI settings data structure pointer */
&rxSettings, /* Rx settings data structure pointer */
&txSettings, /* Tx settings data structure pointer */
&obsRxSettings, /* ObsRx settings data structure pointer */
&mykonosAuxIo, /* Auxiliary IO settings data structure pointer */
&mykonosClocks, /* Holds settings for CLKPLL and reference clock */
0 /* the AD9371 initialize function uses this as an output to
remember which profile data structure pointers are valid */
};

headless.h
/**
* \file headless.h
*
* \brief Contains definitions for headless.c
*/

#ifndef HEADLESS_H_
#define HEADLESS_H_

#ifdef __cplusplus
extern "C" {
#endif

#ifdef __cplusplus
}
#endif

#endif /* HEADLESS_H_ */

headless.c
/**
* \file headless.c
*
* \brief Contains example code for user integration with their application
*
* All data structures required for operation have been initialized with values which
reflect
* these settings:
*
Rev. B | Page 72 of 360
AD9371/AD9375 System Development User Guide UG-992
* Device Clock:
* 122.88MHz
*
* Profiles:
* Rx 20MHz, IQrate 30.72MSPS, Dec5
* Tx 20/100MHz, IQrate 122.88MSPS, Dec5
* ORX 100MHz, IQrate 122.88MSPS, Dec5
* SRx 20MHz, IQrate 30.72MSPS, Dec5
*
* \def Action User needed action
* \def Info information section
*/

#include <stdlib.h>
#include "headless.h"
#include "mykonos.h"
#include "mykonos_gpio.h"
#include "myk_init.h"
/****< Action: Insert rest of required Includes Here >***/

int main()
{
const char* errorString;
uint8_t mcsStatus = 0;
uint8_t pllLockStatus = 0;
uint8_t binary[98304] = {0}; /*** < Action: binary should contain ARM binary file as
array > ***/
uint32_t count = sizeof(binary);
uint8_t errorFlag = 0;
uint8_t errorCode = 0;
uint32_t initCalsCompleted = 0;
uint16_t errorWord = 0;
uint16_t statusWord = 0;
uint8_t status = 0;
mykonosInitCalStatus_t initCalStatus = {0};

uint8_t deframerStatus = 0;
uint8_t obsFramerStatus = 0;
uint8_t framerStatus = 0;
uint32_t initCalMask = TX_BB_FILTER | ADC_TUNER | TIA_3DB_CORNER | DC_OFFSET |
TX_ATTENUATION_DELAY | RX_GAIN_DELAY
| FLASH_CAL | PATH_DELAY | TX_LO_LEAKAGE_INTERNAL | TX_QEC_INIT |
LOOPBACK_RX_LO_DELAY
| LOOPBACK_RX_RX_QEC_INIT | RX_LO_DELAY | RX_QEC_INIT;

uint32_t trackingCalMask = TRACK_RX1_QEC | TRACK_RX2_QEC | TRACK_TX1_QEC |

TRACK_TX2_QEC | TRACK_ORX1_QEC
| TRACK_ORX2_QEC;

mykonosErr_t mykError = MYKONOS_ERR_OK;

mykonosGpioErr_t mykGpioErr = MYKONOS_ERR_GPIO_OK;

/* Allocating memory for the errorString */

errorString = (const char*)malloc(sizeof(char) * 200);

/*** < Action: Insert System Clock(s) Initialization Code Here > ***/

/*** < Action: Insert BBP Initialization Code Here > ***/

/*************************************************************************/
/***** the AD9371 Initialization Sequence *****/
/*************************************************************************/
Rev. B | Page 73 of 360
UG-992 AD9371/AD9375 System Development User Guide

/*** < Action: Toggle RESET pin on the AD9371 device > ***/
if ((mykError = MYKONOS_resetDevice(&mykDevice)) != MYKONOS_ERR_OK)
{
/*** < Info: errorString will contain log error string in order to debug failure >
***/
errorString = getthe AD9371ErrorMessage(mykError);
}

if ((mykError = MYKONOS_initialize(&mykDevice)) != MYKONOS_ERR_OK)

{
/*** < Info: errorString will contain log error string in order to debug failure >
***/
errorString = getthe AD9371ErrorMessage(mykError);
}

/*************************************************************************/
/***** the AD9371 CLKPLL Status Check *****/
/*************************************************************************/
if ((mykError = MYKONOS_checkPllsLockStatus(&mykDevice, &pllLockStatus)) !=
MYKONOS_ERR_OK)
{
/*** < Info: errorString will contain log error string in order to debug failure >
***/
errorString = getthe AD9371ErrorMessage(mykError);
}

if (pllLockStatus & 0x01)

{
/*** < User: code here for actions once CLKPLL locked > ***/
}
else
{
/*** < User: code here here for actions since CLKPLL not locked
* ensure lock before proceeding - > ***/
}

/*************************************************************************/
/***** the AD9371 Perform MultiChip Sync *****/
/*************************************************************************/
if ((mykError = MYKONOS_enableMultichipSync(&mykDevice, 1, &mcsStatus)) !=
MYKONOS_ERR_OK)
{
/*** < Info: errorString will contain log error string in order to debug failure >
***/
errorString = getthe AD9371ErrorMessage(mykError);
}

/*** < Action: minimum 3 SYSREF pulses from Clock Device has to be produced
* for MulticChip Sync > ***/

/************************************************************************/
/***** the AD9371 Verify MultiChip Sync *****/
/************************************************************************/
if ((mykError = MYKONOS_enableMultichipSync(&mykDevice, 0, &mcsStatus)) !=
MYKONOS_ERR_OK)
{
/*** < Info: errorString will contain log error string in order to debug failure >
***/
errorString = getthe AD9371ErrorMessage(mykError);
}

Rev. B | Page 74 of 360

AD9371/AD9375 System Development User Guide UG-992
if ((mcsStatus & 0x0B) == 0x0B)
{
/*** < Info: MCS successful > ***/
/*** < Action: extra User code > ***/
}
else
{
/*** < Info: MCS failed > ***/
/*** < Action: ensure MCS before proceeding > ***/
}

/*************************************************************************/
/***** the AD9371 Load ARM file *****/
/*************************************************************************/
if (pllLockStatus & 0x01)
{
if ((mykError = MYKONOS_initArm(&mykDevice)) != MYKONOS_ERR_OK)
{
/*** < Info: errorString will contain log error string in order to debug
failure > ***/
errorString = getthe AD9371ErrorMessage(mykError);
}

/*** < Action: User must load ARM binary byte array into variable binary[98304]
before calling next command > ***/
if ((mykError = MYKONOS_loadArmFromBinary(&mykDevice, &binary[0], count)) !=
MYKONOS_ERR_OK)
{
/*** < Info: errorString will contain log error string in order to debug why
* ARM did not load properly - check binary and device settings > ***/
/*** < Action: User code > ***/
errorString = getthe AD9371ErrorMessage(mykError);
}

}
else
{
/*** < Action: check settings for proper CLKPLL lock > ***/
}

/*************************************************************************/
/***** the AD9371 Set RF PLL Frequencies *****/
/*************************************************************************/
if ((mykError = MYKONOS_setRfPllFrequency(&mykDevice, RX_PLL, mykDevice.rx-
>rxPllLoFrequency_Hz)) != MYKONOS_ERR_OK)
{
/*** < Info: errorString will contain log error string in order to debug failure >
***/
errorString = getthe AD9371ErrorMessage(mykError);
}

if ((mykError = MYKONOS_setRfPllFrequency(&mykDevice, TX_PLL, mykDevice.tx-

>txPllLoFrequency_Hz)) != MYKONOS_ERR_OK)
{
/*** < Info: errorString will contain log error string in order to debug failure >
***/
errorString = getthe AD9371ErrorMessage(mykError);
}

if ((mykError = MYKONOS_setRfPllFrequency(&mykDevice, SNIFFER_PLL, mykDevice.obsRx-

>snifferPllLoFrequency_Hz))
!= MYKONOS_ERR_OK)
Rev. B | Page 75 of 360
UG-992 AD9371/AD9375 System Development User Guide
{
/*** < Info: errorString will contain log error string in order to debug failure >
***/
errorString = getthe AD9371ErrorMessage(mykError);
}

/*** < Action: wait 200ms for PLLs to lock > ***/

if ((mykError = MYKONOS_checkPllsLockStatus(&mykDevice, &pllLockStatus)) !=

MYKONOS_ERR_OK)
{
/*** < Info: errorString will contain log error string in order to debug failure >
***/
errorString = getthe AD9371ErrorMessage(mykError);
}

if ((pllLockStatus & 0x0F) == 0x0F)

{
/*** < Info: All PLLs locked > ***/
}
else
{
/*** < Info: PLLs not locked > ***/
/*** < Action: Ensure lock before proceeding - User code here > ***/
}

/*************************************************************************/
/***** the AD9371 Set GPIOs *****/
/*************************************************************************/
if ((mykGpioErr = MYKONOS_setupGpio(&mykDevice)) != MYKONOS_ERR_GPIO_OK)
{
/*** < Info: errorString will contain log error string in order to debug failure >
***/
errorString = getGpiothe AD9371ErrorMessage(mykGpioErr);
}

/*************************************************************************/
/***** the AD9371 Set manual gains values *****/
/*************************************************************************/
if ((mykError = MYKONOS_setRx1ManualGain(&mykDevice, 255)) != MYKONOS_ERR_OK)
{
/*** < Info: errorString will contain log error string in order to debug failure >
***/
errorString = getthe AD9371ErrorMessage(mykError);
}

if ((mykError = MYKONOS_setRx2ManualGain(&mykDevice, 255)) != MYKONOS_ERR_OK)

{
/*** < Info: errorString will contain log error string in order to debug failure >
***/
errorString = getthe AD9371ErrorMessage(mykError);
}

if ((mykError = MYKONOS_setObsRxManualGain(&mykDevice, OBS_RX1_TXLO, 255)) !=

MYKONOS_ERR_OK)
{
/*** < Info: errorString will contain log error string in order to debug failure >
***/
errorString = getthe AD9371ErrorMessage(mykError);
}

Rev. B | Page 76 of 360

AD9371/AD9375 System Development User Guide UG-992
if ((mykError = MYKONOS_setObsRxManualGain(&mykDevice, OBS_RX2_TXLO, 255)) !=
MYKONOS_ERR_OK)
{
/*** < Info: errorString will contain log error string in order to debug failure >
***/
errorString = getthe AD9371ErrorMessage(mykError);
}

if ((mykError = MYKONOS_setObsRxManualGain(&mykDevice, OBS_SNIFFER_A, 255)) !=

MYKONOS_ERR_OK)
{
/*** < Info: errorString will contain log error string in order to debug failure >
***/
errorString = getthe AD9371ErrorMessage(mykError);
}

if ((mykError = MYKONOS_setObsRxManualGain(&mykDevice, OBS_SNIFFER_B, 255)) !=

MYKONOS_ERR_OK)
{
/*** < Info: errorString will contain log error string in order to debug failure >
***/
errorString = getthe AD9371ErrorMessage(mykError);
}
if ((mykError = MYKONOS_setObsRxManualGain(&mykDevice, OBS_SNIFFER_C, 255)) !=
MYKONOS_ERR_OK)
{
/*** < Info: errorString will contain log error string in order to debug failure >
***/
errorString = getthe AD9371ErrorMessage(mykError);
}

/*************************************************************************/
/***** the AD9371 Initialize attenuations *****/
/*************************************************************************/
if ((mykError = MYKONOS_setTx1Attenuation(&mykDevice, 0)) != MYKONOS_ERR_OK)
{
/*** < Info: errorString will contain log error string in order to debug failure >
***/
errorString = getthe AD9371ErrorMessage(mykError);
}

if ((mykError = MYKONOS_setTx2Attenuation(&mykDevice, 0)) != MYKONOS_ERR_OK)

{
/*** < Info: errorString will contain log error string in order to debug failure >
***/
errorString = getthe AD9371ErrorMessage(mykError);
}

/*************************************************************************/
/***** the AD9371 ARM Initialization Calibrations *****/
/*************************************************************************/

if ((mykError = MYKONOS_runInitCals(&mykDevice, (initCalMask &

~TX_LO_LEAKAGE_EXTERNAL))) != MYKONOS_ERR_OK)
{
/*** < Info: errorString will contain log error string in order to debug failure >
***/
errorString = getthe AD9371ErrorMessage(mykError);
}

if ((mykError = MYKONOS_waitInitCals(&mykDevice, 60000, &errorFlag, &errorCode)) !=

MYKONOS_ERR_OK)
Rev. B | Page 77 of 360
UG-992 AD9371/AD9375 System Development User Guide
{
/*** < Info: errorString will contain log error string in order to debug failure >
***/
errorString = getthe AD9371ErrorMessage(mykError);
}

if ((errorFlag != 0) || (errorCode != 0))

{
if ((mykError = MYKONOS_getInitCalStatus(&mykDevice, &initCalStatus)) !=
MYKONOS_ERR_OK)
{
/*** < Info: errorString will contain log error string in order to debug
failure > ***/
errorString = getthe AD9371ErrorMessage(mykError);
}

/*** < Info: abort init cals > ***/

if ((mykError = MYKONOS_abortInitCals(&mykDevice, &initCalsCompleted)) !=
MYKONOS_ERR_OK)
{
/*** < Info: errorString will contain log error string in order to debug
failure > ***/
errorString = getthe AD9371ErrorMessage(mykError);
}
if (initCalsCompleted)
{
/*** < Info: which calls had completed, per the mask > ***/
}

if ((mykError = MYKONOS_readArmCmdStatus(&mykDevice, &errorWord, &statusWord)) !=

MYKONOS_ERR_OK)
{
/*** < Info: errorString will contain log error string in order to debug
failure > ***/
errorString = getthe AD9371ErrorMessage(mykError);
}

if ((mykError = MYKONOS_readArmCmdStatusByte(&mykDevice, 2, &status)) !=

MYKONOS_ERR_OK)
{
/*** < Info: errorString will contain log error string in order to debug why
failed > ***/
errorString = getthe AD9371ErrorMessage(mykError);
}
if (status != 0)
{
/*** < Info: Arm Mailbox Status Error errorWord > ***/
/*** < Info: Pending Flag per opcode statusWord, this follows the mask > ***/
}
}
else
{
/*** < Info: Calibrations completed successfully > ***/
}

/*************************************************************************/
/***** the AD9371 ARM Initialization External LOL Calibrations with PA *****/
/*************************************************************************/
/*** < Action: Please ensure PA is enabled operational at this time > ***/
if (initCalMask & TX_LO_LEAKAGE_EXTERNAL)
{

Rev. B | Page 78 of 360

AD9371/AD9375 System Development User Guide UG-992
if ((mykError = MYKONOS_runInitCals(&mykDevice, TX_LO_LEAKAGE_EXTERNAL)) !=
MYKONOS_ERR_OK)
{
/*** < Info: errorString will contain log error string in order to debug
failure > ***/
errorString = getthe AD9371ErrorMessage(mykError);
}
if ((mykError = MYKONOS_waitInitCals(&mykDevice, 60000, &errorFlag, &errorCode)) !=
MYKONOS_ERR_OK)
{
/*** < Info: errorString will contain log error string in order to debug
failure > ***/
errorString = getthe AD9371ErrorMessage(mykError);
}
if ((errorFlag != 0) || (errorCode != 0))
{
if ((mykError = MYKONOS_getInitCalStatus(&mykDevice, &initCalStatus)) !=
MYKONOS_ERR_OK)
{
/*** < Info: errorString will contain log error string in order to debug
failure > ***/
errorString = getthe AD9371ErrorMessage(mykError);
}

/*** < Info: abort init cals > ***/

if ((mykError = MYKONOS_abortInitCals(&mykDevice, &initCalsCompleted)) !=
MYKONOS_ERR_OK)
{
/*** < Info: errorString will contain log error string in order to debug
failure > ***/
errorString = getthe AD9371ErrorMessage(mykError);
}
if (initCalsCompleted)
{
/*** < Info: which calls had completed, per the mask > ***/
}

if ((mykError = MYKONOS_readArmCmdStatus(&mykDevice, &errorWord, &statusWord))

!= MYKONOS_ERR_OK)
{
/*** < Info: errorString will contain log error string in order to debug
failure > ***/
errorString = getthe AD9371ErrorMessage(mykError);
}

if ((mykError = MYKONOS_readArmCmdStatusByte(&mykDevice, 2, &status)) !=

MYKONOS_ERR_OK)
{
/*** < Info: errorString will contain log error string in order to debug
failure > ***/
errorString = getthe AD9371ErrorMessage(mykError);
}
if (status != 0)
{
/*** < Info: Arm Mailbox Status Error errorWord > ***/
/*** < Info: Pending Flag per opcode statusWord, this follows the mask >
***/
}
}
else
{
/*** < Info: Calibrations completed successfully > ***/
Rev. B | Page 79 of 360
UG-992 AD9371/AD9375 System Development User Guide
}
}
/*************************************************************************/
/***** SYSTEM JESD bring up procedure *****/
/*************************************************************************/
/*** < Action: Make sure SYSREF is stopped/disabled > ***/
/*** < Action: Make sure BBP JESD is reset and ready to recieve CGS chars> ***/

if ((mykError = MYKONOS_enableSysrefToRxFramer(&mykDevice, 1)) != MYKONOS_ERR_OK)

{
/*** < Info: errorString will contain log error string in order to debug failure >
***/
errorString = getthe AD9371ErrorMessage(mykError);
}
/*** < Info: the AD9371 is waiting for sysref in order to start
* transmitting CGS from the RxFramer> ***/

if ((mykError = MYKONOS_enableSysrefToObsRxFramer(&mykDevice, 1)) != MYKONOS_ERR_OK)

{
/*** < Info: errorString will contain log error string in order to debug failure >
***/
errorString = getthe AD9371ErrorMessage(mykError);
}
/*** < Info: the AD9371 is waiting for sysref in order to start
* transmitting CGS from the ObsRxFramer> ***/

/*** < User: Make sure SYSREF is stopped/disabled > ***/

if ((mykError = MYKONOS_enableSysrefToDeframer(&mykDevice, 0)) != MYKONOS_ERR_OK)
{
/*** < Info: errorString will contain log error string in order to debug failure >
***/
errorString = getthe AD9371ErrorMessage(mykError);
}

if ((mykError = MYKONOS_resetDeframer(&mykDevice)) != MYKONOS_ERR_OK)

{
/*** < Info: errorString will contain log error string in order to debug failure >
***/
errorString = getthe AD9371ErrorMessage(mykError);
}

/*** < User: make sure BBP JESD framer is actively transmitting CGS> ***/
if ((mykError = MYKONOS_enableSysrefToDeframer(&mykDevice, 1)) != MYKONOS_ERR_OK)
{
/*** < Info: errorString will contain log error string in order to debug failure >
***/
errorString = getthe AD9371ErrorMessage(mykError);
}

/*************************************************************************/
/***** Enable SYSREF to the AD9371 and BBP *****/
/*************************************************************************/
/*** < Action: Sends SYSREF Here > ***/

/*** < Info: the AD9371 is actively transmitting CGS from the RxFramer> ***/

/*** < Info: the AD9371 is actively transmitting CGS from the ObsRxFramer> ***/

/*** < Action: Insert User: BBP JESD Sync Verification Code Here > ***/

/*************************************************************************/
/***** Check the AD9371 Framer Status *****/
Rev. B | Page 80 of 360
AD9371/AD9375 System Development User Guide UG-992
/*************************************************************************/
if ((mykError = MYKONOS_readRxFramerStatus(&mykDevice, &framerStatus)) !=
MYKONOS_ERR_OK)
{
/*** < Info: errorString will contain log error string in order to debug failure >
***/
errorString = getthe AD9371ErrorMessage(mykError);
}
if ((mykError = MYKONOS_readOrxFramerStatus(&mykDevice, &obsFramerStatus)) !=
MYKONOS_ERR_OK)
{
/*** < Info: errorString will contain log error string in order to debug failure >
***/
errorString = getthe AD9371ErrorMessage(mykError);
}

/*************************************************************************/
/***** Check the AD9371 Deframer Status *****/
/*************************************************************************/
if ((mykError = MYKONOS_readDeframerStatus(&mykDevice, &deframerStatus)) !=
MYKONOS_ERR_OK)
{
/*** < Info: errorString will contain log error string in order to debug failure >
***/
errorString = getthe AD9371ErrorMessage(mykError);
}

/*** < Action: When links have been verified, proceed > ***/

/*************************************************************************/
/***** the AD9371 enable tracking calibrations *****/
/*************************************************************************/
if ((mykError = MYKONOS_enableTrackingCals(&mykDevice, trackingCalMask)) !=
MYKONOS_ERR_OK)
{
/*** < Info: errorString will contain log error string in order to debug why
enableTrackingCals failed > ***/
errorString = getthe AD9371ErrorMessage(mykError);
}

/*** < Info: Allow Rx1/2 QEC tracking and Tx1/2 QEC tracking to run when in the radioOn
state
* Tx calibrations will only run if radioOn and the obsRx path is set to
OBS_INTERNAL_CALS > ***/

/*** < Info: Function to turn radio on, Enables transmitters and receivers
* that were setup during MYKONOS_initialize() > ***/
if ((mykError = MYKONOS_radioOn(&mykDevice)) != MYKONOS_ERR_OK)
{
/*** < Info: errorString will contain log error string in order to debug failure >
***/
errorString = getthe AD9371ErrorMessage(mykError);
}

/*** < Info: Allow TxQEC to run when User: is not actively using ORx receive path >
***/
if ((mykError = MYKONOS_setObsRxPathSource(&mykDevice, OBS_RXOFF)) != MYKONOS_ERR_OK)
{
/*** < Info: errorString will contain log error string in order to debug failure >
***/
errorString = getthe AD9371ErrorMessage(mykError);
}
Rev. B | Page 81 of 360
UG-992 AD9371/AD9375 System Development User Guide
if ((mykError = MYKONOS_setObsRxPathSource(&mykDevice, OBS_INTERNALCALS)) !=
MYKONOS_ERR_OK)
{
/*** < Info: errorString will contain log error string in order to debug failure >
***/
errorString = getthe AD9371ErrorMessage(mykError);
}

return 0;
}

Rev. B | Page 82 of 360

AD9371/AD9375 System Development User Guide UG-992

QUADRATURE ERROR CORRECTION, CALIBRATION, AND ARM CONFIGURATION

The device comes with a built in ARM processor. This ARM State 2
processor is tasked with performing some initial calibrations of the After the initial calibrations are performed, the ARM enters its
signal paths of the device, as well as maintaining quadrature idle state. In this state, it can receive configuration settings, such
error correction (QEC) and local oscillator (LO) leakage as which tracking calibrations are to be enabled. This is
performance during device operation through tracking explained in the Tracking Calibrations section.
algorithms. This chapter outlines the application programming
interface (API) functions used to load the ARM, perform the State 3
initial calibrations, and run tracking calibrations. After the required tracking calibrations are enabled, a radio on
command is provided to the ARM, which moves it into State 3.
ARM STATE MACHINE OVERVIEW In this state, the ARM scheduler is active, and the ARM runs
See Figure 29 for the ARM state machine flowchart. tracking calibrations when the necessary signal chains are
available. The RF paths are also made available for use.
STATE 0:
POWER UP/
RESET
LOADING THE ARM
When the device is powered up or reset, it is necessary for the
BOOST SEQUENCE ARM image to be loaded to the device (this is towards the end
SYSTEM INITIALIZATION
of the initialization process, see an initialization script for further
details). Prior to loading the ARM image, the ARM core is reset
STATE 1: and prepared to receive its image with the following API function:
READY
MYKONOS_initARM(mykonosDevice_t *device)

PERFORM INITIALIZATION where *device is the structure pointer to the data structure.
CALIBRATIONS
After this function is run, the ARM image is then loaded with
the following function:
STATE 2:
IDLE/ MYKONOS_loadArmFromBinary(mykonosDevice_t
RADIO OFF
*device, uint8_t *binary, uint32_t count)
where *binary is a pointer to the byte array containing ARM
program memory bytes, and count is the number of bytes in
RUN RADIO_OFF() RUN RADIO_ON() this byte array.
COMMAND COMMAND
The ARM image is provided though the AD9371_M3.bin file,
provided in the Resources folder of the TES install.
After the ARM image is loaded, the MYKONOS_
STATE 3: loadArmFromBinary function enables the ARM, and the ARM
RADIO ON
automatically begins its boot sequence. As part of the boot
14652-028

sequence, the ARM calculates a checksum for the loaded image.

Figure 29. ARM State Machine Flowchart The following application programming interface (API) function
verifies the ARM load has been completed successfully:
State 0
MYKONOS_verifyArmChecksum(mykonosDevice_t
When the ARM core is powered up, the ARM moves into its *device)
power-up/reset state. An image is to be loaded at this point. The
process for loading that ARM is explained in the next section. This function ensures that the boot sequence completes, before
After the ARM image is loaded, the ARM can be enabled and reading back the calculated checksum from the relevant ARM
begins its boot sequence. memory location. It compares this to the precalculated checksum
embedded in the ARM image. A successful load is verified
State 1 when the checksums are equal.
After the ARM has been successfully booted, it enters its ready
state. In this state, it can receive configuration settings or
commands (instructions), such as to perform the initial
calibrations of the device. This is explained in the Initial ARM
Calibrations section.

Rev. B | Page 83 of 360

UG-992 AD9371/AD9375 System Development User Guide
INITIAL ARM CALIBRATIONS The initial calibrations follow a specific order and must occur in
The ARM processor in the device is tasked with scheduling/ a sequential manner. The ARM proceeds through these calibrations
performing initial calibrations to optimize the performance of in the appropriate sequential order. It is important, however,
the signal paths prior to device operation. These calibrations are that the user wait for these routines to complete prior to perform-
called by the following application programming interface ing any further configuration of the device. The following API
(API) function: command is used to verify that these initial calibrations have
been completed by the ARM:
MYKONOS_runInitCals(mykonosDevice_t *device,
uint32_t calMask) MYKONOS_waitInitCals(mykonosDevice_t
*device, uint32_t timeoutMs, uint8_t
where calMask is a 32-bit mask that informs the ARM processor *errorFlag, uint8_t *errorCode)
which calibrations to run.
where timeoutMs is the time in ms the function must wait for
Table 65 shows the bit assignments of the calibration mask. The the calibrations to complete before returning an error, and
ARM processor runs the selected initial calibration for each *errorFlag and *errorCode indicate if an error has occurred,
enabled channel. and if so, which calibration returned the error (see the Initial
The calMask can thus be created using a bit map from Table 65, Calibration Errors section).
or by using the appropriate enums. For example, the following
enable the ADC tuner and ADC flash calibration in a calMask
to be passed to the MYKONOS_runInitCals( ) function:
unit32_t initCalMask = ADC_TUNER |
FLASH_CAL;

Table 65. Calibration Mask Bit Assignments 1

Bits Corresponding Enumerator Function Description
D0 TX_BB_FILTER Tx baseband filter This tunes the corner frequency of the Tx baseband filter.
calibration
D1 ADC_TUNER ADC tuner calibration This configures the ADC for the required profile bandwidth.
D2 TIA_3DB_CORNER Rx TIA filter calibration This tunes the corner frequency of the Rx transimpedance amplifier
(TIA) filter.
D3 DC_OFFSET Rx dc offset calibration This corrects for dc offset within the Rx chain.
D4 TX_ATTENUATION_DELAY Tx attenuation delay This is used to offset the onset of Tx analog and digital attenuations
to compensate for the path delay between these blocks.
D5 RX_GAIN_DELAY Rx gain delay This offsets the onset of Rx analog attenuator and digital gain/
attenuation block to compensate for the path delay between these
blocks.
D6 FLASH_CAL ADC flash calibration This optimally configures the ADC flash.
D7 PATH_DELAY Path delay This computes the Tx to loopback Rx path delay, which is required for
calibration the Tx quadrature error correction (QEC) and Tx local oscillator leakage
(LOL) algorithms.
D8 TX_LO_LEAKAGE_INTERNAL Tx LO leakage internal This performs an initial internal LO leakage calibration for the Tx path.
initial calibration It utilizes the Tx path, the internal loopback and ORx path (see Figure 34).
D9 TX_LO_LEAKAGE_EXTERNAL Tx LO leakage external This performs an initial external LO leakage calibration for the Tx
initial calibration path. It utilizes the Tx path, a required external loopback path and the
ORx path (see Figure 35).
D10 TX_QEC_INIT Tx QEC initial This performs an initial QEC calibration for the Tx path. It utilizes the
calibration Tx path, the internal loopback path and the ORx path (see Figure 34).
D11 LOOPBACK_RX_LO_DELAY Loopback ORx LO This performs an LO delay calibration for the loopback receiver path.
delay
D12 LOOPBACK_RX_RX_QEC_INIT Loopback RxQEC This performs an initial QEC calibration for the Rx path.
initial calibration
D13 RX_LO_DELAY Rx LO delay This performs an LO delay calibration for the receiver path.
D14 RX_QEC_INIT Rx QEC initial This performs an initial QEC calibration for the Rx path.
calibration
[D15:D31] Not applicable Not used Not applicable

1
There are requirements on a system level for these initialization calibrations to perform successfully. These requirements are described in the System Considerations
for ARM Calibrations section.

Rev. B | Page 84 of 360

AD9371/AD9375 System Development User Guide UG-992
TRACKING CALIBRATIONS TRACKING CALIBRATION SCHEDULER
The ARM processor is tasked with ensuring that quadrature The ARM is tasked with the scheduling of the tracking calibrations,
error correction (QEC) and local oscillator leakage (LOL) scheduling its calibrations based on the periodicity required for
corrections are optimal throughout device operation, for example, each calibration. No user input is required to initiate a tracking
over time, attenuation, and temperature. It achieves this by calibration. Receive calibrations are only run when the receive
performing calibrations at regular intervals. These calibrations chains are enabled; likewise, transmit tracking calibrations are
are termed tracking calibrations and utilize normal traffic data only run when the transmit chains are enabled. Transmit tracking
to update the path correction coefficients. calibrations also require the user to assign the ORx path to the
ARM for calibrations for a specified proportion of time, to
The following application programming interface (API)
allow the Tx data to be observed.
function enables the tracking calibrations in the ARM:
After the device is initialized, the ARM enters the idle/radio off
MYKONOS_enableTrackingCals(mykonosDevice_t
*device, uint32_t enableMask) state. When the ARM is in this state, the device is not transmitting/
receiving data. For the device to transmit/receive data, the ARM
where enableMask is a 32-bit mask that informs the ARM
must be in the radio on state with the tracking calibrations enabled.
processor which calibrations to run.
See Figure 29 for an overview of the ARM state machine.
Table 66 shows the bit assignments of the enable mask. There is
Radio Off
also an equivalent function to read which tracking calibrations
are enabled, which uses the same mask: The scheduler is not active in this state. The signal chains are
powered down and the device is not receiving or transmitting data.
MYKONOS_getEnabledTrackingCals(mykonosDevice
_t *device, uint32_t *enableMask) Radio On
This API function must be run in the radio off state, or before The scheduler is active in this state, and tracking calibrations
the device is operational. It cannot be run when the device is are run. The signal chains are available for use (see the System
operational (ARM is in radio on state) because the ARM does Control section).
not accept changes to the enabled tracking calibrations when The ARM is advised to move to the radio off/radio on states
the device is actively sending and receiving traffic data. The with the following application programming interface (API)
device can be returned to radio off, where traffic data is not functions:
being sent or received, if changes to the active tracking calibrations
must be made. However, it is recommended that the respective • MYKONOS_radioOn(mykonosDevice_t *device)
• MYKONOS_radioOff(mykonosDevice_t *device)
tracking calibrations for the enabled channels be active at all
times when the device is in the radio on state. When the ARM moves the state machine into its radio on state,
it initiates its tracking calibration scheduler. It is therefore
The ARM is tasked with the scheduling of the tracking calibrations.
necessary that the required tracking calibrations be specified
No user input is required to initiate a tracking calibration. The
prior to calling the MYKONOS_radioOn() function.
ARM schedules its calibrations based on the periodicity required
for each calibration. Transmit tracking calibrations are run only It is possible to determine which state the ARM is in by using
at times when the user advises that the ORx path is available to the following API function:
the ARM for calibrations. The requirements of this are detailed MYKONOS_getRadioState(mykonosDevice_t
in the Tracking Calibration Scheduler section, whereas the *device, uint32_t *radioStatus)
control of the ORx path to allow calibrations is covered in the where *radioStatus indicates the current ARM state, as
System Control section. indicated in Table 67.
The Rx/ORx channels also have dc correction tracking, which is
Table 67. Radio Status/ARM State
active at all times. This calibration is not an ARM-based
radioStatus Function
calibration.
Table 66. Tracking Calibrations Enable Mask Bit Assignments 0 Power-up/reset
1 Ready
enableMask Bit(s) Function
2 Radio off
D0 Rx1 QEC tracking
3 Radio on
D1 Rx2 QEC tracking
>3 ARM error—check profile configuration
D2 ORx1 QEC tracking
D3 ORx2 QEC tracking After the state machine is in the radio on state, the ARM scheduler
D4 Tx1 LOL tracking performs the tracking calibrations on a periodic basis, ensuring that
D5 Tx2 LOL tracking the correction values are optimal. For each tracking calibration
D6 Tx1 QEC tracking enabled in the tracking calibration mask, a corresponding
D7 Tx2 QEC tracking calibration task is initiated when the ARM is moved into the radio
[D8:D31] Unused on state, as shown in Figure 30.
Rev. B | Page 85 of 360
UG-992 AD9371/AD9375 System Development User Guide
Each calibration task follows the same sequence of processes as through its own pending bit. This bit is set by the calibration
shown in Figure 31. As is shown, each calibration task is task periodically when the calibration timer expires.
responsible for indicating to the scheduler when it must run,
ARM CALIBRATION TASKS

Tx1 LOL Tx2 LOL Tx1 QEC Tx2 QEC ORx1

QEC
CALIBRATION CALIBRATION CALIBRATION CALIBRATION CALIBRATION ....
TASK TASK TASK TASK
TASK

14652-029
Figure 30. Calibration Tasks Run in the ARM Processor Based on the Tracking Calibration Mask Indicated by the User
CALIBRATION TASK

(FOR EXAMPLE, Tx QEC TRACKING)

STARTED AT RADIO ON STATE

SET PENDING BIT

START CALIBRATION TIMER

FOR EXAMPLE,
FOR Tx QEC, TIMER IS
CURRENTLY 30s

RUN TRACKING CALIBRATION

THIS RUNS WHEN THE RADIO
STATE IS SUITABLE, FOR EXAMPLE,
WITH THE
APPROPRIATE STATUS OF
ENABLE/CONTROL SIGNALS.
CALIBRATIONS RUN IN BATCHES
OF AT LEAST 800µs. THIS FUNCTION
RETURNS ONLY AFTER THE COMPLETE
INSTANCE OF THE TRACKING
CALIBRATION COMPLETES.

CLEAR PENDING BIT

DID AN ERROR YES

OCCUR DURING SET ERROR BIT
THE TRACKING
CALIBRATION?

NO

WAIT FOR CALIBRATION

TIMER TO EXPIRE
14652-030

WAIT FOR HOST TO INTERVENE

FOR EXAMPLE, THE REMAINING TIME

Figure 31. Flowchart of the Scheduling of a Single Process

Table 68. Possible Examples of Pending Bits for the Individual Tracking Calibrations
Pending Bits
Tx1 LOL Tx2 LOL Tx1 QEC Tx2 QEC ORx1 QEC ORx2 QEC Rx1 QEC Rx2 QEC
1 0 0 1 1 0 1 1
Rev. B | Page 86 of 360
AD9371/AD9375 System Development User Guide UG-992
To read back the pending bits, use the following application The scheduler determines which calibration task to run at any
programming interface (API) function: time based on three conditions:
MYKONOS_getPendingTrackingCals(mykonosDevice 1. Pending bits. The scheduler reads the pending bits and
_t*device, uint32_t*pendingCalMask) determines which calibrations are requesting to run.
where pendingCalMask is the returned mask that advises if a 2. Priority. Each calibration task is given its own priority
calibration is pending or has returned an error, as indicated in level. The calibration of the highest priority is given preference
Table 69. (highest priority being 1). The order of priority is shown in
Table 70.
Table 69. PendingCalMask Bits Descriptions
pendingCalMask Bit Description Table 70. Priority Levels of the Calibration Tasks
D0 Rx1 quadrature error correction (QEC) Priority Calibration Task
tracking pending bit 1 Tx local oscillator leakage (LOL)
D1 Rx1 QEC tracking error bit 2 Tx quadrature error correction (QEC)
D2 Rx2 QEC tracking pending bit 3 ORx QEC
D3 Rx2 QEC tracking error bit 4 Rx QEC
D4 ORx1 QEC tracking pending bit
D5 ORx1 QEC tracking error bit Note there is no set priority between the individual
D6 ORx2 QEC tracking pending bit channels calibrations (such as Tx1 LOL and Tx2 LOL). For
D7 ORx2 QEC tracking error bit calibration tasks of the same priority; the scheduler prioritizes
D8 Tx1 local oscillator leakage (LOL) the calibration task that completed first.
tracking pending bit 3. Availability of the required paths. The scheduler also
D9 Tx1 LOL tracking error bit determines if the calibration task can be performed.
D10 Tx2 LOL tracking pending bit For example, as illustrated in Figure 32, the Tx QEC task
D11 Tx2 LOL tracking error bit requires the Tx to be enabled and the ORx to be assigned
D12 Tx1 QEC tracking pending bit to ARM calibrations. If both conditions are not true, then
D13 Tx1 QEC tracking error bit the calibration cannot be run. The scheduler determines
D14 Tx2 QEC tracking pending bit this, and, if the calibration cannot run, continues through
D15 Tx2 QEC tracking error bit its priority list to find a calibration which is pending and
can be run (for example, Rx1 QEC may be run at this time).
The scheduler is then tasked with running each calibration See the System Considerations for the Tracking Calibrations
when its corresponding pending bit is set. At any one time, section for more details on the required paths for each
however, more than one calibration task can be pending, as tracking calibration.
indicated by a possible example shown in Table 68, and it is the
responsibility of the scheduler to determine which calibration
must be run at any time.

X SECONDS

SET SET
PENDING PENDING
BIT BIT

ARM SCHEDULER

Tx1 QEC Tx1 QEC

PENDING BIT PENDING BIT

TX_ENABLE

ALL OTHER USES

ORx USAGE
INTERNAL CALS MODE
14652-031

RUN Tx1 RUN Tx1

ARM PROCESSES QEC TRACKING QEC TRACKING

Figure 32. ARM Scheduler Operation

Rev. B | Page 87 of 360

UG-992 AD9371/AD9375 System Development User Guide
The scheduler runs the tracking calibrations in batches, as noted SYSTEM CONSIDERATIONS FOR ARM
in the run tracking calibrations event (see Figure 31). Tx tracking CALIBRATIONS
calibrations typically require Tx data observation in the tens
This section indicates what is necessary from a system perspective
of milliseconds before the calibrations make an update to the
for the ARM to run its calibrations, for example, input/output
correction parameters. It is recognized that the user may not
path conditions for during initial calibrations and enable signal
provide sufficient time in a single run for the tracking calibration
status for tracking calibrations. This section is split between
to complete; therefore, the scheduler performs calibrations in
initial and tracking calibration considerations.
batches, where the Tx data can be observed in chunks of 800 µs.
When sufficient batches of a tracking calibration run, the algorithm System Considerations for the Initial Calibrations
then computes its correction based on the observed data across The figures in this section show how the device is configured
all the batches. It is only after the correction parameters update for notable calibrations with external system requirements, for
that the pending bit is cleared, as shown in Figure 31. example, the quadrature error correction (QEC) and local oscillator
This batch operation means that when a calibration is pending, leakage (LOL) calibrations. In all diagrams, greyed out lines and
and is selected by the scheduler to be run (based on the three blocks are not active in the calibration. Lines showing the path of
conditions described previously), it initiates a batch to observe the local oscilators (LOs) are shown to distinguish them from the
the Tx data for 800 µs. When this batch is complete, the scheduler signal paths. A brief explanation of the calibration is provided. As
again determines which calibrations can be run. If the same the ARM performs each of the calibrations, it is tasked with
calibration cannot continue to run, for example, in time division configuring the device as per the figures in this section, for
duplex (TDD) mode, when the path to be calibrated may be no example, enabling/disabling paths, and so on. No user input is
longer active, or if a higher priority calibration is pending, it required in this regard.
awaits its next opportunity before it takes another batch of data. However, it is important that the user ensures that external
Note that, if a tracking calibration batch is started but the conditions are met, such as having the power amplifier off
observation is disrupted (for example, if the Tx/Rx path is for all calibrations other than the external LOL initialization
disabled, or if the ORx path is reacquired by user for digital calibration, or having the Rx input properly terminated for an
predistortion (DPD) captures) before 800 µs has completed, Rx QEC initialization calibration.
then the observation that has been made up to this point is Rx QEC Initial Calibration
discarded. This does not affect the algorithm; it waits for another
The Rx quadrature error correction (QEC) initialization calibration
batch, as normal. Therefore, when assigning the use of the
algorithm improves the Rx path QEC performance. The Rx QEC
ORx path for tracking calibrations (internal cals mode), it is
calibration functions by sweeping a number of internally generated
recommended that the user do so in slots of at least 800 µs, or
test tones across the band, measuring quadrature performance,
multiples thereof.
and calculating correction coefficients (see Figure 33).
The final requirement is that the ORx path must be assigned to
The following is a system requirement:
internal calibrations for 400 ms of transmit time every 2 sec.
There are no further requirements on this; no exact period of • For optimum performance and lower calibration duration,
tracking calibration batches that must be maintained. It is up to run the Rx QEC initialization at attenuations between 0 dB
the user to determine the structure of the ORx path assignment and 5 dB. For optimal Rx path calibration performance,
to fit around their own ORx path requirements (such as DPD/ ensure a maximum signal power of −92 dBm/MHz is present
voltage standing wave ratio (VSWR), and so on.). It can be supplied at the Rx input. In addition, it is recommended that the
in one full section, or in batches of 800 µs spread across the Rx input be properly terminated while the calibration is
2 sec in a nonperiodic fashion. The ARM never takes control of running, as test tones are output from the receive port.
the assignment of the ORx path, and is reliant on the user to
assign the ORx for calibrations. If the user fails to provide such
instruction, then the calibrations never run.
In summary, for Tx calibrations to run successfully:
• The ORx must be assigned to internal calibrations by the
user for 400 ms of transmit time every 2 sec.
• Assign this time in batches of at least 800 µs, or multiples
thereof.
Note that the assignment of the ORx path for internal calibrations
mode, as required to run Tx tracking calibrations, is discussed
in the System Control section.

Rev. B | Page 88 of 360

AD9371/AD9375 System Development User Guide UG-992

50Ω

JESD204B INTERFACE
Rx HBFs
INPUT LPF ADC AND FIR
QEC
BLOCK

LPF HBFs
ADC AND FIR

CAL

14652-032
PLL Rx LO

Figure 33. Rx QEC Initial Calibration System Configuration

ORx
INPUT

FEEDBACK
PATH HBFs
LPF ADC AND FIR
ATTENUATOR

HBFs
LPF ADC AND FIR

JESD204B INTERFACE
SnRx LO
QEC
BLOCK
CAL
PLL
Tx LO

HBFs
LPF DAC
COUPLER AND FIR
PA

Tx HBFs
OUTPUT LPF DAC
PA POWERED OFF AND FIR

14652-033
SIG
GEN

Figure 34. Device Path Configuration for the Tx LOL and QEC Initial Calibrations

Internal Tx LO Leakage and Tx QEC Initial Calibrations creating a table of initial calibration values. Then, upon application
of a Tx attenuation setting, the corresponding QEC and local
The Tx internal local oscillator (LO) leakage and Tx quadrature oscillator leakage (LOL) correction values are applied to the Tx
error correction (QEC) initial calibrations use the internal channel by the ARM. The device configuration for this calibration
loopback (feedback) path and the ORx baseband path to is shown in Figure 34.
calculate initial correction factors. During these calibrations,
test signals (tones and wideband signals) are output. These The following is a system requirement:
appear at the Tx output; therefore, it is important that the  Power off the power amplifier in the Tx path during these
power amplifier at the output of the device be switched off. calibrations.
Both calibrations sweep through a series of attenuation values,

Rev. B | Page 89 of 360

UG-992 AD9371/AD9375 System Development User Guide
External Tx LO Leakage Initial Calibration

ORx
INPUT

FEEDBACK
PATH HBFs
LPF ADC AND FIR
ATTENUATOR

HBFs
LPF ADC AND FIR

JESD204B INTERFACE
SnRx LO
QEC
BLOCK
CAL
PLL
Tx LO

HBFs
LPF DAC
COUPLER AND FIR
PA

Tx HBFs
OUTPUT LPF DAC AND FIR

14652-034
SIG
GEN

Figure 35. External LOL System Configuration (Greyed Out Circuitry Not Used)

The external local oscillator leakage (LOL) initialization using ORx1, and Tx2 to calibrate using ORx2 (the user does
calibration requires that the power amplifier be enabled such not need to configure this). The ARM cycles through both Tx1
that a full external loop is made between the Tx outputs and the external LOL calibration, and then Tx2 external LOL calibration,
ORx inputs. The purpose of this calibration is to obtain a so it is imperative that both feedback paths are enabled before
reasonable estimate of the external loop channel conditions the calibration is called.
(gain/phase) prior to operation. The device configuration is Alternatively, if both Tx channels are used (txChannels =
shown in Figure 35. The calibration uses a pseudorandom noise TX1_TX2); however, only the ORx1 channel is used
signal to estimate the channel conditions, which is a broadband (obsRxChannelsEnable = MYK_ORX1), then the ARM
signal with a nominal signal level of −78 dBFS out of the DAC. configures Tx1 to calibrate using ORx1, and Tx2 to also
It is important that a suitable attenuator be chosen between the calibrate using ORx1, which also applies vice versa if ORx2
power amplifier output and the ORx input. This is to prevent Tx is selected. This approach is illustrated in Figure 36.
data from saturating the ORx input. This is also be necessary In this case, the calibration must advise the user which path it
from the perspective of digital predistortion (DPD) operation. wishes to calibrate. It does this through the GPIO pin configured
The full-scale input of the ORx path is −13 dBm (with a 0 dB for the txObsSelect output. The user must configure the
attenuation setting) for a single-tone input. txObsSelect output before the external LOL initialization
The system requires that the output of the Tx channel to be calibration is called (see the ARM GPIOs section). By default,
calibrated be routed to the utilized ORx path for the calibration the txObsSelect output indicates that the Tx1 output is to be
signal to be observed. The device must be configured prior to fed back to the required ORx with a low output on this pin,
the calibration to indicate which Tx is routed back to which ORx. while a high output indicates that Tx2 is to be fed back. Again,
Note that the external Tx LOL initialization calibration makes the initialization calibration cycles through both calibrations
certain assumptions in terms of which Tx is fed back to which consecutively; therefore, it is important that both paths are active
ORx. The ARM bases this on the following parameters within and that the request to toggle the external switch is responded
the device data structure: to (the ARM expects to see the feedback path settled within
35 μs of the state change indicated by the txObsSelect output).
 For Tx channels, device → tx → txChannels.
Note that this calibration does not provide good performance if
 For ORx channels, device → obsRx →
an external LO is provided as the Tx LO. In such cases, LOL
obsRxChannelsEnable.
performance is reliant solely on the initialization calibration,
When both Tx channels are used (txChannels = TX1_TX2) and subsequently degrades.
and both ORx channels are used (obsRxChannelsEnable =
MYK_ORX1_ORX2), the ARM configures Tx1 to calibrate

Rev. B | Page 90 of 360

AD9371/AD9375 System Development User Guide UG-992
SWITCH

ORx1 OR ORx2

TxObsSELECT

PA Tx2

PA Tx1

14652-035
Figure 36. The xObsSelect GPIO Used to Toggle an External Switch (Alternatively, the Output Can Be Fed Back for the BBP to Toggle the Switch)

Initial Calibrations in Two Passes System Considerations for the Tracking Calibrations
Due to system considerations, whereby the power amplifier This section describes the operation of the tracking calibrations.
must be off for all calibrations except for the external local Figure 37 through Figure 44 shows how the device is configured
oscillator leakage (LOL) initial calibration, it is necessary to for each calibration, and a brief explanation of the calibration is
run two instances of the following functions: provided. In Figure 37, Figure 39, Figure 41, and Figure 43, the
grayed out lines and blocks are not active in the calibration.
 AD9371_runInitCals()
Lines showing the path of the local oscillators (LOs) are shown in
 AD9371_waitInitCals()
black to distinguish them from the signal paths. As the ARM
In the first instance, all calibrations are set in the calibration performs each of the calibrations, it is tasked with configuring
mask except for the external LOL initial calibration (D9). The whether the feedback path or the ORx input is selected. No user
PA is turned off per Figure 34, and the Rx input is terminated as input is required in this regard. When utilizing external LOL
shown in Figure 33. The ARM cycles through each of the tracking, however, the ensure that the feedback path is available
calibrations in turn. Upon a successful return from the AD9371_ to use.
waitInitCals() function, the baseband processor (BBP) turns on
the power amplifiers used in the Tx paths.
In the second instance, only the external LOL initial calibration
is run (only D9 is set in the cal mask). The signal chains in the
device are then fully calibrated after successful completion of
this calibration.

Rev. B | Page 91 of 360

UG-992 AD9371/AD9375 System Development User Guide
Rx QEC Tracking Calibration device is reporting a high overload condition, it refrains from
The Rx quadrature error correction (QEC) tracking algorithm updating the coefficients on the basis that the data is not
improves the Rx path QEC performance during operation. It representative of QEC performance.
uses normal traffic data to calculate updated corrected The system requires that the Rx channels be enabled. In time
coefficients. It runs continuously in the background while the division duplexed (TDD) mode, Rx QEC tracking only runs
receivers are active. The Rx QEC tracking uses the overload during Rx periods. If only one channel is enabled, the Rx QEC
detectors (utilized by the gain control algorithms of the device) only runs on this channel.
to indicate an overload condition within the device. If the

50Ω

JESD204B INTERFACE
Rx HBFs
INPUT LPF ADC AND FIR
QEC
BLOCK
HBFs
LPF ADC AND FIR

CAL
PLL Rx LO

14652-036
Figure 37. Rx QEC Tracking

AIR TIME Tx Rx Tx Rx

Rx ENABLE

PERIODS WHERE

14652-037
Rx QEC Rx QEC Rx QEC
CAN RUN

Figure 38. Timing Diagram Showing When Rx QEC Can Run in TDD Mode
(In FDD Modes, Rx Enable is High at All Times; Rx Enable Refers to the Enablement of Rx1 and/or Rx2)

Rev. B | Page 92 of 360

AD9371/AD9375 System Development User Guide UG-992
ORx QEC Tracking Calibration It runs continuously in the background while the observation
receiver is active.
The ORx quadrature error correction (QEC) tracking algorithm
improves the ORx path QEC performance during operation. It The system requires that the ORx channel be enabled, as in time
uses normal traffic data (for example, digital predistortion division duplexed (TDD) mode; ORx QEC tracking only runs
(DPD) capture data) to calculate updated corrected coefficients. during ORx periods.

50Ω

JESD204B INTERFACE
ORx HBFs
INPUT LPF ADC AND FIR
QEC
BLOCK
HBFs
LPF ADC AND FIR

SnRx LO
CAL
PLL

14652-038
Tx LO

Figure 39. ORx QEC Tracking

AIR TIME Tx Rx Tx Rx

HIGH = ORx ON

ORx ON/OFF

LOW = ORx OFF

HIGH = ALL OTHER USES

ORx USAGE
LOW = INTERNAL
CALIBRATIONS MODE

PERIODS WHERE

14652-039
ORx QEC ORx QEC
CAN RUN

Figure 40. Timing Diagram Showing When ORx QEC Can Run in TDD Mode
(ORx On/Off and ORx Usage Are Not Real Signals Used in the Control of the Device, But are Generalizations of the Control of the ORx Path)

Rev. B | Page 93 of 360

UG-992 AD9371/AD9375 System Development User Guide
Tx QEC Tracking Calibration updating the table stored during the Tx QEC initialization to
make sure this table has the best values for the current
The Tx quadrature error correction (QEC) tracking is an online operating conditions. Figure 41 shows the device configuration
calibration that runs during transmission to improve the QEC for Tx QEC tracking calibration.
performance. It utilizes the internal loopback path for
operation. Therefore, the Tx QEC tracking must be interleaved The system requires that the Tx channel(s) be enabled and that
with normal digital predistortion (DPD) captures (or channel the ORx path be available for the ARM to use (for internal
sniffing functions) that utilize the ORx path. This tracking calibrations mode).
determines optimal coefficients for the current gain setting,

ORx
INPUT

FEEDBACK
PATH HBFs
LPF ADC AND FIR
ATTENUATOR

HBFs
LPF ADC AND FIR

JESD204B INTERFACE
SnRx LO
QEC
BLOCK
CAL
PLL
Tx LO

HBFs
LPF DAC
COUPLER AND FIR
PA

Tx HBFs
OUTPUT LPF DAC AND FIR

14652-040
SIG
GEN

Figure 41. Tx QEC Tracking Calibration Configuration

AIR TIME Tx Rx Tx Rx

Tx ENABLE

HIGH = ALL OTHER USES

ORx USAGE
LOW = INTERNAL
CALIBRATIONS MODE

PERIODS WHERE
14652-041

TxQEC Tx QEC
CAN RUN

Figure 42. Timing Diagram Showing When Tx QEC Can Run in TDD Mode (In FDD Modes, Tx Enable is High at All Times; Tx Enable Refers to the Enable of Tx1 and/or
Tx2; ORx Usage Refers to Either ORx1 if Considering Tx1, and ORx2 is Considering Tx2, as Tx1 is Calibrated with the Internal Feedback Path of ORx1, and So On; Note
that ORx Usage is Not a Real Signal Used in the Control of the Device, But is a Generalization of How the ORx is Controlled)

Rev. B | Page 94 of 360

AD9371/AD9375 System Development User Guide UG-992
Tx LOL Tracking Calibration device configuration for the Tx LOL tracking calibration with
The Tx local oscillator leakage (LOL) tracking calibration uses the Tx output looped back to the ORx input.
the external digital predistortion (DPD) path to measure LOL Note that this calibration does not provide good performance
and calculate correction factors. This calibration is run while as an external LO is provided as the Tx LO. Thus, in such cases,
user data is being transmitted (with the power amplifier LOL performance is reliant solely on the initialization calibration,
operational). Because it utilizes the loopback path, it must be and is therefore reduced.
interleaved with normal DPD captures. Figure 43 shows the

ORx
INPUT

FEEDBACK
PATH HBFs
LPF ADC AND FIR
ATTENUATOR

HBFs
LPF ADC AND FIR

JESD204B INTERFACE
SnRx LO
QEC
BLOCK
CAL
PLL
Tx LO

HBFs
LPF DAC
COUPLER AND FIR
PA

Tx HBFs
OUTPUT LPF DAC AND FIR

14652-042
SIG
GEN

Figure 43. Tx LOL Tracking Configuration

AIR TIME Tx Rx Tx Rx

Tx ENABLE

HIGH = ALL OTHER USES

ORx USAGE
LOW = INTERNAL
CALIBRATIONS MODE

PERIODS WHERE
14652-043

Tx LOL Tx LOL
CAN RUN

Figure 44. Timing Diagram Showing When Tx LOL Can Run in TDD Mode
(In FDD Modes, Tx Enable is High at All Times; Tx Enable Refers to the Enable of Tx1 and/or Tx2; ORx Usage Refers to the Corresponding ORx Path of the Tx Identified
for Tx External LOL Calibration; Note that ORx Usage is Not a Real Signal Used to Control the Device But is Instead a Generalization of How the ORx is Controlled)

Rev. B | Page 95 of 360

UG-992 AD9371/AD9375 System Development User Guide
External Channel Table 72. Gain Error vs. Maximum Phase Error
The user must ensure that the appropriate external feedback Gain Error (dB) Maximum Phase Error (Degrees)
path is available when the ARM is given access to the ORx path −3 69.26949155
to perform the Tx tracking calibrations. In the case where both −2.5 67.97895638
Tx channels are being fed back to the same ORx input, the user −2 66.59898696
must ensure that the status of the txObsSelect output is monitored, −1.5 65.12136412
and that the requested path is available for calibration (see the −1 63.53663696
Initial ARM Calibrations section). −0.5 61.83382241
0 60
Note that the external local oscillator leakage (LOL) tracking
+0.5 58.0197531
calibration uses an estimate of the external channel (gain/phase
+1 55.87437871
rotation) to calculate the correction coefficients. This estimate
+1.5 53.54073591
is updated over time while tracking on Tx data; therefore, any
+2 50.98950693
phase, gain drift over time, and temperature can be tracked out.
+2.5 48.18245508
However, sudden changes in the phase and gain of the external
+3 45.0678624
path may result in reduced performance until such time as the
algorithm tracks the channel changes out.
ARM GPIOs
By default, the algorithm acquires 67% of the new channel
The ARM has the following interfaces over pins:
estimate in 200 sec. This slow update rate is chosen because the
external channel typically changes slowly over time. To obtain • Signal chain enables. The ARM is in control of activating
an optimal estimate of the external channel in a shorter time, the signal chains of the device under instruction of the user.
reset the external channel estimate by using the following This can be done through SPI control (application
application programming interface (API) function: programming interface (API) functions), or through the
MYKONOS_resetExtTxLolChannel(mykonosDevice_t TXx_ENABLE pin or the RXx_ENABLE pin. (which is
*device, mykonosTxChannels_t channelSel) explained in the System Control section).
• ORx chain control. The ARM controls the assignment of
where channelSel is the channel for which the external LOL
the ORx path based on instruction from the user. This can
channel estimate must be reset, as per Table 71.
be either controlled over the SPI (API functions), or
Table 71. Description of channelSel for through the four GPIO pins (which is explained in the
MYKONOS_resetExtTxLolChannel() System Control section).
Channel Enumeration • ARM acknowledge signals. The ARM can also use the
Tx1 TX1 GPIOs to advise that it has activated the chains as per the
Tx2 TX2 previously described conditions over SPI input/output pins,
Tx1 and Tx2 TX1_TX2 which is explained in the System Control section.
• Tx observation select bit. This bit is used by the ARM to
After the external LOL channel estimate is reset, the next six
indicate which Tx is to be calibrated for local oscillator
tracking instances are used to estimate the external channel.
leakage (see the External Tx LO Leakage Initial Calibration
The correction is not updated during this time; it is frozen with
section).
the values applied before the API call was issued. After the first six
tracking instances, an optimal channel estimate is obtained, and • The GP_INTERRUPT pin. The general-purpose interrupt
further instances of Tx LOL tracking update the LOL correction pin alerts the user when errors occur within the device. A
coefficients. single pin advises numerous potential errors, such as ARM
errors, phase-locked loop (PLL) unlocking events, and
If the sudden changes are large enough, the external channel JESD204B errors. The functionality and configuration of
estimate must be reset using the previous command, whereas at the general-purpose interrupt is discussed in the General-
other times, it is at the discretion of the user. For cases where Purpose Input/Output (GPIO) Configuration section. This
the external channel must be reset, include the following: section also discusses how to mask only certain events
• If the LO frequency of the device has changed trigger the GP_INTERRUPT pin and describes how to
• If the gain and phase have suddenly changed determine which event has occurred. If it is determined
that the source of the error is an ARM error, reset and
reinitialize the device.

Rev. B | Page 96 of 360

AD9371/AD9375 System Development User Guide UG-992
INITIAL CALIBRATION ERRORS Use the following application programming interface (API)
This section describes how to determine what error has command to verify that these initial calibrations have been
occurred in the event if an error occurs during the running of completed by the ARM, and it returns error information from
the initial calibration. If an error does occur during an initial the initialization calibrations:
calibration, isolate the cause of the issue using the following MYKONOS_waitInitCals(mykonosDevice_t
error codes. Then, reinitialize the device with whatever *device, uint32_t timeoutMs, uint8_t
*errorFlag, uint8_t *errorCode)
procedure changes are necessary.
where timeoutMs is the time in ms the function must wait for
An example of such an error is if the external local oscillator
the calibrations to complete before returning an error, and
leakage (LOL) initial calibration runs without the external
*errorFlag and *errorCode are used to indicate if an error has
feedback path complete. In this event, the calibration reports
occurred, and if so, which calibration returned the error.
that it was unable to observe the Tx channel and that the
calibration was unsuccessful. This result may be due to an MYKONOS_waitInitCals returns two error values: errorFlag and
external switch in an incorrect position. errorCode. errorFlag advises the error status of the initialization
calibrations routine. The returned values are defined in Table 73.

Table 73. errorFlag Parameter Definitions Returned from waitInitCals( )

errorFlag Description
0x00 Command completed successfully.
0x01 Reserved.
0x02 Command not allowed in radio on state. The calibrations are not run. The device must not be in a transmit or receive state
when initial calibrations are called.
0x03 Reserved
0x04 Reserved.
0x05 Radio frequency phase-locked loop (PLL) frequencies are not set prior to running initial calibrations. Calibrations were not run.
0x06 Initialization sequence interrupted by an abort command.
0x07 Calibration error.

Table 74. errorCode Designators as Included in the errorCode Parameter Returned from waitInitCals( )
errorCode Calibration
0x00 Tx baseband filter calibration
0x01 ADC tuner calibration
0x02 Rx transimpedance amplifier (TIA) filter calibration
0x03 Rx dc offset calibration
0x04 Tx attenuation delay
0x05 Rx gain delay
0x06 ADC flash calibration
0x07 Path delay calibration
0x08 Tx local oscillator leakage (LOL) initial calibration
0x09 Tx LOL external initial calibration
0x0A Tx quadrature error correction (QEC) initial calibration
0x0B Loopback ORx LO delay
0x0C Loopback Rx QEC initial calibration
0x0D Rx LO delay
0x0E Rx QEC initial calibration

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UG-992 AD9371/AD9375 System Development User Guide
If the errorFlag returns as 0x07, this result indicates that a Table 78. initErrCodes for the LO Delay Calibration
calibration error occurred. The errorCode parameter can then initErrCode Description
be analyzed to advise which calibration error occurred during 0 No error
the initialization calibration routine, as detailed in Table 74. 1 Rx is disabled
It is then possible to determine which error occurred using the 2 Tx is disabled
following application programming interface (API) function: 3 PLL calibration error
4 Reserved
MYKONOS_getInitCalStatus(mykonosDevice_t
*device, mykonosInitCalStatus_t 5 Reserved
*initCalStatus) 6 Reserved
7 Batch time too small
where initCalStatus is the mykonosInitCalStatus structure
returned with the following elements:
• calsDoneLifetime. This is a bit mask that indicates all the Table 79. initErrCodes for the Path Delay Calibration
initialization calibrations that have been run since the initErrCode Description
ARM was booted. For the definition of the bit mask, see 0 No error
Table 65. 1 Rx is disabled
• calsDoneLastRun. This is a bit mask that indicates the 2 Tx is disabled
specific calibrations that were run on the last call to 3 Data captured timed out due to hardware setup
MYKONOS_runInitCals( ). For the definition of the bit 4 Data capture aborted
mask, see Table 65.
• calsMinimum. This is a bit mask that indicates the set Table 80. initErrCodes for the Rx Quadrature Error Correction
calibrations that must be performed before the ARM (QEC) Initial Calibration
allows the user to move it into its radio on state. For the initErrCode Description
definition of the bit mask, see Table 65. 0 No error
• initErrCal. This is the code that indicates which calibration 1 Rx is disabled
returned, if any, an error during MYKONOS_runInitCals( ). It 2 Tx is disabled
is equivalent to errorCode returned by MYKONOS_ 3 PLL calibration error
waitInitCals( ). For the definition of the bit mask, see Table 74. 4 Settling time error
• initErrCode. This is the exact error code returned by the 5 Reserved
calibration if any occurs during MYKONOS_runInitCals( ). 6 Reserved
See Table 75 to Table 84 for details of the possible errors 7 Reserved
returned. 8 Batch time too small

Table 75. initErrCodes for the ADC Tuner Calibration

initErrCode Description Table 81. initErrCodes for the Rx Transimpedance Amplifier
0 No error
(TIA) Calibration
1 Calibration timed out initErrCode Description
0 No error
1 Error configuring PLL—ORx
Table 76. initErrCodes for the Rx DC Offset Calibration 2 Error during TIA calibration—ORx
initErrCode Description 3 Error configuring PLL—Rx
0 No error 4 Error during TIA calibration—Rx
1 Calibration timed out—Rx
2 Calibration timed out—ORx
3 Calibration timed out—loop back receiver
Table 82. initErrCodes for the Tx Baseband Filter Calibration
(LBRx) initErrCode Description
4 Calibration timed out—SRx 0 No error
1 Reserved
2 Calibration timed out
Table 77. initErrCodes for the ADC Flash Calibration
initErrCode Description
0 No error
1 Calibration aborted
2 Calibration timed out
3 No channel is selected
4 Rx is disabled
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AD9371/AD9375 System Development User Guide UG-992
Table 83. initErrCodes for the Tx Local Oscillator Leakage Table 85. Definition of trackingCal Mask for MYKONOS_
(LOL) Calibration rescheduleTrackingCal( )
initErrCode Description Corresponding
0 No error trackingCal Enum Calibration
1 Reserved 0x01 TRACK_RX1_QEC Rx1 quadrature error
2 Tx is disabled correction (QEC) tracking
calibration
3 Path delay not present (invalid)
0x02 TRACK_RX2_QEC Rx2 QEC tracking calibration
4 Not applicable
0x04 TRACK_ORX1_QEC ORx1 QEC tracking calibration
5 Not applicable
0x08 TRACK_ORX2_QEC ORx2 QEC tracking calibration
6 Data capture timed out due to hardware setup
0x10 TRACK_TX1_LOL Tx1 LOL tracking calibration
7 GPIO not configured in single ORx mode
0x20 TRACK_TX2_LOL Tx2 LOL tracking calibration
8 Tx channel is not observable
0x40 TRACK_TX1_QEC Tx1 QEC tracking calibration
0x80 TRACK_TX2_QEC Tx2 QEC tracking calibration
Table 84. initErrCodes for the Tx Quadrature Error
Correction (QEC) Calibration READING THE ARM VERSION
initErrCode Description
After the ARM is booted, it is possible to read back its version
0 No error
using the following application programming interface (API)
1 Reserved function:
2 Tx is disabled
MYKONOS_getArmVersion(mykonosDevice_t
3 No path delay present
*device, uint8_t *majorVer, uint8
minorVer, unit8_t *rcVer)
TRACKING CALIBRATION ERRORS
where:
This section describes some methods of catching errors in the majorVer is the major version of the ARM build.
tracking calibrations. In the event of an ARM exception, the minorVer is the minor version of the ARM build.
GP_INTERRUPT pin triggers (as indicated previously), rcVer is the release candidate version (build number).
advising the user to reset and reinitialize the device.
Each ARM build has a unique combination of these versions,
Alternatively, an error may occur in a calibration that can be read and thus can be determined from these.
back by polling using the following application programming
interface (API) command: PERFORMING AN ARM MEMORY DUMP
MYKONOS_getPendingTrackingCals(mykonosDevice As noted in the ARM GPIOs section, the ARM uses the
_t *device, uint32_t *pendingCalMask) GP_INTERRUPT pin to report if it has detected an error. At
this stage, perform an ARM memory dump, and then provide
where pendingCalMask is the returned mask that advises if a
this dump to Analog Devices for diagnostics. There is no
calibration is pending or has returned an error, as indicated in
application programming interface (API) written to perform a
Table 69.
full ARM memory dump because the API is written to file a
In the event of an error occurring during one of the calibrations, system diagnostic.
the error can be cleared and the calibration rescheduled using
Example code is supplied in the following section for performing
the following API command:
such an ARM memory dump operation. This code reads the
MYKONOS_rescheduleTrackingCal(mykonosDevice_ ARM memory and writes the binary byte data directly to a binary
t *device, mykonosTrackingCalibrations_t
trackingCal) file. Note that an exception is forced if an exception has not
already occurred. When an exception occurs, important
where trackingCal is an enumeration that indicates that the diagnostic information is stored in the ARM memory. Thus,
calibration must be rescheduled, as indicated by Table 85. in the event of the ARM being dumped for debug in situations
where an exception has not occurred, this code calls an exception
such that this diagnostic information is stored before the ARM
memory is dumped.

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UG-992 AD9371/AD9375 System Development User Guide
Example Code for Performing an ARM Memory Dump Operation
/// <summary>

/// Reads the ARM Memory and writes the binary byte array directly to a binary file. Fi
rst 98304 bytes are program
/// memory followed by 65536 bytes of data memory.
The binaryFilename is opened before reading the ARM memory to
/// verify that the filepath is has valid write access before reading ARM memory.
A file IO exception will be
/// thrown if write access is not valid for the binaryFilename path.
/// </summary>
/// <param name="binaryFilename">File path to save the binary data. Make sure you have
write access to the location.</param>
/// <exception cref="InvalidOperationException">Thrown if TCPIP is not connected</except
ion>"
public void dumpArmMemory(string binaryFilename)
{
if (this.hw.Connected)
{
//Write in BINARY FILE format
String filename = binaryFilename;
System.IO.FileStream fileStream = new System.IO.FileStream(filename, System.IO.F
ileMode.Create, System.IO.FileAccess.Write);

byte[] programMem = new byte[98304];

byte[] dataMem = new byte[65536];

//Check if exception has occurred

byte[] exceptionArray = new byte[4];
this.readArmMem(0x01017FF0, 4, 1, ref exceptionArray);
UInt32 exceptionValue = (UInt32)(exceptionArray[0] | (exceptionArray[1] << 8) |
(exceptionArray[2] << 16) | (exceptionArray[3] << 24));

if (exceptionValue == 0)
{
byte armNotBusy = 0;
this.readEventStatus(WAIT_EVENT.ARMBUSY, ref armNotBusy);

if (armNotBusy > 0)
{
//Force an exception during ARM MEM dump for more useful information
this.sendArmCommand(0x0A, new byte[] { 0x69 }, 1);

System.Diagnostics.Stopwatch stopWatch = new System.Diagnostics.Stopwatc

h();
stopWatch.Start();
while (exceptionValue == 0)
{
this.readArmMem(0x01017FF0, 4, 1, ref exceptionArray);
exceptionValue = (UInt32)(exceptionArray[0] | (exceptionArray[1] <<
8) | (exceptionArray[2] << 16) | (exceptionArray[2] << 24));

//timeout to break while loop

if (stopWatch.ElapsedMilliseconds > 5000)
{
break;
}
}
exceptionValue = 0;
stopWatch.Stop();
}
}

this.readArmMem(0x01000000, programMem.Length, 1, ref programMem);

this.readArmMem(0x20000000, dataMem.Length, 1, ref dataMem);
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AD9371/AD9375 System Development User Guide UG-992

if (exceptionValue == 0)
{//if we forced an exception, clear the exception so the ARM will continue to ru
n.
this.writeArmMem(0x01017FF0, 4, new byte[] { 0, 0, 0, 0 });
this.readArmMem(0x01017FF0, 4, 1, ref exceptionArray);
}

fileStream.Write(programMem, 0, programMem.Length);
fileStream.Write(dataMem, 0, dataMem.Length);

fileStream.Close();
}
else
{
throw new InvalidOperationException("No Hardware Connection");
}
}

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UG-992 AD9371/AD9375 System Development User Guide

SYSTEM CONTROL
CONTROL OF SIGNAL CHAINS (Tx/Rx) • For Tx channels, device → tx → txChannels.
The ARM enables and disables the signal chains of the device, • For Rx channels, device → rx → rxChannels.
which can be performed either through pin control or over the Pin Control Mode
SPI interface. In frequency division duplex (FDD) mode, it is
To enable pin control mode, run the following application
possible to use the application programming interface (API) to
programming interface (API) function:
enable or disable paths; however, in TDD mode, it is recommended
to use pin control of the signal chains to adhere to the strict MYKONOS_setRadioControlPinMode(mykonosDevice
_t *device)
timing requirements of TDD operation.
This function relies on the settings stored in the mykonos-
ARM Control Mode
ArmGpioConfig_t data structure, which must be included in
If the device is not in pin control mode, it defaults to command the device structure at device → auxIO → armGpio. The specific
mode. In this mode, the ARM enables all signals paths (Tx/Rx) members of the structure used by this function are shown in
defined in the data structure provided during the initialization of Table 86.
the device upon entering the radio on (operational) state.
Likewise, the ARM powers down the signal paths upon leaving
the radio on state. The parameters in the device structure that
determine the Rx and Tx chains enabled are as follows:

Table 86. ARM GPIO Configuration Structure Member Descriptions for setRadioControlPinMode
Structure Member Valid Values Description
txRxPinMode 0, 1 0 = ARM command mode for powering up or powering down the Rx/Tx chains
1 = pin control mode for powering up or powering down the Rx/Tx chains
orxPinMode 0, 1 0 = ARM command mode for controlling the ORx receiver
1 = pin control mode for controlling the ORx receiver
useRx2EnablePins 0, 1 0 = use the RX1_ENABLE pin to power up or power down both Rx1 and Rx2
1 = use the RX1_ENABLE pin to power up or power down Rx1, and use the RX2_ENABLE pin
to power up or power down Rx2
useTx2EnablePins 0, 1 0 = use the TX1_ENABLE pin to power up or power down both Tx1 and Tx2
1 = use the TX1_ENABLE pin to power up or power down Tx1, and use the TX2_ENABLE pin
to power up or power down Tx2

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AD9371/AD9375 System Development User Guide UG-992
Pin control mode of the signal chains is performed with the required for calibrations to complete is 800 μs. As noted in the
TXx_ENABLE and RXx_ENABLE pins, as shown in Figure 45. Tracking Calibration Scheduler section, the tracking calibrations
When TX_ENABLE is high, the ARM activates the Tx chain. require at least 800 μs of data for a meaningful observation.
When TX_ENABLE is low, the Tx chain is disabled by the Thus, a slot period must also be of this duration if a tracking
ARM, and vice versa for the RX_ENABLE signals. calibration is run during this slot period.
Two enable pins exist for each receiver and transmitter. Note that this function is automatically called at the end of
TX1_ENABLE and RX1_ENABLE can enable the Tx1 and Rx1 MYKONOS_ loadArmFromBinary( ). Thus, the function is
channels, respectively, while TX2_ENABLE and RX2_ENABLE only called again if the power-up or power-down control method
can enable the Tx2 and Rx2 channels, respectively. of the baseband processor (BBP) changes. The control method
Alternatively, TX1_ENABLE can enable both Tx1 and Tx2 can only be changed when the device is in a radio off state.
simultaneously, and RX1_ENABLE can enable Rx1 and Rx2 Note also that if in pin control mode (txRxPinMode = 1),
simultaneously. and Tx1 is used to control both chains (Tx1 and Tx2),
Table 87 describes the minimum time allowed for the Tx/Rx TX2_ENABLE must still be controlled and low at all times.
chains to enable in any one instance. Note that the minimum time If the pin is not used in the reference design, ground it.

AIR TIME Tx Rx Tx Rx

TX_ENABLE

tENABLE_RISE_TO_FALL tENABLE_FALL_TO_RISE

RX_ENABLE

tENABLE_FALL_TO_ACK

TX_ENABLE_ACK

tENABLE_RISE_TO_ACK

RX_ENABLE_ACK

14652-044
Figure 45. Control of Signal Chains Using RX_ENABLE and TX_ENABLE

Table 87. Minimum Time of Active Periods1

Symbol Description Min Min for Calibrations Max
tENABLE_RISE_TO_FALL Tx/Rx enable rising edge to enable falling edge—enable signal width high 10 μs 800 μs N/A
tENABLE_FALL_TO_RISE Tx/Rx enable falling edge to enable rising edge—enable signal width low 10 μs 800 μs N/A
tENABLE_FALL_TO_ACK Tx/Rx enable falling edge to acknowledge signal to baseband processor (BBP) N/A N/A 2 μs
going low
tENABLE_RISE_TO_ACK Tx/Rx enable rising edge to acknowledge signal to BBP going high N/A N/A 2 μs
1
N/A means not applicable.

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UG-992 AD9371/AD9375 System Development User Guide
ORx PATH CONTROL signal indicates to the ARM that the ORx mode pins must
be immediately sampled to change the ORx mode. Figure 46
Table 88 defines the different operational modes of the ORx shows an example timing diagram where ORX_MODE_2 is
path, each with a unique front-end configuration. Two methods Bit D2, and so on. The following API function is used to
can control the ORx path assignment: configure which GPIO pins are used for the ORx mode
1. Application programming interface (API) function, where control if pin control is selected:
the following API function can send instructions to the ARM
MYKONOS_setArmGpioPins(mykonosDevice_t
over the SPI interface to change the ORx path assignment: *device)
MYKONOS_setObsRxPathSource(mykonosDevice_ This function is explained in the ARM GPIOs section.
t *device, mykonosObsRxChannels_t
obsRxCh) To select the required mode for ORx path control, the following
application programming interface (API) function is used:
where obsRxCh is an enumeration defined in t_mykonos.h,
detailed in Table 88. MYKONOS_
setRadioControlPinMode(mykonosDevice_t
2. Pin control, where the ARM can also monitor four GPIO *device)
pins to initiate a change in the ORx configuration. Three
This function is described in the Control of Signal Chains (Tx/Rx)
pins determine the ORx mode (ORX_MODE[D2:D0], see
section.
Table 88). The state of the other pin is assigned to the ORX_
TRIGGER signal. The rising edge of the ORX_TRIGGER

Table 88. ORX_MODE[D2:D0] Word Definitions

ORx Path Front End ORX_MODE[D2:D0] obsRxCh Enumeration
ORx Off 000 OBS_RXOFF
ORx1 with Tx Local Oscillator (LO) 001 OBS_RX1_TXLO
ORx2 with Tx LO 010 OBS_RX2_TXLO
ARM Calibrations 011 OBS_INTERNALCALS
Sniffer Channel 100 OBS_SNIFFER
ORx1 with Sniffer LO 101 OBS_RX1_SNIFFERLO
ORx2 with Sniffer LO 110 OBS_RX2_SNIFFERLO

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AD9371/AD9375 System Development User Guide UG-992
As noted previously, the Tx tracking algorithms need access to make proper adjustments in the path settings, and thus discard
the ORx path so that the Tx data can be monitored and the the result obtained during this instance. When only periods of
ARM can optimize the current correction coefficients. For this less than 800 µs are used, the algorithms never update their
reason, it is necessary to share the ORx path between digital coefficients. When using a duration of 1.6 ms, the calibration
predisposition (DPD) data acquisition and tracking calibrations algorithm samples two valid observations sequentially. However, if
for the Tx path (the SRx also requires a share of the available the duration is 1 ms, the algorithm makes only one observation,
ORx periods, if used). The ARM is tasked with scheduling its taking 800 µs, and the result from the remaining 200 µs of data
tracking algorithms and ensuring that its correction coefficients is discarded.
are optimal at all times. A tracking algorithm may need a number of observations to
The ARM is not in control of when it has access to the ORx path update the correction coefficients. However, the ARM scheduler
for calibration, which ensures that the ARM cannot interrupt a pauses the tracking algorithms when the ORx path is used for
DPD data acquisition. It is tasked to the baseband processor other purposes and continues when the ORx is reassigned for its
(BBP) to ensure that the ARM has sufficient access to the ORx calibrations. Table 89 shows important timing parameters for
path to complete its calibrations. To ensure that the ARM can ORx pin control mode. However, the tORX_TRIGGER_RISE_TO_RISE
keep corrections optimal, it must have access to the ORx path parameter is applicable in both modes of operation, with 800 µs
for a time no less than 400 ms of the transmit time for every 2 sec. being the minimum duration for an ORx mode.
An additional requirement of the ORx path assignment relates Figure 46 also shows ORX1_ENABLE_ACK, ORX2_ENABLE_
to the minimum duration of an ARM tracking calibration in ACK, and SRX_ENABLE_ACK. These acknowledge signals
any one instance. This duration is 800 µs (see Table 89). This can output on the GPIOs and indicate that the ARM enabled
requirement is because tracking calibrations require 800 µs of data the relevant channel for operation. A full list of the available
to make a valid observation of the transmitter output signal. If acknowledge signals, and how they are configured, is provided
durations of less than 800 µs are used, the algorithms cannot in the ARM GPIO Operation section.

Table 89. Observation Receiver Signal Timings

Timing Parameter Description Min 1 Max1
tORx_TRIGGER_RISE_TO_RISE ORx trigger frequency—minimum duration in an ORx mode 800 µs N/A
tORx_TRIGGER_HOLD ORx trigger hold time 1 µs N/A
tMODE_SETUP ORx mode setup time before ORx trigger rising edge 1 µs N/A
tMODE_HOLD ORx mode hold time 2 µs N/A
tMODE_ACK ORx mode acknowledge signal to baseband processor (BBP) from ORx trigger rising edge N/A 2 µs
1
N/A means not applicable.

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UG-992 AD9371/AD9375 System Development User Guide
OBSERVATION RECEIVER MODE ORx1 ORx2 ARM CALIBRATIONS SNRXA ORx OFF
IN FDD
tORX_TRIGGER_RISE_TO_RISE
tORX_TRIGGER_HOLD

ORX_TRIGGER

tMODE_SETUP

ORX_MODE_0

tMODE_HOLD

ORX_MODE_1

ORX_MODE_2

tMODE_ACK

ORX1_ENABLE_ACK

ORX2_ENABLE_ACK

14652-045
SRX_ENABLE_ACK

Figure 46. Observation Receiver Pin Control Timing Diagram

Table 90. ARM GPIO Configuration Structure Member Descriptions for setArmGpioPins( )
Structure Member Input or Output Available on GPIO Pins
orxTriggerPin Input 4 … 15
orxMode2Pin Input 0 … 15, 18
orxMode1Pin Input 0 … 15, 17
orxMode0Pin Input 0 … 15, 16
rx1EnableAck Output 0 … 15
rx2EnableAck Output 0 … 15
tx1EnableAck Output 0 … 15
tx2EnableAck Output 0 … 15
orx1EnableAck Output 0 … 15
orx2EnableAck Output 0 … 15
srxEnableAck Output 0 … 15
txObsSelect Output 0 … 15

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AD9371/AD9375 System Development User Guide UG-992
ARM GPIO OPERATION The following application programming interface (API)
The ARM is assigned the task of enabling and disabling the function is used to control which GPIO pins are used by the
chains of the device. In pin control mode, Tx and Rx enabling ARM for communication with the BBP, and to enable pin
is performed with the defined Rx and Tx enable pins; however, control mode of the Rx and Tx signal chains:
the ORx enabling is performed through four GPIOs used to MYKONOS_setArmGpioPins(mykonosDevice_t
select from the different enabling options. The ARM can also *device)
use GPIOs to advise the baseband processor (BBP) of the This function is automatically called during the loadArm-
current signal path control, with acknowledge signals that FromBinary( ) function call. This function relies on the settings
advise when the path is enabled. When high, an acknowledge stored in the mykonosArmGpioConfig_t data structure, which
signal advises that the path is enabled. is included in the device structure at device → auxIO → armGpio.
The specific members of this structure used by this function are
detailed in the following sections.

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UG-992 AD9371/AD9375 System Development User Guide

Tx POWER CONTROL
The device features transmitter power control (TPC) to provide Table 91. mykonosTxAttenStepSize_t Enumeration Values
precise control of the transmitter output power. The attenuation and Interpretation
control allows 41.95 dB of attenuation within the transmitter
mykonosTxAttenStepSize_t Enumeration Tx Attenuation
datapath with a minimum resolution of 0.05 dB. Note that Enumeration Value Step Size (dB)
transmitter performance may degrade at attenuation settings TXATTEN_0P05_DB 0 0.05
greater than 20 dB. TXATTEN_0P1_DB 1 0.1
Two transmitter signal path components have variable attenuation TXATTEN_0P2_DB 2 0.2
settings. These include the analog RF attenuator located after TXATTEN_0P4_DB 3 0.4
the mixer, and the digital attenuator located prior to the digital
filters. Refer to Figure 47 for a simplified block diagram In SPI mode, the application programming interface (API)
depicting the variable attenuation stages. commands used to change the Tx attenuation setting are as
follows:
Two modes of interaction regarding the TPC are as follows:
MYKONOS_setTx1Attenuation(mykonosDevice_t
• SPI mode. This mode uses the SPI to send a command to *device, uint16_t tx1Attenuation_mdB)
change the Tx1 or Tx2 attenuation. The resolution of the MYKONOS_setTx2Attenuation(mykonosDevice_t
attenuation step size is a minimum of 0.05 dB. Separate *device, uint16_t tx2Attenuation_mdB)
commands exist for control of Tx1 or Tx2. These commands can be called in the radio on or radio off
• GPIO mode. This mode allows changes of the Tx1 or Tx2 states. If the tx1Attenuation_mdB or tx2Attenuation_mdB to
attenuation based on a low to high transition on selected this function is not a multiple of the Tx attenuation step size,
low voltage GPIO pins. Separate pins can be assigned for the value is rounded down to the nearest multiple of the
Tx1 increment attenuation, Tx1 decrement attenuation, txAttenStepSize value.
Tx2 increment attenuation, and Tx2 decrement attenuation. Additionally, API commands can retrieve the current Tx
The resolution of the attenuation step size can be set to attenuation value. These commands can be used in either SPI
multiples of 0.05 dB up to 1.55 dB in the GPIO mode. or GPIO mode. If the Tx datapath is powered down when these
In SPI mode, resolution of attenuation control can be selected as commands are called, the last valid Tx attenuation setting when
0.05 dB, 0.1 dB, 0.2 dB, or 0.4 dB. This control is set within the the Tx was powered up is read back. These commands are as
device data structure, in device → tx → txAttenStepSize. The follows:
control is of data type mykonosTxAttenStepSize_t, whose MYKONOS_getTx1Attenuation(mykonosDevice_t
enumerated values are described in Table 91. Note that this *device, uint16_t *tx1Attenuation_mdB)
value is programmed to device registers during the • MYKONOS_getTx2Attenuation(mykonosDevice_
MYKONOS_initialize() command. t *device, uint16_t
*tx2Attenuation_mdB)
Refer to the General-Purpose Input/Output (GPIO) Configuration
section for information regarding configuration and operation
of GPIO TPC mode.

DIGITAL FILTER
AND DIG DIGITAL
14652-046

LPF IDAC
SIGNAL ATTEN INTERFACE
RF ATTENUATOR CORRECTION

Figure 47. Variable Attenuation Elements for Transmitter Power Control (TPC)

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AD9371/AD9375 System Development User Guide UG-992

POWER AMPLIFIER (PA) PROTECTION

The transmitter channels feature a protection mechanism that can • The assertion of D1 or D0 can trigger an automatic increase
be enabled to help prevent damage to the PA connected to either in Tx attenuation that persists until the signal level on the
transmitter output. This feature is referred to as PA protection. corresponding channel is reduced less than the programmed
When the full-scale output power of the device exceeds the power threshold. The attenuation change is programmable in
maximum input to the PA, the overload can result in damage to steps of 0.2 dB up to 25.4 dB. The attenuation setting occurs after
the PA device. The PA protection feature implements feedback in the PA error flag is asserted and persists until the bit is cleared.
the system to prevent such an overload by measuring the signal Note that if the PA error flag is configured as a sticky error
level and comparing it to the user-programmable threshold. This flag, the attenuation change stays in effect until the error flag
information can be used by the device to reduce the transmit output is manually cleared. This mode is enabled during PA protection
level on the flagged channel and to eliminate the threat of damage. setup using the txAttenuationControlEnable parameter. The
attenuation step size is set by the attenStepSize parameter.
Even though the PA protection feature includes independent
power measurement blocks for each transmitter channel, this PROTECTION ALGORITHM
feature cannot be enabled for one channel at a time. If an overload The PA protection system monitors the 12 most significant bits
is detected on one channel and not another, the overloaded (MSBs) sent to the Tx1 and Tx2 inputs during user defined
channel asserts a PA error flag specific to that channel. measurement intervals. The signal level measurement is made
The following sections describe the components of the PA prior to all on-chip digital filtering. PA protection is configured
protection system. with the MYKONOS_setupPaProtection(…) command and
enabled through the MYKONOS_enablePaProtection(…)
PA ERROR FLAG
command.
An overload condition is noted by the PA error flag. This structure
When the power measurement is completed, the PA protection
contains a bit for each transmitter that is asserted when an overload
block stores the results for the Tx1 and Tx2 datapaths and asserts
on that channel has occurred. Table 92 describes the PA error flag
a PA error flag if the level measured in either path is greater than
bits.
the user defined threshold. The level measurement is an
Table 92. PA Error Flag Conditions instantaneous power measurement performed by calculating
PA Error Flag, I2 + Q2 of samples. The baseband processor (BBP) can read back
[D1:D0] Description the most recently computed measurement for the Tx1 and Tx2
D0 1 = an overload on Tx1 has been detected. channels by using the MYKONOS_getDacPower(…) command.
0 = no overload condition detected on Tx1. This command can only be used when PA protection is enabled.
D1 1 = an overload on Tx2 has been detected. The PA error flag is asserted as soon as the power measurement
0 = no overload condition detected on Tx2. determines that the measured channel power level is greater than
When one of the PA error flag bits asserts, the method by which the user programmed power threshold. This flag can be configured to
PA protection operates depends on how the system has been remain high until the user issues the clear error command
configured. The options follow: MYKONOS_clearPaErrorFlag(…) by setting the stickyFlagEnable
field to 1. If an overload condition occurs with the stickyFlagEnable
• The baseband processor (BBP) polls the device periodically
field set to 1 and txAttenControlEnable set to 1, the PA protection
to check the PA error flag status and uses the application
system will make a single attenuation reduction that persists until
programming interface (API) command,
the user manually clears the PA error flag. If the stickyFlagEnable
MYKONOS_getPaProtectErrorFlagStatus(…).
field is set to 0, the PA error flag remains high until the overload
• The GP_INTERRUPT pin can be configured to allow PA
condition is not present. When the PA error flag is high,
error flag D1 or D0 to control the status of the pin (see the
attenuation cannot be modified by the user.
General-Purpose Interrupt Overview section for details on
the MYKONOS_configGpInterrupt(…) command). Status The PA protection functionality is summarized in Figure 48, along
can be monitored by the BBP through the GP_INTERRUPT with references to programming instructions.
pin, or by reading back the GP_INTERRUPT status with the
API command, MYKONOS_readGpInterruptStatus(…).

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UG-992 AD9371/AD9375 System Development User Guide

DEVICE INTIALIZED

CONFIGURE PA PROTECTION

MYKONOS_setupPaProtection (...)

START PA PROTECTION

MYKONOS_setupPaProtection (...)

START POWER MEASUREMENT

COMPLETE POWER MEASUREMENT USER CAN CALL

MEASUREMENT TIME SET MYKONOS_getDacPower (...)
BY avgDuration

MEASUREMENT POWER > N N

stickyFlagEnable == 1? PA ERROR FLAG GOES LOW
THRESHOLD POWER

Y Y

USER CLEARS PA ERROR FLAG

PA ERROR FLAG GOES HIGH PA ERROR FLAG REMAINS
HIGH IF PREVIOUSLY HIGH MYKONOS_clearPaProtect
ErrorFlag (...)

N Tx1 OR Tx2 ATTENUATION IS

txAttenControlEnable == 1? NOT INFLUENCED BY
PA PROTECTION CIRCUITRY

Tx1 OR Tx2 ATTENUATION IS INCREASED

14652-130
BY Attenstep IF PA ERROR FLAG
IS HIGH

Figure 48. PA Protection Operational Flowchart

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AD9371/AD9375 System Development User Guide UG-992
API COMMANDS FOR PA PROTECTION • stickyFlagEnable: 1 enables the power amplifier (PA) error
The following sections provide detailed information regarding flags to stay high after an overload occurs, even if the data
the application programming interface (API) commands used path power later decreases less than the power threshold.
to setup, enable, and read back status information for the power When the PA error flag is sticky, the error condition
amplifier protection system. persists until the user manually clears the PA error flag
through the MYKONOS_clearPaProtectErrorFlag(…)
MYKONOS_setupPaProtection(…) command. When 0, it disables this functionality.
mykonosErr_t MYKONOS_setupPaProtection • txAttenControlEnable: When 1, it enables autonomous
(mykonosDevice_t *device, uint16_t attenuation changes in response to the PA error flag state, and
powerThreshold, uint8_t attenStepSize,
when 0, it disables this functionality.
uint8_t avgDuration, uint8_t
stickyFlagEnable, uint8_t MYKONOS_enablePaProtection(…)
txAttenControlEnable)
mykonosErr_t MYKONOS_enablePaProtection
This command writes to device registers with settings for the
(mykonosDevice_t* device, uint8_t
PA protection block. It does not enable the PA protection paProtectEnable)
functionality. Note that independent control of the PA
This command enables the power amplfier protection
protection feature for both Tx channels is not possible. The PA
block according to the parameters passed in
protection block allows for PA error flags to go high if the
MYKONOS_setupPaProtection(…).
accumulated power in the datapath exceeds a programmable
threshold level based on samples taken in a programmable Preconditions
duration. Before calling this function, setup the power amplifier
Preconditions protection block by calling MYKONOS_setupPaProtection(…).
This function can only be called after the MYKONOS_ Parameters
initialize(…) command. • * device: This is a pointer to the device data structure.
Parameters • paProtectEnable: When 1, it enables the power amplifier
• *device: This is the pointer to the device data structure. (PA) protection block, and when 0, it disables the PA
protection block.
• powerThreshold: This parameter sets the power level at
which the power amplifier error flag is raised. This threshold MYKONOS_clearPaProtectErrorFlags(…)
applies to both the Tx1 and Tx2 data paths. The range is 0 mykonosErr_t MYKONOS_clearPaErrorFlag
to 4095. Use the following equation to calculate the desired (mykonosDevice_t* device)
power threshold in dBFS converted to the powerThreshold This function manually clears the power amplifier (PA) error
used in this function: flags. Set up the PA protection block to enable sticky error flags.
powerThreshold = 4095 × 10((txPowerThresh_dBFS)/10) Sticky error flags require the user to clear the bit manually even
if the accumulated power is less than the power threshold for
where:
the PA protection block.
powerThreshold is the value input to this API command.
txPowerThresh_dBFS is the power threshold level in dBFS Preconditions
relative to the Tx DAC full scale. Enable the power amplifier protection block with the sticky
• attenStepSize: this parameter sets the attenuation step size error flags field bit set to 1.
when the Tx attenuation control (txAttenControlEnable) is
Parameters
enabled. The range is 0 to 127 with a resolution of 0.2 dB
per LSB. • * device: This is a pointer to the device data structure.
• avgDuration: this parameter sets the number of clock cycles
that the power amplifier protection power measurement
block uses to compute an estimate for the power in the
Tx1 or Tx2 datapath. The range is from 0 to 14. Each LSB
corresponds to 25 samples; 0 corresponds to 32 samples,
1 corresponds to 64 samples. The samples are clocked at
the Tx IQ data rate.

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UG-992 AD9371/AD9375 System Development User Guide
MYKONOS_getDacPower(…) Parameters
mykonosErr_t MYKONOS_getDacPower • *device: This is a pointer to the device data structure.
(mykonosDevice_t *device,
• channel: selects the Tx channel power measurement to
mykonosTxChannels_t channel, uint16_t
*channelPower) obtain. Only use Tx1 (1) or Tx2 (2) enumerations for
mykonosTxChannels_t.
This function obtains an estimate of the accumulated power of
• *channelPower: This is a pointer that stores the power of
the Tx channel over the sample duration provided in
the selected channel. Readback is provided as a 12-bit value.
MYKONOS_setupPaProtection(...). It uses the avgDuration
parameter provided in MYKONOS_setupPaProtection to set MYKONOS_getPaProtectErrorFlagStatus(…)
the number of samples to accumulate to obtain an estimate for a mykonosErr_t
Tx channel specified by the channel parameter. A 12-bit field MYKONOS_getPaProtectErrorFlagStatus
estimating the channel power is returned in the *channelPower (mykonosDevice_t *device, uint8_t
pointer. Use the following equation to calculate the dBFS value *errorFlagStatus)
of the reading: This function provides a readback of the power amplifier (PA)
txChannelPowerdBFS = 10 × log10(channelPower/4095) protection error flag status through the *errorFlagStatus pointer.

where: Preconditions
txChannelPowerdBFS is the channel power when converted into Enable the power amplifier protection block.
units of dBFS relative to the Tx DAC full scale.
Parameters
channelPower is the value of the pointer stored by this command.
For example, if channelPower is reading 409, the channel power • *device: This is a pointer to the device data structure.
in dBFS is −10 dBFS. • *errorFlagStatus: This is a pointer that stores the error flag
Preconditions status indicating which Tx channel error flags are set.

Enable the power amplifier protection block.

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AD9371/AD9375 System Development User Guide UG-992

REFERENCE CLOCK AND SYSREF CONNECTIONS

The external clock is used as the reference clock for the Rx PLL, DEV_CLK PHASE NOISE REQUIREMENTS
Tx PLL, SnRx PLL, and the clocking PLL circuits in the device. To prevent performance degradation, the DEV_CLK reference
To maintain the highest performance levels, a clean clock source must be a stable, low noise signal. Table 93 lists the required
is required. This external clock source must be input into the phase noise of the DEV_CLK signal to ensure device performance
DEV_CLK_IN+ and DEV_CLK_IN− pins. Within this for a 153.6 MHz input and RF frequencies as high as 6000 MHz.
documentation, DEV_CLK refers to the reference clock signal Similar phase noise requirements for a 122.88 MHz input are
supplied to the device, and DEV_CLK_IN refers to the differential displayed in Table 94.
pair input pins on the device.
Table 93. DEV_CLK Phase Noise Requirements,
CONNECTIONS FOR EXTERNAL CLOCK
153.6 MHz Reference
(DEV_CLK_IN)
Frequency Offset from Carrier Phase Noise Level (dBc/Hz)
The reference clock must be supplied as a differential signal
100 Hz −101
connected to E7 and E8. This connection must be terminated
1000 Hz −122
with a 100 Ω resister and be ac-coupled as shown in Figure 49.
10 kHz −132
The device input pins are biased to 618 mV. The inputs are high
100 kHz −134
impedance, with less than 1 pF and 20 kΩ each. The frequency
1 MHz −145
range of the DEV_CLK signal must be between 10 MHz and
10 MHz −155
320 MHz. The maximum voltage level for the DEV_CLK
signal is 2.0 V p-p differential, and the minimum input level is To scale the phase noise requirement for the DEV_CLK signal
300 mV p-p differential. to different frequencies using the following equation:
100nF
E7 NewDEV _CLK
DEV_CLK_IN+
Phase Noise Level  20  log (2)
153.6 MHz
100Ω
14652-148

100nF For example, for DEV_CLK = 122.88 MHz

E8
DEV_CLK_IN–

Figure 49. Reference Clock Input Connections

20 × log(122.88 MHz/153.6 MHz) = −193 dB

Printed circuit board (PCB) routing is made difficult by the Table 94. DEV_CLK Phase Noise Requirements,
location of the DEV_CLK_IN± balls: they are located in the 122.88 MHz Reference
middle of the ball grid array. To avoid potential coupling of the Frequency Offset from Carrier Phase Noise Level (dBc/Hz)
reference input clock to the RF signals, it is recommended to 100 Hz −103
place the termination resistor and ac coupling capacitors on the 1000 Hz −124
opposite side of the PCB from the device, and to use vias to 10 kHz −134
route the clock signals up to the device as close to the input balls 100 kHz −136
as possible to complete the connections. More information 1 MHz −147
regarding PCB routing can be found in the Printed Circuit Board 10 MHz −157
Layout Guidelines section.

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UG-992 AD9371/AD9375 System Development User Guide
SYSREF REQUIREMENTS is accomplished by driving multiple chips with the same
The device provides two balls for the SYSREF interface: SYSREF signal (see the Multichip Synchronization section).
SYSREF_IN+ (K3) and SYSREF_IN− (K4). The SYSREF interface This SYSREF input is by default a differential LVDS input. The
internally aligns the generated clocks. It also provides a mechanism device provides 100 Ω internal termination on the differential
for deterministic latency per the JESD204B standard. Figure 50 SYSREF input. This approach optimizes the termination by
outlines where each SYSREF input pulse is directed. inserting it at the end of the route. It also reduces the routing
The SYSREF input also provides multichip synchronization complexity by allowing the traces to be routed directly to the
(MCS) for systems with more than one device. Synchronization device without any additional external components.

BASEBAND
PROCESSOR
OR FPGA

SPI INTERFACE

AD9371 DIGITAL
DIVIDERS
AD9528 CLOCK SYNTHESIZER PLL
AFTER CLOCK
SYNTHESIZER
REFERENCE
REF_CLK REF_CLK CLOCK
GENERATION AND CLOCK SYNTHESIZER
DIVIDER Σ-∆ MODULATOR
DISTRIBUTION /K2 = 4, 2, 1 JESD204B
(TYPICALLY DISABLED) FRAMER/
DEFRAMER
1
1 2* 3 4 2*
MULTICHIP 4
SYSREF PULSE SYSREF SYNCRONIZATION (MCS)
GENERATION AND  CAPTURE
FF BLOCK 3
DISTRIBUTION

14652-149
*TYPICALLY NOT USED

Figure 50. Use of Each SYSREF Pulse

Rev. B | Page 114 of 360

AD9371/AD9375 System Development User Guide UG-992
Minimum Delay Requirements Between SYSREF Pulses Timing of SYSREF Compared to DEV_CLK
The first SYSREF pulse resets the device clock divider, which SYSREF can be either periodic signal, a one-shot (strobe type)
causes the clock phase-locked loop (PLL) to relock. There is a pulse, or a gapped periodic signal. Ensure that no runt pulses or
required wait period before any further SYSREF pulses are glitches result while turning the SYSREF signal on and off.
registered. The wait period is set to 1,024 phase frequency SYSREF is an active high signal that is sampled by the device
detector (PFD) reference clock periods. The PFD clock must clock. SYSREF is latched internally by DEV_CLK; therefore,
always be less than 80 MHz. The following conditions exist for strictly adhered to the setup and hold times specified in the data
each option: sheet. Figure 51 and Figure 52 illustrate the idea of negative
hold time due to the delay of the DEV_CLK signal vs. the
 If a device clock of 122.88 MHz or 245.76 MHz is used, it
SYSREF signal inside the device.
produces a PFD reference clock of 61.44 MHz, resulting in
a minimum wait of 16.7 μs after the first SYSREF pulse Figure 51 and Figure 52 illustrate the relationship between the
before the next SYSREF pulse is recognized. SYSREF signal and the DEV_CLK signal. In the end application,
 If a device clock of 153.6 MHz or 307.2 MHz is used, it ensure that the user generated SYSREF signal follows the
produces a PFD reference clock of 76.8 MHz, resulting in recommendations.
a minimum wait of 13.3 μs after the first SYSREF pulse, In cases where periodic or gapped periodic SYSREF signals are
before the next SYSREF pulse is recognized. used, the period must be an integer multiple of the local multiframe
counter (LMFC) period. The LMFC and frame clock within a
device must be phase aligned to the DEV_CLK sampling edge
upon which the sampled SYSREF value transitions from 0 to 1.
AT THE MYKONOS DEVICE PINS AT THE MYKONOS DIGITAL CORE
tS tS DEV_CLK DELAY
t′S t′S
tH tH IN REFERENCE TO SYSREF
t ′H t′H

DEV_CLK

SYSREF

14652-150
tH = –1.5ns t′H = –0.5ns
tS = +2.5ns CLK DELAY = 2ns t′S = +0.5ns
Figure 51. Timing Alignment of SYSFREF vs. DEV_CLK at the Device Pins

tS tS tS tS
tH tH tH tH

DEV_CLK

SYSREF

VALID SYSREF INVALID SYSREF

14652-151

tH = –1.5ns
tS = +2.5ns
Figure 52. SYSREF Setup and Hold Timing with Examples of SYSREF Pulse

Rev. B | Page 115 of 360

UG-992 AD9371/AD9375 System Development User Guide

SYNTHESIZER CONFIGURATION
The device contains three radio frequency (RF) phased- JESD204B interface rates typically require that the synthesizer
locked loop (PLL) synthesizers for Tx, Rx, and ORx/sniffer operate in integer mode. Profiles that are included in the
channel tuning. Figure 53 shows these synthesizers and their transceiver evaluation software (TES) configure the clock
interconnectivity with each of the RF signal paths. Each PLL synthesizer appropriately. Reconfiguration of the clock synthesizer
synthesizer employs a fractional–N architecture with a is typically not necessary after initialization. The most direct
completely integrated voltage controlled oscillator (VCO) and approach to the configuration is to follow the recommended
loop filter. No external devices are required to cover the entire programming sequence and use the provided application
frequency range of the device. This configuration allows the use programming interface (API) functions to set the clock
of any convenient reference frequency for operation on any synthesizer to the desired mode of operation.
channel with any sample rate. The fundamental frequency of A calibration PLL (CALPLL) synthesizer is integrated into the
the PLL ranges from 6 GHz to 12 GHz. The local oscillator (LO) device to generate the signals necessary to calibrate the device.
frequency is created by dividing down the PLL VCO frequency. The reference frequency for the CALPLL is scaled from the
The reference frequency for the PLL is scaled from the reference device clock applied to the DEV_CLK_IN± pins. The CALPLL
clock applied to the DEV_CLK_IN± pins. output signal is injected into the input of the Rx signal path.
The device also provides a clock synthesizer to generate all the This calibration is executed during the initialization sequence at
clocking signals necessary to run the device. The reference startup. There must be no signal present at the Rx input during
frequency for the PLL is scaled from the reference clock applied tone calibration time. Solely the internal ARM processor
to the chip DEV_CLK_IN± pins. Although it is a fractional–N controls the CALPLL. This procedure is fully autonomous, and
architecture, note that the signal sampling relationships to the there is no user access to control the CALPLL state.

TO CLK TO CAL
Rx SIGNAL CHAIN SYNTHESIZER SYNTHESIZER

CLK CLK
CLK SCALE SCALE
RX_EXTLO+ SCALE
LO
RX_EXTLO– GENERATOR

CLK DEV_CLK_IN+
SCALE
REFERENCE
Rx DISTRIBUTION
SYNTHESIZER DEV_CLK_IN–
CLK
SCALE

SnRx SIGNAL CHAIN

Tx SIGNAL CHAIN

TX_EXTLO+
LO LO
TX_EXTLO– GENERATOR GENERATOR
14652-047

Tx ORx
SYNTHESIZER SYNTHESIZER

Figure 53. Synthesizer Interconnection Block Diagram

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AD9371/AD9375 System Development User Guide UG-992
ZIN = 100Ω
CONNECTIONS FOR EXTERNAL LO 100pF
E12
TX_EXTLO+
The device provides the user with an option of using internal 50Ω
50Ω
phase-locked loops (PLLs) to generate local oscillator (LO) 100pF 50Ω
E11
TX_EXTLO–
frequencies or receiving the LO signals from two external LO
AD9371
sources. Unlike the internal synthesizers that always operate ZIN = 100Ω 100pF
B8
between 6 GHz to 12 GHz, regardless of the RF tune frequency, RX_EXTLO+
50Ω
when an external LO is used, the frequency applied must be 2× 50Ω
100pF 50Ω

14652-153
the desired RF tune frequency. The signal is divided internally B7
RX_EXTLO–
by 2 to generate the required LO quadrature relationship. The
Figure 54. TX_EXTLO and RX_EXTLO Inputs
range of the external LO signal can be as low as 600 MHz and as
high as 12 GHz, covering the RF tune frequency range from Higher external LO frequencies require higher input power.
300 MHz to 6 GHz. In general, higher input power produces better phase noise
The two separate differential external LO inputs follow: performance. To optimize system design, the minimum input
power that results in phase noise meeting requirements (with
 The external LO for the Rx signal chain uses the B7 some margin) must be used. If an on-board balun is used to
(RX_EXTLO−) and B8 (RX_EXTLO+) balls. connect a single-ended LO supply to the differential inputs,
 The external LO for the Tx signal chain use the E11 the loss of the balun must be taken into account when
(TX_EXTLO−) and E12 (TX_EXTLO+) balls. calculating input power. Table 95 describes the specifications
Both inputs present 100 Ω differential impedance. Differential for the RX_EXT_LO and TX_EXT_LO input pins. Note that
signals applied to the external LO inputs must be ac-coupled. operation is limited to LO frequencies lower than 4000 MHz.
Place a 50 Ω termination resistor on each input line as close as Higher frequencies require use of the internal LO generators.
possible to the external LO input balls. Figure 54 provides a high
level overview of the recommended configuration.

Table 95. Specifications for RF External LO Inputs (RX_EXT_LO and TX_EXT_LO)

Parameter Test Conditions/Comments Min Typ Max Unit
Input Frequency (fEXTLO) 600 8000 MHz
LO Frequency (fCHANNEL) 300 4000 MHz
Input Power 50 Ω matching at the source. Signal amplitude depends on the fEXTLO frequency. 0 3 6 dBm
Typical = 3 dBm for fEXTLO ≤ 2 GHz.

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UG-992 AD9371/AD9375 System Development User Guide
Performance Limitations The combination of these errors must not result in a LO
Local oscillator (LO) quadrature phase error can be caused by quadrature phase noise error greater than 1.5 ps. At 1.8 GHz,
phase imbalance in the external LO input differential signal; this equates to approximately 1° of phase noise. Ensure that the
therefore, it is important to design the input circuit carefully to external LO input signal has less than 10° of differential phase
avoid mismatch between the two inputs that make up the error, less than 1 dB of differential amplitude error, and a duty
differential pair for each external LO signal. Three main cycle between 49% and 51%.
parameters can affect LO phase noise when the external LO
input is used:
 Differential phase error (deviation from 180°)
 Differential amplitude error (deviation from equal
amplitudes on each input pin)
 Duty cycle error (deviation from 50%)

14652-048

Figure 55. Internal and External LO Configuration in the Transceiver Evaluation Software (TES)

Rev. B | Page 118 of 360

AD9371/AD9375 System Development User Guide UG-992
SOFTWARE CONFIGURATION Another user configurable option shown in Figure 53 is the
Device configuration is dependent on the user application selection of the local oscillator (LO) for the observation Rx
requirements. When using an external local oscillator (LO), use signal path. The user can select the desired LO source (SnRx,
the transceiver evaluation software (TES) to generate initial LO, or Tx LO) for ORx1 or ORx2 using the TES dropdown
values for application programming interface (API) structure menu, as shown in Figure 56.
members. The same operation can be performed using the API function
Figure 53 outlines a high level synthesizer block diagram, described in the following section.
including the option to provide external LOs for Rx and Tx
signal chains. To select an external LO for Rx or Tx RF signal
paths, a series of API commands must be executed before
initializing the device. Select the correct frequency settings by
using the following commands:
static mykonosRxSettings_t rxSettings =
uint8_t rxPllUseExternalLo /*
Internal LO = 0, external LO*2 = 1 */
uint64_t rxPllLoFrequency_Hz /*
Rx PLL LO Frequency (internal or external
LO/2) */

and

14652-049
static mykonosTxSettings_t txSettings =
uint8_t txPllUseExternalLo /*
Figure 56. LO Selection for Sniffer and ORx Path in the Transceiver Evaluation
Internal LO = 0, external LO*2 if =1 */ Software (TES)
uint64_t txPllLoFrequency_Hz /*
Tx PLL LO frequency (internal or external MYKONOS_setObsRxPathSource
LO/2) */ mykonosErr_t MYKONOS_setObsRxPathSource (
It is important to note that when an external LO is used, the mykonosDevice_t * device,
mykonosObsRxChannels_t obsRxCh )
value of the RF frequency must still be programmed for the
Tx and Rx channels (see the red box in Figure 55) and the When the ARM radio control is in ARM command mode, this
rxPllLoFrequency_Hz or rxPllLoFrequency_Hz structure function allows the user to selectively power up or power down
members. For more details regarding the initialization the desired ObsRx datapath.
procedure, refer to the System Initialization section. The value set in device → obsRx → obsRxChannel determines
Part of the initialization procedure includes setting up internal the mode of operation for the SnRx path. The user options are
clock generation. All internal clocks are generated based on the as follows:
selected profile; therefore, there is no need for reconfiguration of  OBS_RXOFF: The SnRx path is disabled.
the clock synthesizer after the device finishes the initialization  OBS_RX1_TXLO: The SnRx operates in observation mode
sequence. Initialization of the clock generation block (see Figure 53) on ORx1 with the Tx LO synthesizer.
is done by the API function described in the following section.  OBS_RX2_TXLO: The SnRx operates in observation mode
MYKONOS_initDigitalClocks on ORx2 with the Tx local oscillator (LO) synthesizer.
mykonosErr_t MYKONOS_initDigitalClocks (  OBS_INTERNALCALS: This enables scheduled Tx
mykonosDevice_t * device ) calibrations while using SnRx path. The enableTrackingCals
This function updates the clock synthesizer and loop filter settings function must be called in the radio off state. It sets the
based on a voltage controlled oscillator (VCO) frequency calibration mask, which the scheduler uses later to schedule
lookup table (LUT). The VCO frequency break points for the the desired calibrations. This command is issued in radio off.
synthesizer LUT can be found in the vcoFreqArrayHz array. After the device moves to the radio on state, the internal
This function has no parameters, and there is no need for scheduler uses the enabled calibration mask to schedule
interaction with it from the user. This function is automatically calibrations whenever possible, based on the state of the
called inside the main initialization application programming transceiver. The Tx calibrations are not be scheduled until
interface (API) function. OBS_INTERNALCALS is selected, and the Tx calibrations
are enabled in the calibration mask.
mykonosErr_t
MYKONOS_initialize(mykonosDevice_t
*device)

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UG-992 AD9371/AD9375 System Development User Guide
• OBS_SNIFFER: The SnRx operates in sniffer mode with MYKONOS_getRfPllFrequency
the latest selected sniffer input (for hardware pin control mykonosErr_t MYKONOS_getRfPllFrequency (
operation). In pin mode, the GPIO pins designated for mykonosDevice_t * device,
ORX_MODE select sniffer mode. Then, the MYKONOS_ mykonosRfPllName_t pllName,uint64_t
setSnifferChannel function chooses the channel. rfPllLoFrequency_Hz )
• OBS_RX1_SNIFFERLO: The SnRx operates in observation This function obtains the frequency of the radio frequency (RF)
mode on ORx1 with the sniffer LO synthesizer. phase-locked loop (PLL). It can obtain the frequency for the
• OBS_RX2_SNIFFERLO: The SnRx operates in observation Rx PLL, Tx PLL, sniffer PLL, and clock PLL.
mode on ORx2 with the sniffer LO synthesizer. This function has two parameters:
• OBS_SNIFFER_A: The SnRx operates in sniffer mode on
• pllName: This parameter designates the name of the PLL to
SnRxA with the sniffer LO synthesizer.
configure, which includes the following.
• OBS_SNIFFER_B: The SnRx operates in sniffer mode on
• RF_PLL: reads back the Rx LO operating frequency.
SnRxB with the sniffer LO synthesizer.
• TX_PLL: reads back the Tx LO operating frequency.
• OBS_SNIFFER_C: The SnRx operates in sniffer mode on
• SNIFFER_PLL: reads back the sniffer LO operating
SnRxC with the sniffer LO synthesizer.
frequency.
Note that if this function is called when the ARM is expecting • CLKPLL: reads back the clock LO operating
the GPIO pin control of the ORx path source, an error returns. frequency.
To change the frequency of operation of each radio frequency • rfPllLoFrequency_Hz: This parameter is the LO frequency
local oscillator, use the application programming interface currently set for the specified PLL.
(API) function described in the following section.
The application programming interface (API) function described
MYKONOS_setRfPllFrequency in the following section checks if the lock detector bit for a
mykonosErr_t MYKONOS_setRfPllFrequency ( particular PLL indicates that the corresponding synthesizer has
mykonosDevice_t * device, achieved lock.
mykonosRfPllName_t pllName,uint64_t
rfPllLoFrequency_Hz ) MYKONOS_checkPllsLockStatus
This function sets the radio frequency (RF) phase-locked loop mykonosErr_t MYKONOS_checkPllsLockStatus (
mykonosDevice_t * device, uint8_t *
(PLL) local oscillator (LO) frequency (RF carrier frequency). pllLockStatus )
This function has two parameters:
This function updates the pllLockStatus pointer with a lock
• pllName: This parameter designates the name of the PLL to status per phase-locked loop (PLL) according to the following
configure, which includes the following: assignments:
• RX_PLL changes the operating frequency of the Rx LO.
• pllLockStatus[0]: clock PLL locked
• TX_PLL changes the operating frequency of the Tx LO.
• pllLockStatus[1]: Rx PLL locked
• SNIFFER_PLL changes the operating frequency of the
• pllLockStatus[2]: Tx PLL locked
sniffer LO.
• pllLockStatus[3]: sniffer PLL locked
• rfPllLoFrequency_Hz: This parameter designates the • pllLockStatus[4]: calibration PLL locked
desired LO frequency in Hz.
The following is an example of how MYKONOS_
To read back the value programmed for a particular PLL LO
setRfPllFrequency and MYKONOS_checkPllsLockStatus can
frequency, use the application programming interface (API)
program the radio frequency (RF) PLL frequencies and check
function described in the following section.
the PLL lock status bits. More information can be found in the
System Initialization section.

Rev. B | Page 120 of 360

AD9371/AD9375 System Development User Guide UG-992

/*******************************/
/**** Set RF PLL Frequencies ***/
/*******************************/
mykError = MYKONOS_setRfPllFrequency(&mykDevice, RX_PLL, mykDevice.rx->rxPllLoFrequency_Hz);
mykError = MYKONOS_setRfPllFrequency(&mykDevice, TX_PLL, mykDevice.tx->txPllLoFrequency_Hz);
mykError = MYKONOS_setRfPllFrequency(&mykDevice, SNIFFER_PLL, mykDevice.obsRx-
>snifferPllLoFrequency_Hz);

/*** < wait 200ms for PLLs to lock - user code here > ***/

mykError = MYKONOS_checkPllsLockStatus(&mykDevice, &pllLockStatus);

if ((pllLockStatus & 0x0F) == 0x0F)
{
/*** < All PLLs locked - user code here > ***/
}
else
{
/*** < PLLs not locked - ensure lock before proceeding - user code here > ***/
}

Rev. B | Page 121 of 360

UG-992 AD9371/AD9375 System Development User Guide
if ((pllLockStatus & 0x0F) == 0x07)
RF PLL FREQUENCY CHANGE PROCEDURE {
Small Frequency Step Procedure /*** < Info: Clock, Rx and Tx PLLs
locked > ***/
Use the following procedure when a radio frequency (RF) phased-
}
lock loop (PLL) change is required with the following conditions: else
• A desire to change the Rx, Tx, and ORx frequencies {
/*** < Info: Clock, Rx and Tx PLLs
• The frequency step change is less than 100 MHz. not locked > ***/
• The frequency step does not cross the divide by 2 /*** < Action: Ensure lock before
boundaries outlined in Table 96. proceeding - User code here > ***/
}
1. Move the device into the radio off state by executing the
3. Reset the external channel by executing the following
following command:
command:
if ((mykError =
MYKONOS_radioOff(&mykDevice)) != If((mykError =
MYKONOS_ERR_OK) MYKONOS_resetExtTxLolChannel(&mykDevice,
{ TX1_TX2)) != MYKONOS_ERR_OK) ; //where
/*** < Info: errorString will contain log TX1_TX2 is part of the enum
error string in order to debug failure > mykonosTxChannels_t
***/ {
errorString = getthe /*** < Info: errorString will contain log
AD9371ErrorMessage(mykError); error string in order to debug failure >
} ***/
errorString = getthe
2. Program the new local oscillator (LO) frequency. For AD9371ErrorMessage(mykError);
example, set the Rx LO to 2550 MHz and the Tx LO to }
2500 MHz by executing the following commands: 4. Move the device back into the radio on state by executing
if ((mykError = the following command:
MYKONOS_setRfPllFrequency(&mykDevice,
if ((mykError =
RX_PLL, 2550000000)) != MYKONOS_ERR_OK)
MYKONOS_radioOn(&mykDevice)) !=
{
MYKONOS_ERR_OK)
/*** < Info: errorString will
{
contain log error string in order to
/*** < Info: errorString will contain log
debug failure > ***/
error string in order to debug failure >
errorString = getthe
***/
AD9371ErrorMessage(mykError);
errorString = getthe
}
AD9371ErrorMessage(mykError);
}
if ((mykError =
MYKONOS_setRfPllFrequency(&mykDevice, 5. Some tracking calibrations are active only when the ORx
TX_PLL, 2500000000)) != MYKONOS_ERR_OK) path is set to the internal calibrations input. The user can
{ reenable tracking calibrations by selecting the internal
/*** < Info: errorString will
contain log error string in order to calibrations ORx path by executing the following command
debug failure > ***/ when using application programming interface (API)
errorString = getthe commands to control the ORx input:
AD9371ErrorMessage(mykError);
} if ((mykError =
MYKONOS_setObsRxPathSource(&mykDevice,
/*** < Action: wait 200ms for PLLs OBS_INTERNALCALS)) != MYKONOS_ERR_OK)
to lock > ***/ {
/*** < Info: errorString will
if ((mykError = contain log error string in order to
MYKONOS_checkPllsLockStatus(&mykDevice, debug failure > ***/
&pllLockStatus)) != MYKONOS_ERR_OK) errorString = getthe
{ AD9371ErrorMessage(mykError);
/*** < Info: errorString will }
contain log error string in order to If the ORx input is controlled by the GPIO interface, the
debug failure > ***/ baseband processor (BBP) must configure its pins to select
errorString = getthe
INTERNALCALS. Refer to the ARM GPIOs section and the
AD9371ErrorMessage(mykError);
} Quadrature Error Correction, Calibration, and ARM
Configuration section for more information.
Rev. B | Page 122 of 360
AD9371/AD9375 System Development User Guide UG-992
Large Frequency Step Procedure if ((pllLockStatus & 0x0F) == 0x07)
{
Use the following procedure if a radio frequency (RF) phased- /*** < Info: Clock, Rx and Tx PLLs
lock loop (PLL) change is required with the following conditions: locked > ***/
}
• A desire to change the Rx, Tx, and ORx frequencies.
else
• The frequency step change is more than 100 MHz. {
• The frequency step does cross the divide by 2 boundaries /*** < Info: Clock, Rx and Tx PLLs
outlined in Table 96. not locked > ***/
/*** < Action: Ensure lock before
Use the following procedure: proceeding - User code here > ***/
}
1. Move the device into the radio off state by executing the
following command: 3. Rerun the initialization calibrations by executing the
following set of commands:
if ((mykError =
MYKONOS_radioOff(&mykDevice)) != uint32_t initCalMask = TX_QEC_INIT |
MYKONOS_ERR_OK) LOOPBACK_RX_LO_DELAY |
{ LOOPBACK_RX_RX_QEC_INIT |
/*** < Info: errorString will RX_LO_DELAY | RX_QEC_INIT;
contain log error string in order to
debug failure > ***/ if ((mykError =
errorString = getthe MYKONOS_runInitCals(&mykDevice,
AD9371ErrorMessage(mykError); initCalMask)) != MYKONOS_ERR_OK)
} {
/*** < Info: errorString
2. Program the new local oscillator (LO) frequency. For will contain log error string in order
example, set the Rx LO to 2550 MHz and the Tx LO to to debug failure > ***/
2500 MHz by executing the following commands: errorString = getthe
AD9371ErrorMessage(mykError);
if ((mykError = }
MYKONOS_setRfPllFrequency(&mykDevice,
RX_PLL, 2550000000)) != MYKONOS_ERR_OK) if ((mykError =
{ MYKONOS_waitInitCals(&mykDevice,
/*** < Info: errorString will 60000, &errorFlag, &errorCode)) !=
contain log error string in order to MYKONOS_ERR_OK)
debug failure > ***/ {
errorString = getthe /*** < Info: errorString
AD9371ErrorMessage(mykError); will contain log error string in order
} to debug failure > ***/
errorString = getthe
if ((mykError = AD9371ErrorMessage(mykError);
MYKONOS_setRfPllFrequency(&mykDevice, }
TX_PLL, 2500000000)) != MYKONOS_ERR_OK)
{ if ((errorFlag != 0) ||
/*** < Info: errorString will (errorCode != 0))
contain log error string in order to {
debug failure > ***/ if((mykError =
errorString = getthe MYKONOS_getInitCalStatus(&mykDevice,
AD9371ErrorMessage(mykError); &initCalStatus)) != MYKONOS_ERR_OK)
} {
/*** < Info:
/*** < Action: wait 200ms for PLLs errorString will contain log error
to lock > ***/ string in order to debug failure >
***/
if ((mykError = errorString = getthe
MYKONOS_checkPllsLockStatus(&mykDevice, AD9371ErrorMessage(mykError);
&pllLockStatus)) != MYKONOS_ERR_OK) }
{
/*** < Info: errorString will /*** < Info: abort init
contain log error string in order to cals > ***/
debug failure > ***/ if((mykError =
errorString = getthe MYKONOS_abortInitCals(&mykDevice,
AD9371ErrorMessage(mykError); &initCalsCompleted)) !=
} MYKONOS_ERR_OK)
{
Rev. B | Page 123 of 360
UG-992 AD9371/AD9375 System Development User Guide
/*** < Info: 5. Some tracking calibrations are active only when the ORx
errorString will contain log error path is set to the internal calibrations input. The user can
string in order to debug failure >
reenable tracking calibrations by selecting internal calibrations
***/
errorString = getthe ORx path by executing the following command when using
AD9371ErrorMessage(mykError); application programming interface (API) commands to
} control the ORx input:
if(initCalsCompleted)
{ if ((mykError =
/*** < Info: which MYKONOS_setObsRxPathSource(&mykDevice,
calls had completed, per the mask > OBS_INTERNALCALS)) != MYKONOS_ERR_OK)
***/ {
} /*** < Info: errorString will
contain log error string in order to
if((mykError = debug failure > ***/
MYKONOS_readArmCmdStatus(&mykDevice, errorString = getthe
&errorWord, &statusWord)) != AD9371ErrorMessage(mykError);
MYKONOS_ERR_OK) }
{ If the ORx input is controlled by the GPIO interface, the
/*** < Info: baseband processor (BBP) must configure its pins to select
errorString will contain log error
string in order to debug failure > INTERNALCALS. Refer to the ARM GPIOs section and the
***/ Quadrature Error Correction, Calibration, and ARM
errorString = getthe Configuration section for more information.
AD9371ErrorMessage(mykError);
} Sniffer Receiver PLL Procedure
The sniffer phased-lock loop (PLL) can also be configured
if((mykError = when in the radio off state or when in the radio on state if the
MYKONOS_readArmCmdStatusByte(&mykDevic
sniffer PLL is not in use. This is the case when the obsRxCh
e, 2, &status)) != MYKONOS_ERR_OK)
{ parameter of the MYKONOS_setObsRxPathSource() function
/*** < Info: is set to OBS_RXOFF, OBS_RX1_TXLO, or OBS_RX2_TXLO.
errorString will contain log error To change the sniffer frequency, use the following procedure:
string in order to debug why failed >
***/ 1. Move the device into the radio off state by executing the
errorString = getthe following command:
AD9371ErrorMessage(mykError);
if ((mykError =
}
MYKONOS_radioOff(&mykDevice)) !=
if(status!=0)
MYKONOS_ERR_OK)
{
{
/*** < Info: Arm
/*** < Info: errorString will
Mailbox Status Error errorWord > ***/
contain log error string in order to
/*** < Info: Pending
debug failure > ***/
Flag per opcode statusWord, this
errorString = getthe
follows the mask > ***/
AD9371ErrorMessage(mykError);
}
}
}
else 2. Program the new sniffer local oscillator (LO )frequency.
{ For example, set the sniffer LO to 2600 MHz by executing
/*** < Info: Calibrations the following commands:
completed successfully > ***/
} if ((mykError =
MYKONOS_setRfPllFrequency(&mykDevice,
4. Move the device back into the radio on state by executing
SNIFFER_PLL, 2600000000)) !=
the following command: MYKONOS_ERR_OK)
if ((mykError = {
MYKONOS_radioOn(&mykDevice)) != /*** < Info: errorString will
MYKONOS_ERR_OK) contain log error string in order to
{ debug failure > ***/
/*** < Info: errorString will errorString = getthe
contain log error string in order to AD9371ErrorMessage(mykError);
debug failure > ***/ }
errorString = getthe
AD9371ErrorMessage(mykError);
} if ((pllLockStatus & 0x0F) == 0x08)
Rev. B | Page 124 of 360
AD9371/AD9375 System Development User Guide UG-992
{ /*** < Info: errorString will
/*** < Info: Sniffer PLL locked contain log error string in order to
> ***/ debug failure > ***/
} errorString = getthe
else AD9371ErrorMessage(mykError);
{ }
/*** < Info: Sniffer PLL not
locked > ***/ Or
/*** < Action: Ensure lock
before proceeding - User code here > ***/ if ((mykError =
} MYKONOS_setObsRxPathSource(&mykDevice,
RX2_TXLO)) != MYKONOS_ERR_OK)
3. Move the device back into the radio on state by executing
{
the following command: /*** < Info: errorString will
if ((mykError = contain log error string in order to
MYKONOS_radioOn(&mykDevice)) != debug failure > ***/
MYKONOS_ERR_OK) errorString = getthe
{ AD9371ErrorMessage(mykError);
/*** < Info: errorString will }
contain log error string in order to 5. Program the new sniffer local oscillator (LO) frequency.
debug failure > ***/ For example, set the sniffer LO to 2600 MHz by executing
errorString = getthe
the following commands:
AD9371ErrorMessage(mykError);
} if ((mykError =
MYKONOS_setRfPllFrequency(&mykDevice,
Alternatively, do the following: SNIFFER_PLL, mykDevice.obsRx-
>snifferPllLoFrequency_Hz)) !=
4. While the device is operating in radio on mode, change the
MYKONOS_ERR_OK)
ORx path LO to Tx LO, or disable it by executing any of {
following commands listed: /*** < Info: errorString will
contain log error string in order to
if ((mykError =
debug failure > ***/
MYKONOS_setObsRxPathSource(&mykDevice,
errorString = getthe
OBS_RXOFF)) != MYKONOS_ERR_OK)
AD9371ErrorMessage(mykError);
{
}
/*** < Info: errorString will
if ((pllLockStatus & 0x0F) == 0x08)
contain log error string in order to
{
debug failure > ***/
/*** < Info: Sniffer PLL locked
errorString = getthe
> ***/
AD9371ErrorMessage(mykError);
}
}
else
{
or
/*** < Info: Sniffer PLL not
locked > ***/
if ((mykError =
/*** < Action: Ensure lock
MYKONOS_setObsRxPathSource(&mykDevice,
before proceeding - User code here > ***/
RX1_TXLO)) != MYKONOS_ERR_OK)
}
{

Table 96. Divide by 2 Boundaries vs. Desired LO Frequency

LO Frequency Limits (MHz)
Lower Limit Upper Limit Lower Limit Upper Limit Lower Limit Upper Limit Lower Limit Upper Limit
400 750 750 1500 1500 3000 3000 6000
Divide by 16 8 4 2

Rev. B | Page 125 of 360

UG-992 AD9371/AD9375 System Development User Guide
RF PLL RESOLUTION LIMITATIONS Example 2
The MYKONOS_setRfPllFrequency command and the The DEV_CLK_IN± input is 245.76 MHz. The user wants to
MYKONOS_getRfPllFrequency command both operate tune the Tx LO to a frequency equal to 5,000,000,002 Hz. The
with 1 Hz resolution. The real frequency to which the Rx PLL, LO step size for this range is 3.663003663 Hz. The count number
Tx PLL, and SnRx PLL are tuned can vary by a small amount for the code required to obtain this frequency is as follows:
depending on the region of operation. Table 97 outlines the Rx, Count = (5000000002/3.663003663) = 1365000000.5473 →
Tx, and SnRx PLL frequency step variations vs. the operating band
round to 1365000001
LO frequency. Note that the upper limit is noninclusive; if at the
limit, use the next step size where the limit is lower. Actual Tx LO Frequency = (1365000001) × (3.663003663) =
5000000003.658 Hz
See the following examples to use Table 97 to determine the
correct local oscillator (LO) frequency setting. Example 3
Example 1 The DEV_CLK_IN± input is 245.76 MHz. The user wants to
tune the Tx LO to a frequency equal to 400,000,001 Hz. The LO
The DEV_CLK_IN± input is 153.6 MHz. The user wants to
step size for this range is 0.457875458 Hz. The count number
tune the Tx LO to a frequency equal to 3,600,000,002 Hz. The
for the code required to obtain this frequency is as follows:
local oscillator (LO) step size for this range is 4.578754579 Hz. The
count number for the code required to obtain this frequency is Count = (400000001/0.457875458) = 873600002.184 →
as follows: round to 873 600 002
Count = (3600000002/4.578754579) = 786240000.395 → Actual Tx LO Frequency = (873600002) × (0.457875458) =
round to 786,240,000 400000000.9 Hz.
Actual Tx LO Frequency = (786240000) × (4.578754579) =
3600000000.2 Hz

Table 97. LO Steps Size vs. Desired LO Frequencies

Desired LO Frequency Ranges (MHz)
Lower Upper Lower Upper Lower Upper Lower Upper
Limit Limit Limit Limit Limit Limit Limit Limit
DEV_CLK_IN± (MHz) 400 750 750 1500 1500 3000 3000 6000
LO Step 153.6 0.572344322 1.144688645 2.289377289 4.578754579
Size (Hz) 307.2
122.88 0.457875458 0.9157510916 1.831501832 3.663003663
245.76

Rev. B | Page 126 of 360

AD9371/AD9375 System Development User Guide UG-992

GAIN CONTROL
The device main receivers (Rx1 and Rx2) and sniffer receivers into the configurable settings of the AGC engine. Following the
(SnRxA, SnRxB, and SnRxC) feature automatic and manual receiver gain control programming descriptions, the remaining
gain control modes that provide flexible gain control in a wide sections examine the gain compensation methods available in
array of applications. The observation receivers (ORx1 and the device (slicer/floating point formatter). Details of the API
ORx2) feature manual gain control (MGC) only. Automatic commands and data structures are provided throughout this
gain control (AGC) allows the receivers to autonomously adjust section.
the receiver gain depending on variations of the input signal,
VARIABLE GAIN ELEMENTS IN THE RECEIVER
such as the onset of a strong interferer overloading the receiver
DATAPATHS
datapath. All the receivers are also capable of operating in MGC
mode where changes in gain are initiated by the baseband Gain Control Block Diagram Overview
processor (BBP) over the SPI or the GPIO control mode. The The receivers have several variable gain elements within their
gain control blocks are configured by the application programming datapaths. For the Rx and ORx datapaths, the variable gain
interface (API) data structures, and several API commands exist stages include an internal RF attenuator, an (optional) external
to allow user interaction with the gain control mechanisms. RF attenuator, and a digital gain/attenuation block. The external
attenuator is an optional stage outside of the device that can be
This section begins by explaining the variable gain elements in
controlled by using the GPIO pins. An example of an external
the receiver datapaths, the structure of the gain tables, and how
attenuator is a digital step attenuator (DSA). The datapath for
to develop and program custom gain tables. This information is
the Rx channel is shown in Figure 57.
followed by a description of the AGC peak detectors, overload
detectors, and power measurement detectors to provide insight
Rx DATAPATH 3-PIN CONTROL
TO BBP

EXTERNAL INTERNAL
ATTENUATION ATTENUATION DEC5
(OPTIONAL)

ANALOG DIGITAL DIG DC SLICER/ TO DIGITAL

TIA PEAK ADC RHB3 RHB2 RHB1 RFIR GAIN/ GAIN OFFSET FLOATING BASEBAND
DETECTOR ATTEN COMP CORR POINT INTERFACE

HB2 DATAPATH OVERLOAD

APD DATAPATH OVERLOAD

HB2 POWER
MEASUREMENT DATA CLOCK AT RECEIVER
I/Q DATA RATE
RFIR POWER MEASUREMENT
BBDC2 POWER MEASUREMENT
GAIN CONTROL BLOCK
(AGC OR MGC)

INTERNAL
ATTENUATION WORD[5:0] DIGITAL GAIN/ATTENUATION SELECT[1],
DIGITAL GAIN/ATTENUATION WORD[6:0]
EXTERNAL ATTENUATIONWORD[3:0]

14652-050
Figure 57. Rx Datapath, Highlighting the Gain Control Block and the Variable Gain Elements (Not the Complete Datapath)

Rev. B | Page 127 of 360

UG-992 AD9371/AD9375 System Development User Guide
3-PIN CONTROL
TO BBP
OTHER ORx CHANNELS
(ORx1, ORx2, INTERNAL CALS)
SNRXA DATAPATH DEC5

INTERNAL ORx ANALOG DIGITAL DIG DC SLICER/ TO DIGITAL

ATTENUATION MUX TIA PEAK ADC RHB3 RHB2 RHB1 RFIR GAIN/ GAIN OFFSET FLOATING BASEBAND
SWITCH DETECTOR ATTEN COMP CORR POINT INTERFACE
LNA

HB2 DATA PATH OVERLOAD

APD DATAPATH OVERLOAD
HB2 POWER
MEASUREMENT DATA CLOCK AT RECEIVER
I/Q DATA RATE
RFIR POWER MEASUREMENT
BBDC2 POWER MEASUREMENT
GAIN CONTROL BLOCK
(AGC OR MGC)

INTERNAL ATTENUATION WORD [4:0] DIGITAL GAIN/ATTENUATION SELECT[1],

DIGITAL GAIN/ATTENUATION WORD [6:0]

14652-051
LNA BYPASS ENABLE

Figure 58. SNRXA Datapath, Highlighting the Gain Control Block and the Variable Gain Elements (Not the Complete Datapath)

The SnRx internal attenuator is similar to the ORx and Rx internal

The variable gain elements (the external attenuator control,
attenuators. However, the valid range of internal attenuator index
internal attenuator, and digital gain/attenuator) in the Rx datapath
values extends from 0 to 19 (5-bit control) on the SnRx. The
are also present in the ORx datapath. However, AGC is not
maximum gain condition for the internal attenuator in the SnRx is
supported on the ORx channels.
met when the internal attenuator word is set to 0.
The variable gain elements in the SnRx datapath are similar to
External Attenuator
those of the Rx/ORx paths, excluding the low noise amplifier
(LNA) at the front end of each sniffer channel. The LNA can be The device can control an external DSA with the GPIO pins. A
bypassed to reduce the front-end gain, if desired. Other variable 4-bit word set in the second column of the gain table controls
gain elements in the SnRx datapath include the internal attenuator an external attenuator. If an external attenuator is not used, zeros
and the digital gain and attenuation stage. There is no external may be set in the external attenuator column of the gain table.
attenuator control for the SnRx input. The 4-bit external attenuator control word is output on the
The datapath for the SNRXA input is shown in Figure 58. 3.3 V GPIO pins. Rx1 uses GPIO_3P3_3 to GPIO_3P3_0 and
Rx2 uses GPIO_3P3_7 to GPIO_3P3_4. The ORx channels
Note that the ORx1, ORx2, SNRXA, SNRXB, SNRXC, and
use GPIO_3P3_11 to GPIO_3P3_7. The external attenuator
internal loopback (OBS_INTERNALCALS) paths share a
requires the 3.3 V GPIO source control to be set to the
common baseband datapath. The mixer and internal attenuator
GPIO3V3_EXTATTEN_LUT_MODE parameter and that
for SNRXA, SNRXB, and SNRXC are shared but have separate
the 3.3 V GPIO pins are set to output mode.
front-end LNAs.
External attenuator control is available on the Rx and ORx
Internal Attenuator
ports only.
The ORx and Rx internal attenuators each have a 6-bit control
Digital Gain/Attenuation
word in the first column of the gain table (see Table 98 for the
gain table format). The internal attenuator has 64 attenuation The digital gain/attenuation block allows finer resolution gain
settings in the ORx and Rx datapaths. The valid range of or attenuation adjustments than the internal RF attenuator,
internal attenuator index values is 0 to 63. The amount of resulting in a finer level of receiver datapath attenuation or gain
attenuation provided by the internal attenuator depends on the control than the internal attenuator word, which attempts to
value set in the internal attenuator column of the gain table. compensate for unequal analog gain steps.
The maximum gain condition for the internal attenuator is met The digital gain/attenuation block acts as an attenuator if the
when the internal attenuator word is set to 0. digital attenuation enable holds a 1. The digital gain/attenuation
Increasing values of the attenuator corresponds to an increase of word corresponds to 0.05 dB/LSB of digital attenuation in
attenuation. Equation 3 relates the 6-bit internal attenuator attenuation mode.
word to the internal attenuator attenuation in the ORx and Rx The digital gain/attenuation block provides digital gain if the
channels. digital attenuation enable holds 0. The digital gain/attenuation
Attenuation = 20log((64 − N)/64) (3) word corresponds to 0.25 dB/LSB of digital gain in gain mode.
where N is a 6-bit value.

Rev. B | Page 128 of 360

AD9371/AD9375 System Development User Guide UG-992
LNA Bypass Enable baseband datapath; only one ORx front end can connect to the
The SnRx channel features an integrated LNA at its input. The common baseband at any time. The gain index set or readback
SnRx features an LNA bypass mode. The LNA bypass is enabled for the ORx, therefore, applies only to the selected input. The
for a particular gain index if the second column of the a SnRx ORx gain table supports up to 47 gain index rows. The SnRx
gain table row holds a 1. LNA bypass is disabled when the gain table supports up to 127 gain index rows.
second column of the selected SnRx gain table row holds a 0. Rx and ORx Gain Table
LNAs are not present on the ORx and Rx channels. The format of the columns in the Rx and ORx gain table rows
GAIN TABLE FORMAT are as follows:
The device gain control block, in AGC or MGC, points to a gain • Internal attenuator word
index row in the receiver gain table and programs settings for • External attenuator word
the variable gain elements in the receiver datapath. Separate • Digital gain/attenuation word
gain tables can be implemented for the Rx1, Rx2, ORx, and • Digital attenuation enable
SnRx channels.
An example of the gain table structure is provided in Table 98
The default gain tables can be found in the mykonos_user.c file.
for the Rx gain table. Because the Rx and ORx datapaths have
The mykonos_user.c and mykonos_user.h files can be customized
the same variable gain elements, they have the same gain table
to modify, add, or delete the default gain table settings. Consult
column format.
Analog Devices applications engineering prior to changing the
gain tables. The first row of all gain tables corresponds to Gain Index 255
and the successive rows correspond to Gain Index 254, Gain
The Rx1 and Rx2 channels can operate simultaneously. Rx1 and
Index 253, and so on. In the default gain tables, the first gain
Rx2 may use separate gain tables and point to different gain
index in the table, Gain Index 255, is the maximum gain condition.
index values within those tables. In the default gain tables, Rx1
The first column in Table 98 indicates the gain index. The two
and Rx2 use the same gain table. The Rx1 and Rx2 gain tables
right most columns provide information regarding the attenuation
support up to 255 gain index rows.
level relative to maximum gain condition (defined in the default
The observation receiver system (ORx, including the ORx1, tables as Gain Index 255) and the attenuation level relative to
ORx2, SNRXA, SNRXB, and SNRXC receivers) uses a common the previous gain index.
Table 98. Sample Elements From the Default Rx Gain Table
Gain Digital Attenuation in dB Difference
Table Internal External Digital Gain/ Attenuation (Relative to (dB) (Step
Index Attenuator[5:0] 1 Attenuator[3:0]1 Attenuation[6:0]1 Enable1 Maximum Gain) Size = 1)
255 0 0 0 0 0.00 Not applicable
254 3 0 2 1 −0.52 0.52
253 6 0 3 1 −1.01 0.49
252 10 0 0 0 −1.47 0.47
1
Only the elements shown in these columns are programmed to the device registers.

The following example demonstrates the calculations involved in Gain Table Index 253:
Atten(GainIndex) = AIntAtten(IntAtten[5:0]) + AextAtten(ExtAtten[3:0]) + AdigAttenGain(digAttenEn, digGainAtten[6:0])
Atten(253) = AIntAtten(IntAtten[5:0]) + AdigAttenGain(1, 3)
Atten(253) = 20log10((64 − 6)/64) + AdigAttenGain(1, 3)
Atten(253) = −0.855 + (−1) × (0.05)
Atten(253) = −0.855 – 0.15 = −1.01 dB

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UG-992 AD9371/AD9375 System Development User Guide
The following code excerpt from mykonos_user.c shows the implementation of the Rx gain table:
/**
* \file mykonos_user.c
* \brief Contains the AD9371 default gain table values for Rx, ObsRx, and SnRx
*/

#include <stdint.h>
#include "t_mykonos.h"
#include "mykonos_user.h"

/**
* \brief Default Rx gain table settings
*/
uint8_t RxGainTable [61][4] =
{
/* Order: {FE table, External Ctl, Digital Gain/Atten, Enable Atten} */
{0, 0, 0, 0}, /* Gain index 255 */
{3, 0, 2, 1}, /* Gain index 254 */
{6, 0, 3, 1}, /* Gain index 253 */
{10, 0, 0, 0}, /* Gain index 252 */
{13, 0, 1, 1}, /* Gain index 251 */
{16, 0, 0, 0}, /* Gain index 250 */
…
For example, when the device sets the Rx1 gain index to gain index of 254, the values in the row corresponding to Gain Index 254 are
programmed into the device registers corresponding the four columns within that row. For the default Rx gain tables, this corresponds to
a 0.5 dB decrease in receiver gain compared to the gain condition in Gain Index 255 (maximum gain).

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AD9371/AD9375 System Development User Guide UG-992
Table 99. Sample Rows from the Default SnRx Gain Table
Attenuation in dB
Gain Table Internal LNA Digital Gain/ Digital Attenuation (Relative to Difference (dB)
Index Attenuator[4:0] 1 Bypass1 Attenuation [6:0]1 Enable1 Maximum Gain) (Step Size = 1)
255 0 0 0 0 0 Not applicable
254 1 0 7 1 −0.99 0.99
253 3 0 1 0 −1.97 0.98
252 3 0 15 1 −2.97 1.00
1
Only the elements shown in these columns are programmed to the device registers.

SnRx Gain Table There are two ways to change the default gain tables:
The format of the columns in the SnRx gain table rows are as 1. Modify the mykonos_user.c and mykonos_user.h files with
follows: valid settings and gain tables. Note that gain tables are
• Internal attenuator word programmed to device registers when the MYKONOS_
initArm(…) command is called in the initialization
• LNA bypass enable
sequence.
• Digital gain/attenuation word
2. Perform gain table programming during or after the
• Digital attenuation enable
initialization sequence provided in the headless.c file.
A different gain table column format is used in the SnRx gain After verifying the ARM is loaded properly (executing
table because the variable gain elements are different in the MYKONOS_verifyArmChecksum(…) without returning
SnRx datapath relative to the Rx/ORx datapath. The SnRx gain an error), custom gain tables can be written by using the
table includes a column representing the LNA bypass bit. LNA following application programming interface (API)
bypass is activated when these bits are equal to 1. The SnRx gain function:
table does not allow external attenuator control. When not mykonosErr_t
using the LNA at all during SnRx operation, set the LNA bypass MYKONOS_programRxGainTable(mykonosDevi
column to 1 for all rows. ce_t* device, uint8_t* gainTablePtr,
uint8_t numGainIndexesInTable,
Custom Gain Tables mykonosGainTable_t rxChannel)
The default gain tables can be found in the mykonos_user.c file.
This function takes a pointer to a 4 × N array, the value N,
The mykonos_user.c and mykonos_user.h files can be customized and the channel with the gain table to be overwritten. The
to modify, add, or delete the default gain table settings. Consult N variable specifies the number of rows of the new gain
Analog Devices applications engineering prior to changing gain table. This function can write gain tables for the Rx1, Rx2,
tables. Rx1 channels and the Rx2, ORx, and SnRx channels. Note
In the mykonos_user.c file, receiver gain tables can be modified that Rx1 and Rx2 may have separate gain tables.
for the intended application. In the default gain tables, the gain
step size between neighboring gain indices for the Rx channel
are 0.5 dB, 1 dB for the ORx channel, and 1 dB for the SnRx
channel. These tables have a gain range extending to 30 dB,
18 dB, and 52 dB, respectively. In the default gain tables, the
maximum gain condition for all the tables is the first index in
the gain table, which corresponds to Gain Index 255.
To set a target gain for the Rx datapath, the device allows the
user to configure the maximum gain index (independently for
both Rx1 and Rx2 channels) such that any gain index value can
be configured to be the maximum gain index. For example, if
the target gain for the Rx subsystem is 40 dB, but the factory
calibration returns a total gain of 42 dB, it is possible to
configure the target gain appropriately by changing the
maximum gain index from 255 to 251 (−2 dB).

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UG-992 AD9371/AD9375 System Development User Guide
GAIN TABLE PROGRAMMING DESCRIPTION Rx GAIN DELAY
The MYKONOS_programRxGainTable(…) command is Within the signal path, there are a few variable gain elements,
demonstrated in the following section. such as the RF internal attenuator, the digital gain/attenuation
MYKONOS_programRxGainTable (…) block, and the digital gain compensation clock. Consider the
case of a gain index decrement where new values for the
mykonosErr_t
MYKONOS_programRxGainTable(mykonosDevice_t internal attenuator and digital gain/attenuation are set, ignoring
*device, uint8_t *gainTablePtr, uint8_t the gain compensation and the optional external attenuator for
numGainIndexesInTable, mykonosGainTable_t the moment. If the new settings for the internal attenuator and
rxChannel) digital gain/attenuation block are applied at the same time, data
Description in the Rx datapath between the internal attenuator and the digital
gain/attenuation block experience analog gain of the old gain
This command programs the gain table settings for either the
index and digital gain of the new gain index when the data
Rx1, Rx2, Rx1 and Rx2, ORx, or SnRx receiver types. This
propagates through the digital gain/attenuation block. In the
command is called during MYKONOS_initArm(…). It is not
baseband data, this appears as a double gain step. This scenario
necessary to call this function after initialization.
is shown Figure 59.
The gain table for a receiver type is set with the parameters GAIN CHANGE
passed by the uint8_t gainTablePtr array. gainTablePtr is a 4 × n 40000
array, where there are four elements per index, and the array DIGITAL GAIN APPEARS FIRST
30000
length (n) is dependent upon receiver type. The (n) value is DATA WITH NEW RF
conveyed by numGainIndexesInTable. All gain tables have a ATTENUATION SETTING
20000
maximum index of 255 when used with this function. The
OUTPUT CODE

10000
minimum gain index is application dependent.
For Rx1, Rx2, and ORx (A, B, C, or D), A indicates front end 0

Gain, B indicates external control, C indicates digital attenuation/ –10000

gain, and D indicates attenuation/gain select.
–20000
For SnRx (A, B, C, or D), A indicates front end gain, B indicates
LNA bypass, C indicates digital attenuation/gain, and D indicates –30000

attenuation/gain select.
–40000

14652-052
0 50 100 150 255 250 300 350
The gain table starting address changes with each receiver type.
SAMPLE NUMBER
This function accounts for this change as well as the difference
Figure 59. Double Gain Step Observed in Baseband Data Due to Insufficient
between each byte for the Rx1, Rx2, ORx, and SnRx receiver Digital Gain Delay
array values and programs the correct registers.
The Rx gain delay calibration (ARM calibration) alleviates this
Preconditions double gain step by calculating a delay value for the onset of
The MYKONOS_programRxGainTable(…) command does not digital gain/attenuation. A successful calibration makes it
need to be called by user if following headless.c instructions. appear to the baseband processor that only one gain change has
been made, as shown in Figure 60. The calibration depends on
Parameters
the datapath configuration.
 *device: A pointer to the device data structure. 15000
 *gainTablePtr: A pointer to a 4 × n array containing gain
table values. 10000

 numGainIndexesInTable: The number of n indices in a 4 × n

array. A range check is performed to ensure the maximum 5000
OUTPUT CODE

is not exceeded.
 rxChannel: mykonosGainTable_t enumeration type to 0

select either the Rx1, Rx2, Rx1 and Rx2, ORx, or SnRx gain
table for programming. A channel check is performed to –5000

ensure a valid selection.

–10000
For all custom gain tables, note that the maximum number
of rows in the gain table is limited to 255 for the Rx1 and –15000
14652-053

0 50 100 150 255 250 300 350

Rx2 channels, 127 for the SnRx channels, and 47 for the
SAMPLE NUMBER
ORx channels.
Figure 60. Single Gain Step with Proper Setting for Digital Gain Delay

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AD9371/AD9375 System Development User Guide UG-992
Consider now the digital gain compensation block. This block The device is unable to delay the onset of external attenuator
is described in the Digital Gain Compensation, Slicer, and control word over the GPIO 3.3 V pins. Delays are only
Floating Point Formatter section. The digital gain compensation available for the digital gain/attenuator block and the digital
block applies digital gain based on the current gain index. The gain compensation block.
timing of the onset of digital gain compensation must be
delayed to prevent a double gain step. This value is calculated
and programmed to the device during the Rx gain delay
calibration as well.

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UG-992 AD9371/AD9375 System Development User Guide
MANUAL GAIN CONTROL, HYBRID MODE, AND Parameters
AUTOMATIC GAIN CONTROL OVERVIEW • * device: This is a pointer to the device data structure.
The receiver supports three modes of gain control. These modes • Mode: This is a mykonosGainMode_t enumerated data
are described in brief as follows: type indicating gain control mode, where manual gain is
• Manual gain control (MGC). MGC provides the user manual gain control, automatic gain control is automatic
full control over the current gain index. In MGC mode, gain control, and hybrid mode is hybrid.
the gain index can be controlled by the application MYKONOS_setObsRxGainControlMode(…)
programming interface (API) commands and through mykonosErr_t
GPIO signaling. MYKONOS_setObsRxGainControlMode(mykonosDe
• Hybrid mode. When the user sends a pulse to a GPIO pin vice_t* device, mykonosGainMode_t mode)
enabled as the hybrid mode gain change pin, the automatic Description
gain control (AGC) overload counters are polled to determine
if a gain increase or decrease is necessary. When the pulse This function configures the ORx gain control mode.
is registered by the gain control block, a gain increase is Preconditions
made in the case of an underrange scenario, a gain decrease is Run this function after MYKONOS_initialize(…).It is
made in the case of an overrange signal, or no gain change recommended to wait until after the headless.c instructions are
is made. This mode allows the user to determine when gain complete before running this function.
changes occur. The hybrid mode is a subset of AGC because
hybrid mode uses many of the same circuits, thresholds, Parameters
and counter parameters as AGC • * device: This is a pointer to the device data structure.
• Automatic gain control (AGC). AGC determines when gain • Mode: a mykonosGainMode_t enumerated data type
changes are made. There are several configurations that can indicating gain control mode, where manual gain is
be used in AGC mode. Examples include the option to manual gain control, automatic gain control is automatic
reduce gain as soon as an overrange is detected (fast attack gain control, and hybrid mode is hybrid.
mode), to change gain (if necessary) only at the expiration
of a variable length counter (AGC gain update counter, Functions Common to All Gain Control Modes
operating without fast attack), to synchronize the counter Application programming interface (API) functions can also
to an external pulse (AGC enable sync pulse), among obtain the current gain index for a particular channel. These
others. commands can also be used in any gain control mode. The
commands to get the current gain index are as follows:
Selection between the three different modes of operation is
performed with the MYKONOS_setRxGainControlMode(…) mykonosErr_t
MYKONOS_getRx1Gain(mykonosDevice_t*
command for Rx1and Rx2. The ObsRx uses MYKONOS_ device, uint8_t* rx1GainIndex)
setObsRxGainControlMode(…) to set the gain control mode mykonosErr_t
for the ORx1, ORx2, and all SnRx channels. Note that AGC for MYKONOS_getRx2Gain(mykonosDevice_t*
the ORx depends on the setting in device → obsRx → orxAgcCtrl device, uint8_t* rx2GainIndex)
→ agcObsRxSelect. Descriptions of the gain control selection mykonosErr_t
MYKONOS_getObsRxGain(mykonosDevice_t*
functions are provided in the following sections. device, uint8_t* gainIndex)
MYKONOS_setRxGainControlMode(…) Whether in manual gain control, hybrid, or automatic gain
mykonosErr_t control mode, the GPIO monitor outputs have several helpful
MYKONOS_setRxGainControlMode(mykonosDevice_ status signals that assist users with determining when overloads
t* device,mykonosGainMode_t mode)
occur in real-time. Refer to the General-Purpose Input/Output
Description (GPIO) Configuration section for more information about the
This function configures the Rx gain control mode. signals that can be observed on the GPIO pins.
Preconditions
Run this function after MYKONOS_initialize(…). It is
recommended to wait until after the headless.c instructions
are complete before running this function.

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AD9371/AD9375 System Development User Guide UG-992
MANUAL GAIN CONTROL Parameters
In manual gain control (MGC) mode, there are two ways to • * device: This is a pointer to the device data structure.
change the gain index pointer: application programming • gainIndex: This is the desired Rx2 gain index.
interface (API) commands and GPIO signaling. GPIO signaling
is only available on Rx1 and Rx2. MYKONOS_setObsRxManualGain(…)
mykonosErr_t
API/SPI Mode MGC MYKONOS_setObsRxManualGain(mykonosDevice_
The application programming interface (API) commands used t* device, mykonosObsRxChannels_t
to change gain in manual gain control (MGC) mode are listed in obsRxCh, uint8_t gainIndex)
the following sections. The first two of these commands are Description
specific to the Rx1 and Rx2 channels, respectively. The third This function sets the Rx gain of the selected ORx channel by
command uses an enumerated data type to specify the ORx1, the obsRxCh parameter.
ORx2, SNRXA, SNRXB, or SNRXC channels of the ORx.
Details regarding the API command mode for MGC are The ORx channel can have different RF inputs (ORx1/ORx2/
provided in the following section. SNRXA, SNRXB, or SNRXC) This function sets the ORx gain
index independently for ORx1/ORx2, or SnRx. SNRXA, SNRXB,
MYKONOS_setRx1ManualGain(…) and SNRXC share the same gain index. Note that ORx1/ORx2
mykonosErr_t share a gain table, as does SNRXA, SNRXB, and SNRXC. The
MYKONOS_setRx1ManualGain(mykonosDevice_ maximum index is 255, and the minimum index is application
t* device, uint8_t gainIndex) specific.
Description Preconditions
This function sets the Rx1 manual gain index. Run this function after MYKONOS_initialize(…). It is
If the value passed in the gainIndex parameter is within range of recommended to wait until after headless.c instructions are
the gain table minimum and maximum indexes, the Rx1 gain complete before running this function.
index is updated in the device data structure and written to the Parameters
transceiver. Otherwise, an error is returned. The maximum
index is 255, and the minimum index is application specific. • * device: This is a pointer to the device data structure.
• obsRxCh: This is an enumeration to identify the desired
Preconditions
RF input for gain change.
Run this function after MYKONOS_initialize(…). It is • gainIndex: the desired manual gain table index to be set.
recommended to wait until after headless.c instructions are
complete before running this function. GPIO Mode MGC
Parameters The GPIO pins can also be configured to make gain changes for
Rx1 and Rx2. GPIO manual gain control (MGC) setup commands
• * device: This is a pointer to the device data structure. configure the gain index increment step size, gain index
• gainIndex: This is the desired Rx1 gain index. decrement step size, and pin selection for the increment and
MYKONOS_setRx2ManualGain(…) decrement pins. Some restrictions on the increment and
decrement pin selections are as follows:
mykonosErr_t
MYKONOS_setRx2ManualGain(mykonosDevice_ • The Rx1 increment pin must be either GPIO_0 or GPIO_10.
t* device, uint8_t gainIndex) • The Rx1 decrement pin must be either GPIO_1 or GPIO_11.
Description • The Rx2 increment pin must be either GPIO_3 or GPIO_13.
This function sets the Rx2 manual gain index. • The Rx2 decrement pin must be either GPIO_4 or GPIO_14.

If the value passed in the gainIndex parameter is within range of

the gain table minimum and maximum indexes, the Rx2 gain
index is updated in the device data structure and written to the
transceiver. Otherwise, an error is returned. The maximum
index is 255, and the minimum index is application specific.
Preconditions
Run this function after MYKONOS_initialize(…). It is
recommended to wait until after headless.c instructions are
complete before running this function.

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MYKONOS_setRx1GainCtrlPin(…) HYBRID GAIN CONTROL
mykonosErr_t Hybrid gain control is a hybrid between automatic gain control
MYKONOS_setRx1GainCtrlPin(mykonosDevice_t (AGC) and manual gain control (MGC) modes of operation.
*device, uint8_t incStep, uint8_t
decStep, mykonosGpioSelect_t Hybrid gain control mode allows the device to monitor the state
rx1GainIncPin, mykonosGpioSelect_t of the overload detectors and waits for a baseband processor
rx1GainDecPin) (BBP) signal on a GPIO to make a gain change. When an external
Description pulse on a GPIO pin is provided, the gain control algorithm
either increments the gain index if underrange conditions are
This application programming interface (API) function detected, decrements the gain index if overrange conditions are
configures the GPIO inputs for controlling the Rx gain, detected, or does nothing if neither an underrange or overrange
allowing the user to control the gain index in manual gain condition is detected. If fast attack for the analog peak detector
control (MGC) mode. If there is a high pulse on the (APD) or Half-Band 2 (HB2) is enabled, a gain decrease occurs
rx1GainIncPin in pin control mode, it increments the gain by immediately without the external pulse applied.
the value set in incStep. A high pulse on the rx1GainDecPin in
pin control mode decrements the gain by the number of indices In hybrid gain control mode, the gain update counter does not
set in decStep. run. The peak detector counters do not reset until a pulse is
detected on the selected GPIO pin. For Rx1, the allowed pins
Preconditions for this feature are GPIO_1, GPIO_10, and GPIO_11. For Rx2,
Run this function after MYKONOS_initialize(…). the allowed pins for this feature are GPIO_4, GPIO_10, and
GPIO_13.
Parameters
For proper operation of the hybrid gain control mode, the setup
• *device: This is a pointer to the device data structure.
command for the AGC must be run. This command is
• obsRxCh: This is an enumeration to identify the desired
MYKONOS_setupRxAgc(…). Running this command sets up
RF input for gain change.
all the necessary parameters for the AGC and hybrid mode. The
• gainIndex: the desired manual gain table index to set. parameters include threshold settings, how many indices to
MYKONOS_setRx2GainCtrlPin(…) increment or decrement the gain index, and others. See the
mykonosErr_t following section for an explanation of the AGC parameters.
MYKONOS_setRx2GainCtrlPin(mykonosDevice_t When in hybrid mode, it is necessary to call a setup function to
*device, uint8_t incStep, uint8_t assign a GPIO pin per Rx channel for this feature. The function
decStep, mykonosGpioSelect_t
rx2GainIncPin, mykonosGpioSelect_t MYKONOS_setRxHybridGainChangePin(…) is described in
rx2GainDecPin) the following section. Additionally, the GPIO pin selected must
be set as an input (see the General-Purpose Input/Output
Description
(GPIO) Configuration section).
This application programming interface (API) function configures
MYKONOS_setRxHybridGainChangePin(…)
the GPIO inputs for controlling the Rx gain, allowing the user
to control the gain index in manual gain control (MGC) mode. mykonosErr_t
MYKONOS_setRxHybridGainChangePin(mykonosD
If there is a high pulse on the rx2GainIncPin in pin control evice_t *device, mykonosGpioSelect_t
mode, it increments the gain by the value set in incStep. A high rx1GainChangePin, mykonosGpioSelect_t
pulse on the rx2GainDecPin in pin control mode decrements rx2GainChangePin)
the gain by the number of indices set in decStep. Description
Preconditions This application programming interface (API) function sets the
Run this function after MYKONOS_initialize(…). pins for hybrid gain control.
Parameters To call this function, set the gain mode to hybrid. The gain
change is controlled with the selected GPIO pin. A pulse on
• *device: This is a pointer to the device data structure.
the rx1GainChangePin in hybrid pin control enables the gain
• obsRxCh: This is an enumeration to identify the desired
change for Rx1, and a pulse on the rx2GainChangePin in hybrid
RF input for gain change.
pin control enables the gain change for Rx2. A gain change is only
• gainIndex: the desired manual gain table index to set.
made if deemed necessary by the automatic gain control (AGC).
These obsRxCh and gainIndex commands have complementary Preconditions
get commands for the set functions listed previously. These
commands are MYKONOS_getRx1GainCtrlPin(…) and Run this function after MYKONOS_initialize(…). Set the gain
MYKONOS_getRx2GainCtrlPin(…). control mode to hybrid mode.

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AD9371/AD9375 System Development User Guide UG-992
Parameters Analog Peak Detector (APD) Basics
• *device: This a pointer to the device data structure. The APD overload detector is part of the peak threshold
• rx1GainChangePin: This selects the GPIO pin to be used automatic gain control (AGC). The APD is considered the
for hybrid gain change control. The available pins for Rx1 blocker overload detector because it determines if the received
channel hybrid control are GPIO_1, GPIO_10, and GPIO_11. signal is overloading the blocks before the digital chain, including
Use the MYKGPIONAN parameter for no GPIO selected. the ADC. Because the APD is located after the analog low-pass
• rx2GainChangePin: This selects the GPIO pin to be used filter, attenuation increases for signals further from the Rx local
for hybrid gain change control. The available pins for Rx2 oscillator (LO) frequency. APD thresholds are specified in units of
channel hybrid control are GPIO_4, GPIO_10, and GPIO_13. voltage (peak). The ADC full-scale voltage is 707 mV peak.
Use the MYKGPIONAN parameter for no GPIO selected. The APD high threshold (apdHighThresh) determines if a gain
reduction is necessary. If a detected input signal level is less
AUTOMATIC GAIN CONTROL (AGC) than the APD high threshold but exceeds this threshold by a
When using AGC mode, there are several configurable number of samples equal to or greater than a programmable
parameters allowing the modification of how AGC mode number (apdHighThreshExceededCnt) within the duration of
responds to overrange or underrange conditions. This section the AGC gain update counter (agcGainUpdateCounter), the
provides details regarding configuration of the AGC by explaining AGC decrements the gain index according to the
the AGC theory of operation and the configuration options programmable APD gain step attack parameter
available in the application programming interface (API). This (apdHighGainStepAttack) at a time depending on the APD fast
section explains the AGC at a high level. Parameters referenced attack setting (apdFastAttack). The gain decrement can occur
in this section are data structure members within the following data when the overrange condition is detected by the APD or when
structure types: mykonosAgcCfg_t, mykonosPeakDetAgcCfg_t, the AGC gain update counter expires. If the potential gain index
and mykonosPowerMeasAgcCfg_t. decrement places the gain index less than the AGC minimum
AGC Theory of Operation gain index (for example, agcRx1MinGainIndex), the decrement
is not made.
The automatic gain control (AGC) uses upper and lower thresholds
from two peak detector circuits to determine if a gain index The APD low threshold (apdLowThresh) determines if an
increment or decrement is necessary, depending on input signal increase in gain is necessary. If a detected input signal level
conditions. The peak detector circuits include the analog peak is less than the APD low threshold and does not exceed this
detector (APD) and the Half-Band 2 (HB2) overload detector. threshold by a number of samples equal to or greater than a
Refer to Figure 57 or Figure 58 for the location of these peak programmable number (apdLowThreshExceededCnt)
detectors in the different receivers. within the duration of the AGC gain update counter
(agcGainUpdateCounter), the AGC increments the gain index
Additionally, power measurement detectors can be enabled to
according to the programmable APD low gain step recovery
determine if a gain index increment or decrement is necessary.
parameter (apdLowGainStepRecovery). The gain index
These blocks sample digital data at the HB2, programmable
increment occurs at the expiration of the AGC gain update
receiver finite impulse response (RFIR) filter, or dc correction
counter. If the potential gain index increment puts the gain
block. Refer to Figure 57 or Figure 58 for the location of these
index outside of the AGC maximum gain index (for example,
power measurement detectors in the different receivers.
agcRx1MaxGainIndex), the increment is not made.
It is recommended to configure the AGC in peak threshold
Figure 61 shows the APD response to the presence and removal
mode. However, the best configuration is application dependent.
of an interferer when the APD fast attack bit is not set. Note that
Peak threshold mode uses the APD/HB2 detectors to determine
the gain decrement in response to the APD overrange condition
when to make gain changes. Peak threshold mode can also disable
occurs at the expiration of the AGC gain update counter.
the power-based AGC mode by setting agcPeakThresholdMode =
1. Peak threshold mode, when configured for fast attack response Figure 62 shows the APD response to the presence and removal
to overrange signals mode (apdFastAttack, hb2FastAttack), of an interferer when the APD fast attack bit is set. With this
offers the quickest response to the sudden onset of the blocking setting enabled, the total time when the Rx is overranged is
signals. Peak threshold mode with fast attack response is the reduced because the gain decrement occurs immediately when
recommended operation mode for the AGC. the APD high threshold exceeded counter overflows. All peak
detector counters reset with a gain change. The AGC gain
If it is desired to use only power detector measurement AGC
update counter does not reset with a gain change. The fast attack
mode, set the gain step settings for the APD and HB2 to 0 and
mode can help reduce the time the receiver ADC is overloaded,
set agcPeakThresholdMode to 0 to enable the power measurement
leading to smaller windows where data can be lost.
detectors to make gain changes.

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UG-992 AD9371/AD9375 System Development User Guide
apdHighThreshExceededCnt
overflow
apdHighThreshExceededCnt
overflow
GAIN apdHighThreshExceededCnt
DECREMENT overflow
DECREMENT GAIN BY
GAIN apdHighGainStepAttack
DECREMENT
GAIN
DECREMENT
apdHighThresh
INTERFERER
REMOVED

NO GAIN CHANGE
RECEIVED SIGNAL
POWER
INTERFERER
PRESENT

apdLowThresh GAIN
INCREMENT
INCREMENT GAIN BY
GAIN apdLowGainStepRecovery

14652-054
ACG GAIN UPDATE INCREMENT
TIME

Figure 61. APD Response to Interferer Onset and Removal with APD Fast Attack Disabled

apdHighThreshExceededCnt
overflow
PEAK
DETECTOR
COUNTERS
GAIN RESET ON GAIN
DECREMENT CHANGE. GAIN DECREMENT GAIN BY
GAIN UPDATE COUNTER apdHighGainStepAttack
DDECREMENTEC DOES NOT RESET
GAIN ON GAIN CHANGE.
DECREMENT
apdHighThresh
INTERFERER
REMOVED

NO GAIN CHANGE
RECEIVED SIGNAL
POWER
INTERFERER
PRESENT

apdLowThresh
GAIN
INCREMENT
INCREMENT GAIN BY
GAIN apdLowGainStepRecovery
ACG GAIN UPDATE

14652-055
INCREMENT
TIME

Figure 62. APD Response to Interferer Onset and Removal with APD Fast Attack Enabled

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AD9371/AD9375 System Development User Guide UG-992
Half-Band 2 (HB2) Overload Detector Basics AGC increases the gain according to the programmable
HB2 low threshold gain step recovery parameter
The HB2 overload detector is part of the peak threshold AGC
(hb2LowGainStepRecovery). The gain index increment
mode. The HB2 overload detector can be disabled if desired
occurs at the expiration of the AGC gain update counter. If
(hb2OverloadDetectEnable). The HB2 overload detector has
the potential gain index increment puts the gain index
configurable high, low, and very low thresholds. The HB2
outside of the AGC maximum gain index (for example,
overload detector is considered the decimated data overload
agcRx1MaxGainIndex), the increment is not made.
detector because it uses the data output of the HB2 digital
decimation filter to determine if an overload is occurring. The The HB2 very low threshold (hb2VeryLowThresh) determines
HB2 overload detector is similar in function to the APD. HB2 if a gain increase is necessary. If a detected input signal level is
peak detector thresholds are specified in units of −dBFS relative less than the HB2 very low threshold and does not exceed this
to the ADC full-scale voltage. threshold by a number of samples equal to or greater than a
programmable number (hb2VeryLowThreshExceededCnt)
The HB2 high threshold (hb2HighThresh) determines if a gain
within the duration of the AGC gain update counter
reduction is necessary. If a detected input signal level is less
(agcGainUpdateCounter), the AGC increases the gain
than the HB2 high threshold but exceeds this threshold by a
according to the programmable HB2 very low threshold gain
number of samples equal to or greater than a programmable
step recovery parameter (hb2LowGainStepRecovery). The gain
number (hb2HighThreshExceededCnt) within the duration of
index increment occurs at the expiration of the AGC gain update
the AGC gain update counter (agcGainUpdateCounter), the
counter. If the potential gain index increment puts the gain
AGC reduces the gain according to the programmable HB2
index outside of the AGC maximum gain index (for example,
gain step attack parameter (hb2HighGainStepAttack) at a time
agcRx1MaxGainIndex), the increment is not made. It is
depending on the HB2 fast attack setting (hb2FastAttack). The
recommended to set the very low threshold gain step recovery
gain decrement can occur when the overrange condition is
parameter larger than the low threshold gain step recovery
detected by the HB2 or when the AGC gain update counter
parameter to recovery gain quicker in very low underrange
expires. If the potential gain index decrement puts the gain
situations.
index outside of the programmable gain index limits (for
example, agcRx1MinGainIndex), the decrement is not made. Figure 63 shows an example of HB2 operation within the AGC
when the HB2 fast attack mode is not enabled. The behavior is
The HB2 low threshold (hb2LowThresh) determines if a gain
similar to the behavior of the APD without fast attack. All peak
increase is necessary. If a detected input signal level is less than
detector counters reset upon a gain change. The AGC gain
the HB2 low threshold and does not exceed this threshold by a
update counter does not reset upon a gain change.
number of samples equal to or greater than a programmable
number (hb2LowThreshExceededCnt) within the duration of The diagram in Figure 64 shows the same situation in the case
the AGC gain update counter (agcGainUpdateCounter), the where HB2 fast attack is enabled.

hb2HighThreshExceededCnt
overflow
hb2HighThreshExceededCnt
overflow
GAIN hb2HighThreshExceededCnt
DECREMENT overflow DECREMENT GAIN BY
GAIN hb2HighGainStepAttack
DECREMENT
GAIN
DECREMENT
hb2HighThresh
INTERFERER
REMOVED

NO GAIN CHANGE
RECEIVED SIGNAL
POWER
INTERFERER
PRESENT
GAIN
hb2LowThresh INC
INCREMENT GAIN BY
hb2LowGainStepRecovery

hb2VeryLowThresh GAIN
INCREMENT GAIN BY
14652-056

INCREMENT
ACG GAIN UPDATE hb2VeryLowGainStepRecovery
TIME

Figure 63. HB2 Thresholds and Gain Changes Associated with Underrange and Overrange Conditions with HB2 Fast Attack Mode Disabled

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UG-992 AD9371/AD9375 System Development User Guide

hb2HighThreshExceededCnt
overflow

NOTE: PEAK
DETECTOR
GAIN COUNTERS
DECREMENT RESET ON GAIN DECREMENT GAIN BY
CHANGE. GAIN hb2HighGainStepAttack
GAIN UPDATE COUNTER
DECREMENT DOES NOT RESET
GAIN ON GAIN CHANGE
DECREMENT
hb2HighThresh
INTERFERER
REMOVED

NO GAIN CHANGE

RECEIVED SIGNAL
POWER
INTERFERER
PRESENT
GAIN
hb2LowThresh INC
INCREMENT GAIN BY
hb2LowGainStepRecovery

hb2VeryLowThresh
GAIN
INCREMENT GAIN BY

14652-057
INCREMENT
ACG GAIN UPDATE hb2VeryLowGainStepRecovery
TIME

Figure 64. HB2 Thresholds and Gain Changes Associated with Underrange and Overrange Conditions with HB2 Fast Attack Mode Enabled

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AD9371/AD9375 System Development User Guide UG-992
Power Measurement Detector (PMD) Basics gain index increment is necessary. If the pmdUpperHighThresh
The PMD obtains estimates of the digital power received at is exceeded, a gain index decrement is made according to
various points in the digital signal path. These locations include pmdUpperHighGainStepAttack. If the pmdUpperLowThresh is
the HB2 output, RFIR output, and the output of the baseband exceeded, a gain index decrement is made according to
dc (BBDC) correction block. The power measurement detector is pmdUpperLowGainStepAttack. Gain decrements occur only at
a slower responding automatic gain control (AGC) mode than the end of the AGC gain update counter.
the peak threshold mode with fast attack enabled. There are two PMD lower level thresholds to determine if a gain
The thresholds are set such that the relative magnitude of the increment is necessary. The lower thresholds are further split into
thresholds are pmdUpperHighThresh → pmdUpperLowThresh high (pmdLowerHighThresh) and low (pmdLowerLowThresh)
→ pmdLowerHighThresh → pmdLowerLowThresh. It is thresholds. The PMD is polled at the expiration of the AGC gain
recommended that the gain step associated with the outer update counter (agcGainUpdateCounter) to determine if a gain
thresholds (pmdUpperHighThresh, pmdLowerLowThresh) are index increment is necessary. If the pmdLowerHighThresh is
greater than that of the inner thresholds (pmdUpperLowThresh, exceeded, a gain index increment is made according to
pmdLowerHighThresh) to speed gain attack or recovery in far pmdLowerHighGainStepAttack. If the pmdLowerLowThresh
overrange or far underrange conditions. is exceeded, a gain index decrement is made according to
pmdLowerLowGainStepAttack. Gain decrements occur only
There are two PMD upper level thresholds to determine if a gain
at the end of the AGC gain update counter.
decrease is necessary. The upper thresholds are further split into
high (pmdUpperHighThresh) and low (pmdUpperLowThresh) The diagram in Figure 65 shows the relative threshold levels for
thresholds. The PMD is polled at the expiration of the AGC the PMD.
gain update counter (agcGainUpdateCounter) to determine if a

ACG GAIN UPDATE TIME

DECREMENT GAIN BY
pmdUpperHighGainStepAttack

pmdUpperHighThresh GAIN
DECREMENT DECREMENT GAIN BY
pmdUpperLowGainStepAttack

pmdUpperLowThresh LARGER GAIN

POWER POWER DECREMENT
MEASUREMENT MEASUREMENT
DURATION DURATION
RECEIVED SIGNAL
POWER
POWER
MEASUREMENT
NO GAIN CHANGE
DURATION

pmdLowerHighThresh INCREMENT GAIN BY

GAIN
INCREMENT pmdLowerHighGainStepRecovery

14652-058
pmdLowerLowThresh GAIN
INCREMENT INCREMENT GAIN BY
pmdLowerHighGainStepRecovery

Figure 65. Power Measurement Detector (PMD) Thresholds and Gain Index Changes Associated with Underrange and Overrange Conditions

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UG-992 AD9371/AD9375 System Development User Guide
Automatic Gain Control Operation A time domain depiction of the peak threshold with fast attack
Gain decrements occur due to overrange conditions. AGC operation is shown in Figure 66. Figure 66 also shows the
receiver gain. The right side plot shows an example input wave-
 The analog peak detector (APD) overrange condition form. Due to the presence of the large signal, the AGC reduces
occurs when the apdHighThreshExceededCnt counter the receiver gain at approximately 1000 μs and 11,000 μs. The
overflows. Gain index decrement occurs immediately or at receiver gain decrements immediately after detecting the sufficient
the end of the AGC gain update counter. number of signal peaks, as described previously. When the large
 The Half-Band 2 (HB2) overrange condition occurs when signal is removed from the input, the gain recovers. The gain index
the hb2HighThreshExceededCnt counter overflows. Gain increments at the expiration of the AGC gain update counter.
index decrement occurs immediately or at the end of the The gain recovery instances occur at 2000 μs and 12,000 μs. The
AGC gain update counter. time between gain increments is greater than the time between
 Power-based overrange conditions occur when the power gain decrements because gain increments (recovery) wait until
measurement exceeds either upper level power thresholds, the expiration of the AGC gain update counter.
pmdUpperHighThresh or pmdUpperLowThresh. Gain
index decrements due to power-based overrange conditions
only occur at the end of the AGC gain update counter. GAIN ATTACK

 If multiple overrange conditions are detected, gain step GAIN RECOVERY

priority is given to the APD attack gain step, then the HB2
attack gain step, then the PMD upper high threshold attack

GAIN (dB)
gain step, and then the PMD upper low threshold attack
gain step.
Gain increments occur due to underrange conditions. All gain
index increments occur at the end of the AGC gain update
counter.
 The APD underrange condition occurs when the

14652-601
0 2000 4000 6000 8000 10000 12000 14000
apdLowThreshExceededCnt counter does not overflow by TIME (µs)
the end of the AGC gain update counter. Figure 66. Typical Automatic Gain Control (AGC) Operation vs. Time
 The HB2 underrange condition occurs when the ×10 4
2.5
hb2LowThreshExceededCnt counter does not overflow by
the end of the AGC gain update counter. 2.0

 The HB2 very low underrange condition occurs when the 1.5
hb2VeryLowThreshExceededCnt counter does not
1.0
overflow by the end of the AGC gain update counter
AMPLITUDE

 Power-based underrange conditions occur when the power 0.5

measurement does not exceed either lower level power 0

thresholds, pmdLowerHighThresh or pmdLowerLowThresh.
–0.5
 If multiple underrange conditions are detected, gain step
priority is given to the HB2 very low recovery gain step, –1.0

then the APD low recovery gain step, then the HB2 low –2.0
recovery gain step, then the PMD lower low threshold
–2.5
14652-059

recovery gain step, and then the PMD lower high threshold 0 2000 4000 6000 8000 10000 12000 14000
TIME (µs)
recovery gain step.
Figure 67. Typical Receiver Data Output Codes vs. Time with AGC Active
When configuring the AGC, it is important to ensure that the
difference between the high level thresholds and low level
thresholds, in dB, is greater than the gain decrement step size
and greater than the gain increment step size in dB. Setting the
thresholds and step sizes in this way prevents a small overload
from pushing the receiver from an overrange condition into an
underrange condition when the gain decrement occurs, which
may cause an underrange condition and a gain increment. This
situation may lead to an undesirable gain index oscillation
scenario.

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AD9371/AD9375 System Development User Guide UG-992
AGC API COMMANDS Preconditions
The automatic gain control (AGC) data structure members Run this function after device initialization.
must be programmed to the device registers by an application Parameters
programming interface (API) command prior to putting the
device into AGC mode. To program the AGC registers with the • *device: This is a pointer to the device data structure.
settings in the mykonosAgcCfg_t data structure, the following The AGC enable sync pulse for the gain counter feature allows
API commands can be used. Descriptions of the members of synchronization of the AGC gain update counter to the
the mykonosAgcCfg_t data structure are provided in the beginning of the time slots as signaled on the GPIO pins. The
following sections. function to assign a pin for this functionality is given in the
MYKONOS_setupRxAgc(…) following section. The function can only be assigned to GPIO_1,
mykonosErr_t GPIO_10, or GPIO_11 for Rx1, and GPIO_4, GPIO_10, or
MYKONOS_setupRxAgc(mykonosDevice_t* GPIO_13 for Rx2.
device)
MYKONOS_setRxAgcEnSyncPin(…)
Description mykonosErr_t
This function sets up the device Rx automatic gain control MYKONOS_setRxAgcEnSyncPin(mykonosDevice_t
(AGC) registers. * device, mykonosGpioSelect_t
rx1AgcSyncPin, mykonosGpioSelect_t
Three data structures (mykonosAgcCfg_t, rx2AgcSyncPin)
mykonosPeakDetAgcCfg_t, and mykonosPowerMeasAgcCfg_t) Description
must be instantiated prior to calling this function. Valid ranges
for data structure members must also be provided. This application programming interface (API) function sets the
pins for sync automatic gain control (AGC).
Preconditions
To call this function, set the Rx gain control to AGC mode. The
Run this function after device initialization. It is recommended AGC gain sync is controlled with the selected GPIO pin. A
to wait until after headless.c instructions are complete before pulse on rx1AgcSyncPin in AGC mode enables the AGC gain
running this function. sync for Rx1, and a pulse on rx2AgcSyncPin in AGC enables the
Parameters AGC gain sync for Rx2.
• *device: this is a pointer to the device data structure. Preconditions

MYKONOS_setupObsRxAgc(…) Run this function after device initialization in AGC mode. Set the
device → rx → rxAgcCtrl → agcEnableSyncPulseForGainCounter
mykonosErr_t
MYKONOS_setupObsRxAgc(mykonosDevice_t* parameter to 1 for this feature to work as intended; note that
device) this is not a precondition for this function to be called.
Description Parameters
This function sets up the device Rx AGC registers. • *device: This is a pointer to the device data structure.
Three data structures (of types mykonosAgcCfg_t,
mykonosPeakDetAgcCfg_t, and mykonosPowerMeasAgcCfg_t)
must be instantiated prior to calling this function. Valid ranges
for data structure members must also be provided.

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UG-992 AD9371/AD9375 System Development User Guide
APPLICATION PROGRAMMING INTERFACE (API) PROGRAMMING SUMMARY
To summarize the programming requirements of the different operation of GPIO based functions, refer to the General-
gain control modes, a flowchart is provided in Figure 68 to Purpose Input/Output (GPIO) Configuration section. For
assist users with setting up their desired gain control mode. The GPIO input modes, such as hybrid mode, selected pins must be
chart describes how to set up the manual gain control (MGC), assigned as inputs in addition to the configuration described in
hybrid, and automatic gain control (AGC) modes. For proper the flowchart.

CONFIGURE GAIN TABLES,

DEVICE DATA STRUCTURE, AGC
STRUCTURES

DEVICE INITIALIZATION
SEQUENCE
(headless.c)

USE MGC USE HYBRID GAIN USE AGC

CONTROL

SET GAIN MODE SETUP AGC BEHAVIOR SETTINGS SETUP AGC BEHAVIOR SETTINGS
_setRxGainControl Mode(...) _setupRxAgc(...) _setupRxAgc(...)

SET GAIN MODE SET GAIN MODE

Y ASSIGN MGC GAIN CHANGE PIN(S) _setRxGainControlMode(...) _setRxGainControl Mode(...)
USE GPIO MGC? _setRx1GainCtrlPin(...)
_setRx2GainCtrlPin(...)

N ASSIGN HYBRID GAIN CHANGE PIN(S) Y ASSIGN SYNC PULSE PIN(S)

_setRxHybridGainChangePin ENABLE SYNC
PULSE? _setRxAgcEnSyncPin(...)

14652-060
GAIN CONTROL
SETUP COMPLETE

Figure 68. Gain Control Programming Flowchart

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AD9371/AD9375 System Development User Guide UG-992
Data Structures and Parameters for AGC and Hybrid structures are substructures to the mykonosObsRxSettings_t
Mode data structure.
The automatic gain control (AGC) allows the automatic The AGC configuration data structures are divided into a
adjustment of receiver gain to avoid overrange conditions and higher level data structure, corresponding to general AGC
underrange conditions. The AGC engine compares the received configuration settings called mykonosAgcCfg_t, with two
signal to programmable thresholds at various points in the signal substructures for more specific configuration settings. The two
chain. This section explains the programmable settings of the substructures correspond to peak detector AGC settings
AGC by looking into the AGC configuration data structures. (mykonosPeakDetAgcCfg_t) and power measurement detector
The AGC uses three data structures to store configuration settings (mykonosPowerMeasAgcCfg_t). The Rx AGC and ORx
settings. For the Rx channels, the AGC configuration data AGC use the same data structure types; however, one instance is
structures are substructures to the mykonosRxSettings_t data specific for Rx and the other specific for ORx. The data structures
structure. For the ORx channels, the AGC configuration data are shown in Figure 69.

mykonosPeakDetAgcCfg_t
+ apdHighThresh
+ apdLowThresh
+ hb2HighThresh
+ hb2LowThresh mykonosPowermeasAgcCfg_t
+ hb2VeryLowThresh
+ apdHighThreshExceededCnt + pmdUpperHighThresh
+ apdLowThreshExceededCnt + pmdUpperLowThresh
+ hb2HighThreshExceededCnt + pmdLowerHighThresh
+ hb2LowThreshExceededCnt + pmdLowerLowThresh
+ hb2VeryLowThreshExceededCnt + pmdUpperHighGainStepAttack
+ apdHighGainStepAttack + pmdUpperLowGainStepAttack
+ apdLowGainStepRecovery + pmdLowerHighGainStepRecovery
+ hb2HighGainStepAttack + pmdLowerLowGainStepRecovery
+ hb2LowGainStepRecovery + pmdMeasDuration
+ hb2VeryLowGainStepRecovery + pmdMeasConfig
+ apdFastAttack
+ hb2FastAttack
+ hb2OverloadDetectEnable
+ hb2OverloadDurationCnt
+ hb2OverloadThreshCnt

+peakAgc +powerAgc

mykonosAgcCfg_t
+ agcRx1MaxGainIndex
+ agcRx1MinGainIndex
+ agcRx2MaxGainIndex
+ agcRx2MinGainIndex
+ agcObsRxMaxGainIndex
+ agcObsRxMinGainIndex
+ agcObsRxSelect
+ agcPeakThresholMode
+ agcLowThsPreventGainIncrease
+ agcGainUpdateCounter
+ agcSlowLoopSettlingDelay
+ agcPeakWaitTime
+ agcResetOnRxEnable
+ agcEnableSyncPulseForGainCounter
14652-061

Figure 69. Member Listing of the mykonosAgcCfg_t, mykonosPeakDetAgcCfg_t, and mykonosPowerMeasAgcCfg_t Data Structures

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UG-992 AD9371/AD9375 System Development User Guide
mykonosAgcCfg_t Data Structure Table 101 provides the receiver associated with the valid values
The following sections describe parameters within the data of the agcObsRxSelect member. Only one value is supported for
structure mykonosAgcCfg_t. This data structure contains the this data structure member.
peak detector automatic gain control (AGC) settings, power The MYKONOS_setupRxAgc(…) function does not program
measurement AGC settings, and several other general parameters the parameters specific to the ORx AGC. These ignored parameters
for AGC operation. are agcObsRxSelect, agcObsRxMaxGainIndex, and
AGC Minimum and Maximum Receiver Gain Indices agcObsRxMinGainIndex.

The following sections outline the parameters within the three The MYKONOS_setupObsRxAgc(…) function does not
automatic gain control (AGC) configuration structures with program parameters specific to the Rx AGC. These ignored
recommended settings and minimum and maximum settings. parameters are agcRx1MaxGainIndex, agcRx1MinGainIndex,
At the end of the section is a summary of all default, minimum, agcRx2MaxGainIndex, and agcRx2MinGainIndex.
and maximum settings for the AGC data structures. AGC Peak Threshold Mode
The members of the mykonosAgcCfg_t structure referring to The member agcPeakThresholdMode of the mykonosAgcCfg_t
maximum and minimum gain indices for a given receiver channel data structure determines if the automatic gain control (AGC)
are listed in Table 100. These parameters limit the AGC to make runs in peak threshold mode. This is a 1-bit field. Setting this
gain change decisions that result in gain indices within the bit disables the power measurement detector from making gain
minimum and maximum parameter specified for a given changes. Setting this bit also enables the analog peak detector
channel. (APD)/Half-Band 2 (HB2) lower thresholds to make gain
The current application programming interface (API) increments.
implementation dictates that agcObsRxMaxGainIndex Peak threshold mode is the recommended AGC configuration
and agcObsRxMinGainIndex are used in reference to the because it allows for fast attack response (see apdFastAttack,
SnRx channels. If the user is attempting to set up the hb2FastAttack) in response to the sudden presence of a
mykonosAgcCfg_t data structure for use with an ORx blocking signal.
input, the agcObsRxSelect member must be set for SnRx usage.

Table 100. AGC Minimum and Maximum Gain Index Value Limits
Data Type Parameter Default Value Minimum Value Maximum Value
uint8_t agcRx1MaxGainIndex 255 agcRx1MinGainIndex 255
uint8_t agcRx1MinGainIndex 195 Minimum Rx1 Table Index agcRx1MaxGainIndex
uint8_t agcRx2MaxGainIndex 255 agcRx2MinGainIndex 255
uint8_t agcRx2MinGainIndex 195 Minimum Rx2 Table Index agcRx2MaxGainIndex
uint8_t agcObsRxMaxGainIndex 255 agcObsRxMinGainIndex 255
uint8_t agcObsRxMinGainIndex 203 Minimum ObsRx Table Index agcObsRxMaxGainIndex

Table 101. Parameter Limits and Defaults for agcObsRxSelect

Data Type Parameter Default Value Minimum Value Maximum Value
uint8_t agcObsRxSelect 1 1 1

Table 102. Parameter Definitions for agcPeakThresholdMode 1

Data Type Parameter Value Note
uint8_t agcPeakThresholdMode 0 Power measurement detectors are enabled to make gain changes. Disables
APD/HB2 from making gain step increments.
1 (default) Power measurement detectors are disabled from making gain changes. Enables
APD/HB2 to make gain step increments
1
All values greater than 1 result in an error.
Table 103. Parameter Definitions for agcLowerThreshPreventGainIncrease 1
Data Type Parameter Value Note
uint8_t agcLowerThreshPreventGainInc 0 PMD lower thresholds increase gain; however, disregard if the APD/HB2 low
threshold is exceeded.
1 (default) PMD cannot increase gain when the APD/HB2 low thresholds are exceeded.
1
All values greater than 1 result in an error.

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AD9371/AD9375 System Development User Guide UG-992
AGC Lower Threshold Prevent Gain Increase The total number of IQ data rate clock cycles between expiration of
the AGC gain update counter is given by the following equation:
The agcLowerThreshPreventGainInc member of the
mykonosAgcCfg_t data structure prevents the gain index from IQ Clock Cycles = agcGainupdateCounter[21:0] +
incrementing in certain conditions when this bit is set to 1. This agcSlowLoopSettingDelay[4:0] (4)
is a 1-bit field. If this bit is set, the power measurement detector When the AGC gain update counter expires, the peak detectors
(PMD) cannot initiate a gain increment when either the analog and/or power measurement detectors are polled to determine if
peak detector (APD) or Half-Band 2 (HB2) low thresholds are a gain change is necessary. Gain increments can only occur on
exceeded. If this bit is cleared, APD or HB2 low thresholds are the termination of this counter. Gain decrements can occur at
ignored by the automatic gain control (AGC). the end of the counter or when the apdHighThreshExceededCnt
AGC Gain Update Counter or hb2HighThreshExceeddedCnt counters overflow (see
apdFastAttack and hb2FastAttack).
The automatic gain control (AGC) gain update time (denoted
by the agcGainUpdate-Counter member) is a member that The AGC gain update counter runs at the IQ data rate of the
determines the length of the gain update counter. The interval receiver. The following equation governs the AGC gain update
between the gain update counter expiration is determined by time (the left side indicates the value of the agcGainUpdateCounter
agcGainUpdateCounter and agcSlowLoopSettlingDelay, though for a given gain update counter length on the right side):
agcGainUpdateCounter length is typically several orders of agcGainupdateCounter[21:0] =
magnitude greater than the agcSlowLoopSettling delay. Refer agcGainupdateCounterLength (μs) × IQ Rate (MHz) (5)
to Figure 70 for a depiction of agcSlowLoopSettlingDelay and Using this equation, for an AGC gain update counter length of
agcGainUpdateCounter. 250 μs with an Rx profile that has an IQ data rate of 122.88 MHz,
the agcGainUpdateCounter setting is 30720 (decimal). Table 104
shows the limits of the agcGainUpdateCounter parameter.

EXPIRATION OF EXPIRATION OF EXPIRATION OF

agcGainUpdateCounter agcGainUpdateCounter agcGainUpdateCounter

TIME agcGainUpdateCounter agcGainUpdateCounter

14652-062
agcSlowLoopSettlingDelay agcSlowLoopSettlingDelay

Figure 70. AGC Gain Update Counter Timing Diagram

Table 104. Parameter Limits and Defaults for agcGainUpdateCounter

Data Type Parameter Default Value Minimum Value Maximum Value
uint32_t agcGainUpdateCounter 30720 (0x7800) 1 (0x000001) 4194303 (0x3FFFFF)

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UG-992 AD9371/AD9375 System Development User Guide
Table 105. Parameter Limits and Defaults for agcSlowLoopSettlingDelay
Data Type Parameter Default Value Minimum Value Maximum Value
uint8_t agcSlowLoopSettlingDelay 4 0 31 (0x1F)

Table 106. Parameter Limits and Defaults for agcPeakWaitTime

Data Type Parameter Default Value Minimum Value Maximum Value
uint8_t agcPeakWaitTime 2 2 31 (0x1F)

Table 107. Parameter Definitions for agcResetOnRxEnable 1

Data Type Parameter Value Note
uint8_t agcResetOnRxEnable 0 (default) AGC preserves state on falling edge of Rx enable or wait/radio off state
1 AGC resets on falling edge of Rx enable or wait/radio_off state
1
All values greater than 1 result in an error.

Table 108. Parameter Definitions for agcEnableSyncPulseForGainCounter 1

Data Type Parameter Value Note
uint8_t agcEnableSyncPulseForGainCounter 0 (default) AGC gain update counter operates as normal
1 AGC gain update counter can be synchronized to an external source
1
All values greater than 1 result in an error.

AGC Slow Loop Settling Delay The value of the agcPeakWaitTime member of the
mykonosAgcCfg_t data structure is the number of IQ data clock
The automatic gain control (AGC) slow loop settling delay cycles that elapse after using enabling AGC and prior to peak
(denoted by member agcSlowLoopSettlingDelay) determines detector circuits entering regular operation. This time is also
the number of IQ data rate clock cycles to wait after a gain the minimum time for the AGC to wait after detecting a peak.
change before resuming operation of the analog peak detector
(APD)/Half-Band 2 (HB2) or power measurement detector AGC Reset on Rx Enable
(PMD). This is a 5-bit field. This parameter allows the AGC to The AGC reset on Rx enable (denoted by member
ignore any transients associated with a gain change for the agcResetOnRxEnable) allows for a reset of the AGC when the
number of cycles indicated by this parameter. receiver is turned on. When this bit is set, the receiver resets the
If this parameter is set to 4, for example, the APD/HB2 and AGC to its initial state when the Rx is disabled. The gain index
PMD blocks are held in reset for four IQ data rate clock cycles is reset to the maximum condition when the Rx is disabled.
before resuming normal operation. Table 105 shows the limits When this bit is set to 0, the AGC holds its current state when
of the agcSlowLoopSettlingDelay. Rx enable is taken low. When Rx enable goes high again, AGC
continues its operation.
AGC Peak Wait Time
AGC Enable Sync Pulse for Gain Counter
The AGC peak wait time (denoted by member agcPeakWaitTime)
configures the amount of time that the gain control algorithm The AGC enable sync pulse for gain counter (denoted by the
waits before enabling regular operation of the peak detectors agcEnableSyncPulseForGainCounter member) allows
after AGC is enabled or a peak is detected. This is a 5-bit field. synchronization of the AGC gain update counter to beginning
The peak detectors in the receiver datapaths include the APD of time slots as signaled on GPIO pins. It is also required to call
and HB2 overrange detector. the MYKONOS_setRxAgcEnSyncPin(…)command before
synchronization can occur.

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AD9371/AD9375 System Development User Guide UG-992
mykonosPeakDetAgcCfg_t Data Structure For example, if the apdHighThresh is set as 0x1F, this
The following sections describe parameters within the data corresponds to a peak voltage of 512 mV peak, which is
structure mykonosPeakDetAgcCfg_t. This data structure approximately −2.8 dBFS.
contains several parameters that set the behavior of the peak If the received signal exceeds the apdHighThresh signal level
detector mode AGC. for the number of times set by the apdHighThreshExceededCnt
APD Thresholds during the agcGainUpdateCounter counter duration, a gain
decrease is made based on the apdGainStepAttack. The gain
Two members of the mykonosPeakDetAgcCfg_t data structure decrease can occur either at the expiration of the
determine the high and low threshold levels for the analog peak agcGainUpdateCounter or be made immediately when the
detector (APD) circuit. They are denoted by apdHighThresh apdHighThreshExceededCnt value is exceeded. The timing of
and apdLowThresh. Each are 6-bit fields. The APD determines the gain decrement is controlled by the apdFastAttack member.
if received signals contain peaks greater than or less than the
apdHighThresh and apdLowThresh signal threshold levels. The If the received signal does not exceed the apdLowThresh for the
following equations relate the value of the apdHighThresh and number of times set by the apdLowerThreshExceededCnt
apdLowThresh data structure members to the high and low within the agcGainUpdateCounter, a gain increase is made
peak voltage threshold levels. according to the apdGainStepRecovery member.

apdHighThresh (mV peak) = 16 mV × APD Threshold Counts

(apdHighThresh[D5:D0] + 1) (6) Two members determine the number of times the apdHighThresh
apdLowThresh (mV peak) = 16 mV × or apdLowThresh peak thresholds must be exceeded to trigger a
(apdLowThresh[D5:D0] + 1) (7) gain change. They are denoted by apdHighThreshExceededCnt
for the apdHighThresh threshold exceeded count and
The full-scale voltage of the Rx/ORx ADC is 707 mV peak. The
apdLowThreshExceededCnt for the apdLowThresh threshold
APD thresholds can be approximated in −dBFS with the following
exceeded count. When the count value exceeds the
equation, which is an approximation because some roll-off is
apdHighThreshExceededCnt, a gain index decrement of
introduced by the analog transimpedance amplifier (TIA) low-
apdGainStepAttack indices occurs at a time determined by the
pass filter (LPF) prior to the APD circuitry.
apdFastAttack data structure member. When the count value
Threshold (dBFS) = does not exceed the apdLowThreshExceededCnt within the
20 × log((Threshold (mV peak)/707 mV peak) (8) duration of the agcGainUpdateCounter, a gain index increment
of apdGainStepRecovery indices occurs at the expiration of the
agcGainUpdate-Counter.

Table 109. Parameter Limits and Defaults for apdHighThresh/apdLowThresh 1

Data Type Parameter Default Value Minimum Value Maximum Value
uint8_t apdHighThresh 0x1F 0 0x3F
uint8_t apdLowThresh 0x16 0 0x3F
1
Do not use values less than 0x7.

Table 110. Parameter Limits and Default Values for apdHighThreshExceededCnt/apdLowThreshExceededCnt

Data Type Parameter Default Value Minimum Value Maximum Value
uint8_t apdHighThreshExceededCnt 6 0 255
uint8_t apdLowThreshExceededCnt 4 0 255

Table 111. Parameter Limits and Default Values for apdHighGainStepAttack

Data Type Parameter Default Value Minimum Value Maximum Value
uint8_t apdHighGainStepAttack 2 0 31

Table 112. Parameter Limits and Default Values for apdLowGainStepRecovery

Data Type Parameter Default Value Minimum Value Maximum Value
uint8_t apdLowGainStepRecovery 2 0 31

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UG-992 AD9371/AD9375 System Development User Guide
APD Gain Step Attack The following equations provide the threshold levels for the
The analog peak detector (APD) gain step attack (denoted HB2 overload detector.
by apdHighGainStepAttack) is a member that determines hb 2 HighdBFS

the number of gain indices decremented when the hb2HighThresh[7 : 0] = 256 × 10 20 (9)
apdHighThreshExceededCnt counter is exceeded, which is hb 2 Low dBFS
the APD overrange condition. When a received signal exceeds hb2LowThresh[7 : 0] = 256 × 10 20 (10)
the apdHighThresh level the number of times set by the
hb 2VeryLow dBFS
apdHighThreshExceededCnt, the gain is decremented by the
hb2VeryLowThresh[7 : 0] = 256 × 10 20 (11)
number of indices specified by the apdHighGainStepAttack.
The apdFastAttack member can control the timing of the gain The hb2HighThresh sets a threshold for HB2 overrange conditions.
decrement. If the received signal exceeds the hb2HighThresh the number of
Set the value of this member as the number of gain steps to times specified by hb2HighThreshExceededCnt, the AGC makes a
decrement during APD overrange conditions. This step size gain decrement according to the hb2HighGainStepAttack member,
depends on the application and the implemented gain table. It which is similar to the behavior of the APD high threshold
is recommended to make this step size the same step size as the detection. The timing of the gain decrement is according to the
hb2GainStepAttack parameter. hb2FastAttack bit.

APD Gain Step Recovery Note that the apdHighThresh overload has a higher priority
than the hb2HighThresh overload. If the detected signal exceeds
The analog peak detector (APD) gain step recovery (denoted by both the apdHighThresh and the hb2HighThresh levels for their
apdLowGainStepRecovery) is a member that determines the respective counter values, the AGC makes a gain increment
number of gain indices incremented when the apdLowThresh- according to the higher priority detector gain step, namely,
ExceededCnt counter is not exceeded. This is the APD apdGainStepAttack.
underrange condition. When a received signal does not
The hb2LowThresh sets a threshold for HB2 underrange
exceed the apdLowThresh level the number of times set by the
conditions. If the detected signal does not exceed the
apdLowThreshExceededCnt, the gain is incremented by the
hb2LowThresh the number of times specified by
number of indices specified by the apdLowGainStepRecovery.
hb2LowThreshExceededCnt, the AGC makes a gain
The gain step always occurs at the end of expiration of the
increment according to the HB2 low recovery gain step
agcGainUpdateCounter.
member, hb2LowGainStepRecovery.
Set the value of this member as the number of gain steps to
The hb2VeryLowThresh sets a lower threshold than
increment during APD underrange conditions. This step size
hb2LowThresh to allow faster gain recovery. If the detected
depends on the application and the implemented gain table. It is
signal does not exceed the hb2VeryLowThresh the number of
recommended to make this step size the same step size as the
times specified by hb2VeryLowThreshCnt, the AGC makes a
hb2GainStepRecovery parameter.
gain increase according to the HB2 very low recovery gain step
HB2 Thresholds member hb2VeryLowGainStepRecovery.
Three members determine the high, low, and very low From Equation 9, Equation 10, and Equation 11, the thresholds
threshold levels for the Receive Half-Band 2 (HB2) overload must be input such that the magnitude of the following:
detector. They are denoted by hb2HighThresh, hb2LowThresh,
hb2HighThresh (dBFS) > hb2LowThresh (dBFS) >
and hb2VeryLowThresh (see Table 113). The HB2 overload
hb2VeryLowThresh (dBFS) (12)
detector determines if the decimated data at the output of
the receiver HB2 digital decimation filter exceeds the
hb2HighThresh, hb2LowThresh, and hb2VeryLowThresh.

Table 113. Parameter Limits and Default Values for Half-Band 2 (HB2) Thresholds
Data Type Parameter Default Value Minimum Value Maximum Value
uint8_t hb2HighThresh 0xB5 0 255
uint8_t hb2LowThresh 0x80 0 hb2HighThresh
uint8_t hb2VeryLowThresh 0x40 0 hb2LowThresh

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AD9371/AD9375 System Development User Guide UG-992
HB2 Threshold Counts Set the value of this member as the number of gain steps to
Three members determine the number of times the Half- decrement during HB2 overrange conditions. This step size
Band 2 (HB2) thresholds must be exceeded to trigger a gain depends on the application and the implemented gain table. It is
change. These members are hb2HighThreshExceededCnt recommended to make this step size the same step size as the
for the hb2HighThresh threshold exceeded count, apdGainStepAttack parameter.
hb2LowThreshExceeededCnt for the hb2LowThresh threshold HB2 Gain Step Recovery
exceeded count, and hb2VeryLowThreshExceededCnt for the Two members allow recovery from the HB2 underrange
hb2VeryLowThresh threshold exceeded count. conditions (denoted by hb2LowGainStepRecovery and
For HB2 overrange conditions, the HB2 overload detector must hb2VeryLowGainStepRecovery). If the underrange condition
detect greater than hb2HighThreshExceededCnt number of is with respect to the hb2VeryLowThresh, the gain index increment
overloads above the hb2HighThresh within the agcGain- is made according to the hb2VeryLowGainStepRecovery. If the
UpdateCounter. underrange condition is with respect to the hb2LowThresh,
For HB2 underrange conditions, the HB2 overload detector the gain index increment is made according to the
must detect less than hb2LowThreshExceededCnt or hb2LowGainStepRecovery. It is recommended to set the
hb2VeryLowThreshExceededCnt number of overloads above hb2VeryLowGainStepRecovery parameter larger than the
the hb2LowThresh or hb2VeryLowThresh, respectively. These hb2LowGainStepRecovery to enable quicker recovery. The
overloads must be detected within the agcGainUpdateCounter. timing of the gain index step occurs at the expiration of the
agcGainUpdateCounter.
HB2 Gain Step Attack
APD and HB2 Fast Attack Setting
The HB2 gain step attack (hb2HighGainStepAttack) is a member
that determines the number of gain indices decremented when the The automatic gain control (AGC), in analog peak detector
hb2HighThreshExceededCnt counter is exceeded, which is the (APD) and HB2 overrange conditions, can be programmed to
HB2 overrange condition. When a received signal exceeds the make a gain step immediately when the overrange occurs or to
hb2HighThresh level the number of times set by the make the gain step occur at the end of the agcGainUpdateCounter.
hb2HighThreshExceededCnt, the gain is decremented by the It is recommended to set the fast attack bits for the APD and
number of indices specified by the hb2HighGainStepAttack. HB2. The fast attack setting is controlled by the apdFastAttack
The timing of the gain decrement is controlled by the for APD overrange conditions, and hb2FastAttack for HB2
hb2FastAttack member. overrange conditions. These are both 1-bit fields.

Table 114. Parameter Limits and Default Values for HB2 Threshold Counters
Data Type Parameter Default Value Minimum Value Maximum Value
uint8_t hb2HighThreshExceededCnt 6 0 255
uint8_t hb2LowThreshExceededCnt 4 0 255
uint8_t hb2VeryLowThreshExceededCnt 4 0 255

Table 115. Parameter Limits and Default Values for apdHighGainStepAttack

Data Type Parameter Default Value Minimum Value Maximum Value
uint8_t hb2HighGainStepAttack 2 0 31

Table 116. Parameter Limits and Default Values for apdHighGainStepAttack

Data Type Parameter Default Value Minimum Value Maximum Value
uint8_t hb2LowGainStepRecovery 2 0 31
uint8_t hb2VeryLowGainStepRecovery 4 0 31

Table 117. Parameter Definitions for Fast Attack Settings

Data Type Parameter Value Note
uint8_t apdFastAttack 0 In response to APD overrange, gain decrement occurs at the expiration of the
agcGainUpdateCounter
1 (default) In response to APD overrange, gain decrement occurs immediately
uint8_t hb2FastAttack 0 In response to HB2 overrange, gain decrement occurs at the expiration of the
agcGainUpdateCounter
1 (default) In response to HB2 overrange, gain decrement occurs immediately

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UG-992 AD9371/AD9375 System Development User Guide
HB2 Overload Detect Enable mykonosPowerMeasAgcCfg_t Data Structure
The hb2OverloadDetectEnable parameter is a 1-bit field that The following sections describe parameters within the
enables the High-Band 2 (HB2) detector. It is recommended to mykonosPowerMeasAgcCfg_t data structure. This data
set this bit. structure contains several parameters that set the behavior of
the power measurement mode automatic gain control (AGC).
HB2 Overload Duration Count
PMD Thresholds
The HB2 overload duration count (hb2OverloadDurationCnt)
specifies the size of the window of IQ data rate clock cycles There are four thresholds for the power measurement detector
to meet the overload count set in hb2OverloadThreshCnt to (PMD) that correspond to four gain step sizes. The PMD
increment the HB2 overload detector counters. This is a 3-bit thresholds are located in the mykonosPowerMeasAgcCfg_t
field. If the number of overload counts set in hb2Overload- data structure. The members that set the threshold levels are,
ThreshCnt is exceeded within the window of IQ data rates from highest signal power to lowest, pmdUpperHighThresh,
provided by hb2OverloadThreshCnt, the counter increments, pmdUpperLowThresh, pmdLowerHighThresh, and pmdLower-
which avoids double counting overload instances. LowThresh. The pmdUpperLowThresh and pmdLowerHigh-
Thresh are 7-bit fields that set the absolute threshold level. The
HB2 Overload Threshold Count
pmdUpperHighThresh and pmdLowerLowThresh are 4-bit
The 4-bit field hb2OverloadThreshCnt specifies the number of fields that set offset thresholds relative to pmdUpperLowThresh
individual overload instances within the number of samples and pmdLowerHighThresh.
given by hb2OverloadDurationCnt required to increment the
Each LSB of the threshold words corresponds to 1 dBFS. The
HB2 overload detector counter. For example, if hb2Overload-
threshold levels corresponding to the default PMD thresholds
DurationCnt = 1 (sample size of 4) and hb2OverloadThreshCnt
are −2 dBFS, −3 dBFS, −12 dBFS, and −16 dBFS for pmdUpper-
is 1, then 1 overload instance must be detected within the duration
HighThresh, pmdUpperLowThresh, pmdLowerHighThresh,
of the receiver HB2 overload duration count to trigger the
and pmdLowerLowThresh, respectively.
receiver HB2 overload detector signal. Each LSB in this field
maps to a single sample. The default is 1. The application programming interface (API) returns an error
if pmdUpperLowThresh is set greater than (smaller signal) or
equal to pmdLowerHighThresh.
Table 118. Parameter Definitions for hb2OverloadDetectEnable
Data Type Parameter Value Note
uint8_t hb2OverloadDetectEnable 0 HB2 overload detector disabled
1 (default) HB2 overload detector enabled

Table 119. Parameter Definitions for Fast Attack Settings

Data Type Parameter Value Window Size for HB2 Overload
uint8_t hb2OverloadDurationCnt 0 1
1 (default) 4
2 8
3 12
4 16
5 24
6 32
>7 Invalid

Table 120. Parameter Limits and Default Values for PMD Thresholds
Data Type Parameter Bit Width Default Value Minimum Value Maximum Value
uint8_t pmdUpperHighThresh 4 1 0 15
uint8_t pmdUpperLowThresh 7 3 0 127
uint8_t pmdLowerHighThresh 7 12 0 127
uint8_t pmdLowerLowThresh 4 4 0 15

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AD9371/AD9375 System Development User Guide UG-992
PMD Gain Steps input clock rate (see Figure 57 and Figure 58). The value of
Each of the power measurement detector (PMD) thresholds this member value must satisfy the following relationship with
has a corresponding gain step. If the detected power is greater the agcGainUpdateCounter. Equation 13 assumes that the
than the pmdUpperHighThresh or pmdUpperLowThresh pmdMeasDuration is specified in IQ data rate clock cycles.
threshold, a gain decrement is made according to pmdUpper- Divide pmdMeasDuration by the RFIR decimation factor if
HighGainStepAttack or pmdUpperLowGainStepAttack. When the HB2 output is used.
both power thresholds are exceeded, the gain step is made agcGainUpdateCounter[21:0] > 8 × 2pmdMeasDuration (13)
according to pmdUpperHighGainStepAttack. PMD Measurement Configuration
If the detected power is less than pmdLowerHighThresh or The measurement configuration of the power measurement
pmdLowerLowThresh, a gain increment is made according blocks (denoted by pmdMeasConfig) determines where in the
to pmdLowerHighGainStepRecovery or pmdLowerLow- receiver signal chain the measurement takes place. There are
GainStepRecovery. When both lower power thresholds are three locations where decimated power measurements can
not exceeded, the gain step is made according occur: the output of the finite impulse response (RFIR), the
to pmdLowerLowGainStepAttack. output of the Half-Band 2 (HB2) filter, and the output of the
Because the inner thresholds (pmdUpperLowThresh and BBDC2. This member also controls an enable bit that can
pmdLowerHighThresh) are closer to the desired received signal disable the power measurement detector (PMD) block. See
power than the outer thresholds (pmdUpperHighThresh and Table 123 for details.
pmdLowerLowThresh), it is recommended to make the inner Enabling the PMD at the RFIR output allows only the filtered
gain steps (pmdUpperLowGainStepAttack and pmdLower- data (after the RFIR) to be used to determine the power. In this
HighGainStepRecovery) smaller than the outer gain steps mode, the measurement duration word (pmdMeasDuration)
(pmdUpperHighGainStepAttack and pmdLowerLowGain- obeys Equation 13 because the sample rate is at the IQ data rate,
StepRecovery). This allows the gain to recover very quickly if which is the recommended setting for the PMD.
the signal is far underrange, then slows the recovery as it
approaches the desired received power. Enabling the PMD at the HB2 output increases the bandwidth
of the power measurement approximately by a factor of 2,
PMD Measurement Duration which allows more out of band blocker energy into the
The measurement duration of the power measurement blocks power measurement. When PMD is enabled, note that
(denoted by pmdMeasDuration) sets the number of samples that pmdMeasDuration is determined using the RFIR input clock
the power measurement blocks use to evaluate the received signal rate, which is not necessarily the same as the IQ data rate. This
power level. This counter counts at either the IQ data rate (if refers to pmdMeasDuration at the input clock rate to the RFIR,
receiver finite impulse response (RFIR) or Baseband DC 2 (BBDC2) not necessarily the IQ data rate.
is chosen as the measurement configuration) or at the RFIR
Table 121. Parameter Limits and Default Values for PMD Gain Steps
Data Type Parameter Bit Width Default Value Minimum Value Maximum Value
uint8_t pmdUpperHighGainStepAttack 5 4 0 31
uint8_t pmdUpperLowGainStepAttack 5 2 0 31
uint8_t pmdLowerHighGainStepRecovery 5 2 0 31
uint8_t pmdLowerLowGainStepRecovery 5 4 0 31

Table 122. Parameter Limits and Default Values for pmdMeasDuration

Data Type Parameter Default value Minimum Value Maximum Value
uint8_t pmdMeasDuration 8 0 15

Table 123. Parameter Definitions for pmdMeasConfig

Data Type Parameter Value Note
uint8_t pmdMeasConfig 0 PMD disabled
1 PMD enabled at the HB2 output
2 (default) PMD enabled at the RFIR output
3 PMD enabled at the BBDC2 output

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UG-992 AD9371/AD9375 System Development User Guide
SUMMARY OF THE AGC PARAMETERS
This section provides a summary of all automatic gain control (AGC) data structure parameters, limits, and members. For information
about the parameters and their meanings, refer to the previous sections in this user guide.
Table 124. Parameter Limits and Default Values for mykonosAgcCfg_t
Data Type Parameter Bit Width Default Value Minimum Value Maximum Value
uint8_t agcRx1MaxGainIndex 8 255 agcRx1MinGainIndex 255
uint8_t agcRx1MinGainIndex 8 195 Minimum Rx1 table index agcRx1MaxGainIndex
uint8_t agcRx2MaxGainIndex 8 255 agcRx2MinGainIndex 255
uint8_t agcRx2MinGainIndex 8 195 Minimum Rx2 table index agcRx2MaxGainIndex
uint8_t agcObsRxMaxGainIndex 8 255 agcObsRxMinGainIndex 255
uint8_t agcObsRxMinGainIndex 8 203 Minimum ORx table index agcObsRxMaxGainIndex
uint8_t agcObsRxSelect 1 1 1 1
uint8_t agcPeakThresholdMode 1 1 0 1
uint8_t agcLowThsPreventGainIncrease 1 1 0 1
uint32_t agcGainUpdateCounter 22 30720 1 0x3FFFFF
uint8_t agcSlowLoopSettlingDelay 7 3 0 127
uint8_t agcPeakWaitTime 5 2 2 31
uint8_t agcResetOnRxEnable 1 0 0 1
uint8_t agcEnableSyncPulseForGainCounter 1 0 0 1
*mykonosPeakDetAgcCfg_t
*mykonosPowerMeasAgcCfg_t

Table 125. Parameter Limits and Default Values for mykonosPeakDetAgcCfg_t

Data Type Parameter Bit Width Default Value Minimum Value Maximum Value
uint8_t apdHighThresh 6 31 apdLowThresh 63
uint8_t apdLowThresh 6 22 0 apdHighThresh
uint8_t hb2HighThresh 8 181 hb2LowThresh 255
uint8_t hb2LowThresh 8 128 hb2VeryLowThresh hb2HighThresh
uint8_t hb2VeryLowThresh 8 64 0 hb2LowThresh
uint8_t apdHighThreshExceededCnt 8 6 0 255
uint8_t apdLowThreshExceededCnt 8 4 0 255
uint8_t hb2HighThreshExceededCnt 8 6 0 255
uint8_t hb2LowThreshExceededCnt 8 4 0 255
uint8_t hb2VeryLowExceededCnt 8 4 0 255
uint8_t apdHighGainStepAttack 5 4 0 31
uint8_t apdLowGainStepRecovery 5 2 0 31
uint8_t hb2HighGainStepAttack 5 4 0 31
uint8_t hb2LowGainStepRecovery 5 2 0 31
uint8_t hb2VeryLowGainStepRecovery 5 4 0 31
uint8_t apdFastAttack 1 1 0 1
uint8_t hb2FastAttack 1 1 0 1
uint8_t hb2OverloadDetectEnable 1 1 0 1
uint8_t hb2OverloadDurationCnt 3 1 0 7
uint8_t hb2OverloadThreshCnt 4 1 0 15

Table 126. Parameter Limits and Default Values for mykonosPowerMeasAgcCfg_t

Data Type Parameter Bit Width Default Value Minimum Value Maximum Value
uint8_t pmdUpperHighThresh 4 1 0 15
uint8_t pmdUpperLowThresh 7 3 0 pmdLowerHighThresh
uint8_t pmdLowerHighThresh 7 12 pmdUpperLowThresh 127
uint8_t pmdLowerLowThresh 4 4 0 15
uint8_t pmdUpperHighGainStepAttack 5 4 0 31
uint8_t pmdUpperLowGainStepAttack 5 2 0 31
uint8_t pmdLowerHighGainStepRecovery 5 2 0 31
uint8_t pmdLowerLowGainStepRecovery 5 4 0 31
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AD9371/AD9375 System Development User Guide UG-992
DIGITAL GAIN COMPENSATION, SLICER, AND FLOATING POINT FORMATTER
3-PIN CONTROL TO
BBP (SLICER)

DIGITAL DC SLICER/ TO DIGITAL

DECIMATED Rx DIGITAL OFFSET FLOATING BASEBAND
DATA GAIN COMPENSATION
CORRECTION POINT INTERFACE

EXTRA BITS
ADDED TO 16-BIT
DATAPATH DATA

GAIN CONTROL BLOCK

(ANY MODE)

14652-063
Figure 71. Gain Compensation, Floating Point Formatter, and Slicer Section of the Receiver Datapath

The device contains a digital gain compensation block that, if Digital Gain Compensation
enabled, provides digital gain compensation to offset the gain The digital gain compensation block is capable of fine
reduction from the receiver. Gain compensation allows variation in adjustments in digital gain at a minimum resolution of 0.25 dB
the receiver gain to be transparent to the baseband processor over a total compensation range of 31.75 dB. Gain compensation
(BBP), which can be useful in applications where the gain index occurs only digitally. Gain compensation compensates for changes
may change quickly, leading to undesirable amplitude variations in receiver gain in MGC mode, hybrid mode, and AGC mode.
seen in the BBP that may cause problems with demodulation.
There are two gain table requirements for gain compensation to
Gain compensation is useful in an automatic gain control
work properly:
(AGC) application where the onset of an interferer can force a
sharp and potentially quick reduction in the receiver gain.  Gain table steps (dB) between adjacent indices must be
Without gain compensation, the BBP must request the current uniform throughout the range of the table.
gain index to recover the input signal level from the device via  The gain table step size must be one of the following
an SPI command, which can take much longer than using gain options: 0.25 dB, 0.5 dB, 1 dB, 2 dB, 3 dB, 4 dB, or 6dB.
compensation.
The digital gain compensation uses the programmable gain
Gain compensation can be used in manual gain control (MGC) table step parameter (mykonosGainComp_t → compStep) and
mode, hybrid mode, and AGC mode. The gain compensation how many gain indices from the maximum gain index the
block is capable of applying up to 31.75 dB of digital gain receiver is operating at to set the digital gain compensation level.
compensation, which is sufficient to compensate for the full Figure 72 shows this behavior.
attenuation range supported by the Rx datapath.
The gain compensation, slicer, and floating point formatter
blocks are shown in Figure 71.
Y GAIN INDICES FROM
The bit width at the output of the digital gain compensation GAIN INDEX 245 MAXIMUM GAIN
x dB CONDITION
block is several bits wider than its input. This increase in bit GAIN STEP
width allows support for up to 31.75 dB of gain compensation. GAIN INDEX 244
x dB
The JESD204B data interface supports up to 16-bit data. GAIN STEP
Depending on the amount of compensation applied, the datapath GAIN INDEX 243
may exceed the maximum or minimum value allowed by 16-bit x dB
GAIN STEP
signed integers. To accommodate the expanded bit width in the
GAIN INDEX 242
Rx datapath under gain compensation, two methods are available
to send data to a BBP. These two methods are the slicer and the
14652-064

floating point formatter. The slicer requires three GPIO pins per
receiver. The floating point formatter does not require GPIO pins.
Figure 72. Gain Compensation Parameters for Setting the Digital Gain
Compensation Level

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UG-992 AD9371/AD9375 System Development User Guide
In Figure 72, assume the maximum gain index is 255, and the must be left shifted by 1 bit to recover the original value. When the
gain table step size is 0.5 dB (the default gain table). In the case slicer position is 1, 1 LSB is not sent to the BBP.
that the user selects Gain Index 245, the gain index choice The shift position of 1 is shown in Figure 73. When the shift
results in 5 dB (10 × 0.5 dB) total attenuation. If gain position is 1, bits above B17 are not used. Using the default gain
compensation is enabled, the digital gain compensation adds table and gain compensation configuration, this scenario occurs
5 dB gain (x × y dB) in the digital datapath. when the gain index is set between 254 and 243, or when gain
The gain compensation block is capable of compensating gain compensation is greater than 0 dB and less than 6 dB.
for an external attenuator; however, the table must conform to Table 127 provides information regarding how the amount of
the dB step sizes previously listed. gain compensation affects the slicer position, the shift value,
When digital compensation is enabled, there are potentially and the value expressed over the three GPIO slicer pins. This
6 bits added into the datapath. Not all of these bits can fit into information assumes that the default gain tables are used and that
the 16-bit JESD204B datapath. The device features two methods the gain compensation block is programmed correctly. The slicer
to overcome this limitation: the slicer and the floating point position indicates the reduction, in dB, of the data prior to
formatter. transmission over the JESD204B interface. The shift value
Slicer indicates the number of bits to shift the data in the BBP to
recover the original data. Recall that the amount of gain
The slicer allows 16-bit data transmission over the JESD204B
compensation per LSB from maximum gain condition is
interface along with a 3-bit shift value sent over three GPIO pins
programmable via the mykonosGainComp_t → compStep
per receiver. Six GPIO pins are required if the application uses both
parameter.
Rx1 and Rx2. The slicer bit shifts data down prior to
transmission over the JESD204B interface, such that the The BBP monitors the state of the slicer pins to shift the data to
16 MSBs of data are sent to the baseband processor (BBP). the original signal level. These pins are listed as follows. Note
that no other GPIO pins can be used to indicate the slicer
Slicer Output Mode position. The pins must be set to GPIO_SLICER_OUT_MODE,
The shift value, expressed over GPIO, informs the BBP how and the output must be enabled by the GPIO configuration for
many bits the JESD204B data has shifted. The shift value proper operation. The following groupings are listed from MSB
depends on the amount of gain compensation applied. If the to LSB:
gain index is at its maximum condition, the shift value is zero
 For Rx1, use GPIO10, GPIO9, and GPIO8.
because no shift in the data is necessary (no digital gain
 For Rx2, use GPIO14, GPIO13, and GPIO12.
compensation is applied). If the gain index is reduced from the
 For ORx, use GPIO18, GPIO17, and GPIO16.
maximum gain condition by 1 LSB (for example, 255 to 254), the
shift value is set to 1 to indicate to the BBP that the JESD204B data

SLICER SHIFT POSITION = 1

B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 GAIN COMPENSATED
DATA

B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 JESD204B DATA

0 0 1 14652-065

GPIO SHIFT VALUE

(ADD 6dB IN BBP)

Figure 73. Mapping of Data from Digital Gain Compensation to JESD204B Interface with Slicer Position = 1

Table 127. GPIO Output State for Slicer Position

Gain Compensation (dB) Slicer Position (dB) Shift Value Rx1/Rx2 Slicer GPIO Value (3-Bit)
0 0 0 0
0.25 to 5.75 6 1 1
6 to 11.75 12 2 2
12 to 17.75 18 3 3
18 to 23.75 24 4 4
24 to 29.75 30 5 5
30 to 31.75 36 6 6

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AD9371/AD9375 System Development User Guide UG-992
Slicer Input Mode after adding a bias to the actual exponent value. The user is able
to switch the order from (sign, exponent, significand) to (sign,
Alternatively, the slicer is able to take an input shift value over significand, exponent) if desired.
the GPIO pins and shift the data as desired to allow the baseband MSB LSB MSB LSB
processor (BBP) to set a desired digital gain instead of letting S E (BIASED SIGNIFICAND
EXPONENT)
the slicer position and gain compensation be determined by the

14652-066
w t
internal gain control block. When gain compensation is enabled,
the user must call the MYKONOS_setSlicerCtrl(…) command Figure 74. Floating Point Number Representation
to use this functionality and assign the GPIO pins for this The total precision for the significand is p = t + 1. If t = 10, that
purpose. The user is able to set a slicer gain step for each LSB means 10 bits of the significand are stored explicitly and 1 bit is
over the three slicer input pins of 1 dB, 2 dB, 3 dB, and 4 dB. a sign bit, leading to 11 bits of significand precision.
The valid GPIO pins for the slicer input mode are configurable For example, if the exponent is set as e, the stored exponent is
and include the pin groupings as follows (groupings are listed E = e + bias. The significand precision is p and the significand
from MSB to LSB): itself varies between 1.0 and 1 + 2(1 − p) × t. The value of the
 For Rx1, use the GPIO2, GPIO1, GPIO0 group, the GPIO7, floating point number (Value) is represented by the following
GPIO6, GPIO5 group, and the GPIO10, GPIO9, GPIO8 equation. This formula is important to decode information on
group. the BBP side of the JESD204B link.
 For Rx2, use the GPIO7, GPIO6, GPIO5 group and the Value = (−1)S × 2E − bias × (1 + 21 – p × t) (14)
GPIO13, GPIO12, GPIO11 group. where S is the sign bit (1 or 0).
 For ORx, use the GPIO18, GPIO17, GPIO16 group and the
GPIO16, GPIO15, GPIO14 group. The numbers have an implicit leading significand of 1 unless E = 0
and t = 0. In this case, the number is a signed 0.
Programming information is included in the API Support for Gain
If E = 0 and t ≠ 0, the number is referred to as a subnormal
Compensation, Slicer, and Floating Point Formatter section.
number, and the value is instead found by the following equation:
Floating Point Formatter
Value = (−1)S × 2e min × (0 + 21 – p × t) (15)
The floating point formatter offers an alternative method to
The device allows support for several different formats that
reduce the digital gain compensation output into 16-bit data
conform to the IEEE 754 standard and other formats that do
that can be sent over the JESD204B link. The floating point
not adhere to the IEEE 754 standard, called Analog Devices
formatter is located prior to the JESD204B interface on the
modes. These modes are described in Table 128.
receivers to minimize floating point arithmetic in the receiver
digital datapath. Representing the gain compensation output in Note that the first column in Table 128 includes the value of the
a 16-bit floating point results in a slight loss of resolution. To parameter leading the floating point formatter data structure,
minimize the loss of resolution, multiple modes are included in mykonosFloatPntFrmt_t. This data structure type is described
the device that are modifications to the IEEE 754 half precision in the Floating Point Formatter section. Table 128 shows that
binary floating point format (binary16). the Analog Devices modes of operation allow an increased
maximum value of the exponent.
Figure 74 shows the representation for the binary16 floating
point number. In Figure 74, w is the bit width of the exponent, The user has direct control over the first column (leading) and
and t is the bit width of the significand. The exponent is stored the second column (bit width of exponents). Selecting a desired
w value sets the bias for the exponent.

Table 128. Floating Point Formatter—IEEE 754 Modes Supported

Analog Devices/IEEE Mode Range of e
(Leading) w (Bit Width of Exponent) t (Bit Width of Significand) Precision (p) Bias (E − e) Min Max
IEEE (1) 5 10 11 15 −14 +15
IEEE (1) 4 11 12 7 −6 +7
IEEE (1) 3 12 13 3 −2 +3
IEEE (1) 2 13 14 1 0 +1
Analog Devices (0) 5 10 11 15 −15 +16
Analog Devices (0) 4 11 12 7 −7 +8
Analog Devices (0) 3 12 13 3 −3 +4
Analog Devices (0) 2 13 14 1 −1 +2

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UG-992 AD9371/AD9375 System Development User Guide
API Support for Gain Compensation, Slicer, and Floating A programming flowchart is provided in Figure 75. This diagram
Point Formatter begins where Figure 68 ends, at the completion of gain control
The application programming interface (API) allows setup. The diagram does not explicitly mention the configuration
configuration of the gain compensation, slicer, and floating of the GPIO pins. However, if the user sets up the GPIO pins in
point formatter. Important data structures and their members the device data structure prior to the initialization sequence, the
are outlined in this section. API commands are also described pins are still configured according to the device data structure.
throughout this section. These commands are necessary to
configure gain compensation, the slicer, or the floating point
formatter.

GAIN CONTROL
SETUP COMPLETE

USE GAIN YES SETUP GAIN COMPENSATION

COMPSENSATION? _setRxGainCompensation(...)

NO

YES USE INTERNAL YES

USE SLICER?
SLICER MODE?

NO NO
USE FLOATING POINT USE EXTERNAL SLICER MODE

SETUP FLOATING POINT SET UP SLICER CONTROL

_setFloatPointFrmt(...) _setRxSlicerCtrl(...)

ENABLE FLOATING POINT

_setRxEnFloatPntFrmt(...)

14652-067
GAIN COMPENSATION
SETUP COMPLETE

Figure 75. Rx Gain Compensation Programming Flowchart

Table 129. Parameter Limits and Default Values for mykonosGainComp_t

Data Type Parameter Bit Width Default Value Comments
uint8_t rx1Offset 5 0 This parameter contains the Rx1 offset word used for the gain
compensation when the gain index is at its maximum setting. This
parameter ranges from 0 to 0x1F with a resolution of 0.5 dB/LSB.
uint8_t rx2Offset 5 0 This parameter contains the Rx2 offset word used for the gain
compensation when the gain is at its maximum setting. This
parameter ranges from 0 to 0x1F with a resolution of 0.5 dB/LSB.
uint8_t compStep 3 1 This parameter sets the value (in dB) that gain compensation
applies to an LSB change in the gain index according to the
following settings.
compStep dB Step (dB)
0 0.25
1 0.5
2 1
3 2
4 3
5 4
6 6

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AD9371/AD9375 System Development User Guide UG-992
Gain Compensation Data Structure Parameters
The configuration parameters for the gain compensation block • *device: This is a pointer to the device data structure.
are set up in a data structure of type mykonosGainComp_t. The • *gainComp: This is a pointer to a mykonosGainComp_t
members of the data structure are described in Table 129. structure which holds the current device gain compensation
The data structure mykonosGainComp_t is not a part of the settings.
device data structure and does not need to be instantiated if • enable: This is a pointer to a parameter containing the
gain compensation is not used in the user application. enable state of the gain compensation block (enabled = 1
Gain Compensation API Commands and disabled = 0).

The application programming interface (API) uses the SLICER API COMMANDS AND GPIO INFORMATION
MYKONOS_setRxGainCompensation(…) command to The slicer can be configured in two different ways. The first
configure internal device registers for a desired gain method allows the slicer to determine its own position based on
compensation configuration. This command does not the receiver gain index and output the slicer position value over
determine whether the slicer or the floating point formatter GPIO pins. The second method allows the baseband processor
is used. The command configures the gain compensation (BBP) to control the slicer position over the GPIO pins. Both
block for user values determined by the data structure methods require the gain compensation block to be enabled for
type mykonosGainComp_t. A description of the proper slicer functionality. There is no API data structure
mykonosGainComp_t data type is provided in Table 129. specific to the slicer setup.
MYKONOS_setRxGainCompensation(…) • If the user desires the BBP to read the slicer position over
mykonosErr_t the GPIO pin, and to use that position information to
MYKONOS_setRxGainCompensation(mykonosDevi appropriately shift the data, specific GPIO pins must be
ce_t *device, mykonosGainComp_t set as outputs in the proper mode. The Rx1 channel uses
*gainComp, uint8_t enable)
GPIO_10 to GPIO_8 to output the slicer position. The Rx2
Description channel uses GPIO_14 to GPIO_12 to output the slicer
MYKONOS_setRxGainCompensation(…) is the gain position. No other GPIO pins can be used to indicate the
compensation enable and setup function. slicer position. To configure the device to output the slicer
position over the GPIO signals, ensure that the GPIO pins
The gain compensation block is a function that compensates for
are set as outputs and that the mykonosGpioMode_t for
the attenuation in the internal attenuator for the Rx channels.
GPIO_11 to GPIO_8 and GPIO_15 to GPIO_12 are set to
Preconditions GPIO_SLICER_OUT_MODE.
The gain control setup must be complete. • If the user desires the BBP to control the slicer position, the
desired GPIO pins must be set for input control and the
Parameters
command listed in the following section must be run. This
• *device: This is a pointer to the device data structure. command configures specific sets of GPIO pins as inputs
• gainComp: This is a data structure containing the gain to the slicer (rx1Pins, rx2Pins), sets the step size of the
compensation settings. slicer when external pin control mode is enabled (slicerStep),
• enable: this parameter enables or disables the gain and enables or disables the external pin control feature
compensation block (enable = 1 and disable = 0). (enable). Refer to the following section for the valid pin
configurations. Set the mykonosGpioMode_t for
MYKONOS_getRxGainCompensation(…)
GPIO_BITBANG_MODE.
mykonosErr_t
MYKONOS_getRxGainCompensation(mykonosDevi MYKONOS_setRxSlicerCtrl(…)
ce_t *device, mykonosGainComp_t mykonosErr_t
*gainComp, uint8_t enable)
MYKONOS_setRxSlicerCtrl(mykonosDevice_t
Description *device, uint8_t slicerStep,
mykonosRxSlicer_t rx1Pins,
This function obtains the gain compensation setup and enabled
mykonosRxSlicer_t rx2Pins, uint8_t
function. enable);
The gain compensation block is a function that compensates for Description
the attenuation in the internal attenuator for the Rx channels.
This function is the slicer control over the GPIO inputs.
This function obtains the current setup and the enable state of
the block. The user can control the slicer position via three GPIO inputs
per channel. There are various configurations for the GPIO pins,
Preconditions
and these configurations are enumerated in the
The gain control setup must be complete. mykonosRxSlicer_t.
Rev. B | Page 159 of 360
UG-992 AD9371/AD9375 System Development User Guide
Preconditions A get version of this command is described in the following
Configure the gain control. section.
MYKONOS_getRxSlicerCtrl (…)
Parameters
mykonosErr_t
• *device: This is a pointer to the device data structure. MYKONOS_getRxSlicerCtrl(mykonosDevice_t
• slicerStep: The slicer configuration command also allows *device, uint8_t *slicerStep,
the user to set the slicer step size (slicerStep). The slicer mykonosRxSlicer_t *rx1Pins,
gain is equal to the 3-bit word expressed on the GPIO mykonosRxSlicer_t *rx2Pins, uint8_t
inputs multiplied by the step size. Table 130 shows the *enable);
relationship between the slicer step size and slicerStep Description
parameter value.
This function obtains the programmed slicer control for the
Table 130. slicerStep Parameter Related to dB Steps in the Slicer Rx1 and Rx2 channels.
slicerStep dB Step (dB) The user can control the slicer position via three GPIO inputs
0 1 per channel. There are various configurations for the GPIO
1 2 pins, and these configurations are enumerated in the
2 3 mykonosRxSlicer_t.
3 4 Preconditions
• Rx1Pins: The value of the mykonosRxSlicer_t enumeration Configure the gain control.
determines which grouping of three GPIO pins are used as Parameters
inputs to the device to set the 3-bit slicer position. The valid
• *device: This is a pointer to the device data structure.
pin groupings are listed as follows for the Rx1 channel,
from MSB to LSB, with the mykonosRxSlicer_t • slicerStep: This contains the configured step size.
enumeration value listed in parentheses: • rx1Pins: This contains the configured GPIO combination
• GPIO_2, GPIO_1, and GPIO_0 (GPIO_0_1_2). for Rx1.
• rx2Pins: This contains the configured GPIO combination
• GPIO_7, GPIO_6, and GPIO_5 (GPIO_5_6_7).
for Rx2.
• GPIO_10, GPIO_9, and GPIO_8 (GPIO_8_9_10).
• *enable: This contains the programmed enable setting.
• Rx2Pins: The value of the mykonosRxSlicer_t enumeration
determines which grouping of three GPIO pins are used as The slicer defaults to the first mode (internal mode) of
inputs to the device to set the 3-bit slicer position. The operation when gain compensation is enabled. The slicer is
valid pin groupings are listed as follows for the Rx2 channel, disabled if gain compensation is disabled. Note that enabling
from MSB to LSB, with the mykonosRxSlicer_t gain compensation does not configure the GPIO pins.
enumeration value listed in parentheses:
Floating Point Data Structure
• GPIO_7, GPIO_6, and GPIO_5 (GPIO_5_6_7).
• GPIO_10, GPIO_9, and GPIO_8 (GPIO_8_9_10). The configuration parameters for the floating point formatter
are set up in a data structure of type mykonosFloatPntFrmt_t.
• enable: set enable = 1 to enable the external pin control
The members of the data structure are described in Table 131.
for slicer. Set enable = 0 to disable external pin control for the
slicer.

Table 131. Parameter Limits and Default Values for mykonosFloatPntFrmt_t

Data Bit Default
Type Parameter Width Value Comments
uint8_t roundMode 2 0 This parameter sets the round mode for the significand. The following settings are defined
in the IEEE754 specification. For more information, consult Section 4.3 in IEEE 754-2008:
roundMode Round Mode
0 Round ties to even
1 Round towards positive
2 Round towards negative
3 Round towards 0
4 Round ties to away
uint8_t dataFormat 1 0 This parameter sets the format of the 16-bit output on the JESD204B interface.
dataFormat Format
0 MSB to LSB (sign, exponent, significand)
1 MSB to LSB (sign, significand, exponent)
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AD9371/AD9375 System Development User Guide UG-992
Data Bit Default
Type Parameter Width Value Comments
uint8_t encNan 1 0 If this parameter is set to 1, then the floating point formatter reserves the highest value of
exponent for NaN (not a number) to be compatible with the IEEE754 specification. Setting
this parameter to 0 increases the range of the exponent by 1.
uint8_t expBits 2 2 This parameter is used to indicate the number of exponent bits in the floating point
number according to the following settings.
expBits No. of Exponent Bits No. of Significand Bits No. of Sign Bits
0 2 13 1
1 3 12 1
2 4 11 1
3 5 10 1
uint8_t leading 1 1 Setting this parameter to 1 hides the leading one in the significand to be compatible to the
IEEE754 specification (IEEE mode). Clearing this parameter causes the leading one to be at
the MSB of the significand (Analog Devices mode).

FLOATING POINT API COMMANDS MYKONOS_getFloatPointFrmt(…)

mykonosGpioErr_t
The floating point formatter uses several application
MYKONOS_setFloatPointFrmt(mykonosDevice
programming interface (API) commands that configure _t *device,mykonosFloatPntFrmt_t
the floating point formatter, enable the Rx floating point *floatFrmt);
formatter, and enable the ORx floating point formatter. The
Description
floating point formatter uses the data structure of type
mykonosFloatPntFrmt_t to store configuration parameters. MYKONOS_getFloatPointFrmt(…) is the floating point
formatter setup function. This command obtains the
To set up the configuration parameters of the floating point
programmed floating point formatter settings.
formatter for Rx1, Rx2 and ORx, use the command described in
the following section. The floating point formatter block is a function that works in
conjunction with the gain compensating block, as the gain
MYKONOS_setFloatPointFrmt (…)
compensation requires increased dynamic range, which
mykonosGpioErr_t increases the bit width in the digital datapath.
MYKONOS_setFloatPointFrmt(mykonosDevice
_t *device,mykonosFloatPntFrmt_t Preconditions
*floatFrmt);
Configure the gain control.
Description
Parameters
Floating point formatter enable and setup function.
• *device: This is a pointer to the device data structure.
The floating point formatter block is a function that works in • *floatFrmt: a mykonosFloatPntFrmt_t data structure
conjunction with the gain compensating block, as the gain containing floating point formatter settings.
compensation requires increased dynamic range which
increases the bit width in the digital datapath. The following commands enable the floating point formatter.
The floating point formatter has separate enable commands for
Preconditions
Rx1/Rx2 and the ORx.
Configure the gain control.
MYKONOS_setRxEnFloatPointFrmt (…)
Parameters mykonosGpioErr_t
• *device: This is a pointer to the device data structure. MYKONOS_setFloatPointFrmt(mykonosDevice
_t *device, uint8_t rx1Att, uint8_t
• *floatFrmt: a mykonosFloatPntFrmt_t data structure
rx2Att, uint8_t enable)
containing floating point formatter settings.
Description
A get version of this command is described in the following
MYKONOS_setRxEnFloatPointFrmt (…) is the floating point
section.
formatter enable/disable function for Rx1 and Rx2.
The floating point formatter block is a function that works in
conjunction with the gain compensating block, as the gain
compensation requires increased dynamic range, which
increases the bit width in the digital datapath.

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UG-992 AD9371/AD9375 System Development User Guide
Preconditions MYKONOS_setOrxEnFloatPointFrmt (…)
Configure the gain control. mykonosGpioErr_t
MYKONOS_setOrxEnFloatPointFrmt(mykonosD
Parameters evice_t *device, uint8_t orxAtt,
• *device: This is a pointer to the device data structure. uint8_t enable)
• rx1Att: This parameter sets the integer data attenuation for Description
the Rx1 channel in 6 dB steps to enable the entire data MYKONOS_setOrxEnFloatPointFrmt (…) is the floating point
range to be represented in the selected floating point format. formatter enable/disable for the ORx channel.
• rx2Att: This parameter sets the integer data attenuation for
The floating point formatter block is a function that works in
the Rx2 channel in 6 dB steps to enable the entire data
conjunction with the gain compensating block, as the gain
range to be represented in the selected floating point format.
compensation requires increased dynamic range, which
• enable: This parameter enables or disables the gain
increases the bit width in the digital datapath.
compensation block (enable = 1 and disable = 0).
Preconditions
A get version of this command is described in the following
section. Configure the gain control.

MYKONOS_getRxEnFloatPointFrmt(…) Parameters
mykonosGpioErr_t • *device: This is a pointer to the device data structure.
MYKONOS_getRxEnFloatPointFrmt(mykonosDe • orxAtt: this parameter sets the integer data attenuation for
vice_t *device, uint8_t *rx1Att, the Rx1 channel in 6 dB steps to enable the entire data
uint8_t *rx2Att, uint8_t *enable) range to be represented in the selected floating point format.
Description • enable: This parameter enables or disables the gain
MYKONOS_getRxEnFloatPointFrmt(…) is the floating point compensation block (enable = 1 and disable = 0).
formatter readback function for Rx1 and Rx2. A get version of this command is noted in the following section.
The floating point formatter block is a function that works in MYKONOS_getOrxFloatPointFrmt(…)
conjunction with the gain compensating block, as the gain
mykonosGpioErr_t
compensation requires increased dynamic range, which MYKONOS_setFloatPointFrmt(mykonosDevice
increases the bit width in the digital datapath. _t *device, uint8_t rx1Att, uint8_t
Preconditions rx2Att, uint8_t enable)

Configure the gain control. Description

Parameters MYKONOS_getOrxFloatPointFrmt(…) is the floating point
formatter enable/disable Rx1 and Rx2 function.
• *device: This is a pointer to the device data structure.
The floating point formatter block is a function that works in
• *rx1Att: This parameter sets the integer data attenuation
conjunction with the gain compensating block, as the gain
for the Rx1 channel in 6 dB steps to enable the entire data
compensation requires increased dynamic range which
range to be represented in the selected floating point format.
increases the bit width in the digital datapath.
• *rx2Att: This parameter sets the integer data attenuation
for the Rx2 channel in 6d B steps to enable the entire data Preconditions
range to be represented in the selected floating point format. Configure the gain control.
• *enable: This parameter enables or disables the gain
Parameters
compensation block (enable = 1 and disable = 0).
• *device: This is a pointer to the device data structure.
• rx1Att: This parameter sets the integer data attenuation for
the Rx1 channel in 6 dB steps to enable the entire data
range to be represented in the selected floating point format.
• rx2Att: This parameter sets the integer data attenuation for
the Rx2 channel in 6 dB steps to enable the entire data
range to be represented in the selected floating point format.
• enable: This parameter enables or disables the gain
compensation block (enable = 1 and disable = 0).

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AD9371/AD9375 System Development User Guide UG-992

FILTER CONFIGURATION
This section describes the digital filters within the integrated the Create Config.c file for the Tx, Rx, ORx, and SnRx profile
transceiver. Descriptions of the main receivers, transmitters and data structures. Custom profiles can be generated using other
the observation/sniffer receiver system filters are provided. Also Analog Devices software tools that are not described in this
described in this section is an overview of the application section.
programming interface (API) data structures and commands
RECEIVER SIGNAL PATH
necessary to configure the digital filters for proper operation.
The main receivers have independent signal paths for the Rx1
Analog Devices uses profiles to designate different device and Rx2 ports. Each receiver signal path consists of an
configuration settings for the Tx, Rx, ORx, and SnRx channels. adjustable analog transimpedance low-pass filter, a Σ-Δ ADC,
When selecting a profile, note that Rx1 and Rx2 use the same and digital decimation filters. The fixed coefficient decimation
profile; Tx1 and Tx2 use the same profile; ORx1 and ORx2 use filters (RHB1, RHB2, RHB3, DEC5, and DEC5HR) are designed to
the same profile; and SnRxA, SnRxB, and SnRxC use the same eliminate overranging. The programmable receiver FIR filter
profile. The profile dictates how the digital filters, analog filters, (RFIR) in the Rx digital baseband path can overrange, depending
clock rates, and clock dividers are configured in the device. on coefficients. However, the RFIR output code is limited to a
Some specific parameters set by the profiles include the IQ data maximum code value when overrange conditions occur.
rate, ADC clock rate, analog filter corners, FIR filter coefficients,
and interpolation/decimation factors in the half-band filters. A block diagram of the Rx1 and Rx2 datapath is shown in
Figure 76. Quadrature error correction (QEC), dc offset
Several profiles can be examined in the transceiver evaluation correction, and digital gain are not described in this section.
software (TES) for given device clock frequencies. If the desired The following sections describe the functionality of the digital
profile exists in the software, it is recommended to set up the and analog filters and their configurations.
desired profile in and use the data structure values generated by

DEC5HR
Rx1 SIGNAL PATH, I AND Q CHANNEL

DEC5

RHB3 RHB2 RHB1 RFIR QEC DIG DC REAL

LPF I ADC
(2) (2) (1,2) (1,2,4) CORR GAIN CORR IF

RHB3 RHB2 RHB1 RFIR QEC DIG DC REAL

LPF Q ADC (2) (2) (1,2) (1,2,4) CORR GAIN CORR IF

JESD204B INTERFACE
DEC5HR
90°

DEC5

Rx LOGEN DEC5HR
SYNTHESIZER

DEC5

LPF I ADC RHB3 RHB2 RHB1 RFIR QEC DIG DC REAL

(2) (2) (1,2) (1,2,4) CORR GAIN CORR IF

LPF Q ADC RHB3 RHB2 RHB1 RFIR QEC DIG DC REAL

(2) (2) (1,2) (1,2,4) CORR GAIN CORR IF

DEC5HR
90°
14652-068
Rx2 SIGNAL PATH, I AND Q CHANNEL DEC5

Figure 76. Rx1 and Rx2 Signal Path Diagram

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UG-992 AD9371/AD9375 System Development User Guide
Low-Pass Filter The decimation factor for the first filter after the ADC is set
The Rx low-pass filter (LPF) is a transimpedance amplifier in the device data structure in device → rx → rxProfile →
(TIA) with a single, real pole frequency response. The 3 dB rxDec5Decimation. Set this parameter as 4 to use the series
bandwidth of the TIA LPF ranges from 20 MHz to 100 MHz. combination of the RHB3 and RHB2 filters.
The TIA LPF is calibrated based on the 3 dB bandwidth, resulting RHB1
in a consistent frequency corner across all devices. The TIA The Receiver Half Band 1 (RHB1) filter is a fixed coefficient
3 dB bandwidth is set within the device data structure and is decimating filter. RHB1 can decimate by a factor of 2, or it can
profile dependent. Roll-off within the analog TIA LPF pass be bypassed. The full scale for this filter is 16384 (214). The
band is compensated by the RFIR to ensure a maximally flat RHB1 coefficients are [+9, 0, −41, 0, +124, 0, −304, 0, +665, 0,
pass-band frequency response. −1473, 0, +5074, +8108, +5074, 0, −1473, 0, +665, 0, −304, 0,
The LPF bandwidth is set in the device data structure at device → rx +124, 0, −41, 0, +9].
→ rxProfile → rxBbf3dBCorner_kHz. The decimation factor for RHB1 is set in the device data
DEC5/DEC5HR structure in device → rx → rxProfile → rxDec5Decimation. This
The main Rx signal path features an option to use either the can be either 1 (bypass) or 2 (decimate by 2).
decimate by 5 (DEC5), the decimate by 5 high rejection Programmable Receiver Finite Impulse Response (RFIR)
(DEC5HR), or the series combination of the Receiver Half-Band 3 Filter
(RHB3) and Receiver Half-Band 2 (RHB2) digital decimation The programmable RFIR filter acts as a decimating filter. The
filters. The difference between the DEC5HR and the DEC5 RFIR can decimate by a factor of 1, 2, or 4, or it can be bypassed.
digital filters is that DEC5HR features a higher stop-band The RFIR can use a configurable number of taps from 24 taps to
rejection than DEC5. Both DEC5 and DEC5HR are fixed 72 taps in multiples of 24. The RFIR is typically used to compensate
coefficient, decimating filters. Full scale for the DEC5 digital for the roll-off of the analog TIA LPF and decimating filters.
filter is 8192 (213). Full scale for the DEC5HR is 32768 (215).
The maximum number of taps is limited by the FIR clock rate
Coefficients for the DEC5HR filter are [−64, −165, −305, −442, (data processing clock, DPCLK). The maximum DPCLK is
−499, −273, +280, +1208, +2433, +3762, +4866, +5503, +5503, 400 MHz. The DPCLK is the ADC clock rate divided by either 2
+4866, +3762, +2433, +1208, +280, −273, −499, −442, −305, or 4 to limit the DPCLK below 400 MHz when the DEC5 and
−165, −64]. DEC5HR are disabled. The DPCLK is the ADC clock rate
Coefficients for the DEC5 filter are [+18, +35, +56, +72, +70, divided by 5 or 10 to limit the DPCLK below 400 MHz when
+28, −38, −126, −209, −244, −184, −20, +256, +612, +976, DEC5 or DEC5HR are enabled.
+1273, +1448, +1448, +1273, +976, +612, +256, −20, −184, Maximum Number of Rx FIR Filter Taps =
−244, −209, −126, −38, +28, +70, +72, +56, +35, +18]. (DPCLK/Rx IQ Data Rate) × 24 (16)
The choice between DEC5 and DEC5HR is set in the device The RFIR coefficients are stored in the device data structure in
data structure in device → rx → rxProfile → enHighRejDec5. device → rx → rxProfile → *rxFir, which is a pointer to a
This parameter is typically set to 1 to enable the DEC5HR filter. structure with data type mykonosFir_t.
The decimation factor for the first filter after the ADC is set The RFIR decimation factor is set in the device data structure in
in the device data structure in device → rx → rxProfile → device → rx → rxProfile → rxFirDecimation, which can be either
rxDec5Decimation. Set this parameter as 5 to use the DEC5 1 (bypass), 2, or 4.
or DEC5HR path.
Real IF
RHB3
The real IF block contains an interpolating filter and
The Receive Half-Band 3 (RHB3) filter is a fixed coefficient upconversion mixer used to convert complex signals centered
decimating filter. RHB3 decimates by a factor of 2. The full scale around dc into real valued signals centered around an offset IF
for this filter is 16 (24). The RHB3 coefficients are [1, 4, 6, 4, 1]. frequency. The real IF conversion block is typically bypassed,
RHB2 but it does provide the capability to operate at an IF frequency
The Receive Half-Band 2 (RHB2) filter is a fixed coefficient near baseband for systems that prefer to perform complex
decimating filter. RHB2 decimates by a factor of 2. The series demodulation in their digital baseband. The full-scale value for
combination of RHB2 and RHB3 can be bypassed using the the real IF interpolating filter is 16384 (214). The filter
DEC5 or DEC5HR filter. The full scale for this filter is 128 (27). coefficients for the real IF filter are [−3, 0, +8, 0, −19, 0, +40, 0,
The RHB2 coefficients are [+1, +0, −7, 0, +38, +64, +38, 0, −7, −75, 0, +130, 0, −214, 0, +336, 0, −514, 0, +773, 0, −1169, 0,
0, +1]. +1845, 0, −3327, 0, +10380, +16384, +10380, 0, −3327, 0,
+1845, 0, −1169, 0, +773, 0, −514, 0, +336, 0, −214, 0, +130, 0,
−75, 0, +40, 0, −19, 0, +8, 0, −3].

Rev. B | Page 164 of 360

AD9371/AD9375 System Development User Guide UG-992
20
The real IF mode can be enabled in the device data structure in
device → rx → realIfData, which can be either 0 (disable real IF)
or 1 (enable real IF). –40

Rx SIGNAL PATH EXAMPLE

MAGNITUDE (dB)
The transceiver evaluation software (TES) provides examples –100

depicting how the baseband filtering stages are used for particular
profiles. In this example, the Rx = 100 MHz, the IQ rate = –160
122.88 MHz, and the DEC5 profile is selected for the Rx
channels. This profile is compatible with the other examples
–220 ADC
provided in this user guide. DIGITAL
Rx TIA
Descriptions of the profile name conventions are as follows: COMPOSITE
–280

14652-070
0 245.76 491.52 737.28 983.04 1228.8
 Rx 100 MHz, which implies a RF (complex) receiver
BASEBAND FREQUENCY (MHz)
bandwidth of 100 MHz. In Figure 77 and Figure 78, note
Figure 77. Main Receiver Filter Responses
that the profile pass band is set to 50 MHz because the real
IF mode is disabled and the received data is centered around An examination of the profile pass-band frequency shows that
dc. The filter responses are also symmetrical around dc. the Rx TIA 3 dB setting slightly attenuates information within
Only the positive half of the spectrum is shown. The pass the pass band. This analog attenuation is compensated by the
band extends from −50 MHz to +50 MHz in the figure, digital filter response to obtain a maximally flat pass band for
which corresponds to RF frequencies of ±50 MHz from the this profile. A zoom in view of the pass band is shown in Figure 78.
Rx LO frequency. 2

 IQ Rate 122.88 MHz refers to the IQ data rate across the

JESD204B interface.
1
 DEC5 string determines which profiles are compatible with
each other. A given Rx (or Tx, or SnRx, or ORx) profile can
MAGNITUDE (dB)

only be used if all profiles (Rx, Tx, SnRx, ORx) have the same 0

tag in the profile name string. Constraints in digital clocking

prevent using DEC5 profiles with non DEC5 profiles.
–1
Figure 79 shows the filter configuration for this profile,
excluding correction stage blocks such as dc offset correction.
–2
Note that the clocking frequencies are in blue. The signal rate ADC
DIGITAL
after the RFIR block is equal to the IQ data rate of the profile. Rx TIA
COMPOSITE
–3
Also available in the transceiver evaluation software (TES) Rx

14652-071
0 11.61 23.22 34.83 46.44 58.05
Summary tab is the frequency response of the analog BASEBAND FREQUENCY (MHz)
transimpedance amplifier (TIA) low-pass filter (LPF), digital Figure 78. Pass-Band Frequency Response of the Rx = 100 MHz, 122.88 MHz,
filters, the ADC transfer function, and the composite response DEC5 Profile (Pass Band Zoom In View)
from dc to the sampling rate of the ADC (see Figure 77).

14652-069

Figure 79. Filter Configuration for the Rx = 100 MHz, 122.88 MHz, DEC5 Profile

Rev. B | Page 165 of 360

UG-992 AD9371/AD9375 System Development User Guide
TRANSMITTER SIGNAL PATH THB1
The transmitter has independent signal paths for the Tx1 and The Transmit Half-Band 1 (THB1) is a fixed coefficient half-
Tx2 ports. The Tx signal path receives data from the JESD204B band interpolating filter. THB1 can interpolate by a factor of 2
interface block and sends this data through interpolating filters or it can be bypassed. The full-scale range for this filter is 8192 (213).
prior to a Σ-Δ DAC. The analog output of the DAC is low pass The THB2 filter coefficients are [+21, 0, −56, 0, +108, 0, −188, 0,
filtered by the Tx low-pass filter (LPF) prior to the upconversion +319, 0, −526, 0, +876, 0, −1632, 0, +5179, +8192, +5179, 0, −1632,
mixer. The I and Q paths are identical to one another. Overranging 0, +876, 0, −526, 0, +319, 0, −188, 0, +108, 0, −56, 0, +21].
is detected in the Tx digital signal path at each stage and is limited The THB2 interpolation factor is set by device → tx → txProfile →
to the maximum code value to prevent data wrapping. A block thb1Interpolation. Set this to either 1 (bypass) or 2.
diagram of the Tx1 and Tx2 signal paths is shown in Figure 80.
TFIR
Blocks are shown that correspond to the digital or analog filters in
the Tx datapath. The programmable transmitter finite impulse response (TFIR)
filter acts as a interpolating filter in the Tx path. The TFIR can
LPF
interpolate by a factor of 1, 2, or 4, or it can be bypassed. The
The low-pass filter (LPF) is an analog, second-order Butterworth TFIR is typically used to compensate for roll-off caused by the
LPF with an adjustable 3 dB corner. The LPF is calibrated based post DAC analog LPF. The TFIR can use a configurable number of
on the 3 dB bandwidth, resulting in a consistent frequency taps from 16 to 96 in multiples of 16.
corner across all devices. The transimpedance amplifier (TIA)
The maximum number of taps is limited by the TFIR clock rate
bandwidth is set within the device data structure and is profile
(data processing clock, DPCLK). The maximum DPCLK is
dependent. Roll-off within the analog LPF pass band is
400 MHz. The DPCLK is the DAC clock (DACCLK) or
compensated by the transmitter finite impulse response (TFIR)
DACCLK/2 to ensure that the DPCLK below 400 MHz.
to ensure a maximally flat pass-band frequency response.
Maximum Number of Tx FIR Filter Taps =
The Tx LPF bandwidth is determined by the parameter device →
(DPCLK/TX_IQDataRate) × 16 (17)
tx → txProfile → txBbf3dBCorner_kHz.
The TFIR coefficients are stored in the device data structure in
THB2
device → tx → txProfile → *txFir, which is a pointer to a structure
The Transmit Half-Band 2 (THB2) is a fixed coefficient half- with data type mykonosFir_t.
band interpolating filter. THB2 can interpolate by a factor of 2
or it can be bypassed. The full-scale range for this filter is 256 (28). The TFIR interpolation factor is set in the device data structure
The THB2 filter coefficients are [−17, 0, +145, +256, +145, 0, −17]. in device → tx → txProfile → txFirInterpolation, which can be
either 1 (bypass), 2, or 4.
The THB2 interpolation factor is set by device → tx → txProfile →
thb2Interpolation. Set this to either to 1 (bypass) or 2.

Tx1 SIGNAL PATH, I AND Q CHANNEL

LPF I DAC THB2 THB1 TFIR QUAD DIG THBO

(1,2) (1,2) (1,2,4) CORR GAIN (1,2,4)

JESD204B INTERFACE
THB2 THB1 TFIR QUAD DIG THBO
LPF Q DAC (1,2) (1,2) (1,2,4) CORR GAIN (1,2,4)

Tx LOGEN 90°
SYNTH

LPF I DAC THB2 THB1 TFIR QUAD DIG THBO

(1,2) (1,2) (1,2,4) CORR GAIN (1,2,4)

LPF I DAC THB2 THB1 TFIR QUAD DIG THBO

(1,2) (1,2) (1,2,4) CORR GAIN (1,2,4)

90°
14652-072

Tx2 SIGNAL PATH, I AND Q CHANNEL

Figure 80. Tx1 and Tx2 Signal Path Diagram

Rev. B | Page 166 of 360

AD9371/AD9375 System Development User Guide UG-992
Tx SIGNAL PATH EXAMPLE An examination of the profile pass band in Figure 82 shows that
The transceiver evaluation software (TES) provides an example the analog response slightly attenuates information within the
depicting how the baseband filtering stages are used in profile profile pass band. This analog attenuation is compensated by
configurations for a signal datapath. In this example, Tx 75 MHz/ the digital filter response to obtain a maximally flat pass band
200 MHz, IQ rate = 245.76 MHz, and the DEC5 profile are for this profile. Recall that the primary signal bandwidth is
selected for the Tx channels. This profile is compatible with the restricted to 75 MHz. There is minimal digital gain applied to
other examples provided in this user guide. signals with baseband frequency less than 75 MHz from dc.
Transmitting signals near the DAC full scale outside of this
There is a difference in the naming convention for Tx profiles in bandwidth may cause undesirable spurs.
the portion of the 75/200 MHz profile string. The 75 refers to 6.0
the primary signal bandwidth, which is the bandwidth at which
the user transmits large signal data, such as modulated carriers. COMPOSITE
4.2 DIGITAL
The 200 refers to the digital predistortion (DPD) synthesis ANALOG + DAC SYNC
bandwidth.

MAGNITUDE (dB)
Figure 83 shows the filter configuration for this profile. Note 2.4

that the clocking frequencies are in blue. The signal rate after
the TFIR block is equal to the IQ data rate of the profile. 0.6

The Tx Summary tab also shows the frequency response of the

digital filters, the analog filters, the DAC sinc response, and the –1.2
composite response of the signal chain. The response is plotted
from dc to the DAC clock rate (see Figure 81).
–3.0

14652-075
20 0 23.238 46.476 69.714 92.952 116.19
BASEBAND FREQUENCY (MHz)

Figure 82. Examination of the Pass-Band Frequency Response of the

–16 Tx 75 MHz/200 MHz, 245.76 MHz, DEC5 Profile
MAGNITUDE (dB)

–52

–88

–124
COMPOSITE
DIGITAL
ANALOG + DAC SYNC
–160
14652-074

0 98.304 196.608 294.912 393.216 491.52

BASEBAND FREQUENCY (MHz)

Figure 81. Transmitter Filter Responses

14652-073

Figure 83. Filter Configuration for the Tx 75 MHz/200 MHz, 245.76 MHz, DEC5 Profile

Rev. B | Page 167 of 360

UG-992 AD9371/AD9375 System Development User Guide
OBSERVATION RECEIVERS SIGNAL PATH Receiver Half-Band 3 (RHB3) and Receive Half-Band 2 (RHB2)
The observation system receiver (ORx) selects one signal from digital filters. The DEC5 filter is a fixed coefficient decimating
five available receiver signal inputs: two observation receiver filter. Full scale for the DEC5 digital filter is 8192 (213). The
inputs (ORx1 and ORx2) and three sniffer receiver inputs coefficients for the DEC5 filter are [+18, +35, +56, +72, +70,
(SnRxA, SnRxB, and SnRxC). It can also be used for internal +28, −38, −126, −209, −244, −184, −20, +256, +612, +976, +1273,
calibration at initialization by connecting to one of two internal +1448, +1448, +1273, +976, +612, +256, −20, −184, −244, −209,
loopback paths This mode is designated as −126, −38, +28, +70, +72, +56, +35, +18].
OBS_INTERNALCALS and allows the ARM to switch between The decimation factor for the first filter after the ADC is set in
ORx configurations as needed. the device data structure in device → obsRx → orxProfile →
This path has two filter banks: one for the sniffer channels and rxDec5Decimation for the ORx1 and ORx2 channels, and in
another for the observation channels, where coefficients for the device → obsRx → snifferProfile → rxDec5Decimation for the
respective receiver type are loaded. The device switches from SnRxA, SnRxB, and SnRxC channels. Set this parameter as 5 to
one bank to the other when switching the ORx input from one use the DEC5 path.
source to another. See the Observation Receiver (ORx) section RHB3
for additional details about the ORx. The RHB3 filter is a fixed coefficient decimating filter. RHB3
The ORx passes downconverted I/Q data from one of the seven decimates by a factor of 2. The full scale for this filter is 16 (24).
channels into the ORx baseband signal path. The ORx baseband The RHB3 coefficients are [1, 4, 6, 4, 1].
signal path consists of a programmable low-pass filter (LPF), a RHB2
Σ-Δ ADC, and digital decimation stages. The fixed coefficient
The RHB2 filter is a fixed coefficient decimating filter. RHB2
decimation filters (RHB1, RHB2, RHB3, and DEC5) eliminate
can decimate by a factor of 2. The series combination of RHB2
overranging. The programmable receiver FIR filter (RFIR) in
and RHB3 can be bypassed using the DEC5 filter. The full scale
the ORx digital baseband path can overrange, depending on
for this filter is 128 (27). The RHB2 coefficients are [+1, 0, −7, 0,
coefficients. However, the RFIR output code is limited to a
+38, +64, +38, 0, −7, 0, +1].
maximum code value when overrange conditions occur.
The decimation factor for the first filter after the ADC is set in
Low-Pass Filter
the device data structure in device → obsRx → orxProfile →
The ORx LPF is a transimpedance amplifier (TIA) with a single, rxDec5Decimation for the ORx1 and ORx2 channels and device →
real pole frequency response. The 3 dB bandwidth of the TIA obsRx → snifferProfile → rxDec5Decimation for the SnRxA,
LPF ranges from 20 MHz to 100 MHz. The TIA LPF is calibrated SnRxB, and SnRxC channels. Set this parameter as 4 to use the
based on the 3 dB bandwidth, resulting in a consistent frequency series combination of the RHB3 and RHB2 filters.
corner across all devices. The TIA 3 dB bandwidth is set within
RHB1
the device data structure and is profile dependent. Any roll-off
within the pass band is compensated by the RFIR to ensure a The RHB1 filter is a fixed coefficient decimating filter. The
maximally flat pass-band frequency response. RHB1 can decimate by a factor of 2, or it can be bypassed. The
full scale for this filter is 16384 (214). The RHB1 coefficients are
The LPF bandwidth is set in the device data structure in device →
[+9, 0, −41, 0, +124, 0, −304, 0, +665, 0, −1473, 0, +5074, +8108,
obsRx → orxProfile → rxBbf3dBCorner_kHz for the ORx1 and
+5074, 0, −1473, 0, +665, 0, −304, 0, +124, 0, −41, 0, +9].
ORx2 channels, and in device → obsRx → snifferProfile →
rxBbf3dBCorner_kHz for the SnRxA, SnRxB, and SnRxC The decimation factor for RHB1 is set in the device data structure
channels. in device → obsRx → orxProfile → rhb1Decimation for the ORx1
and ORx2 channels and device → obsRx → snifferProfile →
DEC5
rhb1Decimation for the SnRxA, SnRxB, and SnRxC channels.
The main ORx signal path features an option to use either the This can be either 1 (bypass) or 2 (decimate by 2).
decimate by 5 (DEC5) or the series combination of the decimating
DEC5
OBSERVATION CHANNEL

JESD204B INTERFACE
FRONT END I/Q MUX

LPF I ADC RHB3 RHB2 RHB1 RFIR QEC DIG DC REAL

(2) (2) (1,2) (1,2,4) CORR GAIN CORR IF

LPF Q ADC RHB3 RHB2 RHB1 RFIR QEC DIG DC REAL

(2) (2) (1,2) (1,2,4) CORR GAIN CORR IF
14652-076

DEC5

Figure 84. ORx Signal Path After the I/Q Mux Stage

Rev. B | Page 168 of 360

AD9371/AD9375 System Development User Guide UG-992
RFIR 0, +1845, 0, −1169, 0, +773, 0, −514, 0, +336, 0, −214, 0, +130, 0,
The programmable receiver finite impulse response (RFIR) −75, 0, +40, 0, −19, 0, +8, 0, −3].
filter acts as a decimating filter. The RFIR can decimate by a The real IF mode can be enabled in the device data structure in
factor of 1, 2, or 4, or it can be bypassed. The RFIR can use a device → obsRx → realIfData, which can be either 0 (disable real IF)
configurable number of taps from 24 taps to 72 taps in multiples of or 1 (enable real IF).
24. The RFIR is typically used to compensate for the roll-off of
OBSERVATION RECEIVER SIGNAL PATH EXAMPLE
the analog transimpedance amplifier (TIA) low-pass filter and
decimating filters. The transceiver evaluation software (TES) provides an example
depicting how the baseband filtering stages are used in profile
The maximum number of taps is limited by the FIR clock rate
configurations for a signal path. In this example, the ORx
(data processing clock, DPCLK). The maximum DPCLK is
200 MHz, IQ rate 245.76 MHz, and DEC5 profile are selected
400 MHz. The DPCLK is the ADC clock rate divided by either 2
for the ORx channels. This profile is compatible with the other
or 4 to limit the DPCLK below 400 MHz when the DEC5 is
examples provided in this user guide.
disabled. The DPCLK is the ADC clock rate divided by 5 or 10
to limit the DPCLK below 400 MHz when DEC5 is enabled. Figure 86 shows the filter configuration for this profile,
excluding correction stage blocks such as dc offset correction.
Maximum Number of Rx FIR Filter Taps =
Note that the clocking frequencies are in blue. The signal rate
(DPCLK/ObsRx_IQDataRate) × 24 (18)
after the RFIR block is equal to the IQRate of the profile.
The RFIR coefficients are stored in the device data structure in
Also available on the TES ObsRx/Sniffer Summary tab is the
device → obsRx → orxProfile → *rxFir for the ORx1 and ORx2
graphed frequency response of the TIA, digital filters, the ADC
channels and device → obsRx → snifferProfile → *rxFir for the
transfer function, and the composite response from dc to the
SnRxA, SnRxB, and SnRxC channels, which is a pointer to a
sampling rate of the ADC, which is shown in Figure 85.
structure with data type mykonosFir_t.
20
The RFIR decimation factor is set in the device data structure in
device → obsRx → orxProfile → rxFirDecimation for the ORx1
–28
and ORx2 channels and device → obsRx → snifferProfile →
rxFirDecimation for the SnRxA, SnRxB, and SnRxC channels,
MAGNITUDE (dB)

which can be either 1 (bypass), 2, or 4. –76

Real IF
–124
The real IF block contains an interpolating filter and mixer used
to convert complex signals centered around dc into real valued
signals centered around some IF frequency. The real IF conversion –172
ADC
block is typically bypassed, but it does provide the capability to DIGITAL
Rx TIA
operate at an IF frequency near baseband for systems that prefer –220
COMPOSITE

14652-078
to perform complex demodulation in their digital baseband. 0 245.76 491.52 737.28 983.04 1228.8
BASEBAND FREQUENCY (MHz)
The full-scale value for the real IF interpolating filter is 16384
(214). The coefficients for the real IF filter are [−3, 0, +8, 0, −19, Figure 85. ORx Filter Responses
0, +40, 0, −75, 0, +130, 0, −214, 0, +336, 0, −514, 0, +773, 0,
−1169, 0, +1845, 0, −3327, 0, +10380, +16384, +10380, −3327,
14652-077

Figure 86. Filter Configuration for the ORx 200 MHz, IQRate 245.76 MHz, Dec5 Profile

Rev. B | Page 169 of 360

UG-992 AD9371/AD9375 System Development User Guide
An examination of the profile pass-band frequency shows that  mykonosTxProfile_t. This data structure contains members
the ORx transimpedance amplifier (TIA) 3 dB setting slightly such as dacDiv, txFirinterpolation, thb1Interpolation,
attenuates information within the pass band. This analog thb2Interpolation, iqRate_kHz, primarySigBandwidth_Hz,
attenuation is compensated by the digital filter response to rfBandwidth_Hz, txDac3dBCorner_kHz, and the data
obtain a maximally flat pass band for this profile. A zoom in structure txFir of type mykonosFir_t.
view of the pass band is shown in Figure 87.
mykonosFir_t Data Structure
4.0
ADC The mykonosFir_t data structure is a structure that contains the
DIGITAL
Rx TIA
COMPOSITE finite impulse response (FIR) settings for the configurable
2.6
transmitter finite impulse response (TFIR) and receiver finite
impulse response (RFIR) filters. These filters are programmable
MAGNITUDE (dB)

1.2 to ensure digital compensation for analog filter roll-off to

ensure a maximally flat pass band for any valid profile. Include
–0.2
an instance of the mykonosFir_t data structure for each profile
used, for example, the Rx channels have a mykonosFir_t
structure populated with the desired RFIR configuration, the Tx
–1.6
channels have a mykonosFir_t data structure populated with the
TFIR configuration, and so on.
–3.0
The data structure prototype is as follows:
14652-079

0 22.02 44.04 66.06 88.08 110.0

BASEBAND FREQUENCY (MHz)
/**
Figure 87. Examination of the Pass-Band Frequency Response of the Rx * \brief Data structure to hold FIR
100 MHz, 122.88 MHz, DEC5HR Profile
filter settings */
APPLICATION PROGRAMMING INTERFACE (API) typedef struct
{
DATA STRUCTURES AND API COMMANDS
int8_t gain_dB;
Analog Devices software tools, such as the transceiver evaluation /*!< Filter gain in dB*/
software (TES), populate the Tx, Rx, ORx, and SnRx profile uint8_t numFirCoefs;
data structures with the correct values that allow accurate pass- /*!< Number of coefficients in the FIR
band flatness. If the desired profile exists in the software, it is filter */
recommended to set up the desired profile and use the data int16_t *coefs;
/*!< A pointer to an array of filter
structure values generated by the Create Config.c file for the
coefficients */
Tx, Rx, ORx, and SnRx profile data structures.
} mykonosFir_t;
The following are subsets of the data structures and a partial
The parameter descriptions are as follows:
listing of data structure members related to the configuration of
the digital filters. Many of these data structure members have  gain_dB. For Rx, ORx, and SnRx profiles, the valid gain
been covered in previous sections. Consult the device API.chm settings are +6 dB, 0 dB, −6 dB, and −12 dB. For Tx
file for additional reference. profiles, the valid gain settings are 6 dB and 0 dB.
 numFirCoefs. For Rx, ORx, and SnRx profiles, the valid
 mykonosRxSettings_t. This data structure contains
number of FIR coefficients are 24, 48, or 72. For Tx profiles,
members such as realIFData, the data structure rxProfile of
the valid number of FIR coefficients are 16, 32, 48, 64, 80
the mykonosRxProfile_t type.
or 96.
 mykonosRxProfile_t. This data structure contains
 *coefs. This parameter points to an array of filter
members such as adcDiv, rxFirDecimation,
coefficients. The range of these coefficients can span the
enHighRejDec5, rhb1Decimation, iqRate_kHz,
range of 16-bit signed integers.
rfBandwidth_Hz, rxBbf3dBCorner_kHz, and the data
structure rxFir of type mykonosFir_t. These parameters are typically generated by Analog Devices or
 mykonosFir_t. This data structure contains gain_dB, Analog Devices filter tools but must be loaded into data
numFirCoefs, and coefs members. structures in the user application for desired operation.
 mykonosObsRxSettings_t. This data structure contains
members such as realIFData, and the data structures for
orxProfile and snifferProfile. These data structures are of
type mykonosRxProfile_t.
 mykonosTxSettings_t. This data structure contains
members such as the data structure txProfile of type
mykonosTxProfile_t.
Rev. B | Page 170 of 360
AD9371/AD9375 System Development User Guide UG-992
Programming Filter Settings via API filters to be clocked at the appropriate data rates. The
Assuming that the device data structure, specifically the Tx, Rx, MYKONOS_initDigitalClocks(…) command does not
ORx, and SnRx profiles, are loaded properly, the procedure typically need to be called outside of
described in headless.c/headless.h sets up the digital and MYKONOS_initialize(…).
analog filters correctly. Some commands of note are listed as • MYKONOS_initArm(…). This command resets the ARM
follows, with descriptions related to the digital filter settings: processor and performs initialization. This command calls
MYKONOS_initSubRegisterTables(…), which calls
• MYKONOS_initialize(…). This command initializes the
MYKONOS_programFir(…). These commands do not
device based on the desired device settings. This command
need to be called outside of the MYKONOS_initArm(…)
calls MYKONOS_initDigitalClocks(…), which allows the
command.

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OBSERVATION RECEIVER (ORx)

This section describes the configuration and operation of the feeds the signal to the ADC and then to the digital signal path.
ORx. There are five receiver front-end inputs available in the The digital signal path consists of digital filters and signal
ORx. The ORx also features a calibration mode, allowing Tx conditioning stages. Refer to the Filter Configuration section
tracking calibration updates. This section includes a description for more information on the ORx digital filters. Note that only
of the signal chain of the ORx as well as references to application one input channel of the ORx inputs can be active at any time.
programming interface (API) commands and data structures A high level block diagram of the ORx datapath is shown in
used to configure the ORx. Figure 88. Note that the digital filtering and signal conditioning
The five front-end inputs include two observation receiver between the ADC and the JESD204B interface is omitted from
channels (ORx1 and ORx2) suitable for transmitter output this diagram.
observation and three sniffer receiver channels (SnRxA, SnRxB, Proper functionality of the ORx requires power supplied to the
and SnRxC) to monitor radioactivity at frequencies of interest. 3.3 V and 1.3 V analog supply pins.
There is also an internal ORx input for Tx loopback calibration
signals, OBS_INTERNALCALS. In OBS_INTERNALCALS To achieve optimal device performance levels from the ORx
mode, the ARM microprocessor controls the ORx. ports, the receiver input pins likely need to be impedance matched.
This matching typically involves a single-ended to differential
The signal flow through the ORx is as follows: frequency signal conversion. Proper impedance matching facilitates ORx
downconverted I/Q data from one of the five receiver inputs performance comparable to levels indicated in the data sheet.
passes through the I/Q mux switch into to the I/Q Information regarding RF port impedance matching is found in
transimpedance amplifier (TIA) low-pass filter (LPF), which the RF Port Interface section.

(3x) SNIFFER Rx FE

SNRX I
LNA

SNRX Q
TIA ADC

SNIFFER A DIGITAL
DECIMATION,
SNIFFER B AGC,
I/Q MUX DC OFFSET,
SNIFFER C SWITCH RSSI,
JESD204B

(2x) OBSERVATION Rx TIA ADC

ORx I

ORx Q

ORx 1
ORx 2

SNIFFER PLL
LO MUX

LOGEN
14652-080

Tx PLL
LOGEN

Figure 88. Simplified Block Diagram of the ORx Front End

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AD9371/AD9375 System Development User Guide UG-992
OBSERVATION SYSTEM RECEIVER DETAILS share an inphase and quadrature mixer for the SnRxA, SnRxB, and
This section outlines the different front-end selections available SnRxC inputs. The sniffer mixer LO is generated by the SnRx LO.
in the ORx, explains how to select the active ORx channel, and Because there are three SnRx channels, it is useful to design
other details regarding operation of the ORx. matching networks with different center frequencies such that
Observation Receiver (ORx) Overview each SnRx channel can sniff in a different frequency band with
optimum signal quality. Note that only one input can be activated
The two independent observation receiver inputs have at any given time.
programmable bandwidths up to 250 MHz. The local oscillator
(LO) source for the ORx1 and ORx2 mixers can come from the The SnRx inputs run a dc offset calibration when the channel is
Tx LO or the SnRx LO. The SnRx LO facilitates the use of an enabled to improve the SnRx dc offset performance. These
LO frequency different than that of the Tx LO to monitor the calibrations use SnRx data to calculate calibration update words.
Tx output. Each ORx channel has an independent analog front These calibrations only execute when the channel is active.
end up to the I/Q mux switch that is common to all ORx analog OBS_INTERNALCALS
front ends. The ORx must be set to OBS_INTERNALCALS to allow Tx
The ORx inputs run a quadrature error correction (QEC) tracking calibrations to update properly. This ORx input selection
tracking calibration and dc offset calibration when the channel allows the ARM to control the ORx to generate update information
is enabled to improve the ORx image rejection and dc offset for the active Tx tracking calibrations. The tracking calibrations
performance. These calibrations use ORx data to calculate that can update when in OBS_INTERNALCALS mode are the
calibration update words. The dc offset calibration runs any Tx LO leakage tracking calibration and the Tx QEC tracking
time the ORx channels are used. The QEC tracking calibration calibration. Baseband processor (BBP) access to the ORx is not
only runs if it is included in the tracking calibration mask set by possible when this input is selected. It is recommended to set
the MYKONOS_enable-TrackingCals(…) command. ORx1 and the ORx to OBS_INTERNALCALS when ORx data is not
ORx2 have independent bit masks in the tracking calibration required by the BBP.
mask. See the Quadrature Error Correction, Calibration, and Refer to the Quadrature Error Correction, Calibration, and
ARM Configuration section for more information. ARM Configuration section for more information.
An external Tx LO signal can also be used in place of the Single ORx Mode
integrated Tx LO. In this case, the external LO signal frequency
The single ORx mode is a mode that allows reduction of the
must be twice that of the desired LO frequency of operation.
number of ORx channels that must be used to maintain Tx LO
When using the external LO, it is still necessary to program
leakage calibration performance. Typical modes of operation
device data structures to represent the desired LO frequency,
involve looping back the output of Tx1 into ORx1 and Tx2 into
which allows the ARM calibration algorithms to function properly
ORx2. With the single ORx mode, both Tx1 and Tx2 can be
with respect to the LO frequency. There is no external LO
looped back into a switch that sends data from one of the
option when the SnRx LO is selected.
transmitters into an ORx port.
Sniffer Receiver (SnRx)
See the Initial ARM Calibrations section for additional
Three SnRx inputs with maximum bandwidth of 20 MHz are information.
also available on the ORx channel. Each SnRx has its own
integrated low noise amplifier (LNA). The sniffer receivers Selecting the ORx Front End
Table 132 lists all front-end inputs available in the ORx.

Table 132. ORx Front-End Input Selections

Enumeration Name ORx Front End Enumeration Value ORX_MODE[2:0]
OBS_RXOFF None 0 000
OBS_RX1_TXLO ORx1 1 001
OBS_RX2_TXLO ORx2 2 010
OBS_INTERNALCALS Dependent on calibration scheduling 3 011
OBS_SNIFFER Sniffer (select channel) 4 100
OBS_RX1_SNIFFERLO ORx1 5 101
OBS_RX2_SNIFFERLO ORx2 6 110
OBS_SNIFFER_A SnRxA 0x14 100
OBS_SNIFFER_B SnRxB 0x24 100
OBS_SNIFFER_C SnRxC 0x34 100

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There are two control modes that select the ORx front-end the shared baseband datapath at any given time. The available
channel: ORx ARM command mode or ORx ARM pin control ORx modes are indicated in Table 132. The ORX_MODE[2:0]
mode. Selection between these two modes is determined in pins are sampled after the rising edge of the ORX_TRIGGER
mykonosArmGpioConfig_t, which is in the orxPinMode data signal. Refer to the right column of Table 132 to correlate the
structure. ORX_MODE[2:0] word to the ORx front end.
Set the orxPinMode member to 0 for ORx ARM command Note the following specifics about the GPIO pin assignments
mode, or set it to 1 for ORx ARM pin control mode. Assuming for ORX_MODE[2:0] and ORX_TRIGGER:
the desired mode is set in the mykonosArmGpioConfig_t
• The ARM ignores the ORX_MODE[2:0] and ORX_
structure, the ORx control mode updates with successful
TRIGGER pin inputs if the ORx is set to command mode,
execution of the MYKONOS_setRadioControlPinMode(…)
even if the ORX_MODE[2:0] and ORX_TRIGGER signals
API command. The MYKONOS_setRadioControlPinMode(…)
are assigned to GPIO input pins.
command is called during MYKONOS_loadArmFromBinary(…).
• If the ORX_MODE[2:0] signals are assigned to GPIO_18
The ORx does not need to be under the same control mode as to GPIO_16, the ARM assumes ORX_MODE[0] maps to
the Tx/Rx (txRxPinMode). GPIO_16, ORX_MODE[1] maps to GPIO_17, and ORX_
ORx ARM Command Mode MODE[2] maps to GPIO_18.
• Configure all three ORX_MODE[2:0] pins to GPIO pins
The ORx ARM command mode method uses application
within the pin ranges of GPIO_3 to GPIO_0, GPIO_15 to
programming interface (API) commands to switch between the
GPIO_4, or GPIO_18 to GPIO_16.
various ORx inputs. The API command to switch between the ORx
inputs is MYKONOS_setObsRx-PathSource(…). This command The ARM GPIO pins are configured to the settings within the
passes an argument of the mykonosObsRxChannels_t type. The mykonosArmGpioConfig_t data structure with the API
enumerators corresponding to the various front ends of the command MYKONOS_setArmGpioPins(…).
ORx are listed in Table 132. When the ARM is set in ORx pin control mode, SnRxA, SnRxB,
When calling the MYKONOS_setObsRxPathSource(…) and SnRxC are not specified by ORX_MODE[2:0]. To select a
command, the device must be set into the radio on mode. The sniffer channel, use the MYKONOS_setSnifferChannel(…) API
MYKONOS_setObsRxPathSource(…) command can only be command.
used when the ARM is in ORx command mode; otherwise, an Note that the ARM can also send output signals indicating the
error is returned. status of the ORx (ARM acknowledge signals). These outputs
ORx ARM Pin Control Mode are specified by the orx1EnableAck, orx2EnableAck, and
srxEnableAck members of mykonosArmGpioConfig_t. These
Alternatively, the ARM can be set into ORx ARM pin control
ARM acknowledge signals can be assigned to any GPIO pin
mode. ORx ARM pin control mode is helpful in cases requiring
from GPIO_0 to GPIO_15. For the pin assignment members, Bit 4
precise control over the state of the ORx, such as in time
of the assignment 8-bit word must be set to enable the output.
division duplexed (TDD) applications.
Figure 89 shows the relationship between ORX_MODE[2:0],
When the device is set in ORx ARM pin control mode, the ORX_TRIGGER, and the ORx ARM acknowledge signals. Note
orxTriggerPin, orxMode2Pin, orxMode1Pin, and orxMode0Pin that, while the ORX_MODE[2:0] signals may toggle, they are
members of the mykonosArmGpioConfig_t data structure not sampled until the ORX_TRIGGER satisfies the tORX_TRIGGER_HOLD
assign the GPIO pins for the 3-bit word, ORX_MODE[2:0] and timing constraint.
for ORX_TRIGGER. These four signals are ARM inputs and
The timing characteristics of Figure 89 are described in Table 133.
control the active channel of the ORx when in ORx pin control
Note that the minimum times for ORx switching depend on if
mode.
the user is enabling tracking calibrations. The ORx must be set
The ORX_MODE[2:0] is a 3-bit value, set by three GPIO pins to OBS_INTERNALCALS to update for the minimum time for
that are assigned to the orxMode2Pin, orxMode1Pin, and the Tx tracking calibrations (for example, Tx quadrature error
orxMode0Pin functions. These functions set the active channel correction (QEC) tracking and Tx local oscillator leakage (LOL)
of the ORx. At most, one of the ORx channels is connected to tracking) to update.

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OBSERVATION FRONT END
SELECTION ORx1 ORx2 INTERNALCALS SNIFFER ORx OFF

tORX_TRIGGER_RISE_TO_RISE
tORX_TRIGGER_HOLD

ORX_TRIGGER
ARM INPUT SIGNALS

tMODE_SETUP tMODE_HOLD

ORX_MODE0

ORX_MODE1

ORX_MODE2
ARM OUTPUT SIGNALS

ORX1_ENABLE_ACK

ORX2_ENABLE_ACK

14652-081
SRX_ENABLE_ACK

Figure 89. ORx Pin Control Mode Timing Diagram

Table 133. ORx Pin Control Timing Characteristics

Absolute Minimum Time for Tx
Symbol Description Minimum Time Tracking Calibrations Maximum
tENABLE_RISE_TO_FALL Tx/Rx enable rising edge to enable falling 10 μs 800 μs Not applicable
edge—ENABLE signal width high
tENABLE_FALL_TO_RISE Tx/Rx enable falling edge to enable rising 10 μs 800 μs Not applicable
edge—ENABLE signal width low
tENABLE_FALL_TO_ACK Tx/Rx enable falling edge to acknowledge signal, Not applicable Not applicable 3 μs
to BBP going low
tENABLE_RISE_TO_ACK Tx/Rx enable rising edge to acknowledge signal, Not applicable Not applicable 3 μs
to BBP going high

ORx AGC, HYBRID, AND MGC To change the gain of the active channel, use the MYKONOS_
The device supports manual gain control (MGC) for all channels in setObsRxManualGain(…) API command. The ORx must be in
the ORx path. The SnRx has the added capability of supporting MGC mode to use this function. This API command returns an
hybrid gain control mode and automatic gain control (AGC) exception if the argument passed is out of range for the gain
mode as well. In MGC, the baseband processor (BBP) can index of the active channel. For example, if the SnRx gain table
control the gain index of the channel via the application is defined for Gain Index 255 to Gain Index 203, values outside
programming interface (API) commands to set the gain. The of that range cause an error.
gain control block adjusts the gain of the ORx or SnRx receiver Readback of the current gain index for the active channel is
based on settings provided in the corresponding gain table. Gain available using MYKONOS_getObsRxGain(…). This function
settings and gain control only affect the active input of the ORx is valid in the MGC, hybrid, and AGC modes of operation.
because only one input can be active at any given time. Custom gain tables can be created in the mykonos_user.c and
To change the gain mode of the ORx channel, use the the mykonos_user.h files. The gain tables provide a means to
MYKONOS_setObsRxGainControlMode(…) API command, vary the internal radio frequency (RF) attenuation, the external
using the proper enumerated value for the gain control mode. RF attenuation, the digital attenuation, and the digital gain. The
The enumerated data type is mykonosGainMode_t. data structure that sets up the AGC operation parameters is of
the mykonosAgcCfg_t. type.
Additional details regarding the implementation of gain control
schemes are provided in the Gain Control section.
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UG-992 AD9371/AD9375 System Development User Guide
OBSERVATION SYSTEM RECEIVER FRONT-END • mykonosJesd204bFramerConfig_t (device → obsRx →
PROGRAMMING framer). This data structure type contains configuration
Programming Prior to Device Initialization settings for the JESD204B digital interface. Information
regarding the data structure members and how to set up
This section provides a brief explanation of the data structures
the interface are provided in the JESD204B Interface section.
and application programming interface (API) commands used
• mykonosFir_t (device → obsRx → orxProfile → rxFir and
to configure the ORx channel.
device → obsRx → snifferProfile → rxFir). This data
Several data structures must be initialized and configured prior to structure type contains members required to program the
initializing the device. Some of these data structures are members programmable finite impulse response (PFIR) digital filter
of other data structures, such as the mykonosObsRxSettings_t in the ORx channel.
data structure, which is one of several members of the
mykonosDevice_t data structure. Programming After Initialization
Assuming all the device data structures are valid, when the After initialization, some settings can be altered using other API
MYKONOS_initialize(…) API command is executed, the commands. A list of the API commands relevant to the ORx are
settings contained within the members of the device data listed in this section. Refer to the section of the device API.chm
structures are programmed to device registers. file under Files/File List/mykonos.c for more information
about the parameters to pass into these functions.
Refer to the device API.chm file for clarification on data
structure definitions and their member data types. This file is • MYKONOS_enableObsRxFramerPrbs(…). This function
located under Files/File List/t_mykonos.h. selects the pseudorandom bit sequence (PRBS) type and
enables or disables ORx framer PRBS20 generation.
Important data structures for the ORx are listed as follows, with
• MYKONOS_enableSysrefToObsRxFramer(…). This
hierarchy details and short descriptions:
function enables or disables the SYSREF signal to the ORx
• mykonosDevice_t (device). This data structure type contains framer of the transceiver.
all device settings. The members of the structure relevant • MYKONOS_getObsRxGain(…). This function obtains the
to the ORx setup include the mykonosObsRxSettings_t gain index of the currently enabled ORx channel. The ORx
and mykonosTxSettings_t data structures. This data datapath can have multiple RF sources. This function reads
structure type also includes the mykonosDigClocks_t and back the gain index of the currently enabled RF source. If
profilesValid members. the ORx datapath is disabled, an error is returned. If the
• mykonosObsRxSettings_t (device → obsRx). This data uint8_t *gainIndex parameter is a valid pointer, the gain
structure type contains all ORx profile settings, JESD204B index is returned at the pointers address. Or, if the uint8_t
interface settings, and all other parameters specific to the *gainIndex pointer is null, the gainIndex readback is stored
operation of the available receivers of the ORx. This data in the device data structure.
structure sets up the SnRx LO frequency. • MYKONOS_obsRxInjectPrbsError(…). This function
• mykonosOrxGainControl_t (device → obsRx → orxGainCtrl). initiates a PRBS error injection into the ORx datapath.
This data structure type contains general gain control • MYKONOS_radioOff(…). This function instructs the
settings related to the gain mode of the ORx1 and ORx2 ARM processor to move the radio state to the off state.
channels, the gain setting of the ORx1 and ORx2 channels When the ARM moves from the radio on state to the radio
when active, and their minimum and maximum gain indices. off (idle) state, the ARM tracking calibrations are stopped,
• mykonosAgcCfg_t (device → obsRx → orxAgcCtrl). This and the Tx enable, Rx enable, and GPIO control pins
data structure type contains gain control settings specific to (among others) are ignored. This stoppage also keeps the
the AGC for a specific ObsRx channel. receive and transmit chains powered down until the
• mykonosSnifferGainControl (device → obsRx → MYKONOS_radioOn() function is called again.
snifferGainCtrl). This data structure type contains general • MYKONOS_radioOn(…). This function instructs the
gain control settings related to the gain mode of the sniffer ARM processor to move the radio state to the radio on
channels, the gain setting of the sniffer channel when active, state. When the ARM moves to the radio on state, the
and the minimum and maximum gain indices of the sniffer enabled Rx and Tx signal chains power up, and the ARM
channel. The SnRxA, SnRxB, and SnRxC inputs use the tracking calibrations begin. To exit this state back to a low
same gain index. power, offline state (MYKONOS_radioOff(…) function).
• mykonosRxProfile_t (device → obsRx → orxProfile and • MYKONOS_readOrxFramerStatus(…). This function
device → obsRx → snifferProfile). This data structure type reads the status of the transceiver ORx framer.
contains profile settings used to configure the main receivers • MYKONOS_setObsRxGaincontrolMode(…). This
or observation receivers. This data structure type is used to function configures the ORx gain control mode.
define the profile for the SnRx and ORx channels.

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AD9371/AD9375 System Development User Guide UG-992
• MYKONOS_setObsRxManualGain(…). This function sets • MYKONOS_setupObsRxAgc(…). This function sets up
the Rx gain of the ORx channel. The ORx channel can have the ORx AGC registers. Due to the dependencies, the
different RF inputs, for example, ORx1, ORx2, SnRxA, instantiated AGC setting structure (mykonosAgcCfg_t)
SnRxB, or SnRxC. This function sets the ORx gain index must be initialized with valid settings before this function
independently for ORx1 and ORx2, or SnRx. SnRxA, can be used
SnRxB, and SnRxC share the same gain index. Note that • MYKONOS_setupJesd204bObsRxFramer(…). This
ORx1 and ORx2 share a gain table, as do SnRxA, SnRxB, function sets up the JESD204B ORx framer.
and SnRxC. The maximum index is 255 and the minimum • MYKONOS_setArmGpioPins(…). This function programs
index is application specific. register values to the device based on the current values
• MYKONOS_setObsRxPathSource(…). This function stored in the mykonosArmGpioConfig_t data structure.
powers up or powers down the observation Rx signal This function does not write the entirety of the structure,
chain. When the ARM radio control is in ARM command only the orxTriggerPin, orxMode2Pin, orxMode1Pin,
mode, this function allows the user to selectively power up orxMode0Pin, rx1EnableAck, rx2EnableAck, tx1EnablePin,
or power down the desired ORx datapath. If this function tx2EnableAck, orx1EnableAck, orx2EnableAck,
is called when the ARM is expecting GPIO pin control of srxEnableAck, or txObsSelect data structure members.
the ORx path source, an error is returned. • MYKONOS_setRadioControlPinMode(…). This function
• MYKONOS_setRfPllFrequency(…). This function sets the programs register values to the device based on the current
RF PLL local oscillator frequency (RF carrier frequency). values stored in the mykonosArmGpioConfig_t data
This function must be called in the radio off state. structure. This function does not write the entirety of the
• MYKONOS_setSnifferChannel(…). This function selects structure, only the useRx2EnablePin, useTx2EnablePin,
the sniffer RF input to use for the observation receiver when txRxPinMode, or orxPinMode data structure members.
in ORx pin mode (ORX_MODE = Sniffer 4). This function
is only valid when using ORx pin mode. In pin mode, three
GPIO pins select an observation Rx source for mykonos-
ObsRxChannels_t enumerator values less than 7. When
the ORX_MODE GPIO pins are set to 4 for sniffer mode,
Sniffer Input A, Sniffer Input B, and Sniffer Input C can be
chosen by calling this function. This function can be called
any time after the ARM is loaded and running, and it can
be called in the radio on or radio off state.

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TDD CONFIGURATION AND SETUP

This section describes how to configure the device for time division TDD IN THE MYKONOS EVALUATION SYSTEM
duplexed (TDD) use cases. This section describes how to The evaluation system allows users to implement TDD use
program the ZC706 (Zynq) evaluation platform and the cases. For TDD operation, the device must be set into ARM pin
evaluation board, the timing requirements for operating the control mode for the Tx/Rx. The ORx can be set to either ARM
device in ARM pin control mode, and relevant application pin control mode or ARM command mode. The setting that
programming interface (API) and .dll commands that configure determines ARM pin control mode vs. ARM command mode is
the system for TDD operation. The guidelines in this section contained within the mykonosArmGpioConfig_t data structure
enable users to set up programming environments for TDD (txRxPinMode, orxPinMode) in the API, and the procedure to
performance evaluation without the graphical user interface (GUI). modify this data structure is described in the ARM Pin Mode
The transceiver evaluation software (TES) can configure the Configuration section. Pin control mode allows strict timing
device and field programmable gate array (FPGA) into a TDD control over the state of the transceiver required by TDD use
use case. The TDD page in the GUI configures the FPGA for cases.
Tx/Rx/ORx enable/disable timing and data timing, and it In the evaluation system, FPGA output signals can be programmed
configures the device for pin control mode. To determine what to drive the GPIO pins. The voltage on these pins can be monitored
commands are executed when the GUI configures TDD, see the on the GPIO headers on the evaluation card. In ARM pin control
log (found under File → View Log Files) in the GUI. This log is a mode, these pins act as inputs to the ARM to control the enable
helpful reference to configure TDD functionality with the or disable state of the Tx/Rx/ORx. The FPGA, which can be
evaluation system outside of the GUI. See the TES Interface for implemented as a baseband processor (BBP) in user systems,
TDD Mode section for more information. controls the state of the transceiver through the GPIO pins.
In this document, the .dll or the .dll layer refers to the Refer to the TddFsmParameters_us Class Details section (in
AdiCmdServerClient.dll library, which is a .NET framework .dll layer) and the mykonosArmGpioConfig_t Data Structure
library allowing interaction with the device API from .NET- Details section (in the Mykonos API) to become familiar with
compatible languages such as C#, MATLAB, or IronPython. The the configurable parameters available for TDD implementation.
.dll is typically run in a PC environment and facilitates TddFsmParameters_us configures the FPGA, while
communication between a PC and the ZC706 motherboard. mykonosArmGpioConfig_t is used to configure the device.
Example scripts in this document are provided in IronPython and Also note that although there are descriptions of several
can be used in the Iron Python Script tab in TES. API/.dll commands in this document, they are not related to
the ARM command mode unless otherwise specified.
Note that the prefix MYKONOS_ implies that the function
described exists in the Mykonos API. The prefix FpgaMykonos
or Mykonos implies that the command exists in the
AdiCommandServerClient.dll. All functions in the API have a
.dll counterpart.
ARM Input and Output Signals
A BBP controls the Tx/Rx/ORx state of the device by interfacing
through the GPIO pins to the ARM microcontroller in pin
control mode. The ARM core has two main responsibilities with
respect to TDD use cases: the real-time control of the Tx/Rx/ORx
and the scheduling and execution of device calibrations. This
section focuses on the real-time control of Tx/Rx/ORx data paths
with respect to ARM pin control mode.
Refer to the mykonosArmGpioConfig_t Data Structure Details
section for a brief overview of the GPIO controls available for
the ARM.

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ARM Pin Mode Configuration The Rx1/Rx2 and Tx1/Tx2 channels can be powered up together
The ADRV9371-N/PCBZ and ADRV9371-W/PCBZ evaluation or independently. The member useTx2EnablePin of the data
boards have pin headers for the TX1_ENABLE, TX2_ENABLE, structure mykonosArmGpioConfig_t, if set to 0, allows the
TX1_ENABLE pin voltage level to control the state of Tx1 and
RX1_ENABLE, and RX2_ENABLE signals. The silkscreen
indicators adjacent to the enable header pins are highlighted Tx2 simultaneously. If useTx2EnablePin is set to 1, the
in Figure 90. The channel enable header pins are routed to TX1_ENABLE pin only controls the enable signal for Tx1 while
corresponding balls (M6, M8, M5, and M9, respectively). The the TX2_ENABLE pin controls the enable signal for Tx2. Similarly,
FPGA outputs enable signals to drive these pins. These signals setting the useRx2EnablePin in the mykonosArmGpioConfig_t
allows independent control of Rx1 and Rx2.
are ignored unless the device is set to pin mode.
Pin control mode offers real-time control of the Tx/Rx/ORx Note that updating the mykonosArmGpioConfig_t data structure
does not change device settings. Two commands exist in the API
channels. In pin control mode, the enable signals determine if
the Tx/Rx/ORx signal chain is powered up or down. The API to write ARM pin control settings (denoted useRx2EnablePin,
allows the Tx/Rx control mode to be set independently of the useTx2EnablePin, txRxPinMode, orxPinMode) or ARM GPIO
ORx control mode. The members that determine pin mode vs. configuration settings (denoted orxTriggerPin, orxMode2Pin,
command mode are txRxPinMode and orxPinMode within the orxMode1Pin, orxMode0Pin, rx1EnableAck, rx2EnableAck,
tx2EnableAck, tx2EnableAck, orx1EnableAck, srxEnableAck,
mykonosArmGpioConfig_t data structure. If these parameters
txObsSelect). MYKONOS_setRadioControlMode(…) and
are set to 0, the device is in command mode. If set to 1, the
device is set to pin mode. The user is able to configure the MYKONOS_setArmGpioPins(…) are these commands,
Tx/Rx in pin mode and ORx in command mode, if desired. respectively. The equivalent commands at the delay-locked loop
(DLL) level are Mykonos.setRadioPinControlMode(…) and
Mykonos.setArmGpioPins(…).

14652-189

Figure 90. Tx1/Tx2 and Rx1/Rx2 Enable Pins

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ARM Acknowledge Signals the ARM ACK output GPIO pin assignments. This two step
The ARM microcontroller provides real-time control of Tx and process follows:
Rx channels in the device when in Tx/Rx pin control mode. The 1. The device must be told what GPIO pin to output an
ARM features several output signals that can be configured to ARM ACK signal. Pin assignment is accomplished by
output at user defined GPIO pins. The ARM acknowledgement the rx1EnableAck, rx2EnableAck, tx1EnableAck,
(ARM ACK) signals go high (or low) to indicate that the ARM tx2EnableAck, orx1EnableAck, orx2EnableAck, and
has powered up (or down) a Tx/Rx/ORx channel. For example, srxEnableAck members of the mykonosArmGpioConfig_t
when the TX1_ENABLE signal goes high, the ARM outputs a data structure in the API. Set these members to user
signal when it enables the Tx1 channel. Table 134 shows the desired configuration in the data structure instance. The
available ARM ACK signals. data structure members listed previously are of Type uint8_t.
The valid pin assignments for these signals are GPIO_0
Table 134. Available ARM Acknowledgement Signals through GPIO_15. In the 8-bit word, Bits[3:0] designate
ARM Output Signal Description the pin, and Bit 4 enables the signal. The ARM ACK
RX1_ENABLE_ACK Indicates that Rx1 (or Rx2)1 is/are enabled signals are not sent to the GPIO without the enable bit
RX2_ENABLE_ACK Indicates that Rx2 is enabled (Bit 4) set to 1.
TX1_ENABLE_ACK Indicates that Tx1 (or Tx2)2 is/are enabled 2. Write the mykonosArmGpioConfig_t data structure values
TX2_ENABLE_ACK Indicates that Tx2 is enabled to the device by calling the
ORX1_ENABLE_ACK Indicates that ORx1 is enabled for BBIC use MYKONOS_setArmGpioPins(…) API command, which
ORX2_ENABLE_ACK Indicates that ORx2 is enabled for BBIC use can be done through the .dll command in the Mykonos
SNRX_ENABLE_ACK Indicates that SnRxA, B, or C is enabled for class, Mykonos.setArmGpioPins(…).
BBIC use
1
Additionally, the ARM ACK signals can be used as a data path
Determined by member useRx2EnablePin in mykonosArmGpioConfig_t. 0 =
RX1_ENABLE controls Rx1 and Rx2, 1 = separate RX1_ENABLE/RX2_ENABLE pins. trigger in the evaluation system for the Tx and Rx. See the
2
Determined by member useTx2EnablePin in mykonosArmGpioConfig_t. 0 = Datapath Trigger Modes section for more information about
TX1_ENABLE controls Tx1 and Tx2, 1 = separate TX1_ENABLE/TX2_ENABLE pins
how to use the ARM ACK signals as trigger sources for Tx and
The ARM ACK signals are valid even when not in pin control Rx datapaths.
mode; however, they must be assigned and enabled in the Figure 91 illustrates the timing relationship between the Tx and
mykonosArmGpioConfig_t data structure. Rx enable signals and the Tx and Rx ARM ACK signals. Note
Assigning the GPIO pin for an ARM acknowledge signal is a that the minimum time period for any enable or disable state is
two step process in the device, and this procedure is specific to 800 μs.

AIR TIME Tx Rx Tx Rx

TX_ENABLE

tENABLE_RISE_ TO_FALL tENABLE_ FALL_TO_RISE

RX_ENABLE

tENABLE_FALL_TO_ACK

TX_ENABLE_ACK

tENABLE_RISE_ TO_ACK

RX_ENABLE_ACK
14652-190

Figure 91. Tx and Rx Enable and Enable Acknowledge Signal Timing Diagram

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AD9371/AD9375 System Development User Guide UG-992
Table 135. Tx and Rx Timing Characteristics
Absolute Minimum Time for
Symbol Description Minimum (µs) Tracking Calibrations (µs) Maximum (µs)
tENABLE_RISE_TO_FALL Tx/Rx enable rising edge to enable falling edge—enable 10 800
signal width high
tENABLE_FALL_TO_RISE Tx/Rx enable falling edge to enable rising edge—enable 10 800
signal width low
tENABLE_FALL_TO_ACK Tx/Rx enable falling edge to ACK signal to BBP going low 2
tENABLE_RISE_TO_ACK Tx/Rx enable rising edge to ACK signal to BBP going high 2

Regarding calibrations, the internal tracking calibrations in the control the active channel of the ORx when in ORx pin control
device are scheduled by the ARM microprocessor. The calibrations mode.
perform data captures in batches, with each batch guaranteed to The ORX_MODE[2:0] is a 3-bit value (set by three GPIO pins:
have a duration greater than the value listed in the Minimum orxMode2Pin, orxMode1Pin, and orxMode0Pin) that sets the
Time for Tracking Calibrations column of Table 135. Each active channel of the ORx. At most, one of the ORx channels is
calibration needs to capture a certain number of batches of data connected to the shared baseband datapath at any given time.
per second to keep up with device parameter (temperature, The ORX_MODEs available are detailed in Table 136. The
voltage supply variation) drift. If the transceiver state switches ORX_MODE[2:0] pins are sampled after the rising edge of the
before a batch of data can be collected, the corresponding data ORX_TRIGGER signal.
is unusable by the calibration and thrown out.
Assuming that all tracking calibrations are active, Rx tracking Table 136. ORX_MODE[2:0] Word Definitions
calibrations update when the Rx is enabled. Tx tracking ORX_MODE[2:0] ORx Front End
calibrations only update when the Tx channel is enabled and 000 ORx off
the ObsRx path source is set to INTERNAL_CALS mode. 001 ORx1 with Tx local oscillator (LO)
When in INTERNAL_CALS mode, the ARM has access to the 010 ORx2 with Tx LO
ObsRx, temporarily preventing the baseband processor (BBP) 011 Internal calibrations (OBS_INTERNALCALS)
access to the ORx datapath. 100 Sniffer channel
101 ORx1 with sniffer LO
ORX_MODE and ORX_TRIGGER
110 ORx2 with sniffer LO
When the ARM is set in pin control mode for the ORx, the 111 Reserved
members orxTriggerPin, orxMode2Pin, orxMode1Pin, and
Figure 92 shows these relationships between the ORX_TRIGGER,
orxMode0Pin of the mykonosArmGpioConfig_t data structure
ORX_MODE[2:0], and the ObsRx ARM ACK signals.
assign GPIO pins for the ORX_MODE[2:0] 3-bit word and the
ORX_TRIGGER. These four signals are ARM inputs and

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UG-992 AD9371/AD9375 System Development User Guide
OBSERVATION FRONT END ORX1 ORX2 INTERNALCALS SNIFFER ORX OFF
SELECTION
tORX_TRIGGER_RISE_TO_RISE
tORX_TRIGGER_HOLD

ORX_TRIGGER

tMODE_SETUP tMODE_HOLD

ORX_MODE_0
ARM INPUT SIGNALS

ORX_MODE_1

ORX_MODE_2

ORX1_ENABLE_ACK
ARM OUTPUT SIGNALS

ORX2_ENABLE_ACK

14652-191
SRX_ENABLE_ACK

Figure 92. Observation Receiver (ORx) Signal Timing in TDD Mode

Table 137. Observation Receiver (ORx) Timing Characteristics

Absolute Minimum Time for
Symbol Description Minimum (μs) Tracking Calibrations (μs)
tORX_TRIGGER_RISE_TO_RISE ORX_TRIGGER frequency—how often ORX_MODE[2:0] can be 10 800
changed in the device.
tORX_TRIGGER_HOLD ORX_TRIGGER hold time 1
tMODE_SETUP ORX_MODE[2:0] setup time before ORX_TRIGGER rising edge 1
tMODE_HOLD ORX_MODE[2:0] hold time to be sample by ARM 2

Figure 92 illustrates that the ORX_MODE[2:0] is setup before To change the ORX_MODE[2:0] and ORX_TRIGGER GPIO
the rising edge of the ORX_TRIGGER. This setup time is given pin assignments, set the members orxTriggerPin, orxMode2Pin,
by tMODE_SETUP. The ORX_MODE[2:0] is not sampled until the orxMode1Pin, and orxMode0Pin to the desired GPI O pins.
ORX_TRIGGER has been high for tORX_TRIGER_HOLD. The Valid pin assignments for these signals range from GPIO Pin 0
ORX_MODE[2:0] must have a hold time relative to ORX_ to GPIO Pin 18. Be sure that orxPinMode is set to 1 to set the
TRIGGER going high of tMODE_HOLD. The ORX_MODE[2:0] can device into orxPinMode; otherwise, the pin assignments for
be changed at a minimum period of tORX_TRIGGER_RISE_TO_RISE. This ORX_MODE[2:0] and ORX_TRIGGER are ignored. Write the
time is dependent on whether tracking calibrations are mykonosArmGpioConfig_t data structure values to the device
operational for the Tx, because the Tx tracking calibrations use by calling the MYKONOS_setArmGpioPins(…) API command,
the ObsRx in OBS_INTERNALCALS mode. This timing is through the .dll command in the Mykonos.setArmGpioPins(…)
summarized in Table 137. class. This procedure is a similar procedure to the one outlined
Timing constraints for the ORX_MODE[2:0] and ORX_TRIGGER in the ARM Acknowledge Signals section.
signals are summarized in Table 138. Additionally, it is
recommended that the ORX_TRIGGER signal stay low for at
least 10 μs prior to the ORX_TRIGGER signal going high (high
to low to high transition) to properly detect the rising edge.

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Note the following details about the GPIO pin assignments for FPGA Output Signals
ORX_MODE[2:0] and ORX_TRIGGER: In the evaluation system, the field programmable gate array
• The ARM ignores the ORX_MODE[2:0] and (FPGA) is capable of outputting the TX1_ENABLE/
ORX_TRIGGER pin inputs if the ORx is set to command TX2_ENABLE, RX1_ENABLE/RX2_ENABLE, ORX_MODE[2:0],
mode, even if the ORX_MODE[2:0] and ORX_TRIGGER and ORX_TRIGGER signals to the GPIO pins. The ARM responds
signals are assigned to GPIO input pins. to some or all of these FPGA output signals depending on the value
• If the ORX_MODE[2:0] signals are assigned to of txRxPinMode and orxPinMode. This section describes how to
GPIO[18:16], ARM assumes ORX_MODE[0] maps to program the FPGA enable and trigger signals to setup a variety
GPIO[16], ORX_MODE[1] maps to GPIO[17], and of time division duplexed (TDD) use cases. A major software
ORX_MODE[2] maps to GPIO[18]. class in the evaluation system is the TddFsmParameters_us,
• Configure all three ORX_MODE[2:0] pins to GPIO pins which offers a highly configurable class to set TDD configuration
within the pin ranges of GPIO[3:0], GPIO[15:4], or parameters, and Tx/Rx/ORx enable and disable timing in the
GPIO[18:16]. FPGA.

The ORx can also run in ARM command mode if desired. This
Datapath Trigger Modes
mode does not allow as precise timing control over the state of The FPGA used with the evaluation system provides several trigger
the ORx mode; however, it can free up GPIO pins. See the sources that initiate either data captures in the case of the receivers
Observation Receiver (ORx) section for more details. or data transmission in case of the transmitters.
The trigger sources for data captures include an IMMEDIATE
capture mode, a TDD_SM_PULSE mode, an EXT_SMA mode,
and an ARM_ACK mode. These modes and some associated
details are listed in Table 138.

Table 138. Rx Trigger Modes and Descriptions

RXTRIGGER Enumeration Name Description
IMMEDIATE Data in the Rx datapath is loaded into the FPGA memory immediately and stops when the capture is
complete.
TDD_SM_PULSE Data from the Rx datapath is loaded into the FPGA memory at the beginning of the frame and
continues until the end of the capture. The sample captures are fixed to start at the beginning of the
frame, given by TDD_SM_PULSE, but the number of samples to capture can be changed. This is the
recommended data capture trigger.
EXT_SMA Data from the Rx datapath is loaded into the FPGA at the rising edge of an external signal applied to the
J68 surface-mount SMA on the ZC706 platform. The external trigger pin is configured with the
FpgaMykonos.setupRxExtTrigPin(…) .dll command.
ARM_ACK Data from the Rx datapath is loaded into the FPGA memory at the onset of the RX_ENABLE_ACK
signal from the ARM. The FPGA must know the GPIO pin assignment for the Rx1, Rx2, and/or ObsRx
ARM ACK pins, as configured in mykonosArmGpioConfig_t, for proper data capture. This setup is
performed with the following commands in the .dll: FpgaMykonos.setupRx1ArmAckGpio(…),
FpgaMykonos.setupRx2ArmAckGpio(…), and FpgaMykonos.setupOrxArmAckGpio(…).

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UG-992 AD9371/AD9375 System Development User Guide
For the evaluation system, the field programmable gate array The trigger sources for data transmission include an
(FPGA) programming mandates that the GPIO pin assignment IMMEDIATE transmit mode, a TDD_SM_PULSE mode,
for ARM acknowledge outputs to be the same pin (that is, pin EXT_SMA mode, and an ARM_ACK mode. These modes and
assignments for orx1EnableAck = orx2EnableAck = some associated details are listed in Table 139.
srxEnableAck).

Table 139. Tx Trigger Modes and Descriptions

TXTRIGGER Enumeration Name Description
IMMEDIATE The FPGA transmits data from memory immediately into the Tx datapath.
TDD_SM_PULSE The FPGA transmits data from memory into the Tx datapath at the beginning of the frame and
continues until all samples have been transmitted. It is important to keep the duration of the
transmitted samples equal to one frame length because the data loops to the beginning when the
FPGA has transmitted the last sample of the frame. The wrong number of samples can lead to looping
unsynchronized to the beginning of the frame.
EXT_SMA The FPGA transmits data from memory into the Tx datapath at the rising edge of an external signal
applied to the J67 throughhole SMA on the ZC706 platform. The external trigger pin is configured
with the FpgaMykonos.setupRxExtTrigPin(…) .dll command.
ARM_ACK Data from the FPGA is loaded into the Tx datapath at the onset of the Tx enable acknowledge signal
from the ARM on the device. The FPGA must know the GPIO pin assignment for the Tx1 and/or Tx2
ARM acknowledge pins, as configured in mykonosArmGpioConfig_t, for proper data transmission. This
setup is performed with the following commands in the .dll: FpgaMykonos.setupTx1ArmAckGpio(…)
and FpgaMykonos.setupTx2ArmAckGpio(…).

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AD9371/AD9375 System Development User Guide UG-992
TDD Finite State Machine Class • Delay values: These are not included in the FPGA
The .dll offers a mechanism to program configuration settings, Version 0x46000030 or earlier. The option to delay the
enable timings, disable timings, and datapath delays for the Tx, datapaths relative to the Tx/Rx/ObsRx enable events will be
Rx, and ORx channels in the field programmable gate array included in a future release of FPGA code. Setting a delay
(FPGA). The TddFsmParameters_us class is a .dll features that value has no effect in FPGA Version 0x46000030 or earlier.
sets up several variables that control the timing settings, allowing • Other: includes pointers for the start and stop time for the
the user to program a variety of time division duplexed (TDD) EXT TRIG signal. The EXT TRIG can be further configured
uplink/downlink configuration timing on the evaluation system. with the FpgaMykonos.setupTxExtTri(…) and/or
The TDD finite state machine (FSM) is implemented on the FpgaMykonos.setupRxExtTrig(…) commands in the .dll.
FPGA to provide the Tx/Rx enable, ORX_MODE[2:0], Writing new values into this class does not update the FPGA
ORX_TRIGGER, and EXT TRIG signals. registers with new values. After creating an instance and
A full listing of the parameters in the TddFsmParameters_us class setting TDD FSM parameters to the desired values, the
and a short description is provided in the TddFsmParameters_us FpgaMykonos.initTdd(…) command passes an instance of
Class Details section. The five major member categories of the the class to the cmd_server to update the FPGA.
TddFsmParameters_us class are as follows: Quick Help for Programming FPGA/Mykonos
• Configuration settings: includes members such as To summarize the setup and configuration concepts described
TddSecondPtrEnable, TddLoopCount, TddFrameCount_us, in this document thus far, general strategies on how to program
and more. The length of the frame is defined in this region by the evaluation system are provided as follows.
the TddFrameCount_us member.
• To configure the ARM pin control mode setup, GPIO pin
• Primary region pointers: includes the start time and stop
assignments for ARM inputs (enable/ORX_MODE/
time pointers for a primary region within a frame. In this
ORX_TRIGGER[2:0]) and ARM outputs (ARM ACKs):
case, primary refers to the first event within a frame when
• From the application programming interface (API),
a Tx/Rx/ObsRx channel is enabled. If a UL/DL frame
first, write the desired values into the Mykonos-
configuration has two separate Tx/Rx/ObsRx enable
ArmGpioConfig_t type data structure. Two commands
events, the primary region pointers set up the first event,
exist to update the ARM. Table 140 depicts which
and the secondary region pointers set up the second
parameters are updated using specific API commands.
event. These values must be positive and less than the
• From the delay-locked loop (DLL), first, write the
TddFrameCount_us duration.
desired values into the mykonosArmGpioConfig_t
• Secondary region pointers: includes the start and stop time
type data structure by using the Mykonos.init_
pointers for a secondary region within a frame. These values
armGpioStructure(…) command. Two commands
must be positive and less than the TddFrameCount_us.
exist to update the ARM. Table 140 depicts which
parameters are updated using specific DLL commands.
Table 140. Commands to Program mykonosArmGpioConfig_t Data Structure Members to the ARM
mykonosArmGpioConfig_t
Parameter How to Update the ARM from the API How to Update the ARM from the DLL
useRx2EnablePin MYKONOS_setRadioControlPinMode(…) Mykonos.setRadioControlPinMode()
useTx2EnablePin MYKONOS_setRadioControlPinMode(…) Mykonos.setRadioControlPinMode()
txRxPinMode MYKONOS_setRadioControlPinMode(…) Mykonos.setRadioControlPinMode()
orxPinMode MYKONOS_setRadioControlPinMode(…) Mykonos.setRadioControlPinMode()
orxTriggerPin MYKONOS_setArmGpioPins(…) Mykonos.setArmGpioPins(…)
orxMode2Pin MYKONOS_setArmGpioPins(…) Mykonos.setArmGpioPins(…)
orxMode1Pin MYKONOS_setArmGpioPins(…) Mykonos.setArmGpioPins(…)
orxMode0Pin MYKONOS_setArmGpioPins(…) Mykonos.setArmGpioPins(…)
rx1EnableAck MYKONOS_setArmGpioPins(…) Mykonos.setArmGpioPins(…)
rx2EnableAck MYKONOS_setArmGpioPins(…) Mykonos.setArmGpioPins(…)
tx1EnableAck MYKONOS_setArmGpioPins(…) Mykonos.setArmGpioPins(…)
tx2EnableAck MYKONOS_setArmGpioPins(…) Mykonos.setArmGpioPins(…)
orx1EnableAck MYKONOS_setArmGpioPins(…) Mykonos.setArmGpioPins(…)
srxEnableAck MYKONOS_setArmGpioPins(…) Mykonos.setArmGpioPins(…)
txObsSelect MYKONOS_setArmGpioPins(…) Mykonos.setArmGpioPins(…)

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UG-992 AD9371/AD9375 System Development User Guide
• To configure the field programmable gate array (FPGA) in
The ORX_MODE[2:0] and ORX_TRIGGER Seen by the FPGA
the Mykonos evaluation system, including Tx/Rx/ORx start The ORX_MODE[2:0] and ORX_TRIGGER are ARM input
and stop primary and secondary regions, time division signals driven by the FPGA. The FPGA must send commands
duplexed (TDD) configuration parameters, delay variables, to the appropriate GPIO pins configured in the device. The
and external trigger setup: following two commands set up the FPGA to drive the
• From the application programming interface (API), it ORX_MODE[2:0] and ORX_TRIGGER signals:
is not applicable. • FpgaMykonos.setupFpgaGpio(…)
• From the delay-locked loop (DLL), first, write the • FpgaMykonos.setupFpgaOrxGpio(…)
desired values into an instance of the
TddFsmParameters_us class. Second, program the The first command sets the FPGA to enable the ORX_MODE[2:0]
values to device with FpgaMykonos.initTdd_us(…) and ORX_TRIGGER signals from the FPGA. The second
and passing the TddFsmParameters_us instance as the command assigns the pin that these signals are sent to. It is
argument. important that these assignment match with the Mykonos
• Set up the Tx trigger source as follows: GPIO pin assignments for the ORX_MODE[2:0] and
ORX_TRIGGER set in the mykonosArmGpioConfig_t data
• From the API, it is not applicable.
structure. These commands are explained in the API/DLL
• From the DLL, pass the desired trigger source into the
Commands for TDD Configuration section.
FpgaMykonos.setTxTrigger(…) command.
• Set up the Rx trigger source as follows: Refer to the ORX_MODE and ORX_TRIGGER section for
• From the API, it is not applicable. GPIO pin assignment constraints.
• From the DLL, pass the desired trigger source into the Example TDD Script in IronPython
FpgaMykonos.setRxTrigger(…) command. The following script is an example used to configure the device
• Set up the external trigger sources from the DLL as follows: for TDD operation in LTE UL/DL Configuration 3. This script
• For the Tx external trigger, set up with the does not demonstrate the steps necessary to capture Rx/ObsRx
FpgaMykonos.setupTxExtTrigPin(…) command, samples or to transmit a Tx data file. This functionality can be
which is the J67 SMA connector on the ZC706 performed in the transceiver evaluation software (TES) or in
motherboard. the scripting tab itself.
• For the Rx external trigger, set up with the Commands related to TDD that have not been explained to this
FpgaMykonos.setupRxExtTrigPin(…) command, point are described in the API/DLL Commands for TDD
which is the J68 SMA connector on the ZC706 Configuration section.
motherboard.
Note that details such as file paths and TCPIP addresses may
need to be modified to properly connect to the device. This script
is set up for LTE Uplink/Downlink Configuration 0 (D, S, U, U,
U, D, S, U, U, U). To achieve best performance, the timing of the
enable pointers may need to be adjusted. Note that for the
TddFsmParamters_us pointers, Time 0 corresponds to the
beginning of the frame in the FPGA counter.
Run this script after a successful program device execution.

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AD9371/AD9375 System Development User Guide UG-992
########################
#ADI Demo Python Script
########################

#Import Reference to the DLL

import clr
clr.AddReferenceToFileAndPath("C:\\Program Files (x86)\\Analog Devices\\Mykonos Transceiver
Evaluation Software\\AdiCmdServerClient.dll")
from AdiCmdServerClient import AdiCommandServerClient
from AdiCmdServerClient import TddFsmParameters_us

#Create an Instance of the Command server client, FpgaMykonos, Mykonos, and

TddFsmParameters_us classes
Link = AdiCommandServerClient.Instance
FPGA = Link.FpgaMykonos.Instance
MYK = Link.Mykonos.Instance

#Connect to the Zynq Platform

if(Link.hw.Connected == 1):
Connect = 0
else:
Connect = 1
Link.hw.Connect("192.168.1.10", 55555)

#Read the Version

print Link.version()

DISABLE = 0
ENABLE = 1
OUTPUT = 0
INPUT = 1

################################
### ENABLE TDD ###
################################

MYK.radioOff()
Link.hw.ReceiveTimeout = 0

##############
# FPGA SETUP #
##############
FPGA.disableTdd() #Disable TDD FSM in FPGA
FPGA.gateDataTdd(ENABLE) #Enable data gating for Tx

#Set FPGAs to output ORX_MODE/ORX_TRIG on GPIO pins

FPGA.setupFpgaGpio(FPGA.GPIO_FEATURES.TDDORXMODE, OUTPUT)

#Assign GPIO pins for ORX_MODE/ORX_TRIG signals

FPGA.setupFpgaOrxGpio(FPGA.ORXGPIO_SELECT.GPIO_15, #ORX_TRIGGER
FPGA.ORXGPIO_SELECT.GPIO_16, #ORX_MODE[0]
FPGA.ORXGPIO_SELECT.GPIO_17, #ORX_MODE[1]
FPGA.ORXGPIO_SELECT.GPIO_18) #ORX_MODE[2]

#Setup ARM ACK Output Signals on FPGA side

FPGA.setupTx1ArmAckGpio(0x80) #GPIO 7
FPGA.setupTx2ArmAckGpio(0x100) #GPIO 8
FPGA.setupRx1ArmAckGpio(0x200) #GPIO 9
FPGA.setupRx2ArmAckGpio(0x400) #GPIO 10
FPGA.setupOrxArmAckGpio(0x800) #GPIO 11

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UG-992 AD9371/AD9375 System Development User Guide
#Enable ARM ACK Output Signals on FPGA
FPGA.enableArmAckOutputs(ENABLE)

#Setup FPGA TX/RX Data Path Trigger to TDD_SM_PULSE signals

FPGA.setTxTrigger(FPGA.TXTRIGGER.TDD_SM_PULSE)
FPGA.setRxTrigger(FPGA.RXTRIGGER.TDD_SM_PULSE)

#Create instance of TDD FSM Class

tddFsm = TddFsmParameters_us()

#Set Miscellaneous TDD Settings

tddFsm.TddLoopCount = 0
tddFsm.TddFrameCount_us = 10000
tddFsm.TddSecondPtrEnable = 1
tddFsm.TddExtTrigOnPtr_us = 9900
tddFsm.TddExtTrigOffPtr_us = 0

#Set Tx Timings
tddFsm.TddTx1OnPtr_us = 9950
tddFsm.TddTx1OffPtr_us = 1800
tddFsm.Tdd2ndTx1OnPtr_us = 4950
tddFsm.Tdd2ndTx1OffPtr_us = 6800
tddFsm.TddTx2OnPtr_us = 9950
tddFsm.TddTx2OffPtr_us = 1800
tddFsm.Tdd2ndTx2OnPtr_us = 4950
tddFsm.Tdd2ndTx2OffPtr_us = 6800
tddFsm.TddIntCalsOnPtr_us = 50
tddFsm.TddIntCalsOffPtr_us = 1700
tddFsm.Tdd2ndIntCalsOnPtr_us = 5050
tddFsm.Tdd2ndIntCalsOffPtr_us = 6700

#tddFsm.TddTx1DataPathDel_us = 40
#tddFsm.TddTx2DataPathDel_us = 40
#tddFsm.Tdd2ndTx1DataPathDel_us = 40
#tddFsm.Tdd2ndTx2DataPathDel_us = 40

#Set Rx Timings
tddFsm.TddRx1OnPtr_us = 1800
tddFsm.TddRx1OffPtr_us = 4950
tddFsm.Tdd2ndRx1OnPtr_us = 6800
tddFsm.Tdd2ndRx1OffPtr_us = 9950
tddFsm.TddRx2OnPtr_us = 1800
tddFsm.TddRx2OffPtr_us = 4950
tddFsm.Tdd2ndRx2OnPtr_us = 6800
tddFsm.Tdd2ndRx2OffPtr_us = 9950

#tddFsm.TddRx1DataPathDel_us = 40
#tddFsm.TddRx2DataPathDel_us = 40
#tddFsm.Tdd2ndRx1DataPathDel_us = 40
#tddFsm.Tdd2ndRx2DataPathDel_us = 40

#Load Tdd Fsm parameters into FPGA

FPGA.initTdd_us(tddFsm)

#Setup the Tx/Rx External Trigger Output (J67/J68 SMA on Zynq)

FPGA.setupTxExtTrigPin(FPGA.FPGA_TRIGGER_DIRECTION.FPGA_OUTPUT,
FPGA.FPGA_EXT_TRIGGER_SOURCE.TDD_FSM_TRIG)
FPGA.setupRxExtTrigPin(FPGA.FPGA_TRIGGER_DIRECTION.FPGA_OUTPUT,
FPGA.FPGA_EXT_TRIGGER_SOURCE.TDD_FSM_TRIG)

#############
# ARM SETUP #
Rev. B | Page 188 of 360
AD9371/AD9375 System Development User Guide UG-992
#############
useRx2EnablePin = ENABLE
useTx2EnablePin = ENABLE
txRxPinMode = ENABLE
orxPinMode = ENABLE
orxTriggerPin = 15
orxMode2Pin = 18
orxMode1Pin = 17
orxMode0Pin = 16
rx1EnableAck = (9 | 0x10) #OR the pin assignment with 0x10 to make the pin an output pin.
rx2EnableAck = (10 | 0x10)
tx1EnableAck = (7 | 0x10)
tx2EnableAck = (8 | 0x10)
orx1EnableAck = (11 | 0x10)
orx2EnableAck = (11 | 0x10)
srxEnableAck = (11 | 0x10)
txObsSelect = 0

MYK.init_armGpioStructure(useRx2EnablePin, useTx2EnablePin,
txRxPinMode, orxPinMode, orxTriggerPin, orxMode2Pin, orxMode1Pin,
orxMode0Pin, rx1EnableAck, rx2EnableAck, tx1EnableAck, tx2EnableAck,
orx1EnableAck, orx2EnableAck, srxEnableAck, txObsSelect)

FPGA.enableArmAckOutputs(ENABLE)
MYK.setArmGpioPins()
MYK.setRadioControlPinMode()

##########################################
## Write Tx Data To RAM ##
##########################################

FPGA.stopTxData()
FPGA.setTxTransmitMode(1) #Set Tx into continuous data transmit mode in data path
FPGA.enableTxDataPaths(FPGA.TX_DATAPATH.TX1_TX2)
FPGA.startTxData()
MYK.radioOn()
FPGA.enableTdd()

#Disconnect from the Zynq Platform

if(Connect == 1):
Link.hw.Disconnect()

Rev. B | Page 189 of 360

UG-992 AD9371/AD9375 System Development User Guide
API/DLL COMMANDS FOR TDD CONFIGURATION • Argument configSetting: Several configuration settings are
This section provides a list of functions that can assist in available. These modes can be enabled simultaneously so
configuration of time division duplexed (TDD) mode. Note that that the enumeration type GPIO_FEATURES provides
the MYKONOS_ prefix implies that the function described combinations of the modes listed as follows. In the .dll
exists in the Mykonos application programming interface layer, the available GPIO modes are as follows:
(API). The FpgaMykonos. or Mykonos. prefix implies that the • SPI2 is over GPIO[4:0].
command exists in the AdiCommandServerClient.dll. All • ORX_TRIGGER and ORX_MODE interface
functions in the API have a .dll counterpart. enable. The user can define GPIO pins indicating
the ORX_MODE over three pins set by the
TDD Specific Commands in the FPGA
setupFpgaOrxGpio(…) command. The
FpgaMykonos.disableTdd() setupFpgaOrxGpio(…) also sets a GPIO pin for
the ORX_TRIGGER signal.
• Purpose: This command disables the field programmable • HSCP mode over GPIO[17:12] and GPIO[8:5].
gate array (FPGA) TDD finite state machine (FSM). • TESTPIN mode.
• Arguments: None.
FpgaMykonos.setupFpgaOrxGpio(ORXGPIO_SELECT
FpgaMykonos.gateDataTdd(byte enable) gpioOrxTrig, ORXGPIO_SELECT gpioOrxMode_0,
• Purpose: This command gates zeros into the datapath to ORXGPIO_SELECT gpioOrxMode_1,
the JESD204B framer until the TDD module is enabled, if ORXGPIO_SELECT gpioOrxMode_2)
the Tx RAM is connected to the Tx datapath. This command
• Purpose: Set GPIO pins for the ORX_MODE and
is useful before and after the TDD module is enabled.
ORX_TRIGGER signals.
• Argument enable: set enable to 1 to enable TDD data
• Argument gpioOrxTrig: Designates a GPIO pin for the
gating, and set enable to 0 to disable TDD data gating.
ORX_TRIGGER signal. ORX_TRIGGER goes high for
FpgaMykonos.initTdd_us(byte rw, ref ~1 µs at the start and stop time of an ORX_MODE.
TddFsmParameters_us tddParameters) • Arguments gpioOrxMode_0, gpioOrxMode_1,
gpioOrxMode_2: Designates GPIO pins for the 3-bit word
• Purpose: This command sets up the FPGA registers with the
describing the active ObsRx mode. See Table 136 for
timing information set by the TddFsmParameters_us class.
ORX_MODES available and The ORX_MODE[2:0] and
This class contains the start time and stop time for the
ORX_TRIGGER Seen by the FPGA section for GPIO
primary and secondary pointers of a TDD frame,
restrictions.
secondary pointer enable, continuous capture and
transmit, and several other TDD FSM parameters. FpgaMykonos.enableArmAckOutputs(byte enableArmAck
• Argument rw: this is a read/write (0 = read, 1 = write) Output)
control. If read is selected, the FPGA registers values
• Purpose: This command enables or disables the ARM
corresponding to the TDD FSM parameters are loaded into
acknowledge signal output sent to the GPIO pins specified
the tddFsmParameters_us structure. If write is selected, the
by the setup commands (setupTx1ArmAckGpio(…),
FPGA registers are written to with the values in the
setupTx2ArmAckGpio(…), and so on).
tddFsmParameters_us structure.
• Argument enableArmAckOutput: 0 = disable, and 1 =
• Argument tddParameters: see the TddFsmParameters_us
enable.
Class Details section for more information.
FpgaMykonos.setupTx1ArmAckGpio(UInt32 tx1ArmAck
GPIO Specific Commands
Gpio)
FpgaMykonos.setupFpgaGpio(GPIO_FEATURES
configSetting, UInt32 gpioDirection) • Purpose: This command sets up a GPIO pin to output
the ARM acknowledge signal for TX1_ENABLE_ACK.
• Purpose: This command sets the pin direction (input or The signal does not appear on GPIO until the
output) of the GPIO pins. enableArmAckOutputs(…) command runs.
• Argument gpioDirection: This argument uses the lower • Argument tx1ArmAckGpio: Sets the GPIO output pin for
19 bits to individually map to the GPIO pins, 0 through 18. the TX1_ENABLE_ACK signal. The argument is a 19-bit
Bit 0 corresponds to GPIO_0, Bit 1 corresponds to [18:0] bit mask aligned for each GPIO pin.
GPIO_1, and so on. Setting a bit sets the corresponding
GPIO pin as an input.

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AD9371/AD9375 System Development User Guide UG-992
FpgaMykonos.setupTx2ArmAckGpio(UInt32 tx2ArmAck • Arguments: See Mykonos API .chm file on
Gpio) mykonosArmGpioConfig_t.
• Purpose: This command sets up a GPIO pin to output Mykonos.setArmGpioPins(…)
the ARM acknowledge signal for TX2_ENABLE_ACK.
• Purpose: Program register values to Mykonos based on the
The signal does not appear on GPIO until the
current values stored in the mykonosArmGpioConfig_t
enableArmAckOutputs(…) command is run.
data structure. This does not write the entirety of the
• Argument tx2ArmAckGpio: Sets the GPIO output pin for
structure, only the following data structure members:
the TX2_ENABLE_ACK signal. The argument is a 19-bit
orxTriggerPin, orxMode2Pin, orxMode1Pin, orxMode0Pin,
[18:0] bit mask aligned for each GPIO pin.
rx1EnableAck, rx2EnableAck, tx1EnablePin, tx2EnableAck,
FpgaMykonos.setupRx1ArmAckGpio(UInt32 rx1ArmAck orx1EnableAck, orx2EnableAck, srxEnableAck, and
Gpio) txObsSelect. This function also exists in the API as
MYKONOS_setArmGpioPins(…).
• Purpose: This command sets up a GPIO pin to output
• Arguments: none.
the ARM acknowledge signal for RX1_ENABLE_ACK.
The signal does not appear on GPIO until the Mykonos.setRadioControlPinMode(…)
enableArmAckOutputs(…) command runs.
• Purpose: Program register values to Mykonos based on the
• Argument rx1ArmAckGpio: Sets the GPIO output pin for
current values stored in the mykonosArmGpioConfig_t
the RX1_ENABLE_ACK signal. The argument is a 19-bit
data structure. This does not write the entirety of the
[18:0] bit mask aligned for each GPIO pin.
structure, only the following data structure members:
FpgaMykonos.setupRx2ArmAckGpio(UInt32 rx2ArmAck useRx2EnablePin, useTx2EnablePin, txRxPinMode, and
Gpio) orxPinMode. This function also exists in the API
MYKONOS_setRadioControlPinMode(…).
• Purpose: This command sets up a GPIO pin to output
• Arguments: none.
the ARM acknowledge signal for RX2_ENABLE_ACK.
The signal does not appear on GPIO until the Trigger Specific Commands
enableArmAckOutputs(…) command runs. FpgaMykonos.setRxTrigger(RXTRIGGER rxTrig)
• Argument rx2ArmAckGpio: Sets the GPIO output pin for • Purpose: The Rx trigger determines what event triggers the
the RX2_ENABLE_ACK signal. Argument is a 19-bit receiver datapath to move data into the field programmable
[18:0] bit mask aligned for each GPIO pin. gate array (FPGA). Table 138 contains descriptions of the
FpgaMykonos.setupOrxArmAckGpio(UInt32 orxArmAck available RXTRIGGER enumerations in the FpgaMykonos
Gpio) class.
• Argument rxTrig: Refer to Table 138.
• Purpose: This command sets up a GPIO pin to output
FpgaMykonos.setTxTrigger(TXTRIGGER txTrig)
the ARM acknowledge signal for ORX_ENABLE_ACK.
The signal does not appear on GPIO until the • Purpose: The Tx trigger determines what event triggers the
enableArmAckOutputs(…) command runs. Note that all beginning of Tx data transmission.
ObsRx channels acknowledge signal (ORx1, ORx2, SnRx) • Argument txTrig: Refer to Table 139.
share an acknowledge pin.
TddFsmParameters_us Class Details
• Argument orxArmAckGpio: Sets the GPIO output pin for
the TX1_ENABLE_ACK signal. Argument is a 19-bit This section provides an explanation for the members of the
[18:0] bit mask aligned for each GPIO pin. TddFsmParameters_us class. Primary and secondary region
timing are relative to the beginning of a frame.
Mykonos.init_armGpioStructure(byte useRx2EnablePin,
Configuration Options
byte useTx2EnablePin, byte txRxPinMode, byte
orxPinMode, byte orxTriggerPin, byte orxMode2Pin, byte The configuration options are as follows:
orxMode1Pin, byte orxMode0Pin, byte rx1EnableAck, byte • TddSecondPtrEnable: enables the second pointer regions.
rx2EnableAck, byte tx1EnableAck, byte tx2EnableAck, byte • TddLoopCount: loop count determines the number of
orx1EnableAck, byte orx2EnableAck, byte srxEnableAck) frames. 0 = continuous loop mode, 1 = one total frame, 2 =
• Purpose: This command writes to the mykonos- two total frames, and so on, 4-bit value.
ArmGpioConfig_t data structure in the Mykonos • TddContRxCapture: This value is ignored. Continuous
application programming interface (API). This command sample capture is default.
also has an overload function providing read/write access • TddContTxTransmit: This value is ignored. Continuous
to the mykonosArmGpioConfig_t data structure. sample transmit is default.
• TddSyncExtTrig: sync frames to the external sync trigger.
Rev. B | Page 191 of 360
UG-992 AD9371/AD9375 System Development User Guide
• TddEnableSnRxPtr: enables pointers for SnRxA, SnRxB, • TddOrx1SnifferLoOffPtr_us: stop time for the ORx1
and SnRxC regions. with SnRx LO receive region. Must be less than the
• TddEnableOrx1SnifferLoPtrs: enables pointers for ORx1 TddFrameCount_us value.
with SnRx local oscillator (LO) input to the mixer. • TddOrx2SnifferLoOnPtr_us: Start time for the ORx2
• TddEnableOrx2SnifferLoPtrs: enables pointers for ORx2 with SnRx LO receive region. Must be less than the
with SnRx LO input to the mixer. TddFrameCount_us value.
• TddOrx2SnifferLoOffPtr_us: Stop time for the ORx2
Primary Region Pointers
with SnRx LO receive region. Must be less than the
The primary region pointers include the following: TddFrameCount_us value.
• TddFrameCount_us: duration of the frame. Secondary Region Pointers
• TddTx1OnPtr_us: start time of primary Tx1 transmit
The secondary region pointers include the following:
region. Must be less than the TddFrameCount_us value.
• TddTx1OffPtr_us: stop time of primary Tx1 transmit • Tdd2ndTx1OnPtr_us: start time of the secondary Tx1
region. Must be less than the TddFrameCount_us value. transmit region. Must be less than the TddFrameCount_us
• TddTx2OnPtr_us: start time of primary Tx2 transmit value.
region. Must be less than the TddFrameCount_us value. • Tdd2ndTx1OffPtr_us: stop time of the secondary Tx1
• TddTx2OffPtr_us: stop time of primary Tx2 transmit transmit region. Must be less than the TddFrameCount_us
region. Must be less than the TddFrameCount_us value. value.
• TddRx1OnPtr_us: start time of primary Rx1 receive • Tdd2ndTx2OnPtr_us: start time of the secondary Tx2
region. Must be less than the TddFrameCount_us value. transmit region. Must be less than the TddFrameCount_us
• TddRx1OffPtr_us: start time of primary Rx1 receive value.
region. Must be less than the TddFrameCount_us value. • Tdd2ndTx2OffPtr_us: stop time of the secondary Tx2
• TddRx2OnPtr_us: start time of primary Rx2 receive transmit region. Must be less than the TddFrameCount_us
region. Must be less than the TddFrameCount_us value. value.
• TddRx2OffPtr_us: start time of primary Rx2 receive • Tdd2ndRx1OnPtr_us: start time of the secondary Rx1
region. Must be less than the TddFrameCount_us value. receive region. Must be less than the TddFrameCount_us
• TddOrx1TxLoOnPtr_us: start time of primary ORx1 value.
with Tx LO receive region. Must be less than the • Tdd2ndRx1OffPtr_us: stop time of the secondary Rx1
TddFrameCount_us value. receive region. Must be less than the TddFrameCount_us
• TddOrx1TxLoOffPtr_us: stop time of primary ORx1 value.
with Tx LO receive region. Must be less than the • Tdd2ndRx2OnPtr_us: start time of the secondary Rx2
TddFrameCount_us value. receive region. Must be less than the TddFrameCount_us
• TddOrx2TxLoOnPtr_us: start time of primary ORx2 value.
with Tx LO receive region. Must be less than the • Tdd2ndRx2OffPtr_us: stop time of the secondary Rx2
TddFrameCount_us value. receive region. Must be less than the TddFrameCount_us
• TddOrx2TxLoOffPtr_us: stop time of primary ORx2 value.
with Tx LO receive region. Must be less than the • Tdd2ndOrx1TxLoOnPtr_us: start time of the secondary
TddFrameCount_us value. ORx1 with Tx LO receive region. Must be less than the
• TddIntCalsOnPtr_us: start time of the primary ORx TddFrameCount_us value.
internal calibrations receive region. Must be less than the • Tdd2ndOrx1TxLoOffPtr_us: stop time of the secondary
TddFrameCount_us value. ORx1 with Tx LO receive region. Must be less than the
• TddIntCalsOffPtr_us: start time for the primary ObsRx TddFrameCount_us value.
internal calibrations receive region. Must be less than the • Tdd2ndOrx2TxLoOnPtr_us: start time of the secondary
TddFrameCount_us value. ORx2 with Tx LO receive region. Must be less than the
• TddSnRxOnPtr_us: start time for the SnRx (A, B, or C) TddFrameCount_us value.
receive region. Must be less than the TddFrameCount_us • Tdd2ndOrx2TxLoOffPtr_us: Stop time of the secondary
value. ORx2 with Tx LO receive region. Must be less than the
• TddSnRxOffPtr_us: stop time for the SnRx (A, B, or C) TddFrameCount_us value.
receive region. Must be less than the TddFrameCount_us • Tdd2ndIntCalsOnPtr_us: start time for the secondary
value. ObsRx internal calibrations receive region. Must be less
• TddOrx1SnifferLoOnPtr_us: start time for the ORx1 than the TddFrameCount_us value.
with SnRx LO receive region. Must be less than the
TddFrameCount_us value.
Rev. B | Page 192 of 360
AD9371/AD9375 System Development User Guide UG-992
• Tdd2ndIntCalsOffPtr_us: stop time for the secondary • TddOrx1SnifferLoPathDel_us: ORx1 with SnRx LO
ObsRx internal calibrations receive region. Must be less secondary start and stop time delay. Can be positive or
than the TddFrameCount_us value. negative. Maximum/minimum delay is
abs(215/(TxLaneRate_MHz/40)).
Delay Values (Secondary Datapath Delays (in Gray Blocks)
• TddOrx2SnifferLoPathDel_us: ORx2 with SnRx LO
are Ignored in the TDD FSM)
secondary start and stop time delay. Can be positive or
The delay values (secondary datapath delays are ignored in the negative. Maximum/minimum delay is
time division duplexed, TDD, finite state machine, FSM) abs(215/(TxLaneRate_MHz/40)).
include the following:
Other Values
• TddTx1DataPathDel_us: Tx1 primary start and stop time
delay. Can be positive or negative. Maximum/minimum Other values include the following:
delay is abs(215/(TxLaneRate_MHz/40)). • TddExtTrigOnPtr_us: start time for the external trigger
• TddTx2DataPathDel_us: Tx2 primary start and stop time signal. The rising edge of the external trigger signal can
delay. Can be positive or negative. Maximum/minimum indicate the beginning of a frame if set to 0.
delay is abs(215/(TxLaneRate_MHz/40)). • TddExtTrigOffPtr_us: stop time for the external trigger
• TddRx1DataPathDel_us: Rx1 primary start and stop time signal.
delay. Can be positive or negative. Maximum/minimum
mykonosArmGpioConfig_t Data Structure Details
delay is abs(215/(TxLaneRate_MHz/40)).
• TddRx2DataPathDel_us: Rx2 primary start and stop time The mykonosArmGpioConfig_t data structure contains the
delay. Can be positive or negative. Maximum/minimum following members. They are all data type uint8_t.
delay is abs(215/(TxLaneRate_MHz/40)). Configuration Modes
• TddOrx1TxLoDataPathDel_us: ORx1 with Tx local oscillator Configuration modes include the following:
(LO) primary start and stop time delay. Can be positive or
negative. Maximum/minimum delay is • useRx2EnablePin: 0 = RX1_ENABLE controls Rx1 and
abs(215/(TxLaneRate_MHz/40)). Rx2. 1 = separate RX1_ENABLE/RX2_ENABLE pins.
• TddOrx2TxLoDataPathDel_us: ORx2 with Tx LO primary • useTx2EnablePin: 0 = TX1_ENABLE controls TX1 and
start and stop time delay. Can be positive or negative. TX2. 1 = separate TX1_ENABLE/TX2_ENABLE pins.
Maximum/minimum delay is abs(215/(TxLaneRate_MHz/40)). • txRxPinMode: 0 = ARM command mode. 1 = pin mode to
• Tdd2ndTx1DataPathDel_us: Tx1 secondary start and stop power up Tx/Rx chains.
time delay. Can be positive or negative. Maximum/ • orxPinMode: 0 = ARM command mode. 1 = pin mode to
minimum delay is abs(215/(TxLaneRate_MHz/40)). power up ORx receiver.
• Tdd2ndTx2DataPathDel_us: Tx2 secondary start and stop Mykonos ARM Input GPIO Pins (Only Valid if
time delay. Can be positive or negative. Maximum/ orxPinMode = 1)
minimum delay is abs(215/(TxLaneRate_MHz/40)).
Mykonos ARM input GPIO pins (only valid if orxPinMode = 1)
• Tdd2ndRx1DataPathDel_us: Rx1 secondary start and stop
includes the following:
time delay. Can be positive or negative. Maximum/
minimum delay is abs(215/(TxLaneRate_MHz/40)). • orxTriggerPin: Select desired GPIO pin (valid 0 to 18).
• Tdd2ndRx2DataPathDel_us: Rx2 secondary start and stop • orxMode2Pin: Select desired GPIO pin (valid 0 to 18).
time delay. Can be positive or negative. Maximum/ • orxMode1Pin: Select desired GPIO pin (valid 0 to 18).
minimum delay is abs(215/(TxLaneRate_MHz/40)). • orxMode0Pin: Select desired GPIO pin (valid 0 to 18).
• Tdd2ndOrx1TxLoDataPathDel_us: ORx1 with Tx LO
secondary start and stop time delay. Can be positive or
negative. Maximum/minimum delay is
abs(215/(TxLaneRate_MHz/40)).
• Tdd2ndOrx2TxLoDataPathDel_us: ORx2 with Tx LO
secondary start and stop time delay. Can be positive or
negative. Maximum/minimum delay is
abs(215/(TxLaneRate_MHz/40)).
• TddSnRxDataPathDel_us: SnRx (A, B, or C) secondary
start and stop time delay. Can be positive or negative.
Maximum/minimum delay is
abs(215/(TxLaneRate_MHz/40)).

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UG-992 AD9371/AD9375 System Development User Guide
Mykonos ARM Output GPIO Pins (Always Available, • orx2EnableAck: select desired GPIO pin (0 to 15),
Even When Pin Mode Not Enabled) [4] = output enable.
Mykonos ARM output GPIO pins (always available, even when • srxEnableAck: select desired GPIO pin (0 to 15),
pin mode is not available) include the following: [4] = output enable.
• txObsSelect: select desired GPIO pin (0 to 15), [4] = output
• rx1EnableAck: select desired GPIO pin (0 to 15), enable. When two Tx are used with only one ORx input,
[4] = output enable. this GPIO tells the baseband processor (BBP) which Tx
• rx2EnableAck: select desired GPIO pin (0 to 15), channel is active for calibrations, so that the BBP can route
[4] = output enable. the correct radio frequency (RF) Tx path into the single
• tx1EnableAck: select desired GPIO pin (0 to 15), ORx input.
[4] = output enable.
• tx2EnableAck: select desired GPIO pin (0 to 15),
[4] = output enable.
• orx1EnableAck: select desired GPIO pin (0 to 15),
[4] = output enable.

Rev. B | Page 194 of 360

AD9371/AD9375 System Development User Guide UG-992

GENERAL-PURPOSE INPUT/OUTPUT (GPIO) CONFIGURATION

The device provides 19 general-purpose input/output (GPIO) programming interface (API) functions created to manage this
capable signals that can be used for a variety of control functions. block allow the user to configure pins as inputs or outputs for
These signals can be configured using the transceiver evaluation specific functions. This section describes the GPIO signals and
software (TES) to demonstrate the available configurations. This their behavior in detail, while also describing how to program
user guide refers to these signals as GPIO_x, where x is the GPIO the device using the API functions so that the desired signals
number 0 through 18. All 19 signals have output buffers powered are available on the appropriate pins.
from the VDD_IF domain. The voltage range for these outputs Figure 93 outlines different functionalities that can be enabled
is the same as the VDD_IF supply: 1.8 V to 2.5 V. in the device and then controlled using the GPIO interface. Not
In addition to being used as general-purpose control signals, all functionalities can be enabled at the same time. Use the TES
certain GPIO pins can be used as real-time control signals that to preconfigure API structures, ensuring that the desired
provide operational details from the device to the baseband combination is possible, and that there are no conflicts on the
processor (BBP) when configured as outputs, enabling transceiver GPIO interface.
performance monitoring in different situations. The application

GPIO MODES OF OPERATION 1

I/O CROSSPOINT 1 I/O BUFFER
GPIO_18 J3
GENERAL-PURPOSE INPUT/OUTPUT
GPIO_17 M10
GPIO_16 M11
CONTROL OUTPUT
GPIO_15 L11
ARM GPIO INTERFACE GPIO_14 K11
GPIO_13 J11
GPIO_12 H11

GPIO MODES OF OPERATION 2 GPIO_11 H12

GPIO_10 J12
I/O CROSSPOINT 2
Rx MANUAL GAIN CONTROL GPIO_9 K12
GPIO_8 L12

Tx ATTENUATION CONTROL GPIO_7 L6

GPIO_6 L8

Rx AGC GPIO INTERFACE GPIO_5 K5

GPIO_4 K6

SLICER CONTROL GPIO_3 K7

GPIO_2 J7
GPIO_1 J8
ORx AGC GPIO CONTROL
GPIO_0 K8

14652-082

Figure 93. Overview of the GPIO Modes of Operation

Rev. B | Page 195 of 360

UG-992 AD9371/AD9375 System Development User Guide
GPIO OPERATION GPIO mode can only be configured in the radio off state. Use
Figure 94 outlines the flow of events to follow while configuring the transceiver evaluation software (TES) to set member values for
the GPIO in a desired configuration. In general, all general- all GPIO structures, ensuring that there is no conflict among the
purpose input/output (GPIO) configuring can be performed in different GPIO functionalities.
the radio on or radio off state, except ARM GPIO mode. ARM

START

USE TRANSCEIVER EVALUATION

SOFTWARE TO CONFIGURE GPIO STRUCTURES
FOR DESIRED MODE OF OPERATION

setGpioDrv()

setGpioSlewRate()

ENABLE Rx GAIN YES

setRx1GainCtrlPin()
CONTROL?
setRx2GainCtrlPin()
NO

ENABLE Tx ATTEN. YES

setTx1AttenCtrlPin()
CONTROL?

NO Tx1 GPIO FOR NO

ATTEN.CTRL.OF Tx1 setTx2AttenCtrlPin()
AND Tx2?

YES

YES
SET GPIO FOR
ARM?

NO IN (RADIO OFF) YES

init_armGpioStructure()
STATE?
setArmGpioPins()
NO
setRadioControlPinMode()

setupGpio()

SET GPIO FOR YES

MANUAL?

NO IS GPIO STRUCTURE
CONFIGURED FOR MANUAL YES
getGpioPinLevel()
MODE USING setupGpio()? AND/OR
setGpioPinLevel()

NO

YES
ENABLE MONITOR
OUTPUTS?

NO IS GPIO STRUCTURE
CONFIGURED FOR MONITOR YES
getGpioMonitorOut()
OUT USING setupGpio()?

NO
14652-083

STOP

Figure 94. GPIO Interface Configuration and Control Flowchart

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AD9371/AD9375 System Development User Guide UG-992
API Description MYKONOS_setupGpio
As shown in Figure 93, there are many functionalities available mykonosGpioErr_t
that can be enabled and to interact with the baseband processor MYKONOS_setupGpio(mykonosDevice_t *device)
(BBP) over the general-purpose input/output (GPIO) interface. This function sets the GPIO configuration registers. It
Two separate crosspoint switches and one buffer must be configures the pin direction for each GPIO, as well as the
configured properly to enable a particular functionality. The crosspoints. This function relies on the correct settings of the
application programming interface (API) package includes device → auxIo → gpio structure members. An overview of this
functions that can configure all blocks to desired states. The structure follows:
following sections contain general API functions and short
descriptions of their functionalities.

typedef struct
{
uint32_t gpioOe; /*!< Output Enable per low voltage GPIO pin
(1=output, 0=input) */
mykonosGpioMode_t gpioSrcCtrl3_0; /*!< Mode for low voltage GPIO[3:0] pins */
mykonosGpioMode_t gpioSrcCtrl7_4; /*!< Mode for low voltage GPIO[7:4] pins */
mykonosGpioMode_t gpioSrcCtrl11_8; /*!< Mode for low voltage GPIO[11:8] pins */
mykonosGpioMode_t gpioSrcCtrl15_12; /*!< Mode for low voltage GPIO[15:12] pins */
mykonosGpioMode_t gpioSrcCtrl18_16; /*!< Mode for low voltage GPIO[18:16] pins */
} mykonosGpioLowVoltage_t;

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UG-992 AD9371/AD9375 System Development User Guide
The gpioOe function controls configuration of the I/O buffer MYKONOS_setGpioSourceCtrl
shown in Figure 93. The gpioSrcCtrlNN_nn function controls mykonosGpioErr_t
the configuration of I/O Crosspoint 1, as shown in Figure 93. MYKONOS_setGpioSourceCtrl(mykonosDevice_t
The values for gpioSrcCtrlNN_nn are as follows: *device, uint32_t gpioSrcCtrl)
• GPIO_MONITOR_MODE. This value allows a choice of This is a helper function called by the MYKONOS_setupGpio()
debug signals to output from the device to monitor the state function (the helper function must not be called by the user).
of the device. See the Monitor Output section for more details. This function configures crosspoints for different GPIO
• GPIO_BITBANG_MODE—(manual mode). This functionality. This function only affects the GPIO pins that have
application programming interface (API) function sets the their output enable direction set by the MYKONOS_getGpioOe()
output pin levels and reads the input pin levels. See the function as outputs.
GPIO Manual Mode section for more details. Parameters
• GPIO_ARM_OUT_MODE. This value allows the internal
ARM processor to output on the GPIO pins. See the ARM • gpioSrcCtrl: This parameter is a nibble-based source
GPIO Interface section for more details. control, and it is a 32-bit value containing five nibbles that
• GPIO_SLICER_OUT_MODE. This value assigns the slicer set the source control. Use the TES to generate correct
active configuration to the GPIO output pins. See the ARM settings for a desired configuration.
GPIO Interface section for more details. MYKONOS_getGpioSourceCtrl
mykonosGpioErr_t
Use the transceiver evaluation software (TES) to set member MYKONOS_getGpioSourceCtrl(mykonosDevice_t
values of this structure, which ensures that there are no conflicts *device, uint32_t *gpioSrcCtrl)
with other GPIO functions. This function reads back the current status of the GPIO source
MYKONOS_setGpioOe control for different GPIO functionality.
mykonosGpioErr_t Parameters
MYKONOS_setGpioOe(mykonosDevice_t
*device, uint32_t gpioOutEn, uint32_t • *gpioSrcCtrl: This parameter is a nibble-based source
gpioUsedMask) control, and it is a 32-bit value containing five nibbles that
This is a helper function called by the MYKONOS_setupGpio() represent the current settings of the source control
function (this helper function must not be called by the user). (crosspoint configuration).
MYKONOS_setGpioDrv
This function sets the GPIO direction given by the passed
parameter. This direction can be either output or input. The mykonosGpioErr_t
gpioUsedMask parameter allows the function to affect only the MYKONOS_setGpioDrv(mykonosDevice_t
*device, mykonosGpioSelect_t gpioDrv)
GPIO pins of interest.
This function configures the drive strength of each GPIO. This
Parameters function only affects the GPIO pins that have their OE direction
• gpioOutEn: The valid range for this variable is from 0x0 to set by the MYKONOS_getGpioOe() function as outputs.
0x07FFFF. Each bit represents the corresponding GPIO pin Parameters
(Bit 0 represents GPIO_0, Bit 1 represents GPIO_1, and so
on). The direction of the input buffer is set by each bit • gpioDrv: This parameter indicates which GPIO is to be
value: 0 indicates input, and 1 indicates output. selected to set its drive strength. If the bit in gpioDrv
corresponds to particular a GPIO is set to 0, the drive
• gpioUsedMask: This parameter is the mask used to control
strengths of this GPIO is set as described in the data sheet.
which bits are set/cleared. If a mask bit = 1, that bit is
If a bit in gpioDrv corresponds to a particular GPIO is set
modified by the value in GPIOOUTEN.
to 1, the drive strengths of this GPIO is doubled, compare
MYKONOS_getGpioOe to the description in the data sheet. The valid range of this
mykonosGpioErr_t parameter is from 0x00000 to 0x7FFFF. There are
MYKONOS_getGpioOe(mykonosDevice_t limitations for the way drive strength can be configured.
*device, uint32_t *gpioOutEn)
Table 141 outlines these limitations in the configuration
This function reads back the current status of the GPIO direction flexibility.
set in the device. The direction can be either output or input.
The range of GPIO pins from GPIO_8 to GPIO_17 can only
The function parameter returns a bit per GPIO pin where 1
be selected in pairs. Setting one of the corresponding bits
indicates output and 0 indicates input
automatically selects the other one, meaning, for example, if it is
Parameters required to double the drive strength for GPIO_17, the drive
• *gpioOutEn: This parameter is a pointer to the data to be strength is also doubled for GPIO_16, and so on.
returned with the output enable GPIO pins.
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AD9371/AD9375 System Development User Guide UG-992
Table 141. GPIO Configuration Limitations—gpioDrv
GPIO Pin Corresponding Bits in the gpioDrv Parameter
GPIO_0 xxx xxxx xxxx xxxx xxxN
GPIO_1 xxx xxxx xxxx xxxx xxNx
… xxx xxxx xxxx xNNN NNxx
GPIO_7 xxx xxxx xxxx Nxxx xxxx
GPIO_8 xxx Nxxx xxxN xxxx xxxx
GPIO_9 xxx xxxx xNNx xxxx xxxx
GPIO_10 xxx xxxx xNNx xxxx xxxx
GPIO_11 xxx xxxN Nxxx xxxx xxxx
GPIO_12 xxx xxxN Nxxx xxxx xxxx
GPIO_13 xxx xNNx xxxx xxxx xxxx
GPIO_14 xxx xNNx xxxx xxxx xxxx
GPIO_15 xxx Nxxx xxxN xxxx xxxx
GPIO_16 xNN xxxx xxxx xxxx xxxx
GPIO_17 xNN xxxx xxxx xxxx xxxx
GPIO_18 Nxx xxxx xxxx xxxx xxxx

MYKONOS_getGpioDrv Parameters
mykonosGpioErr_t
MYKONOS_getGpioDrv(mykonosDevice_t • *gpioDrv: This parameter is a pointer to the data to be
*device, mykonosGpioSelect_t *gpioDrv) returned with the current GPIOs drive strength setting.
Refer to the MYKONOS_setGpioDrv() function
This function reads back the current status of the GPIO drive
description for bit field interpretation.
strength setting, set by the MYKONOS_setGpioDrv() function.

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UG-992 AD9371/AD9375 System Development User Guide
MYKONOS_setGpioSlewRate The GPIO pins from GPIO_8 to GPIO_17 can only be selected
mykonosGpioErr_t in pairs. Setting one bit automatically selects the other one. For
MYKONOS_setGpioSlewRate(mykonosDevice_t example, if it is required to set the slew rate for GPIO_17, the
*device, mykonosGpioSelect_t gpioSelect, same slew rate is also applied for GPIO_16, and so on.
mykonosGpioSlewRate_t slewRate)
MYKONOS_getGpioSlewRate
This function configures the slew rate of the selected GPIO. mykonosGpioErr_t
This function only affects the GPIO pins that have their output MYKONOS_getGpioSlewRate(mykonosDevice_t
enable direction set by the MYKONOS_getGpioOe() function *device, mykonosGpioSelect_t gpioSelect,
as outputs. mykonosGpioSlewRate_t *slewRate)

Parameters This function reads back the current status of the GPIO slew
rate setting set by the MYKONOS_setGpioSlewRate() function.
• gpioSelect: This parameter indicates which GPIO is to be
Parameters
selected to set its slew rate. If the bit in gpioSelect that
corresponds to a particular GPIO is set to 0, its slew rate • gpioSelect: This parameter indicates which GPIO is
does not change. If the bit in gpioSelect that corresponds to selected to read back its programmed slew rate settings
a particular GPIO is set to 1, its slew rate changes to the Each bit in gpioSelect corresponds to a particular GPIO.
value selected by the slewRate parameter. The valid range GPIO_0 is selected by Bit 0, GPIO_1 is selected by Bit 1,
for this parameter is from 0x00000 to 0x7FFFF. There are and so on. Setting a bit to 1 selects the corresponding
limitations in the way that GPIO can be selected for its GPIO. Only a single GPIO can be selected at one time. The
slew rate settings. Table 142 outlines these limitations in valid range on this parameter is from 0x00000 to 0x7FFFF.
the configuration flexibility. • *slewRate: This parameter is a pointer to the data to be
• slewRate: This parameter contains information of slew rate returned with the current slew rate programmed for the
that to be applied to the GPIO selected using the gpioSelect GPIO selected by the gpioSelect parameter. Refer to the
parameter.The valid slew rate settings are given by the MYKONOS_setGpioSlewRate() function for a description
enumeration type mykonosGpioSlewRate_t. of the mykonosGpioSlewRate_t enumeration type.
• MYK_SLEWRATE_NONE—lower slew rate for the
selected GPIO.
• MYK_SLEWRATE_LOW—low slew rate for the
selected GPIO.
• MYK_SLEWRATE_MEDIUM—medium slew rate for
the selected GPIO.
• MYK_SLEWRATE_HIGH—high slew rate for the
selected GPIO

Table 142. GPIO Configuration Limitations—gpioSelect

GPIO Pin Corresponding Bits in the gpioDrv Parameter
GPIO_0 xxx xxxx xxxx xxxx xxxN
GPIO_1 xxx xxxx xxxx xxxx xxNx
… xxx xxxx xxxx xNNN NNxx
GPIO_7 xxx xxxx xxxx Nxxx xxxx
GPIO_8 xxx Nxxx xxxN xxxx xxxx
GPIO_9 xxx xxxx xNNx xxxx xxxx
GPIO_10 xxx xxxx xNNx xxxx xxxx
GPIO_11 xxx xxxN Nxxx xxxx xxxx
GPIO_12 xxx xxxN Nxxx xxxx xxxx
GPIO_13 xxx xNNx xxxx xxxx xxxx
GPIO_14 xxx xNNx xxxx xxxx xxxx
GPIO_15 xxx Nxxx xxxN xxxx xxxx
GPIO_16 xNN xxxx xxxx xxxx xxxx
GPIO_17 xNN xxxx xxxx xxxx xxxx
GPIO_18 Nxx xxxx xxxx xxxx xxxx

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AD9371/AD9375 System Development User Guide UG-992
GPIO MANUAL MODE higher priority when accessing the I/O buffer. To configure the
device for GPIO manual mode only, or for manual mode when
Figure 95 shows the GPIO_x signals in GPIO manual mode. In working with any other GPIO mode in parallel, use the transceiver
this mode, the user can configure GPIOs as outputs or inputs. evaluation software (TES) to preconfigure the application
If a GPIO pin is configured as an output, the user can also programming interface (API) auxIo/gpio structure with valid
control its logic level. If a GPIO pin is configured as an input, configurations prior to writing the code to accomplish this
the user can read back the voltage level present at the input. function.
In both cases, low (or 0) corresponds to the ground level and Manual mode uses Crosspoint 1. This crosspoint operates using
high (or 1) corresponds to the VDD_IF voltage level. nibbles (4 bits); the GPIOs are controlled in groups of four. The
Note that two I/O crosspoints (Crosspoint 1 and Crosspoint 2) exception to this is that the three most significant GPIOs operate in
access a single I/O buffer (see Figure 93). Crosspoint 2 has a a block of three (GPIO_16, GPIO_17, and GPIO_18).

I/O CROSSPOINT 1 I/O BUFFER

BIT 18 GPIO_18
BIT 17 GPIO_17
BIT 16 GPIO_16
SETUP
1 = HIGH
BIT N
0 = LOW BIT 15 GPIO_15
BIT 14 GPIO_14
x x x x x BIT 18 BIT 17 BIT 16
setGpioPinLevel BIT 13 GPIO_13
(gpioPinLevel) BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 12 GPIO_12

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

BIT 11 GPIO_11
BIT 10 GPIO_10
BIT 9 GPIO_9
BIT 8 GPIO_8
READBACK
1 = HIGH
BIT N
BIT 7 GPIO_7
0 = LOW
BIT 6 GPIO_6
x x x x x BIT 18 BIT 17 BIT 16 BIT 5 GPIO_5
getGpioPinLevel BIT 4 GPIO_4
(gpioPinLevel) BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

BIT 3 GPIO_3
BIT 2 GPIO_2
BIT 1 GPIO_1
BIT 0 GPIO_0

setGpioDrv (gpioDrv) getGpioSourceCtrl getGpioOe

setGpioSlewRate (gpioSrcCtrl) (gpioOutEn)
(gpioSelect, slewRate)

setGpio (auxio->gpio STRUCTURE)

14652-084

Figure 95. GPIO Manual Mode

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UG-992 AD9371/AD9375 System Development User Guide
API Description MYKONOS_getGpioSetLevel
The application programming interface (API) provides mykonosGpioErr_t
functions designed to operate the GPIO in manual mode. Before MYKONOS_getGpioSetLevel(mykonosDevice_t
the user can employ manual mode, the crosspoints and the I/O *device, uint32_t *gpioPinSetLevel)
buffer must be configured. Use the MYKONOS_setupGpio() This function provides readback of the value describing how
function to properly configure the crosspoints and the I/O GPIO output pins are set in the manual mode.
buffer. This function relies on correct configuration of device → Parameters
auxIo → gpio structure members. Use the transceiver evaluation
software (TES) to generate correct settings for this structure. • *gpioPinSetLevel: This parameter is a pointer to the 32-bit
After the crosspoints and I/O buffer are configured, the user variable that contains the level of each GPIO pin, 1 bit per
can start operating the GPIOs in manual mode. The following pin (0 = sets output to low level, and 1 = sets output to high
sections list the manual mode API functions, along with short level).
descriptions of their functionalities. MONITOR OUTPUT
MYKONOS_getGpioPinLevel The device offers the capability to output a real-time status for a
mykonosGpioErr_t variety of internal conditions or states through the GPIO interface
MYKONOS_getGpioPinLevel(mykonosDevice_t to the baseband processor (BBP). Information, such as the state
*device, uint32_t *gpioPinLevel) of the overload detectors in the receiver signal path or
This function reads the GPIO pins that are set as inputs in automatic gain control (AGC) states, are just a few of the many
manual mode. Pin levels are returned in the form of a single 32-bit options available. This section describes these signals and also
word. The return value is 1 bit per pin. The GPIO_0 level returns how to use API functions to make the desired signals available
on Bit 0 of the gpioPinLevel parameter, the GPIO_1 level returns on the appropriate GPIO pins. Figure 96 shows the possible
on Bit 1, and so on. A logic low level returns a 0, and a logic connections between the monitor output signals and the GPIO
high level returns a 1. pins. Note that the logic block format of the figure shows the
Parameters functional operation of the GPIO signals, but it does not necessarily
represent the method of implementation inside the device.
• *gpioPinLevel: the input GPIO pin levels read back on the
The monitor output signals allow the user to monitor selected
pins assigned as inputs (1 bit per pin).
internal device functions by outputting a single row from the
MYKONOS_setGpioPinLevel monitor output signal table. Table 143 lists the available signal
mykonosGpioErr_t combinations that can be routed to the selected GPIO pins. The
MYKONOS_setGpioPinLevel(mykonosDevice_t user can only monitor the signals in one row at a time. Selection
*device, uint32_t gpioPinLevel) of one signal over another depends on which other signals the
This function sets the GPIO output pin levels. This function BBP must monitor simultaneously. Some internal signals are
only affects the GPIO pins that are set as outputs in manual available on more than one table row using different GPIO
mode. GPIO_0 reflects the Bit 0 status of the gpioPinLevel assignments. Some of the signals are helpful in a production
parameter, GPIO_1 reflects the Bit 1 status, and so on. A logic system, while others are useful for debugging purposes. In
low is set at the GPIO output if its corresponding bit is set to 0. either case, Analog Devices recommends connecting the device
A logic high is set at the GPIO output if its corresponding bit is monitor outputs to the BBP inputs so that the signals can be
set to 1. monitored under real-time conditions.
Parameters
• gpioPinLevel: This parameter describes the output level for
each bit per GPIO pin (0 = low output, and 1 = high output).

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AD9371/AD9375 System Development User Guide UG-992

setGpioMonitorOut MONITOR OUTPUTS SIGNALS I/O CROSSPOINT 1 I/O BUFFER

(monitorIndex, D7 D6 D5 D4 D3 D2 D1 D0
monitorMask D6 GPIO_18
D5 GPIO_17
D4 GPIO_16
D6 TO D4

D7 GPIO_15
D6 GPIO_14
D5 GPIO_13
D7 TO D4 D4 GPIO_12

D3 GPIO_11
D2 GPIO_10
D1 GPIO_9
D0 D3 TO D0 D0 GPIO_8
0b xxxx xxxN
D1
0b xxxx xxNx D7 GPIO_7
D2 D6 GPIO_6
0b xxxx xNxx
D5 GPIO_5
D3
0b xxxx Nxxx D7 TO D4 D4 GPIO_4
D4
0b xxxN xxxx
D5 D3 GPIO_3
0b xxNx xxxx
D2 GPIO_2
D6 D1 GPIO_1
0b xNxx xxxx
D3 TO D0 D0 GPIO_0
D7
0b Nxxx xxxx

setGpioMonitorOut setGpioDrv (gpioDrv) getGpioSourceCtrl getGpioOe

(monitorIndex, setGpioSlewRate (gpioSrcCtrl) (gpioOutEn)
monitorMask) (gpioSelect, slewRate)

setGpio (auxio->gpio STRUCTURE)

14652-085
Figure 96. Monitor Output Signal Routing

Table 143. Monitor Output Signals

Monitor Bits
Index D7 D6 D5 D4 D3 D2 D1 D0
0x01 Rx1: gain change Rx1: APD upper Rx1: HB2 upper Rx1: HB2 lower Rx2: gain Rx2: APD upper Rx2: HB2 upper Rx2: HB2 lower
(OR of gain threshold threshold threshold change (OR of threshold threshold threshold
increment/ counter counter counter gain increment/ counter counter counter
gain decrement) exceeded exceeded exceeded gain decrement) exceeded exceeded exceeded
(slow loop)
0x02 Rx1: gain change Rx1: APD upper Rx1: HB2 upper Rx1: digital Rx2: gain Rx2: APD upper Rx2: HB2 upper Rx2: digital
(OR of gain threshold threshold saturation change (OR of threshold threshold saturation
increment/ exceeded exceeded gain increment/ exceeded exceeded
gain decrement) gain decrement)
0x03 Rx1: gain lock Rx1: APD upper Rx1: HB2 upper Rx1: energy lost Rx2: gain lock Rx2: APD upper Rx2: HB2 upper Rx2: energy lost
threshold threshold threshold threshold
exceeded exceeded exceeded exceeded
0x04 Rx1: low Rx1: high Rx1: gain update Reserved Rx1: gain Rx1: gain Rx1: gain change
threshold threshold counter expired change change decrement
exceeded exceeded increment
0x05 Rx2: low Rx2: high Rx2: gain update Reserved Rx2: gain Rx2: gain Rx2: gain change
threshold threshold counter expired change change decrement
exceeded exceeded increment
0x06 Rx1: gain change Rx1: gain change Rx2: gain change Rx2: gain change Reserved
increment decrement increment decrement

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UG-992 AD9371/AD9375 System Development User Guide
Monitor Bits
Index D7 D6 D5 D4 D3 D2 D1 D0
0x07 Rx1: APD upper Rx1: HB2 upper Rx1: gain update Rx1: gain change Rx2: APD upper Rx2: HB2 upper Rx2: gain Rx2: gain change
threshold threshold counter expired threshold threshold update counter
counter counter counter counter expired
exceeded exceeded exceeded exceeded
(slow loop)
0x08 Rx1: decrement Rx1: gain update Rx1: APD upper Rx1: HB2 upper Rx2: decimate Rx2: gain Rx2: APD upper Rx2: HB2 upper
power ready counter expired threshold threshold power ready update counter threshold threshold
counter counter expired counter counter
exceeded exceeded exceeded exceeded
(slow loop)
0x09 Rx1: gain index Rx1: gain index Rx1: gain index Rx1: gain index Rx1: gain index Rx1: gain index Rx1: gain index Rx1: gain index
(Bit D7) (Bit D6) (Bit D5) (Bit D4) (Bit D3) (Bit D2) (Bit D1) (Bit D0)
0x0A Rx2: gain index Rx2: gain index Rx2: gain index Rx2: gain index Rx2: gain index Rx2: gain index Rx2: gain index Rx2: gain index
(Bit D7) (Bit D6) (Bit D5) (Bit D4) (Bit D3) (Bit D2) (Bit D1) (Bit D0)
0x0C Rx1: gain index Rx1: gain index Rx1: gain index Rx1: gain index Rx2: gain index Rx2: gain index Rx2: gain index Rx2: gain index
(Bit D3) (Bit D2) (Bit D1) (Bit D0) (Bit D3) (Bit D2) (Bit D1) (Bit D0)
0x22 Tx2: RFIR Tx2: Tx HB2 Tx2: Tx HB1 Tx2: TFIR Tx1: RFIR Tx1: Tx HB2 Tx1: Tx HB1 Tx1: TFIR
overflow overflow overflow overflow overflow overflow overflow overflow
0x23 Reserved Rx1: Signal of Rx1: correction Rx1: update Rx1: gain Rx1: update dc Rx1: measure dc Rx1: RF dc count
interest (SOI) word above counter expired change offset in the RF offset in the RF reached
present threshold section section
0x24 Reserved Rx2: SOI present Rx2: correction Rx2: update Rx2: gain Rx2: update dc Rx2: measure dc Rx2: RF dc count
word above counter expired change offset in the RF offset in the RF reached
threshold section section
0x42 Rx2 overrange Rx2 overrange Rx2 overrange Rx2 gain update Rx1 overrange Rx1 overrange Rx1 overrange Rx1 gain update
very low counter low counter high counter counter expired very low low counter high counter counter expired
exceeded exceeded exceeded counter exceeded exceeded
exceeded
0x43 Reserved ORx overrange ORx overrange ORx overrange ORx gain update
very low low counter high counter counter expired
counter exceeded exceeded
exceeded

Table 144 through Table 159 provide the detailed descriptions of the signals available for each monitor index address listed in Table 143.

Table 144. Monitor Index: 0x01 (Name: AGC Monitor 1)

Bits Description Reset
D7 Rx1: gain change. The gain index (in automatic gain control (AGC) and manual gain control (MGC) mode) is used to select an 0x0
entry in the gain table. This signal is active (output level toggle between high and low) only if there is a difference in entries
in the gain table when the AGC or MGC index changes. If the entries of the two indices are identical, the Rx gain change signal
is not generated (toggled).
D6 Rx1 APD upper threshold counter exceeded. The Rx1 analog peak detector (APD) is set when the upper threshold counter is 0x0
exceeded. This bit operates in real-time.
D5 Rx1 HB2 upper threshold counter exceeded. Set this bit when the Rx1 ADC/High-Band 2 (HB2) upper threshold overflow counter is 0x0
exceeded.
D4 Rx1 HB2 lower threshold counter exceeded. Set this bit when the Rx1 ADC/HB2 lower threshold overflow counter is exceeded. 0x0
D3 Rx2: gain change. The gain index (in AGC and MGC mode) selects an entry in the gain table. This signal is active (the output 0x0
level toggles between high and low) only if there is a difference in entries in the gain table when the AGC or MGC index
changes. If the entries of the two indices are identical, the Rx gain change signal is not generated (toggled).
D2 Rx2 APD upper threshold counter exceeded. The Rx2 APD set when the upper threshold counter is exceeded. This bit 0x0
operates in real-time.
D1 Rx2 HB2 upper threshold counter exceeded. Set this bit when the Rx2 ADC/HB2 upper threshold overflow counter is exceeded. 0x0
D0 Rx2 HB2 lower threshold counter exceeded. Set this bit when the Rx2 ADC/HB2 lower threshold overflow counter is exceeded. 0x0

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Table 145. Monitor Index: 0x02 (Name: AGC Monitor 2)
Bits Description Reset
D7 Rx1: gain change. The gain index (in automatic gain control (AGC) and manual gain control (MGC) mode) is used to select an 0x0
entry in the gain table. This signal is active (the output level toggles between high and low) only if there is a difference in
entries in the gain table when the AGC or MGC index changes. If the entries of the two indices are identical, the Rx gain
change signal is not generated (toggled).
D6 Rx1: analog peak detector (APD) upper threshold exceeded. Set this bit when the upper threshold is exceeded. This bit 0x0
operates in real-time.
D5 Rx1: High-Band 2 (HB2) upper threshold. Set this bit when high threshold detector overflow occurs. 0x0
D4 Rx1: digital saturation. Set this bit when the signal is saturated after digital gain is applied. 0x0
D3 Rx2: gain change. The gain index (in AGC and MGC mode) is used to select an entry in the gain table. This signal is active (the 0x0
output level toggles between high and low) only if there is a difference in entries in the gain table when the AGC or MGC
index changes. If the entries of the two indices are identical, the Rx gain change signal is not generated (toggled).
D2 Rx2: APD upper threshold exceeded. Set this bit when the upper threshold is exceeded. This bit operates in real-time. 0x0
D1 Rx2: HB2 upper threshold exceeded. Set this bit when high threshold detector overflow occurs. 0x0
D0 Rx2 digital saturation. Set this bit when the signal is saturated after digital gain is applied. 0x0

Table 146. Monitor Index: 0x03 (Name: AGC Monitor 3)

Bits Description Reset
D7 Rx1: gain lock. Set this bit when the gain locks. 0x0
D6 Rx1: APD upper threshold exceeded. Set this bit when the upper threshold is exceeded. This bit operates in real-time. 0x0
D5 Rx1: HB2 upper threshold. Set this bit when high threshold detector overflow occurs. 0x0
D4 Rx1: energy lost. Set this bit when the signal power change exceeds the lower threshold. 0x0
D3 Rx2: gain lock. Set this bit when the gain locks. 0x0
D2 Rx2: APD upper threshold exceeded. Set this bit when the upper threshold is exceeded. This bit operates in real-time. 0x0
D1 Rx2: HB2 upper threshold. Set this bit when high threshold detector overflow occurs. 0x0
D0 Rx2: energy lost. Set this bit when the signal power change exceeds the threshold. 0x0

Table 147. Monitor Index: 0x04 (Name: AGC Monitor 4)

Bits Description Reset
D7 Rx1: low threshold exceeded. Set this bit when the low power threshold is exceeded. 0x0
D6 Rx1: high threshold exceeded. Set this bit when the high power threshold is exceeded. 0x0
D5 Rx1: gain update counter expired. This bit signals when the gain update counter expires. 0x0
[D4:D3] Reserved. 0x0
D2 Rx1: gain change. The gain index (in AGC and MGC mode) is used to select an entry in the gain table. This signal is active 0x0
(the output level toggles between high and low) only if there is a difference in entries in the gain table when the AGC or
MGC index changes. If the entries of the two indices are identical, the Rx gain change signal is not generated (toggled).
D1 Rx1: gain change increment. This bit toggles when the gain increases. 0x0
D0 Rx1: gain change decrement. This bit toggles when the gain decreases. 0x0

Table 148. Monitor Index: 0x05 (Name: AGC Monitor 5)

Bits Description Reset
D7 Rx2: low threshold exceeded. Set this bit when the low power threshold is exceeded. 0x0
D6 Rx2: high threshold exceeded. Set this bit when the high power threshold is exceeded. 0x0
D5 Rx2: gain update counter expired. This bit signals when the gain update counter expires. 0x0
[D4:D3] Reserved. 0x0
D2 Rx2: gain change. This bit toggles when the gain changes value. 0x0
D1 Rx2: gain change increment. This bit toggles when the gain increases. 0x0
D0 Rx2: gain change decrement. This bit toggles when the gain decreases. 0x0

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Table 149. Monitor Index: 0x06 (Name: AGC Monitor 6)
Bits Description Reset
D7 Rx1: gain change increment. This bit toggles when the gain increases. 0x0
D6 Rx1: gain change decrement. This bit toggles when the gain decreases. 0x0
D5 Rx2: gain change increment. This bit toggles when the gain increases. 0x0
D4 Rx2: gain change decrement. This bit toggles when the gain decreases. 0x0
[D3:D0] Reserved. 0x0

Table 150. Monitor Index: 0x07 (Name: AGC Monitor 7)

Bits Description Reset
D7 Rx1 APD upper threshold counter exceeded. The Rx1 analog peak detector (APD) is set when the upper threshold counter is 0x0
exceeded. This bit operates real-time.
D6 Rx1 HB2 upper threshold counter exceeded. Set this bit when the Rx1 ADC/High-Band 2 (HB2) upper threshold overflow 0x0
counter is exceeded.
D5 Rx1: gain update counter expired. This bit signals when the gain update counter expires. 0x0
D4 Rx1: gain change. The gain index (in automatic gain control (AGC) and manual gain control (MGC) mode) is used to select an 0x0
entry in the gain table. This signal is active (the output level toggles between high and low) only if there is a difference in
entries in the gain table when the AGC or MGC index changes. If the entries of the two indices are identical, the Rx gain change
signal is not generated (toggled).
D3 Rx2 APD upper threshold counter exceeded. The Rx2 analog peak detector (APD) is set when the upper threshold counter is 0x0
exceeded. This bit operates real-time.
D2 Rx2 HB2 upper threshold counter exceeded. Set this bit when the Rx2 ADC/HB2 upper threshold overflow counter is exceeded. 0x0
D1 Rx2: gain update counter expired. This bit signals when the gain update counter expires. 0x0
D0 Rx2: gain change. The gain index (in AGC and MGC mode) is used to select an entry in the gain table. This signal is active (the 0x0
output level toggles between high and low) only if there is a difference in entries in the gain table when the AGC or MGC
index changes. If the entries of the two indices are identical, the Rx Gain change signal is not generated (toggled).

Table 151. Monitor Index: 0x08 (Name: AGC Monitor 8)

Bits Description Reset
D7 Rx1: decimated power ready. The received signal strength indicator (RSSI) power word is ready. 0x0
D6 Rx1: gain update counter expired. Signals when the gain update counter expires. 0x0
D5 Rx1 APD upper threshold counter exceeded. The Rx1 APD is set when the upper threshold counter is exceeded. This bit 0x0
operates real-time.
D4 Rx1 HB2 upper threshold counter exceeded. Set this bit when the Rx1 ADC/HB2 upper threshold overflow counter is exceeded. 0x0
D3 Rx2: decimated power ready. RSSI power word is ready. 0x0
D2 Rx2: gain update counter expired. This bit signals when the gain update counter expires. 0x0
D1 Rx2 APD upper threshold counter exceeded. The Rx2 APD is set when the upper threshold counter is exceeded. This bit 0x0
operates real-time.
D0 Rx2 HB2 upper threshold counter exceeded. Set this bit when the Rx2 ADC/HB2 upper threshold overflow counter is exceeded. 0x0

Table 152. Monitor Index: 0x09 (Name: AGC Monitor 9)

Bits Description Reset
[D7:D0] AGC—Rx1 gain index 0x0

Table 153. Monitor Index: 0x0A (Name: AGC Monitor 10)

Bits Description Reset
[D7:D0] AGC—Rx2 gain index 0x0

Table 154. Monitor Index: 0x0C (Name: AGC Monitor 11)

Bits Description Reset
[D7:D4] AGC—Rx1 gain index (4 LSBs only) 0x0
[D3:D0] AGC—Rx2 gain index (4 LSBs only) 0x0

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AD9371/AD9375 System Development User Guide UG-992
Table 155. Monitor Index: 0x22 (Name: Datapath Overflow)
Bits Description Reset
D7 Tx2 datapath—RFIR overflow error 0x0
D6 Tx2 datapath—HB2 overflow 0x0
D5 Tx2 datapath—HB1 overflow 0x0
D4 Tx2 datapath—TFIR overflow 0x0
D3 Tx1 datapath—RFIR overflow error 0x0
D2 Tx1 datapath—HB2 overflow 0x0
D1 Tx1 datapath—HB1 overflow 0x0
D0 Tx1 datapath—TFIR overflow 0x0

Table 156. Monitor Index: 0x23 (Name: RF DC Offset Correction Tracking Signals, Channel 1)
Bits Description Reset
D7 Reserved. 0x0
D6 Rx1: Signal of interest (SOI) present. The SOI is calculated in the decimated power block. 0x0
D5 Rx1: correction word above threshold. The calculated radio frequency (RF) DC offset word is above the threshold. 0x0
D4 Rx1: update counter expired. The RF DC update counter is expired. 0x0
D3 Rx1: gain change. The gain index (in automatic gain control (AGC) and manual gain control (MGC) is used to select an entry 0x0
in the gain table. This signal is active (the output level toggles between high and low) only if there is a difference in entries
in the gain table when the AGC or MGC index changes. If the entries of the two indices are identical, the Rx gain change signal is
not generated (toggled).
D2 Rx1: update dc offset in the RF section. Updates the RF dc offset word. 0x0
D1 Rx1: measure dc offset in the RF section. Calibration and tracking is in measurement mode. 0x0
D0 Rx1: RF dc count reached. Calibration and tracking measurement counter expired. 0x0

Table 157. Monitor Index: 0x24 (Name: RF DC Offset Correction Tracking Signals, Channel 2)
Bits Description Reset
D7 Reserved. 0x0
D6 Rx2: SOI present. The SOI is calculated in the decimated power block. 0x0
D5 Rx2: correction word above threshold. The calculated RF dc offset word is above threshold. 0x0
D4 Rx2: update counter expired. The RF dc update counter is expired. 0x0
D3 Rx2: gain change. The gain index (in AGC and MGC mode) is used to select an entry in the gain table. This signal is active (the 0x0
output level toggles between high and low) only if there is a difference in entries in the gain table when the AGC or MGC
index changes. If the entries of the two indices are identical, the Rx gain change signal is not generated (toggled).
D2 Rx2: update dc offset in the RF section. Updates the RF dc offset word. 0x0
D1 Rx2: measure dc offset in the RF section. Calibration and tracking is in measurement mode. 0x0
D0 Rx2: RFDC count reached. Calibration/tracking measurement counter expired. 0x0

Table 158. Monitor Index: 0x42 (Name: AGC Monitor 12)

Bits Description Reset
D7 Rx2: overrange very low counter exceeded. This pin goes high when High-Band 2 (HB2) detects a number of peaks greater 0x0
than the counter value (hb2VeryLowThreshExceededCnt—refer to Automatic Gain Control section for more details). These
peaks must be greater than the hb2VeryLowThresh threshold to increment the count. If this signal is high at the end of the
AGC gain update time counter, no gain decrement is made. This signal resets at the expiration of the AGC gain update counter.
D6 Rx2: overrange low counter exceeded. This pin goes high when HB2 detects a number of peaks greater than the counter 0x0
value (hb2LowThreshExceededCnt—refer to Automatic Gain Control section for more details). These peaks must be greater
than the hb2LowThresh threshold to increment the count. If this signal is high at the end of the AGC gain update time
counter, no gain decrement is made. This signal resets at the expiration of the AGC gain update counter.
D5 Rx2: overrange high counter exceeded. This pin goes high when HB2 detects a number of peaks greater than the counter 0x0
value (hb2HighThreshExceededCnt—refer to Automatic Gain Control section for more details). These peaks must be greater
than the hb2HighThresh threshold to increment the count. This signal going high initiates a gain decrement immediately if
hb2FastAttack mode is enabled or at the expiration of the AGC gain update counter if hb2FastAttack mode is disabled. This
signal resets at the expiration of the AGC gain update counter.
D4 Rx2: gain update counter expired. This bit signals when the gain update counter expires. 0x0

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UG-992 AD9371/AD9375 System Development User Guide
Bits Description Reset
D3 Rx1: overrange very low counter exceeded. This pin goes high when High-Band 2 (HB2) detects a number of peaks greater 0x0
than the counter value (hb2VeryLowThreshExceededCnt—refer to Automatic Gain Control section for more details). These
peaks must be greater than the hb2VeryLowThresh threshold to increment the count. If this is high at the end of the
automatic gain control (AGC) gain update time counter, no gain decrement is made. This signal resets at the expiration of
the AGC gain update counter.
D2 Rx1: overrange low counter exceeded. This pin goes high when HB2 detects a number of peaks greater than the counter 0x0
value (hb2LowThreshExceededCnt —refer to Automatic Gain Control section for more details). These peaks must be greater
than the hb2LowThresh threshold to increment the count. If this signal is high at the end of the AGC gain update time
counter, no gain decrement is made. This signal resets at the expiration of the AGC gain update counter.
D1 Rx1: overrange high counter exceeded. This pin goes high when HB2 detects a number of peaks greater than the counter 0x0
value (hb2HighThreshExceededCnt—refer to Automatic Gain Control section for more details). These peaks must be greater
than the hb2HighThresh threshold to increment the count. This signal going high initiates a gain decrement immediately if
hb2FastAttack mode is enabled or at the expiration of the AGC gain update counter if hb2FastAttack mode is disabled. This
signal resets at the expiration of the AGC gain update counter.
D0 Rx1: gain update counter expired. This bit signals when the gain update counter expires. 0x0

Table 159. Monitor Index: 0x43 (Name: AGC Monitor 13)

Bits Description Reset
[7:4] Reserved. 0x0
3 ORx: overrange very low counter exceeded. This pin goes high when HB2 detects a number of peaks greater than the 0x0
counter value (hb2VeryLowThreshExceededCnt—refer to the Automatic Gain Control section for more details). These peaks
must be greater than the hb2VeryLowThresh threshold to increment the count. If this is high at the end of the AGC gain
update time counter, no gain decrement is made. This signal resets at the expiration of the AGC gain update counter.
2 ORx: overrange low counter exceeded. This pin goes high when HB2 detects a number of peaks greater than the counter 0x0
value (hb2LowThreshExceededCnt—refer to the Automatic Gain Control section for more details). These peaks must be
greater than the hb2LowThresh threshold to increment the count. If this signal is high at the end of the AGC gain update
time counter, no gain decrement is made. This signal resets at the expiration of the AGC gain update counter.
1 ORx: overrange high counter exceeded. This pin goes high when HB2 detects a number of peaks greater than the counter 0x0
value (hb2HighThreshExceededCnt —refer to the Automatic Gain Control section for more details). These peaks must be
greater than the hb2HighThresh threshold to increment the count. This signal going high initiates a gain decrement
immediately if hb2FastAttack mode is enabled or at the expiration of the AGC gain update counter if hb2FastAttack mode
is disabled. This signal resets at the expiration of the AGC gain update counter.
0 ORx: gain update counter expired. Signals when the gain update counter has expired. 0x0

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AD9371/AD9375 System Development User Guide UG-992
API Description Parameters
The application programming interface (API) package provides • monitorIndex: This parameter selects a row from
functions that allow users to operate GPIO in monitor output Table 143, which in turn selects the desired monitor
mode. Before the user can use this mode, the crosspoints and output signal assignments for the GPIO outputs.
the input/output buffer must be configured. Use the • monitorMask: This parameter enables or disables active
MYKONOS_setupGpio() function to properly configure the monitor output bits in the selected word. Setting Bit 0 of
crosspoints and input/output buffers. This function relies on that word enables the D0 monitor output, setting Bit 1 of
correct configuration of the device → auxIo → gpio structure that word enables the D1 monitor output, and so on. The
members. device holds low any pins that are not enabled.
For an example, see the following configuration:
MYKONOS_getGpioMonitorOut
• device → auxIo → gpio → gpioOe = 0xXXXFF, the first eight mykonosGpioErr_t
GPIOs (Bits[D7:D0]) have the output enabled MYKONOS_getGpioMonitorOut(mykonosDevice_t
• device → auxIo → gpio → gpioSrcCtrl3_0 = *device, uint8_t *monitorIndex, uint8_t
GPIO_MONITOR_MODE *monitorMask)
• device → auxIo → gpio → gpioSrcCtrl4_7 = This API function reads back the current monitor index and
GPIO_MONITOR_MODE monitor mask used to control monitor outputs.
These commands enable monitor Output D3 to Output D0 on Parameters
GPIO_3 through GPIO_0, and Output D7 to Output D4 on • *monitorIndex: Pointer to a variable storing the current
GPIO_7 through GPIO_4. Refer to the API Description section monitor index to which outputs are set.
in the GPIO Operation section for more details. In general, use • *monitorMask: Pointer to a variable storing current monitor
the transceiver evaluation software (TES) to generate correct output bits in the word selected by *monitorIndex. Bit 0 of
settings for this structure. After the crosspoint and input/output that word outlines the status of the D0 monitor output, Bit 1 of
buffers are configured, the user can start to operate GPIOs in that word outlines status of the D1 monitor output, and so
monitor output mode. A list of API functions dedicated for on. If a bit is set to 1, then that monitor output signal is
monitor output configuration, with short description of their enabled. If a bit is set to 0, then that monitor output signal
functionalities, is in the following section. is disabled.
As described previously, the control output signals are mapped
as a table. Use the API MYKONOS_setGpioMonitorOut()
ARM GPIO INTERFACE
function to select a particular row in the monitor output in The ARM microcontroller in the device can communicate with
Table 143, as well as to enable particular bits from the selected external devices using the GPIO interface. Various ARM input
row. The device holds low any pins that are not enabled. and output signals can be configured to map to specific GPIO pins.
The specific pin location for ARM microcontroller GPIO
MYKONOS_setGpioMonitorOut
functionalities can be configured using API commands.
mykonosGpioErr_t
MYKONOS_setGpioMonitorOut(mykonosDevice_t Several external (GPIO) pins are used for controlling timing
*device, uint8_t monitorIndex, uint8_t critical functionality provided by the ARM. When planning the
monitorMask) routing of ARM microcontroller signals to the GPIO interface,
This API function configures the monitor output function for the user must adhere to some routing limitations. Figure 97 and
the GPIOs. The monitor outputs are grouped in sets of nibbles Table 160 outline the restrictions that apply to configuring the
(4 bits). The user can set individual nibbles for having the monitor GPIOs as an ARM interface.
output function across the available GPIO. Use the TES to
generate correct settings for this structure.

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UG-992 AD9371/AD9375 System Development User Guide

I/O CROSSPOINT 1 I/O BUFFER

ORX_MODE, BIT 2 ORX_MODE 2 GPIO_18

ORX_MODE 1 GPIO_17
ORX_MODE, BIT 1 ORX_MODE 0
RX1_ENABLE GPIO_16

LIMITED FLEXIBILITY. REFER TO ARM ROUTING TABLE FOR DETAILS

M5 ORX_MODE, BIT 0
RX2_ENABLE
M7
GPIO_15
TX1_ENABLE ORX_TRIGGER
GPIO_14
M6 TX2_ENABLE GPIO_13
M8 GPIO_12

GPIO_11
ARM GPIO_10
RX1_ENABLE_ACK
PROCESSOR GPIO_9
GPIO INTERFACE RX2_ENABLE_ACK
GPIO_8
TX1_ENABLE_ACK
TX2_ENABLE_ACK
ORX1_ENABLE_ACK GPIO_7
GPIO_6
ORX2_ENABLE_ACK
GPIO_5
SNRX1_ENABLE_ACK
GPIO_4
TX_OBS_SELECT

GPIO_3
GPIO_2
GPIO_1
ARM_ERROR ARM_WATCHDOG GPIO_0

INTERRUPT CONTROLLER

setRadioControlPinMode setArmGpioPins setGpioDrv (gpioDrv)

(auXlo->armGpio STRUCTURE) (auXlo->armGpio STRUCTURE) setGpioSlewRate

14652-086
(gpioSelect, slewRate)

Figure 97. ARM Microcontroller to GPIO Interface

Table 160. GPIO Routing Options for ARM Signals

Signal Name Description Possible GPIO pin
RX1_ENABLE This pin can be configured to enable/disable Rx1 by itself, or to enable/disable both Rx1 and RX1_ENABLE pin
Rx2 simultaneously.
RX2_ENABLE Optionally, this pin can be configured to enable/disable Rx2. RX2_ENABLE pin
TX1_ENABLE This pin can be configured to enable/disable Tx1 by itself, or to enable/disable both Tx1 and TX1_ENABLE pin
Tx2 simultaneously.
TX2_ENABLE Optionally, this pin can be configured to enable/disable Tx2. TX2_ENABLE pin
ORX_TRIGGER A rising edge on this signal triggers a change in the configuration of the ORx receiver. On the Any pin from
rising edge, the ORX_MODE[2:0] pins are sampled to determine the target ORx configuration. GPIO_15 to GPIO_4
ORX_MODE[2:0] Selects the ORx mode. Sampled on rising edge of ORX_TRIGGER. Any three pins
000 = ORx powered off. from GPIO_3 to
GPIO_0 or any
001 = ORx1 (with Tx local oscillator (LO)).
three pins from
010 = ORx2 (with Tx LO). GPIO_15 to
011 = no baseband processor (BBP) access. ORx available to internal Tx calibrations. GPIO_4; or,
100 = sniffer Rx. ORX_MODE[0] on
GPIO_16,
101 = ORx1 (with sniffer LO).
ORX_MODE[1]
110 = ORx2 (with sniffer LO). on GPIO_17, or
111 = reserved (trigger ignored). ORX_MODE[2]
Note that all three ORX_MODE[2:0] pins must come from the same bank of GPIOs. Banks are on GPIO_18.
defined as GPIO_3 to GPIO_0, or GPIO_15 to GPIO_4, or GPIO_18 to GPIO_16. When GPIO_18 to
GPIO_16 are used, the only valid assignments are ORX_MODE[0] on GPIO_16, ORX_MODE[1] on
GPIO_17, and ORX_MODE[2] on GPIO_18.

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AD9371/AD9375 System Development User Guide UG-992
Signal Name Description Possible GPIO pin
RX1_ENABLE_ACK Indicates that Rx1 is (or both Rx1 and Rx2 are) enabled. Any pin from
GPIO_15 to GPIO_0
RX2_ENABLE_ACK Indicates that Rx2 is enabled. Any pin from
GPIO_15 to GPIO_0
TX1_ENABLE_ACK Indicates that Tx1 is (or both Tx1 and Tx2 are) enabled. Any pin from
GPIO_15 to GPIO_0
TX2_ENABLE_ACK Indicates that Tx2 is enabled. Any pin from
GPIO_15 to GPIO_0
ORX1_ENABLE_ACK Indicates that ORx1 is enabled for BBP use. Any pin from
GPIO_15 to GPIO_0
ORX2_ENABLE_ACK Indicates that ORx2 is enabled for BBP use. Any pin from
GPIO_15 to GPIO_0
SNRX_ENABLE_ACK Indicates that SnRx is enabled for BBP use. Any pin from
GPIO_15 to GPIO_0
TX_OBS_SELECT When two transmitters are used with only one ORx input, this GPIO tells the BBP which Any pin from
transmitter channel is active for calibrations. BBP controls an RF switch that routes the desired GPIO_15 to GPIO_0
RF Tx path into the single ORx input.
ARM_ERROR Indicates that the ARM must be rebooted because of some error. The ARM was able to detect a GP_INTERRUPT pin
problem and record some diagnostic information before setting this flag.
ARM_WATCHDOG Indicates that the watchdog has expired because of some error that the ARM was unable to GP_INTERRUPT pin
respond to (for example, the ARM was unable to set the ARM_ERROR flag). The ARM must be
rebooted.

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UG-992 AD9371/AD9375 System Development User Guide
API Description The ARM GPIO interface configurations rely on correct values
The application programming interface (API) package provides set to the device → auxIo → armGpio structure members. A
functions that allow the user to operate the GPIO in ARM quick overview of this structure is as follows (use the transceiver
GPIO interface mode. The ARM GPIO input and output signals evaluation software (TES) to generate correct settings for this
that are desired for Rx/Tx control in pin mode must be set up structure):
before the device enters radio on mode.

typedef struct
{
uint8_t useRx2EnablePin; /*!< 0= RX1_ENABLE controls RX1 and RX2, 1 = separate
RX1_ENABLE/RX2_ENABLE pins */
uint8_t useTx2EnablePin; /*!< 0= TX1_ENABLE controls TX1 and TX2, 1 = separate
TX1_ENABLE/TX2_ENABLE pins */
uint8_t txRxPinMode; /*!< 0= ARM command mode, 1 = Pin mode to power up Tx/Rx
chains */
uint8_t orxPinMode; /*!< 0= ARM command mode, 1 = Pin mode to power up ObsRx
receiver*/

/* the AD9371 ARM input GPIO pins -- Only valid if orxPinMode = 1 */

uint8_t orxTriggerPin; /*!< Select desired GPIO pin (valid 4-15) */
uint8_t orxMode2Pin; /*!< Select desired GPIO pin (valid 0-18 - limited combin.) */
uint8_t orxMode1Pin; /*!< Select desired GPIO pin (valid 0-18) - limited combin.) */
uint8_t orxMode0Pin; /*!< Select desired GPIO pin (valid 0-18) - limited combin.) */

/* the AD9371 ARM output GPIO pins -- always available, even when pin mode not enabled*/
uint8_t rx1EnableAck; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
uint8_t rx2EnableAck; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
uint8_t tx1EnableAck; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
uint8_t tx2EnableAck; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
uint8_t orx1EnableAck; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
uint8_t orx2EnableAck; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
uint8_t srxEnableAck; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
uint8_t txObsSelect; /*!< Select desired GPIO pin (0-15), [4] = Output Enable */
/* When 2Tx are used with only 1 ORx input, this GPIO tells the
BBP which Tx channel is active for calibrations, so BBP can
route correct RF Tx path into the single ORx input */
} mykonosArmGpioConfig_t;

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AD9371/AD9375 System Development User Guide UG-992
The previously described structure controls all sections of the Tx ATTENUATION CONTROL
ARM GPIO interface hardware shown in Figure 97, including The device uses an accurate and efficient method of transmit
the input/output (I/O) buffer, I/O Crosspoint 1, and the ARM power control (Tx attenuation control) that involves minimum
processor. The previous description outlines the structure interaction with the BBP. The power control in the transmit
members values and their interpretations. For the orxMode2Pin, chain is implemented with two variable attenuations: one in
orxMode1Pin, and orxMode0Pin structure members, refer to the digital domain and one in the analog domain. The digital
Table 160 for limitations in possible routing combinations. Note attenuator is programmable from 0 dB to −6 dB in steps of
that the ORX_MODE and ORX_TRIGGER signals are ignored 0.05 dB. The analog RF attenuator is programmable from 0 dB
if ORx control orxPinMode is set to command mode, even if to −36.12 dB. There are 64 possible settings for the analog
these signals are mapped to GPIO pins. attenuator. An internal table is provided within the device that
MYKONOS_setArmGpioPins adjusts both analog and digital attenuators simultaneously. Each
mykonosGpioErr_t row in this table provides a unique combination of analog and
MYKONOS_setArmGpioPins(mykonosDevice_t digital gain. The table is arranged in increasing attenuation,
*device)
with Row 0 being the lowest attenuation setting (0 dB) and
This function sets the input and output GPIO pin selections for Row 839 being the largest attenuation setting (41.95 dB). A
ARM related signals. The baseband processor (BBP) does not consistent attenuation step size of 0.05 dB is maintained
have to call this function because it is automatically set up between each consecutive row of the table.
during the MYKONOS_loadArmFromBinary() function call. If
Figure 98 shows the location of the analog and digital attenuation
the BBP wishes to change the GPIO assignments, this function
blocks within the Tx chain, as well as the GPIO interface to
can be called again to change the configuration while the ARM
control it. The attenuation table is controlled by a pointer. By
is in the radio off state. This function relies on correct settings
moving the pointer to the required row of the table, the
in the armGpio structure. Use the transceiver evaluation
corresponding analog and digital attenuation settings of this
software (TES) to generate correct settings for this structure.
row are applied.
MYKONOS_setRadioControlPinMode
The pointer to the attenuation table can be controlled through
mykonosGpioErr_t
MYKONOS_setRadioControlPinMode(mykonosDev the GPIO pins. In this mode, four GPIO pins control the Tx
ice_t *device) attenuation values for Tx1 and Tx2: two pins for Tx1 (one to
increase pointer index, one to decrease), and two pins for Tx2.
This function configures the radio power-up/power-down
There is also an option to use just two GPIO pins to control Tx
control for the Rx and Tx paths to be controlled by pins
attenuation for both Tx1 and Tx2 at the same time. Minimum
(TX1_ENABLE, TX2_ENABLE, RX1_ENABLE, RX2_ENABLE,
lengths of pulse are present at the GPIO input to be latched is
and the GPIO pins) or an application programming interface
2 clock radio frequency (RF) cycles. The clock RF frequency
(API) function call. The GPIO setup and configuration can be
can be found in the Rx Summary tab of the TES.
performed in both the ready and idle state; it can be performed
as many times as desired. The BBP does not have to call this
function because it is automatically set up at the end of the
MYKONOS_loadArm-FromBinary() function call. If the BBP
wishes to change the GPIO assignments, this function can be
recalled to change the configuration while the ARM is in the
radio off state.
This function relies on correct settings in the armGpio
structure. Use the TES to generate correct settings for this
structure.

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UG-992 AD9371/AD9375 System Development User Guide

I/O BUFFER

GPIO_18
ATTEN. Tx1 DATAPATH
GPIO_17
I/O CROSSPOINT 2 GPIO_16
DAC THB2/ TFIR DIGITAL
THB1 ATTEN.

Tx2 ATTEN DEC GPIO_15

Tx2 ATTEN INC GPIO_14
Tx1 ATTEN DEC GPIO_13
Tx1 ATTEN INC GPIO_12

GPIO_11
ANALOG DIGITAL
ATTENUATION ATTENUATION GPIO_10
ATTENUATION
CONTROL GPIO_9
GPIO_8

CHANNEL SELECTION
AND
ATTENUATION Tx2 ATTEN DEC GPIO_7
STEP SIZE Tx2 ATTEN INC GPIO_6
Tx1 ATTEN DEC GPIO_5
ANALOG ATTENUATION DIGITAL Tx1 ATTEN INC GPIO_4
ATTENUATION CONTROL ATTENUATION

GPIO_3
GPIO_2
GPIO_1
THB2/ TFIR DIGITAL GPIO_0
DAC
THB1 ATTEN.
ATTEN.
Tx2 DATAPATH

setGpioOe
setTx1AttenCtrlPin (stepSize, tx1AttenIncPin, tx1AttenDecPin, ENABLE, useTx1ForTx2 setGpioDrv(gpioDrv) (gpioOutEn)
setTx2AttenCtrlPin (stepSize, tx2AttenIncPin, tx2AttenDecPin, ENABLE) setGpioSlewRate
(gpioSelect, slewRate)
setupGpio
(auxlo->gpio

14652-087
STRUCTURE)

Figure 98. GPIO Interface for Tx Attenuation Control

API Description MYKONOS_setTx1AttenCtrlPin

The application programming interface (API) package provides mykonosGpioErr_t
MYKONOS_setTx1AttenCtrlPin(mykonosDevice_
functions that allow users to operate the GPIO in Tx attenuation t *device, uint8_t stepSize,
control mode. Before users can use the device in Tx attenuation mykonosGpioSelect_t tx1AttenIncPin,
control mode, Crosspoint 2 and the input/output (I/O) buffer mykonosGpioSelect_t tx1AttenDecPin,
must be configured. Use the MYKONOS_setupGpio() function uint8_t enable, uint8_t useTx1ForTx2)
to properly configure the crosspoint and I/O buffers. This This API function allows the user to control the Tx1 attenuation
function relies on correct configuration of device → auxIo → gpio using GPIO inputs. When a low to high transition is applied to
structure members. Use the transceiver evaluation software (TES) configure the GPIO input, the attenuation changes by the
to generate correct settings for this structure. After a crosspoint and desired step.
I/O buffer are configured, the user can start to operate GPIOs in
Parameters
Tx attenuation control mode. The following sections list Tx
attenuation control mode API functions and short descriptions  stepSize: This parameter is the step that increases or
of their functions. decreases the Tx1 channel attenuation. This parameter sets
the change in Tx attenuation for each increment or decrement
signal received in increment/decrement mode. A step of 1
changes attenuation by 0.05 dB.
 tx1AttenIncPin: This parameter is the GPIO pin configuration
that controls the increment of Tx1 attenuation. The available
pins are MYKGPIO4 and MYKGPIO12.
 tx1AttenDecPin: This parameter is the GPIO pin configuration
that controls the decrement of Tx1 attenuation. The available
pins are MYKGPIO5 and MYKGPIO13.
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AD9371/AD9375 System Development User Guide UG-992
• enable: This parameter enables or disables Tx attenuation MYKONOS_getTx1AttenCtrlPin
pin control mode for Tx1. mykonosGpioErr_t
• 0 = disables the attenuation pin control for Tx1. MYKONOS_getTx1AttenCtrlPin(mykonosDevice_
• 1 = enables the attenuation pin control for Tx1. t *device, uint8_t *stepSize,
mykonosGpioSelect_t *tx1AttenIncPin,
• useTx1ForTx2: This parameter enables use of Tx1 GPIOs mykonosGpioSelect_t *tx1AttenDecPin,
to control attenuation for both the Tx1 and Tx2 channels. uint8_t *enable, uint8_t *useTx1ForTx2)
• 0 = disables use of Tx1 GPIOs to control attenuation
This API function returns the current configuration of Tx1
for both the Tx1 and Tx2 channels.
attenuation in pin control mode.
• 1 = enables use of Tx1 GPIOs to control attenuation
for both the Tx1 and Tx2 channels. Parameters
• *stepSize: This is a pointer to the variable that contains the
MYKONOS_setTx2AttenCtrlPin
mykonosGpioErr_t step used for increment and decrement of Tx1 attenuation.
MYKONOS_setTx2AttenCtrlPin(mykonosDevice_ • *tx1AttenIncPin: This is a pointer to the variable that stores
t *device, uint8_t stepSize, information about the pin used for Tx1 attenuation increment.
mykonosGpioSelect_t tx2AttenIncPin, • *tx1AttenDecPin: This is a pointer to the variable that
mykonosGpioSelect_t tx2AttenDecPin,
stores information about the pin used for Tx1 attenuation
uint8_t enable)
decrement.
This application programming interface (API) function allows
• *enable: This is a pointer to the variable that contains the
the user to control the Tx2 attenuation using GPIO inputs. When
enable status for this channel. If it is set to 1, then this
a low to high transition is applied to configure the GPIO input,
function is enabled for this channel, and if it is 0, it is not
the attenuation changes by the desired step.
enabled.
Parameters • *useTx1ForTx2. This is a pointer to the variable that
• stepSize: This parameter is the step that increases or contains the parameter indicating if Tx1 settings are used
decreases the Tx2 channel attenuation. This parameter sets to control attenuation in the Tx2 channel.
the change in Tx attenuation for each increment or decrement MYKONOS_getTx2AttenCtrlPin
signal received in increment/decrement mode. A step of 1
mykonosGpioErr_t
changes attenuation by 0.05 dB. MYKONOS_getTx2AttenCtrlPin(mykonosDevice_
• tx2AttenIncPin: This parameter is the GPIO pin configuration t *device, uint8_t *stepSize,
that controls the increment of Tx2 attenuation. The available mykonosGpioSelect_t *tx2AttenIncPin,
pins are MYKGPIO6 and MYKGPIO14. mykonosGpioSelect_t *tx2AttenDecPin,
uint8_t *enable, uint8_t *useTx1ForTx2)
• tx2AttenDecPin: This parameter is the GPIO pin configuration
that controls the decrement of Tx2 attenuation. The available This API function returns the current configuration of Tx2
pins are MYKGPIO7 and MYKGPIO15. attenuation in pin control mode.
• enable: This parameter enables or disables Tx attenuation Parameters
pin control mode for Tx2.
• *stepSize: This is a pointer to the variable that contains the
• 0 = disables the attenuation pin control for Tx2.
step used for increment and decrement of Tx2 attenuation.
• 1 = enables the attenuation pin control for Tx2.
• *tx2AttenIncPin: This is a pointer to the variable that stores
information about the pin used for Tx2 attenuation
increment.
• *tx2AttenDecPin: This is a pointer to the variable that
stores information about the pin used for Tx2 attenuation
decrement.
• *enable: This is a pointer to the variable that contains the
enable status for this channel. If it is set to 1, then this
function is enabled for this channel, and if it is 0, it is not
enabled.
• *useTx1ForTx2: This is a pointer to the variable that
contains parameter indicating if Tx1 settings are used to
control attenuation in the Tx2 channel.

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UG-992 AD9371/AD9375 System Development User Guide
SECONDARY SERIAL PERIPHERAL INTERFACE be particularly useful for solutions that need to adjust the Tx
(SPI2) attenuation at a precise instance in time but need a wider
attenuation range than what is available over the GPIO based
The transmitter (Tx) features an optional dedicated SPI, or
Tx attenuation increment/decrement control. Note that when
SPI2, interface that can adjust Tx attenuation. The SPI2 interface
SPI2 is enabled, the primary SPI port cannot be used to adjust
is included exclusively for the control of Tx attenuation on both
Tx attenuation.
channels. It can only be used to write to the 8 registers mentioned
in this section; it does not offer write access to any other A block diagram depicting the use of the SPI2 interface is
registers. shown in Figure 99.
The SPI2 interface allows users to program two distinct Figure 100 shows another way to look at the use case where the
attenuation states (S1 and S2) per transmitter and use an Tx1 and Tx2 attenuation are changed to accommodate a special
additional pin to toggle between these states. This interface can slot in time.

Tx1 S1 ATTENUATION
TX1 S1[D9:D8] = SPI2 REG 0x318[D1:D0]
0
TX1 S1[D7:D0] = SPI2 REG 0x319[D7:D0]
Tx ATTEN TO Tx1 ATTEN
Tx1 S2 ATTENUATION LUT HARDWARE
TX1 S2[D9:D8] = SPI2 REG 0x31A[D1:D0] 1
TX1 S2[D7:D0] = SPI2 REG 0x31B[D7:D0]

Tx2 S1 ATTENUATION
TX2 S1[D9:D8] = SPI2 REG 0x31C[D1:D0]
TX2 S1[D7:D0] = SPI2 REG 0x31D[D7:D0] 0

Tx ATTEN TO Tx2 ATTEN

Tx2 S2 ATTENUATION LUT HARDWARE
TX2 S2[D9:D8] = SPI2 REG 0x31E[D1:D0] 1
TX2 S2[D7:D0] = SPI2 REG 0x31F[D7:D0]

14652-098
S1/S2 SELECT
[GPIO_4, GPIO_8, OR GPIO_14]

Figure 99. Block Diagram of SPI2 Operation

Tx
SPECIAL Tx
Tx SLOT SLOT 1 Tx SLOT
SPECIAL
ANT 1 DwPTS SLOT 2
– FOR TD-S
AIR INTERFACE

Tx
SPECIAL Tx
Tx SLOT SLOT 1 Tx SLOT
SPECIAL
ANT 2 DwPTS SLOT 2
– FOR TD-S
AIR INTERFACE

TOGGLE PIN

GAIN WORD 1 GAIN WORD 2 GAIN WORD 1

FOR Tx1 FOR Tx1 FOR Tx1

GAIN WORD 1 GAIN WORD 2 GAIN WORD 1

FOR Tx2 FOR Tx2 FOR Tx2
TIME
14652-099

GAIN WORD 1 IS NORMAL GAIN SETTING OF WHOLE Tx CHANNEL, CONFIGURED BY SPI.

GAIN WORD 2 IS ANOTHER GAIN SETTING, CONFIGURED BY SPI.
TOTAL TWO SET OF Tx GAIN SETTING OF EACH Tx PATH, WHICH OF THEM IS TO BE EFFECTIVE IS SELECTED BY TOGGLE PIN.

Figure 100. Timing Diagram of SPI2 Operation

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AD9371/AD9375 System Development User Guide UG-992
The SPI2 interface uses the GPIO_3 to GPIO_0 pins for the SPI txAttenStepSize. The txAttenStepSize is written over the primary
control pins and an additional pin that toggle between Tx SPI interface during MYKONOS_initialize(…).
attenuation states, S1 and S2. The additional pin, S1/S2 select, can The attenuation readback registers (0x2E8 to 0x2EB) can be
be designated as one of the following pins: GPIO_4, GPIO_8, and read over the SPI port or the SPI2 port. These allow the user to
GPIO_14. The pin mapping is described in Table 161. read the currently applied Tx attenuation settings. The SPI2
The SPI2 port uses the same SPI protocol as the primary SPI port register map is shown in Table 162.
in terms of MSB/LSB first and descending/ascending order. Note API Description
that the GPIO output enables must be set correctly for SPI2 to
The SPI2 is set up with the application programming interface
work properly.
(API) command as described as follows.
Table 161. GPIO Pin Mappings for SPI2 MYKONOS_spi2GpioSetup
GPIO Pin I/O Function Description
mykonosGpioErr_t
GPIO_0 Input SDIO2 SPI2 port data input MYKONOS_spi2GpioSetup(mykonosDevice_t
GPIO_1 Output SDO2 SPI2 port data output *device, uint8_t enable, uint8_t
GPIO_2 Input SCLK2 SPI2 port data clock updateTxAttenPinSelect)
GPIO_3 Input CSB2 SPI2 port chip select bar This API function configures and enables the secondary SPI
(negative logic) port. This port allows control compatibility with baseband
GPIO_4/GPIO_8/ Input S1/S2 Selection of Tx processors (BBPs) that employ dual SPI ports. The GPIO
GPIO_14 Select attenuation word
(0 = S1, 1 = S2) mapping for SPI2 is fixed, excluding a configurable select pin
that selects Tx attenuation between Attenuation State 1 (S1) and
SPI2 Register Map Attenuation State 2 (S2).

The SPI2 interface is restricted to 8 addresses. These addresses Parameters

cannot be accessed via the main SPI interface. The SPI2 registers  enable: This is the parameter that enables the secondary
correspond to 10-bit words for Tx1 attenuation S1, Tx1 attenuation SPI port. 1 = enable, and 0 = disable.
S2, Tx2 attenuation S1, Tx2 attenuation S2 as detailed in the  updateTxAttenPinSelect: This parameter sets the GPIO pin
SPI2 register map. Because the Tx attenuation is set as a 10-bit to be toggled for determining the S1 or S2 state. Configuration
word, it takes two SPI writes to write a single Tx attenuation word. options include the following:
Note that the LSB in the 10-bit words are programmable. The step  GPIO_4 → updateTxAttenPinSelect = 0x00
size can be set to 0.05dB (default), 0.1dB, 0.2dB, or 0.4dB per LSB.  GPIO_8 → updateTxAttenPinSelect = 0x01
Refer to the parameter in the device data structure device → tx →
 GPIO_14 → updateTxAttenPinSelect = 0x02
Table 162. SPI2 Register Map
Register I/O
Address Name D7 D6 D5 D4 D3 D2 D1 D0 Default R/W Scope
0x2E8 Tx1 atten index Tx1 attenuation index readback[7:0] 0x00 R Digital
readback LSB
0x2E9 Tx1 atten index Unused Tx1 attenuation index 0x00 R Digital
readback MSB readback[9:8]
0x2EA Tx2 atten index Tx2 attenuation index readback[7:0] 0x00 R Digital
readback LSB
0x2EB Tx2 atten index Unused Tx2 attenuation index 0x00 R Digital
readback MSB readback[9:8]
0x318 Tx1 attenuation S1 MSB Unused Tx1 attenuation S1[9:8] 0x00 R/W Digital
0x319 Tx1 attenuation S1 LSB Tx1 attenuation S1[7:0] (update happens when this byte is written, write 0x00 R/W Digital
this byte after S1[9:8] to see update)
0x31A Tx1 attenuation S2 MSB Unused Tx1 attenuation S2[9:8] 0x00 R/W Digital
0x31B Tx1 attenuation S2 LSB Tx1 attenuation S2[7:0] (update happens when this byte is written, write 0x00 R/W Digital
this byte after S2[9:8] to see update)
0x31C Tx2 attenuation S1 MSB Unused Tx2 attenuation S1[9:8] 0x00 R/W Digital
0x31D Tx2 attenuation S1 LSB Tx2 attenuation S1[7:0] (update happens when this byte is written, write 0x00 R/W Digital
this byte after S1[9:8] to see update)
0x31E Tx2 attenuation S2 MSB Unused Tx2 attenuation S2[9:8] 0x00 R/W Digital
0x31F Tx2 attenuation S2 LSB Tx2 attenuation S2[7:0] (update happens when this byte is written, write 0x00 R/W Digital
this byte after S2[9:8] to see update)

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UG-992 AD9371/AD9375 System Development User Guide
Rx MANUAL GAIN CONTROL of attenuation. The device also has a digital gain block that can
The device provides gain control blocks that are externally provide higher resolution than provided by the internal RF
controllable through GPIO pins, allowing the user complete attenuator. The digital gain has 128 indices (0 to 127) that
control over the applied attenuation. This section describes the corresponds to a gain range of 0 dB to 31.75 dB in 0.25 dB steps.
GPIO configuration for and the operation of manual gain The device also has functionality allowing the user to control a
control (MGC). Refer to the Gain Control section for more digital stepped attenuator with GPIO_3P3_x pins. There are up
information about the gain control block. to four bits (on GPIO_3P3 interface) available.

Figure 101 shows a block diagram of the receiver paths together In MGC mode, the baseband processor (BBP) controls the gain
with the gain control blocks and the GPIO interface connection. index pointer(s), which is the pointer used to select the required
There are two variable gain elements in the receive path: the row of the gain table. In MGC mode, the gain index pointer can
internal RF attenuator and the digital gain/attenuator block. be controlled either by using the SPI interface or by using the
The MGC blocks control the gains of both these components GPIO interface. The GPIO interface method is implemented by
simultaneously; the Gain Control block outputs in Figure 101 toggling the GPIO pins to initiate gain changes according to the
indicate this control. following process. The gain control GPIO pins are driven high.
A transition from a logic low to a logic high, held high for at
Note that this device has two receiver chains. Each receiver has least 2 clock RF cycles, initiates a gain change in the device
its own gain table that simultaneously controls each of the (clock RF is the clock at the input to the Rx finite impulse
variable gain blocks in Figure 101. Each row of this table has a response (FIR), refer to transceiver evaluation software (TES) for
unique combination of gain settings. A pointer to the table more information). Similarly, a logic low must be maintained
determines which settings from this table are used. The internal for at least 2 clock RF cycles. The number of gain indices that an
radio frequency (RF) attenuator has 64 different attenuation increase or decrease corresponds to is user programmable.
settings, or indices (0 to 63), which range from 0 dB to 36.12 dB

I/O BUFFER
EXTERNAL
ATTEN. INTERNAL GPIO_18
ATTEN. Rx1 DATAPATH
(OPTIONAL) GPIO_17
I/O CROSSPOINT 2 GPIO_16
ADC RHB3/ RHB1/ DIGITAL
RHB2 RFIR GAIN

GPIO_15
Rx2 GAIN DEC GPIO_14
Rx2 GAIN INC GPIO_13
INTERNAL ATTEN DIGITAL GAIN/ATTEN
WORD [5.0] WORD [6.0] GPIO_12
GAIN
CONTROL
EXTERNAL ATTEN Rx1 GAIN DEC GPIO_11
WORD [3.0]
Rx1 GAIN INCREMENT Rx1 GAIN INC GPIO_10
GPIO_9
Rx1 GAIN DECREMENT
GPIO_8
Rx2 GAIN INCREMENT GAIN STEP SIZE
Rx2 GAIN DECREMENT
EXTERNAL ATTEN GPIO_7
WORD [3.0] GPIO_6
GAIN GPIO_5
CONTROL
Rx2 GAIN DEC GPIO_4
INTERNAL ATTEN DIGITAL GAIN/ATTEN
WORD [5.0] WORD [6.0]

Rx2 GAIN INC GPIO_3

GPIO_2
Rx2 DATAPATH
Rx1 GAIN DEC GPIO_1
RHB3/ RHB1/ DIGITAL Rx1 GAIN INC GPIO_0
ADC
RHB2 RFIR GAIN
EXTERNAL INTERNAL
ATTEN. ATTEN.
(OPTIONAL)

setGpioOe
setRx1GainCtrlPin (incStep, decStep, rx1GainIncPin, rx1GainDecPin, ENABLE) setGpioDrv (gpioDrv) (gpioOutEn)
setRx2GainCtrlPin (incStep, decStep, rx2GainIncPin, rx2GainDecPin, ENABLE) setGpioSlewRate
(gpioSelect, slewRate)
setupGpio
(auxlo->gpio
14652-088

STRUCTURE)

Figure 101. GPIO Configuration for Manual Gain Control Mode

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AD9371/AD9375 System Development User Guide UG-992
API Description MYKONOS_setRx2GainCtrlPin
The application programming interface (API) package provides mykonosGpioErr_t
MYKONOS_setRx2GainCtrlPin(mykonosDevice_t
functions that allow users to operate the GPIO in Rx manual
*device, uint8_t incStep, uint8_t
gain control mode. Before the user can use the device in Rx manual decStep, mykonosGpioSelect_t
gain control mode, Crosspoint 2 and the input/output (I/O) rx2GainIncPin, mykonosGpioSelect_t
buffers must be configured. Use the MYKONOS_setupGpio() rx2GainDecPin, uint8_t enable)
function to properly configure the crosspoint and I/O buffers. This This API function configures the GPIO input pin and step size
function relies on correct configuration of device → auxIo → gpio to allow the BBP to control gain changes in the Rx2 signal
structure members. Use the transceiver evaluation software chain. A high pulse on the GPIO pin set by rx2GainIncPin
(TES) to generate correct settings for this structure. After the increments the gain by the value set in incStep. A high pulse on the
crosspoint and I/O buffers are configured, the user can start to GPIO pin set by rx2GainDecPin decrements the gain by the
operate GPIOs in Rx manual gain control mode. The following value set in decStep.
sections list the Rx manual gain control mode API functions and
short descriptions of their functionalities.
Parameters

MYKONOS_setRx1GainCtrlPin • incStep: This parameter sets the change (increase) in gain

index that is applied when the increment gain pin (in MGC
mykonosGpioErr_t
pin control mode) is pulsed.
MYKONOS_setRx1GainCtrlPin(mykonosDevice_t
*device, uint8_t incStep, uint8_t • decStep: This parameter sets the change (decrement) in
decStep, mykonosGpioSelect_t gain index to be applied when the decrement gain pin (in
rx1GainIncPin, mykonosGpioSelect_t MGC pin control mode) is pulsed high and none of the
rx1GainDecPin, uint8_t enable) peak detector signals have triggered. If any combination
This API function configures the GPIO input pin and step size of the peak detector signals are high, the gain step that
to allow the baseband processor (BBP) to control gain changes corresponds to that combination of peak detector signals
in Rx1 signal chain. A high pulse on the GPIO pin set by is used as the decrement step size.
rx1GainIncPin increments the gain by the value set in incStep. A • rx2GainIncPin: This parameter selects the GPIO used for
high pulse on the GPIO pin set by rx1GainDecPin decrements the Rx2 manual gain increment input. The available pins are
the gain by the value set in decStep. MYKGPIO3 and MYKGPIO13.
Parameters • rx2GainDecPin: This parameter selects the GPIO used for
the Rx2 manual gain decrement input. The available pins are
• incStep: This parameter sets the change (increase) in the MYKGPIO4 and MYKGPIO14.
gain index that is applied when the increment gain pin (in
• enable: This parameter enables or disables manual gain
manual gain control (MGC) pin control mode) is pulsed.
control mode for Rx2.
• decStep: This parameter sets the change (decrement) in
• 0 = disables the manual gain control pin mode for Rx2.
gain index to be applied when the decrement gain pin (in
• 1 = enables the manual gain control pin mode for Rx2.
MGC pin control mode) is pulsed high and none of the
peak detector signals trigger. If any combination of the peak MYKONOS_getRx1GainCtrlPin
detector signals are high, the gain step that corresponds to mykonosGpioErr_t
that combination of peak detector signals is used as the MYKONOS_getRx1GainCtrlPin(mykonosDevice_t
decrement step size. *device, uint8_t *incStep, uint8_t
• rx1GainIncPin: This parameter selects the GPIO used for *decStep, mykonosGpioSelect_t
*rx1GainIncPin, mykonosGpioSelect_t
the Rx1 manual gain increment input. The available pins are
*rx1GainDecPin, uint8_t *enable)
MYKGPIO0 and MYKGPIO10.
• rx1GainDecPin: This parameter selects the GPIO used for This API function returns the configuration for the GPIO
inputs and step sizes used to control the gain index in MGC
the Rx1 manual gain decrement input. The available pins are
input pin control mode for the Rx1 signal chain.
MYKGPIO1 and MYKGPIO11.
• enable: This parameter enables or disables manual gain Parameters
control mode for Rx1. • *incStep: A pointer to a variable that contains the step used
• 0 = disables the manual gain control pin mode for Rx1. for gain increment.
• 1 = enables the manual gain control pin mode for Rx1. • *decStep: A pointer to a variable that contains the step used
for gain decrement.
• *rx1GainIncPin: A pointer to a variable that has the pin
used for gain increment.
• *rx1GainDecPin: A pointer to a variable that has the pin
used for gain decrement.

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UG-992 AD9371/AD9375 System Development User Guide
• *enable: A pointer to a variable that contains the enable Parameters
status for the Rx1 channel. • *incStep: A pointer to a variable that contains the step used
• 1 = function is enabled for the Rx1 channel. for gain increment.
• 0 = function is not enabled for the Rx1 channel. • *decStep: A pointer to a variable that contains the step used
MYKONOS_getRx2GainCtrlPin for gain decrement.
• *rx2GainIncPin: A pointer to a variable that has the pin
mykonosGpioErr_t
MYKONOS_getRx2GainCtrlPin(mykonosDevice_t used for gain increment.
*device, uint8_t *incStep, uint8_t • *rx2GainDecPin: A pointer to a variable that has the pin
*decStep, mykonosGpioSelect_t used for gain decrement.
*rx2GainIncPin, mykonosGpioSelect_t
• *enable: A pointer to a variable that contains the enable
*rx2GainDecPin, uint8_t *enable)
status for the Rx2 channel.
This application programming interface (API) function returns • 1 = function is enabled for the Rx2 channel.
the configuration for the GPIO inputs and step sizes used to
• 0 = function is not enabled for the Rx2 channel.
control the gain index in manual gain control (MGC) input pin
control mode for the Rx2 signal chain.

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AD9371/AD9375 System Development User Guide UG-992

3.3 V GENERAL-PURPOSE INPUT/OUTPUT OVERVIEW

The device provides 12, 3.3 V capable (GPIO_3P3_x) general- This section describes control of the GPIO_3P3_x signals and
purpose input/output signals that can be configured for numerous their behavior in detail. It also outlines how to program the
functions. The GPIO_3P3_x pins control or monitor external GPIO_3P3_x API structure parameters and use API functions
devices, and several features are included to facilitate this control/ so that the desired signals are available on the appropriate pins.
monitor function. In this user guide, the naming convention API Description
used to describe these pins is GPIO_3P3_x, where x is the number
As shown in Figure 102, there are a number of functionalities
of the port.
available in this block that can be enabled and then interacted
Some of the GPIO_3P3_x pins can also be configured as with over the GPIO_3P3_x interface. There are crosspoints and
outputs for the auxiliary DACs. To prevent any conflict on the an I/O buffer that must be configured properly to enable particular
GPIO_3P3_x pins, the auxiliary DAC has priority; that is, if the functionality. The API package provides functions that allow
auxiliary DAC is powered up using the application programming users to configure those blocks to their desired states. The
interface (API) function, the pin takes on the auxiliary DAC following sections provides a list of general API functions and
function and the GPIO output buffer is tristated. Refer to the short descriptions of their functionalities.
Auxiliary DACs section for more details on auxiliary DAC
configuration and operation.

I/O BUFFER
I/O CROSSPOINT
GPIO_3P3_11 F14
GPIO_3P3_10 D14
GPIO_3P3_9 C13
GPIO_3P3_8 D13

GPIO_3P3_7 D12
3.3V GPIO MODES OF OPERATION 1
GPIO_3P3_6 E14
3.3V GENERAL-PURPOSE INPUT/OUTPUT GPIO_3P3_5 D5
GPIO_3P3_4 E1

GPIO_3P3_3 D1
GPIO_3P3_2 F1
GPIO_3P3_1 C2
GPIO_3P3_0 C1

3.3V GPIO MODES OF OPERATION 2

10 × AUXILIARY DAC

14652-089

Figure 102. High Level Overview of the GPIO_3V3_x Interface

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UG-992 AD9371/AD9375 System Development User Guide
MYKONOS_setupGpio3v3 For example, setting gpio3v3OutEn = 0x02 configures
mykonosGpioErr_t GPIO_3P3_2 as an output and the rest of the GPIO_3P3_x pins
MYKONOS_setupGpio3v3(mykonosDevice_t as inputs.
*device)
The function parameter is as follows:
This function sets the GPIO_3P3_x configuration registers. It
configures the pin direction for each GPIO_3P3_x pin, as well • gpio3v3OutEn. The valid range for this variable is from
as the crosspoint. This function relies on correct settings of the 0x0 to 0x0FFF. Each bit represents the corresponding
device → auxIo → gpio3v3 structure members. A quick overview GPIO_3P3_x pin (Bit 0 represents GPIO_3P3_0, Bit 1
of this structure follows: represents GPIO_3P3_1, and so on.). The direction of the
input buffer is set by each bit value: 0 = input, and 1 =
typedef struct
{ output.
uint16_t gpio3v3Oe; MYKONOS_getGpio3v3Oe
/*!< Pin direction: bit per 3.3v GPIO,
0=Input, 1=Output from the AD9371 device mykonosGpioErr_t
*/ MYKONOS_getGpio3v3Oe(mykonosDevice_t
mykonosGpio3v3Mode_t *device, uint16_t *gpio3v3OutEn)
gpio3v3SrcCtrl3_0; /*!< Mode for This function reads back the current status of the GPIO_3P3_x
GPIO3v3[3:0] pins */ direction set in the device. The direction can be either output or
mykonosGpio3v3Mode_t
input. The function parameter returns a bit per the
gpio3v3SrcCtrl7_4; /*!< Mode for
GPIO3v3[7:4] pins */ GPIO_3P3_x pin, where 1 outputs from the device and 0 inputs
mykonosGpio3v3Mode_t to the device.
gpio3v3SrcCtrl11_8; /*!< Mode for Parameters
GPIO3v3[11:8] pins */
} mykonosGpio3v3_t; • *gpio3v3OutEn: a pointer to the data to be returned with
The gpio3v3Oe member controls the configuration of the the output to enable the GPIO_3P3_x pins in a bit field
input/output (I/O) buffer shown in Figure 102. The format.
gpio3v3SrcCtrlNN_N structure member control configuration MYKONOS_setGpio3v3SourceCtrl
of the I/O crosspoint is shown in Figure 102. Options for
mykonosGpioErr_t
gpio3v3SrcCtrlNN_N are as follows: MYKONOS_setGpio3v3SourceCtrl(mykonosDevic
• GPIO3V3_LEVELTRANSLATE_MODE—level translate e_t *device, uint16_t gpio3v3SrcCtrl)
mode, signal level on low voltage GPIO output on the This is a helper function that is called by the MYKONOS_
GPIO_3P3_x pins. setupGpio3v3() function.
• GPIO3V3_INVLEVELTRANSLATE_MODE—inverted This function configures the crosspoint for different
level translate mode, inverse of signal level on low voltage GPIO_3P3_x functionality. This function only affects the
GPIO output on GPIO_3P3_x pins. GPIO_3P3_x pins that have their output enable direction set
• GPIO3V3_BITBANG_MODE—manual mode; the API by the MYKONOS_getGpio3v3Oe() function as outputs.
function sets the output pin levels and reads the input pin
Parameters
levels.
• GPIO3V3_EXTATTEN_LUT_MODE—GPIO_3P3_x • gpioSrcCtrl (nibble-based source control): This parameter
output level follows the Rx1/Rx2 gain table external control is a 12-bit number that contains three nibbles that set the
4-bit field. source control. Use the TES to generate correct settings for
the desired configuration.
Use the transceiver evaluation software (TES) for setting the
values for the members of this structure, ensuring that there is MYKONOS_getGpio3v3SourceCtrl
no conflict with the other GPIO functionalities. mykonosGpioErr_t
MYKONOS_setGpio3v3Oe MYKONOS_getGpio3v3SourceCtrl(mykonosDev
ice_t *device, uint16_t
mykonosGpioErr_t *gpio3v3SrcCtrl)
MYKONOS_setGpio3v3Oe(mykonosDevice_t
*device, uint16_t gpio3v3OutEn) This function reads back the current status of the GPIO_3P3
source control for different GPIO functionality.
This is a helper function that is called by the MYKONOS_
setupGpio3v3() function. Parameters
This function sets the GPIO_3P3_x direction given by the • gpio3v3SrcCtrl (nibble-based source control): this is a 12-bit
gpio3v3OutEn parameter. The direction can be either output or number that contains three nibbles that represent the
input. A bit set to 1 indicates that the pin is configured as an output. current settings of the source control (crosspoint
A bit set to 0 indicates that the pin is configured as an input. configuration).
Rev. B | Page 222 of 360
AD9371/AD9375 System Development User Guide UG-992
3.3 V GENERAL-PURPOSE INPUT/OUTPUT DAC has priority. If the auxiliary DAC is powered up using its
CONTROL application programming interface (API) function, the pin takes
on the auxiliary DAC function and the GPIO output buffer is
Figure 103 shows a graphical representation of the GPIO_3P3_x
tristated. Refer to the Auxiliary DACs section for more details
signals in manual mode. In this mode, the user can configure
on auxiliary DAC configuration and operation.
the GPIO_3P3_x inputs/outputs as outputs or inputs. If a
GPIO_3P3_x pin is configured as an output, the user can When using GPIO manual mode only or when working with
control its logic level. If a GPIO_3P3_x pin is configured as an any other GPIO mode in parallel, use the transceiver evaluation
input, the user can read back the voltage level present at the pin. software (TES) to set up the API auxIo/gpio3v3 structure with a
In both cases, a logic low or 0 corresponds to the ground voltage valid configuration.
level. A logic high or 1 corresponds to the 3.3 V voltage level The GPIO_3P3_x interface in manual mode uses the input/
present at the VDDA_3P3 pin. output crosspoint. This crosspoint operates using nibbles
Some of the GPIO_3P3_x pins can also be configured to (4 bits), meaning that the GPIO_3P3_x pins are controlled in
provide access to the auxiliary DAC outputs (as per Figure 102). groups of four.
To prevent any conflict on the GPIO_3P3_x pins, the auxiliary

I/O BUFFER
SETUP
I/O CROSSPOINT
1 = HIGH BIT 11 GPIO_3P3_11
BIT N
BIT 10 GPIO_3P3_10
0 = LOW
BIT 9 GPIO_3P3_9
x x x x BIT 11 BIT 10 BIT 9 BIT 8 BIT 8 GPIO_3P3_8
setGpio3vPinLevel
(gpio3vPinLevel)
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

BIT 7 GPIO_3P3_7
BIT 6 GPIO_3P3_6
BIT 5 GPIO_3P3_5
BIT 4 GPIO_3P3_4

READBACK
BIT 3 GPIO_3P3_3
1 = HIGH
BIT N BIT 2 GPIO_3P3_2
0 = LOW BIT 1 GPIO_3P3_1
x x x x BIT 11 BIT 10 BIT 9 BIT 8 BIT 0 GPIO_3P3_0
getGpio3vPinLevel
(gpio3vPinLevel) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

getGpio3v3SourceCtrl getGpio3v3Oe
(gpio3v3SrcCtrl) (gpio3v3OutEn)

setGpio3v3 (auxio->gpio3v3 STRUCTURE)

14652-090
Figure 103. GPIO_3P3_x in Manual Mode of Operation

Rev. B | Page 223 of 360

UG-992 AD9371/AD9375 System Development User Guide
API Description MYKONOS_setGpio3v3PinLevel
The application programming interface (API) package provides mykonosGpioErr_t
functions that allow users to operate the GPIO_3P3_x signals in MYKONOS_setGpio3v3PinLevel(mykonosDevice_
t *device, uint16_t gpio3v3PinLevel)
manual mode. Before the user can set the GPIO_3P3_x signals
in manual mode, the crosspoint and input/output (I/O) buffers This function sets the GPIO_3P3_x output pin level. This function
must be configured. Use the MYKONOS_setupGpio3v3() only affects the GPIO_3P3_x pins that are set to be outputs in
function to properly configure the crosspoints and I/O buffers. manual mode. GPIO_3P3_0 reflects the status of Bit 0 of the
This function relies on correct configuration of device → auxIo → gpio3v3PinLevel parameter, GPIO_3P3_1 reflects the status of
gpio3v3 structure members. Use the transceiver evaluation Bit 1 of the gpio3v3PinLevel, and so on. A logic low is set at the
software (TES) to generate correct settings for this structure. GPIO output and its corresponding bit is set to 0. A logic high is
After the crosspoints and I/O buffers are configured, the user set at the GPIO_3P3_x output (the corresponding bit is set to 1).
can operate GPIO_3P3_x signals in manual mode. The following Parameters
sections describe the manual mode API functions and provide
short descriptions of their functionalities. • gpio3v3PinLevel: This parameter describes the level output
for each GPIO_3P3_x pin (0 = low output, and 1 = high
MYKONOS_getGpio3v3PinLevel output).
mykonosGpioErr_t
MYKONOS_getGpio3v3PinLevel(mykonosDevice_ MYKONOS_getGpio3v3SetLevel
t *device, uint16_t *gpio3v3PinLevel) mykonosGpioErr_t
This function reads the GPIO_3P3_x pins that are set to be MYKONOS_getGpio3v3SetLevel(mykonosDevice_
t *device, uint16_t *gpio3v3SetLevel)
inputs in manual mode. Any pin set to be an output reads back
as zero. The pin level is returned in the form of a single 16-bit This function allows the user to read the value of each
word. The returned value is a bit per pin. GPIO_3P3_0 returns GPIO_3P3_x output pin set to output in manual mode.
on Bit 0 of the gpio3v3PinLevel parameter, GPIO_3P3_1 returns Parameters
on Bit 1 of the gpio3v3PinLevel, and so on. A logic low level
• *gpio3v3PinSetLevel: a pointer to the 16-bit variable that
returns 0, and a logic high level returns 1.
contains the level of each GPIO_3P3_x pin (1 bit per pin).
Parameters 0 sets the output to a low level, and 1 sets the output to a high
• *gpio3v3PinLevel: input GPIO pin levels are read back on level.
the pins assigned as inputs (1 bit per pin).

Rev. B | Page 224 of 360

AD9371/AD9375 System Development User Guide UG-992

GENERAL-PURPOSE INTERRUPT OVERVIEW

The device provides the user with an interrupt signal in the API Description
form of a single, general-purpose interrupt output pin MYKONOS_configGpInterrupt
GP_INTERRUPT. This pin asserts to a logic high level when
mykonosGpioErr_t
interrupt events occur. When the baseband processor (BBP) MYKONOS_configGpInterrupt(mykonosDevice_t
detects a rising edge on the GP_INTERRUPT pin, the BBP uses *device, uint16_t gpMask)
an application programming interface (API) function to
This function sets the general-purpose (GP) interrupt register
determine the source of the interrupt.
bit mask to enable interrupt sources that assert the GP_
The user can control (enable or disable) assertion of the INTERRUPT pin. The GP_INTERRUPT pin only asserts for
GP_INTERRUPT pin by certain events. Figure 104 shows the enabled sources. The events that cause the GP_INTERRUPT
interrupt sources for the device and outlines control blocks for pin to assert are user selectable by setting the gpMask parameter
them. The ARM error interrupt cannot be ignored and can in this function. The device default is gpMask = x1FF, which
always assert the GP_INTERRUPT pin. Note that the logic means ignore all events. The ARM error interrupt cannot be
block format in Figure 104 is intended to show the functional ignored and can always assert the GP_INTERRUPT pin. Table 163
operation of the GP_INTERRUPT signal but does not necessarily outlines possible interrupt sources for this device.
represent the method of implementation inside the device.
Parameters
 gpMask: This value is passed to enable one or more general
purpose interrupt sources (1 = ignores the source, and 0 =
enables the source interrupt to the GP_INTERRUPT pin).

Tx PLL LOCK

Rx PLL LOCK

SNIFFER PLL LOCK

CALL PLL LOCK

CLOCK PLL LOCK GP INTERRRUPT

J5
JESD204B DEFRAMER

Tx1 PA PROTECTION

Tx2 PA PROTECTION

ARM WATCHDOG

ARM ERROR

BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

readGpinterruptStatus
(status)
14652-091

configGpinterrupt
(gpMask)

Figure 104. General-Purpose Interrupt Structure

Table 163. GP_Interrupt Configurations

gpMask Bits Description Reset
0 Tx PLL lock 0x1
0 = allows phased-locked loop (PLL) unlocking to assert the GP_INTERRUPT pin
1 = ignores Tx PLL lock
1 Rx PLL lock 0x1
0 = allows PLL unlocking to assert the GP_INTERRUPT pin
1 = ignores Rx PLL lock

Rev. B | Page 225 of 360

UG-992 AD9371/AD9375 System Development User Guide
gpMask Bits Description Reset
2 Sniffer PLL lock 0x1
0 = allows PLL unlocking to assert the GP_INTERRUPT pin
1 = ignores sniffer PLL lock
3 Calibration PLL lock 0x1
0 = allows PLL unlocking to assert the GP_INTERRUPT pin
1 = ignores calibration PLL lock
4 Clock PLL lock 0x1
0 = allows PLL unlocking to assert the GP_INTERRUPT pin
1 = ignores clock PLL lock
5 JESD204 deframer interrupt 0x1
0 = allows the JESD204B deframer interrupt to assert the GP_INTERRUPT pin
1 = ignores JESD204 deframer interrupt
6 Tx1 PA protection 0x1
0 = allows the Tx1 PA protection event to assert the GP_INTERRUPT pin
1 = ignores Tx1 PA protection
7 Tx2 PA protection 0x1
0 = allows the Tx2 PA protection event to assert the GP_INTERRUPT pin
1 = ignores Tx2 PA protection
8 ARM watchdog 0x1
0 = allows the ARM watchdog timeout to assert the GP_INTERRUPT pin
1 = ignores the watchdog timeout event
9 ARM error. 0x1
0 = allows the ARM to assert the GP_INTERRUPT pin when an error occurs.
1 = ignores the ARM error event.
[15:10] Reserved for future use 0x0

MYKONOS_readGpInterruptStatus Parameters
mykonosGpioErr_t • status: This parameter returns the IRQ source(s) that
MYKONOS_readGpInterruptStatus(mykonosDevi caused the GP_INTERRUPT pin to assert.
ce_t *device, uint16_t *status)
This function reads the GP interrupt status to determine what Table 164. GP_INTERRUPT Status
caused the GP_INTERRUPT pin to assert. When the baseband Status Bit(s) Description
processor (BBP) detects a rising edge on the GP_INTERRUPT 0 1 = Tx PLL unlock
pin, this function allows the BBP to determine the source of the 1 1 = Rx PLL unlock
interrupt. The value returned in the status parameter shows one 2 1 = sniffer PLL unlock
or more sources for the interrupt, as shown in Table 164. 3 1 = calibration PLL unlock
Note that the phase-locked loop (PLL) unlock bits are not sticky. 4 1 = clock PLL unlock
These bits follow the current status of the PLLs. If the PLL relocks, 5 1 = JESD204 deframer interrupt occurred
the status bit clears as well. The GP_INTERRUPT pin is the 6 1 = Tx1 PA protection event
logical OR of all the sources. When all the status bits are low, the 7 1 = Tx2 PA protection event
GP_INTERRUPT pin is low. The status word readback shows the 8 1 = ARM watchdog timeout
current value for all interrupt sources, even if they are disabled 9 1 = ARM interrupt occurred
by the mask using the MYKONOS_configGpInterrupt() [15:10] Reserved for future use
function. However, the GP_INTERRUPT pin only asserts for
the enabled sources.

Rev. B | Page 226 of 360

AD9371/AD9375 System Development User Guide UG-992

AUXILIARY CONVERTERS—AUXDAC_x, AUXADC_x, AND TEMPERATURE SENSOR

This section describes the setup and operation of the auxiliary Hardware Configuration
data converters in the device. These features are included to The auxiliary DACs have priority use of the pins when a given
simplify control tasks, take static measurements during normal auxiliary DAC is enabled. The pin takes on the auxiliary DAC
operation, and provide flexibility that can be used across multiple function and the corresponding GPIO_3P3_x output driver is
applications without adding external components. The following tristated. See Table 166 for auxiliary DAC to GPIO_3P3_x pin
sections provide details needed to set up each block and the mapping.
application programming interface (API) functions required to
The auxiliary DACs are designed to be used in feedback loop
control operation.
operations. For example, one can generate a voltage supply used
AUXILIARY DACs to control a voltage controlled crystal oscillator (VCXO) input.
The 10 auxiliary digital-to-analog converters (DACs) are 10-bit, For such control system uses, the absolute value of the voltage
general-purpose DACs. An auxiliary DAC is a segmented 10-bit output is not critical, but it is recommended that the voltage
current source array. Two additional bits of dynamic range are steps be 12-bit accurate and monotonic. The feedback of the
created through a reference voltage selection. The aggregate servo loop renders the absolute level unimportant.
auxiliary DAC spans approximately 12 bits of dynamic range. The Note that when using an auxiliary DAC as a controlled voltage
auxiliary DAC output range spans from 0.5 V to 3.0 V (Changed to reference, take care regarding the tolerances on the 3.3 V
3.0 V to match d/s). Each auxiliary DAC is capable of sourcing 10 domain that serve as the supplies for the auxiliary DACs.
mA. The auxiliary DACs and the 12 GPIO_3P3_x ports are
Auxiliary DAC Control Software Control Procedure
multiplexed onto the same pins. Figure 105 shows the auxiliary
DAC block. Note that, for stability, a 100 nF bypass capacitor The flowchart shown in Figure 106 illustrates the process
must be placed at each active auxiliary DAC output. required to properly control the auxiliary DACs when using
them to generate control voltage outputs.
AUX DAC 9
VREF Rise and Fall Times
10 GPIO_3P3_8
SLOPE 100nF
Table 165 provides an example of auxiliary DAC rise and fall times.

AUX DAC 0 Table 165. Example Auxiliary DAC Rise and Fall Times
VREF
Voltage Change (V) Bit Change Rise Time (μs) Fall Time (μs)
10 GPIO_3P3_9
SLOPE 100nF
1.325 768 2.86 11.86
14652-092

ENABLE

Figure 105. Auxiliary DACs Block Diagram PSRR

The auxiliary DAC power supply rejection ratio (PSRR) is
measured to 100 kHz (20 mV ripple injection). Worst case
PSRR is approximately 6 dB and occurs near the maximum
output levels.

Table 166. Auxiliary DAC to GPIO_3P3_x Pin Mapping

Pin Number Type Mnemonic Description
C13 Output GPIO_3P3_9 Auxiliary DAC 0 output pin.
D12 Output GPIO_3P3_7 Auxiliary DAC 1 output pin
E14 Output GPIO_3P3_6 Auxiliary DAC 2 output pin
D14 Output GPIO_3P3_10 Auxiliary DAC 3 output pin
C1 Output GPIO_3P3_0 Auxiliary DAC 4 output pin
C2 Output GPIO_3P3_1 Auxiliary DAC 5 output pin
D1 Output GPIO_3P3_3 Auxiliary DAC 6 output pin
E1 Output GPIO_3P3_4 Auxiliary DAC 7 output pin
D5 Output GPIO_3P3_5 Auxiliary DAC 8 output pin
D13 Output GPIO_3P3_8 Auxiliary DAC 9 output pin

Rev. B | Page 227 of 360

UG-992 AD9371/AD9375 System Development User Guide
START

DEVICE IS INITIALIZED BY
MYKONOS_initialize() function

POPULATE mykonosAuxIo_t structure

MEMBERS WITH CORRECT VALUES

CALL MYKONOS_setupAuxDacs() function

to configure all 10 AuxDACs

SET AuxDAC OUTPUT LEVEL USING

MYKONOS_writeAuxDac()
SELECT PARTICULAR AuxDAC USING auxDacIndex
PARAMETER

YES
CHANGE AuxDAC OUTPUT CODE?

NO
NO CHANGE AUX DAC SLOPE
OR VREF SETTINGS?

STOP

14652-093
YES

Figure 106. Auxiliary DAC Control Procedure

Rev. B | Page 228 of 360

AD9371/AD9375 System Development User Guide UG-992
AUXILIARY DAC STEP FACTOR = 0
Auxiliary DACs Software Configuration 3500
The process required to enable the auxiliary DACs requires the
15
user to select values for members in the mykonosAuxIo_t 3000 376
5.2
+ 184
substructure associated with the auxiliary DAC. The following 0x 87
655

AUXILIARY DAC V OUT (mV)

749 2.7
2500 1.63 3 5
descriptions outline the possible values for the mykonosAuxIo_t Y= +1
2x
361 958
structure members and the interpretation of these values. Each .61 964
2000 Y=
1
8 32.
+
auxiliary DAC can be independently configured. 57x
901 714
= 1.5 933
1500 Y 18.
The device → auxIo → auxDacEnable structure member settings x +3
71
606
follow: 1.5
1000 Y=

 When set to 0, this structure member disables the VREF

VREF
= 3,
= 2,
STEP FACTOR = 0
STEP FACTOR = 0
500
corresponding auxiliary DAC (Bit 0 corresponds to VREF = 1, STEP FACTOR = 0
VREF = 0, STEP FACTOR = 0
Auxiliary DAC 0, Bit 1 corresponds to Auxiliary DAC 1, 0

14652-094
0 200 400 600 800 1000 1200
and so on).
AUXILIARY DAC CODE
 When set to 1, this structure member enables the Figure 107. Auxiliary DAC Output Voltage (VOUT) vs. Auxiliary DAC Code for
corresponding auxiliary DAC (Bit 0 corresponds to the Different auxDacVref Values (auxDacSlope = 0)
Auxiliary DAC 0, Bit 1 corresponds to Auxiliary DAC 1, AUXILIARY DAC STEP FACTOR = 1
and so on). 3500

The device → auxIo → auxDacSlope[i] structure member 3000 67455

2206.4
08x +
settings follow: = 0.8226

AUXILIARY DAC V OUT (mV)

Y
2500 35222
1719.0
 When set to 0, this structure member sets the .81 09 32x +
Y=0
corresponding auxiliary DAC voltage output (VOUT) codes 2000 2761
03.70
81 28 x + 12
to be 1.404 mV/code (see Figure 107). .79
Y=0
1500 67374
 When set to 1, this structure member sets the 8 39 51x +
693.2
.7
Y=0
corresponding auxiliary DAC voltage output (VOUT) codes 1000
to be 0.702 mV/code (see Figure 108).
VREF = 3, STEP FACTOR = 0
500 VREF = 2, STEP FACTOR = 0
The device → auxIo → auxDacVref[i] structure member settings VREF
VREF
= 1,
= 0,
STEP FACTOR = 0
STEP FACTOR = 0
follow: 0

14652-095
0 200 400 600 800 1000 1200
 When set to 0, this structure member sets the corresponding AUXILIARY DAC CODE
auxiliary DAC output midpoint to 1 V (see Figure 107 and Figure 108. Auxiliary DAC Output Voltage (VOUT) vs. Auxiliary DAC Codes for
Figure 108). Different auxDacVref Values (auxDacSlope = 1)
 When set to 1, this structure member sets the corresponding MYKONOS_setupAuxDacs
auxiliary DAC output midpoint to 1.5 V (see Figure 107
After correctly configuring all structure members mentioned in
and Figure 108).
the Auxiliary DACs Software Configuration section, execute the
 When set to 2, this structure member sets the corresponding
following application programming interface (API) function:
auxiliary DAC output midpoint to 2 V (see Figure 107 and
Figure 108). mykonosErr_t
MYKONOS_setupAuxDacs(mykonosDevice_t
 When set to 3, this structure member sets the corresponding *device)
auxiliary DAC output midpoint to 2.5 V (see Figure 107 and
This function reads data from the device auxiliary input/output
Figure 108).
substructure and then loads this data into the device. This
The device → auxIo → auxDacValue[i] structure member function programs all configuration parameters for 10 auxiliary
settings follow: DACs at the same time, including the enable/disable, slope, VREF
 The value programmed to this structure member is loaded (midpoint), and the initial auxiliary DAC code.
to the corresponding auxiliary DAC and is output as the This function can be called any time after MYKONOS_initialize()
corresponding analog voltage. The value programmed to to reconfigure, enable, or disable the different auxiliary DAC
this member must be in range between 0 and 1023 (10-bit outputs. The auxiliary DACs are used in manual control mode.
DAC code).

Rev. B | Page 229 of 360

UG-992 AD9371/AD9375 System Development User Guide
AUX ADC_0
MYKONOS_writeAuxDac
AUX ADC_1 AUX ADC
After calling this setup function, it is possible to change a AUX ADC_2 DECIMATION
12
particular auxiliary DAC code by calling the following function: AUX ADC_3

14652-096
mykonosErr_t
ENABLE
MYKONOS_writeAuxDac(mykonosDevice_t SELECT
*device, uint8_t auxDacIndex, uint16_t Figure 109. Auxiliary ADC Input Block Diagram
auxDacCode)
Table 167 outlines the hardware connections on the device for
This function updates the 10-bit code that controls the auxiliary
the auxiliary ADC inputs. A small value capacitor (680 pF) can
DAC output voltage. The auxiliary DAC code is updated for the
be placed on the auxiliary ADC input pins to improve noise
specified auxiliary DAC and is written to the device data structure
performance.
for future reference.
Auxiliary (AUX) ADC Readback Software Control
Parameters
Procedure
 *device: This is a pointer to the device settings structure. The flowchart shown in Figure 111 illustrates the process
 auxDacIndex: an index that selects which auxiliary DAC to required to properly control the auxiliary ADCs when using
set the new DAC code. The allowable values are from 0 to 9. them to read voltage levels. A typical plot of output code vs.
 auxDacCode: the DAC code to update the auxiliary DAC; input voltage is shown in Figure 110.
sets the output voltage of selected DAC. The programmed 4500
value must be in range between 0 and 1023 (10-bit DAC
4000 Y = 1290x – 45
code).
AUXILIARY ADC CODE (Decimal) 3500
This function can be called any time after MYKONOS_
3000
initialize() and MYKONOS_setupAuxDacs().
2500
AUXILIARY ADC
2000
The auxiliary analog-to-digital converter (ADC) is a single 12-bit
auxiliary converter with four multiplexed inputs that cover an 1500

input level range from 0.05 V to 3.25 V. The auxiliary ADC 1000
allows monitoring of the desired voltages, such as a power
500
amplifier (PA) power detector or an external temperature
sensor. Figure 109 shows the general auxiliary ADC input 0

14652-097
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2
connection scheme. INPUT VOLTAGE (V)

Figure 110. Auxiliary ADC Code vs. Input Voltage

Table 167. Auxiliary ADC Input Mapping

Pin Number Type Mnemonic Description
E13 Input AUXADC_0 Auxiliary ADC 0 input pin
C11 Input AUXADC_1 Auxiliary ADC 1 input pin
C12 Input AUXADC_2 Auxiliary ADC 2 input pin
D11 Input AUXADC_3 Auxiliary ADC 3 input pin

Rev. B | Page 230 of 360

AD9371/AD9375 System Development User Guide UG-992
START

DEVICE IS INITIALIZED BY
MYKONOS_initialize() FUNCTION

CALL MYKONOS_setupAuxAdc ()
FUNCTION TO SETUP AuxADC

USING FUNCTION MYKONOS_setAuxAdc Channel () SETUP

AuxDC INPUT MUX TO DESIRE CHANNEL

WAIT AT LEAST
6 × AUX ADC CONVERSION TIME

READ BACK TEMPERATURE AuxADC MEASUREMENT

RESULTS USING MYKONOS_readAuxAdc ()

YES
PERFORM ANOTHER AUX ADC
MEASUREMENT?

NO
NO
CHANGE AUX ADC INPUT MUX
SETTINGS?

YES

14652-198
STOP

Figure 111. Auxiliary (AUX) ADC Readback Procedure

Auxiliary ADCs Software Configuration Parameters

The user must use an application programming interface (API)  *device: This is a pointer to the device settings structure.
command to read back the ADC code for a selected input. A list  adcDecimation: ADC decimation factor. The allowable
of API commands with instructions detailing how to use them values are in the 0 to 7 range.
is outlined in this section.
Decimation = 256 × 2adcDecimation (19)
MYKONOS_setupAuxAdcs
Conversion Time = ADC Clock Cycles × Decimation (20)
The following function configures an auxiliary ADC with the
requested decimation factor; excecute this command first. where ADC Clock Cycles = (1/40 MHz) = 25 ns.
mykonosErr_t MYKONOS_setupAuxAdcs For example, if adcDecimation = 4, the ADC conversion time is
(mykonosDevice_t *device, uint8_t approximately 0.1 ms
adcDecimation,uint8_t enable)
 enable: When set to 0, this disables the auxiliary ADC.
The auxiliary ADC clock is automatically set as close as possible When set to 1, this enables the auxiliary ADC.
to 40 MHz. The auxiliary ADC conversion time = (1/40 MHz) ×
decimation, where the decimation ranges from 256 auxiliary This function can be called any time after MYKONOS_
ADC clock cycles to 32,768 auxiliary ADC clock cycles. initializer().

Rev. B | Page 231 of 360

UG-992 AD9371/AD9375 System Development User Guide
MYKONOS_setAuxAdcChannel Parameters
The next API function to be used with the auxiliary ADC is as  *device: This is a pointer to the device settings structure.
follows:  *adcCode: This is a pointer for the 12-bit ADC read value.
mykonosErr_t MYKONOS_setAuxAdcChannel
This function can be called any time after MYKONOS_
(mykonosDevice_t *device, uint8_t
auxAdcChannel ) initialize(). First, configure the auxiliary ADC using the
MYKONOS_setupAuxAdcs() and MYKONOS_
This function sets the selected input channel of the auxiliary
setAuxAdcChannel() functions.
ADC. After setting the auxiliary ADC channel, wait at least 1
auxiliary ADC conversion time before reading back the TEMPERATURE SENSOR
auxiliary ADC value. The transceiver provides the user with an option to use the
Parameters auxiliary ADC to measure the transceiver die temperature. This
temperature sensor is on the die; therefore, it cannot be used to
 *device: A pointer to the device settings structure measure the ambient device temperature.
 auxAdcChannel: this parameter selects the auxiliary ADC
inputs and internal temperature sensor as follows: Figure 112 shows the temperature sensor output vs. the
temperature measured at the surface of the device.
 When set to 0, this parameter selects Auxiliary ADC
430
Input 0. Refer to Table 167 for hardware configuration.
 When set to 1, this parameter selects Auxiliary ADC

INTERNAL TEMPERATURE SENSOR CODE

410

Input 1. Refer to Table 167 for hardware configuration. 390

 When set to 2, this parameter selects Auxiliary ADC 370

Input 2. Refer to Table 167 for hardware configuration. 350
 When set to 3, this parameter selects Auxiliary ADC
330
Input 3. Refer to Table 167 for hardware configuration.
310
 When set to 16, this parameter selects the internal
temperature sensor. 290

270
This function can be called any time after MYKONOS_
250
initialize() and MYKONOS_setupAuxAdcs().
230
MYKONOS_readAuxAdc
–39.286
–35.159
–30.022
–24.623
–20.314
–15.426
–10.354
–5.425
0.312
5.181
9.916
14.537
20.169
24.860
30.422
35.066
39.791
45.210
49.663
54.714
59.601
64.54
69.806
75.083
79.645
85.297
89.951
95.457
100.533
105.419
110.114

14652-199
To read the auxiliary ADC data for the selected auxiliary ADC
CASE TEMPERATURE (°C)
input, use the following application programming interface Figure 112. Internal Temperature Sensor Code vs. Case Temperature
(API) function:
Software Configuration
mykonosErr_t MYKONOS_readAuxAdc
(mykonosDevice_t *device, uint16_t The API provides functions to read back the internal die
*adcCode ) temperature sensor output. Figure 113 outlines the procedure
Before using this function to read back the output value of the that must be followed to read back the internal temperature
selected auxiliary ADC, ensure that at least one ADC conversion sensor. A list of API commands with instructions detailing how
time passes after setting the auxiliary ADC channel. to use them is outlined in the following section.

Rev. B | Page 232 of 360

AD9371/AD9375 System Development User Guide UG-992
START

DEVICE IS INITIALIZED BY
MYKONOS_initialize() FUNCTION

POPULATE TempSensorConfig_t
STRUCTURE MEMBERS WITH CORRECT VALUES

CALL MYKONOS_setupTempSensor ()
FUNCTION TO SETUP TEMPERATURE SENSOR

USING FUNCTION MYKONOS_setAuxAdc Channel () SETUP

AuxADC INPUT MUX TO CHANNEL 16

INITIATE TEMPERATURE SENSOR MEASUREMENT

USING FUNCTION MYKONOS_startTempMeasurement ()

WAIT AT LEAST
6 × AuxADC CONVERSION TIME

READ BACK TEMPERATURE SENSOR MEASUREMENT

RESULTS USING MYKONOS_readTempSensor ()

IS tempValid OF
mykonosTempSensorConfig_t NO
STRUCTURE SET?

YES

VALID TEMPERATURE RESULTS ARE STORED IN

TEMP CODE OF mykonosTempSensorConfig_t STRUCTURE

YES
PERFORM ANOTHER TEMPERATURE
MEASUREMENT?

NO
14652-200

STOP

Figure 113. Temperature Sensor Readback Procedure

Rev. B | Page 233 of 360

UG-992 AD9371/AD9375 System Development User Guide
The user must use API commands to read back the ADC code mykonosGpioErr_t
for a selected input. A list of API commands with instructions MYKONOS_getTempSensorConfig(mykonosDevice
_t *device,mykonosTempSensorConfig_t
detailing how to use them is outlined in this section.
*tempSensor)
MYKONOS_setupTempSensor Parameters
The following function sets up the operation of the internal
• *device: This is a pointer to the device setting structure.
temperature sensor:
• *tempSensor: This is a pointer to the mykonosTemp-
mykonosGpioErr_t SensorConfig_t structure, which holds the configuration
MYKONOS_setupTempSensor(mykonosDevice_t *
settings for the temperature sensor.
device, mykonosTempSensorConfig_t
*tempSensor) This function can be called any time after MYKONOS_
Before using this function, ensure that the MYKONOS_ initialize().
setupAuxADC() function executes and MYKONOS_ MYKONOS_startTempMeasurement
setAuxAdcChannel() is configured to read back from
the internal temperature sensor. Also ensure that the This API function initiates a temperature sensor measurement.
mykonosTempSensorConfig_t structure is populated with mykonosGpioErr_t
correct values. MYKONOS_startTempMeasurement(mykonosDevic
e_t *device)
Parameters
Before this function can be executed, the user must do the
• * device: This is a pointer to the device settings structure. following:
• *tempSensor: this is a pointer to the mykonos-
• Set up the temperature sensor using the MYKONOS_
TempSensorConfig_t structure that holds the
setupTempSensor() function.
configuration settings for the temperature sensor.
• Connect the auxiliary ADC input mux to the internal
The following members are the mykonosTempSensorConfig_t temperature sensor (Channel 16 = 0x10) using the
structure members: MYKONOS_setAuxAdcChannel() function.
• uint8_t tempDecimation—a 3-bit value that controls the After this function is executed, the internal temperature sensor
auxiliary ADC decimation factor when used for temperature block performs a measurement and updates the register values.
sensor calculations, according to the following: The user can read back the temperature sensor information
using the MYKONOS_readTempSensor() function.
Auxiliary ADC decimation = 256 × 2tempDecimation (21)
Parameters
• uint8_t offset—an 8-bit offset added to the temperature
sensor code internally. • *device: This is a pointer to the device settings structure.
• uint8_t overrideFusedOffset—a bit that overrides the
This function can be called any time after MYKONOS_
factory calibrated offset value; uses the value stored in the
initialize().
offset member.
• uint8_t tempWindow—a 4-bit code with a resolution of MYKONOS_readTempSensor
1°C/LSB. Each time a temperature measurement is To read temperatures from the internal on die temperature
performed, the device compares the current temperature sensor and update temperature sensor status information, use
against the previous value. If the value exceeds the following API command:
tempWindow, the windowExceeded member of the mykonosGpioErr_t
mykonosTempSensorStatus_t structure is set. MYKONOS_readTempSensor(mykonosDevice_t
*device, mykonosTempSensorStatus_t
In the scenario where structure member values are outside of
*tempStatus)
range, the MYKONOS_setupTempSensor() returns an error.
Refer to the description in the application programming Before using this function to read back the temperature sensor
interface (API) help file for more details. information, the user must do the following:

This function can be called any time after MYKONOS_ • Set up the temperature sensor using the MYKONOS_
initialize(). setupTempSensor() function.
• Set up the auxiliary ADC input mux to the internal
MYKONOS_getTempSensorConfig
temperature sensor (Channel 16 = 0x10 ) using the
The next API function reads data from the temperature sensor MYKONOS_setAuxAdcChannel() function.
registers and populates the *tempSensor data structure. After • Initiate temperature sensor measurements using the
this function is executed, the *tempSensor parameter holds MYKONOS_startTempMeasurement() function. The user
updated values from the device registers. This parameter is used must call this function every time temperature readings
as follows: must be performed.

Rev. B | Page 234 of 360

AD9371/AD9375 System Development User Guide UG-992
The user must allow at least one computation period to elapse The description of the mykonosTempSensorStatus_t structure
between the temperature measurement request function call, members is as follows:
MYKONOS_startTempMeasurement(), and the temperature
• int16_t tempCode. This structure member contains a
readback using the MYKONOS_readTempSensor() function.
16-bit signed temperature value. This value is reported in
The temperature sensor computation period equals six times degrees Celsius.
the auxiliary ADC conversion time, which is determined by • uint8_t windowExceeded. This flag is set if the absolute
256 × 2 tempDecimation value of the difference between the previous and current
Auxiliary ADC Conversion Time = (22) temperature measurement is greater than the value stored
40 × 106
in the temperature configuration tempWindow, a member
The tempDecimation parameter is stored in the mykonos- of mykonosTempSensorConfig_t structure.
TempSensorConfig_t structure. • uint8_t windowHiLo. When windowExceeded flag is set,
The results of a temperature measurement function call are this bit is set to 1 if the current value is greater than the
stored in the mykonosTempSensorStatus_t structure. If a valid previous value. This bit is set to 0 if the current value is less
measurement is achieved, the tempValid member of the mykonos- than or equal to the previous value.
TempSensorStatus_t structure is set, and the tempCode of the • uint8_t tempValid. This structure member indicates valid
mykonosTempSensorStatus_t structure contains the actual measurement results when the temperature reading is
reading. complete, and a valid temperature value is stored in the
tempCode structure member.
Parameters
• *device: This is a pointer to the device settings structure.
• *tempStatus: a pointer to the mykonosTempSensorStatus_t
structure that is updated with the temperature sensor
readings.

Rev. B | Page 235 of 360

UG-992 AD9371/AD9375 System Development User Guide

RF PORT INTERFACE
This section provides the recommended RF transmitter and Mathematically, the PEDZ model is represented as
receiver interfaces to obtain optimal device performance. This PEDZ = RP||jXP (24)
section includes data regarding the expected RF port impedance
values, potential impedance matching network techniques, and The notation, a || b is short for a in parallel with b. The term,
examples of impedance matching networks. Some reference jXP, can be positive (inductive) or negative (capacitive).
material is also provided regarding board layout techniques and Conversions Between SEDZ and PEDZ
balun selection guidelines. From a network theory perspective, the SEDZ model and the
The device is a highly integrated transceiver with two PEDZ model are equivalent. The following equations provide a
transmitters, two main receivers, and an observation channel means to calculate a PEDZ model from a SEDZ model. Note
with two observation receiver inputs and three sniffer receiver that SEDY is the series equivalent differential admittance, which
inputs. All input and output ports are differential; therefore, is the reciprocal of SEDZ. Similarly, PEDY is the parallel equivalent
external impedance matching networks are required on differential admittance, which is the reciprocal of PEDZ.
transmitter and receiver ports to convert them from single- 1 1
 1    
RP = Re 
ended to differential as well as to achieve performance levels 1
  Re  (25)
indicated on the data sheet.   SEDZ    RS  jXS 
SERIES AND PARALLEL IMPEDANCE MODELS 1 1
 1    
jXP = −  Im
1
In describing differential impedances, two equivalent models     Im  (26)
are commonly used: series equivalent differential impedance   SEDZ    RS  jX S 
(SEDZ) and parallel equivalent differential impedance (PEDZ). Conversion from and to the SEDZ model from the PEDZ
Both formats are used throughout this user guide, and descriptions model is accomplished using the following equations:
of the models and the conversion between the two formats are
provided in the following sections.  
 1 
Series Equivalent Differential Impedance (SEDZ) Models RS = Re  1 j  (27)
  
The SEDZ model is depicted in Figure 114. Note that series  RP XP 
refers to the fact that the resistance is in series with the reactance
formed by the parallel combination of the capacitor and  
inductor (see Figure 114).  1 
jXS = Im  1 j  (28)
L   
L1  RP XP 
R L = LS
R1
+
TERM R = RS C
Example 1 and Example 2 that follow illustrate the simplicity of
TERM 1 C1 the conversion process.
NUM = 1 C = CS
– Z = 50Ω
Example 1: SEDZ to PEDZ Conversion
14652-202

Given SEDZ = 100 – j20 Ω, the PEDZ model calculation uses

Figure 114. SEDZ Definition Equation 25 and Equation 26 as follows:
Mathematically, the differential series impedance is represented by 1 1
 1    
RP = Re
1
SEDZ = RS + jXS (23)   Re  =
  SEDZ    RS  jX S 
The + sign implies that the elements are in series. The jXS can
[0.0096]–1 = 104 Ω (29)
be positive (inductive) or negative (capacitive).
1 1
Parallel Equivalent Differential Impedance (PEDZ) Model   1    1 
jXP = −  
Im   Im  =
The PEDZ model is depicted in Figure 115. In contrast to the   SEDZ   100  j20 
SEDZ model, the resistance is in parallel with the reactance −[0.0019]–1 = −j520 Ω (30)
formed by the parallel combination of the capacitor and inductor.
The preceding calculations show that PEDZ = RP || jXP = 104 ||
(−j520 Ω).
+ R C L
TERM R1 C1 L1
TERM 1 R = RP C = CP L = CP
NUM = 1
Z = 50Ω
–
14652-203

Figure 115. PEDZ Definition

Rev. B | Page 236 of 360

AD9371/AD9375 System Development User Guide UG-992
Example 2: PEDZ to SEDZ Conversion  Understanding the differential impedance models is
Given PEDZ = 104 || −j520 Ω, the SEDZ model calculation uses critical when interpreting the data within this user guide.
Equation 27 and Equation 28 as follows: RF PORT IMPEDANCE DATA
    This section provides the port impedance data for all transmitters
RS = Re  1  = Re  1  = 100 Ω (31) and receivers in the device. The following points of consideration
 1  1 j 
j    
   are important for this section:
 R P X P   104  520 
 ZO is defined as 50 Ω.
   
jXS = Im  1  = Im  1  = −j20 Ω (32)  The reference plane for this data is the device ball pads.
 1  1 j 
j     Figure 116, Figure 118, Figure 120, Figure 122, Figure 124,
  
 R P X P   104  520 
Figure 126, Figure 128, and Figure 130 show the SEDZ vs.
The preceding calculations show SEDZ = RS + jXS = 100 – j20 Ω. frequency in the Smith chart. Figure 117, Figure 119, Figure 121,
Thus, Example 1 and Example 2 illustrate that conversion Figure 123, Figure 125, Figure 127, Figure 129, and Figure 131
between the two models is straightforward. show PEDZ vs. frequency. The X STATUS parameter in the
PEDZ plot indicates if the L or C PE parameter represents a
The following two major factors must be kept in mind: capacitance measured in pF (X STATUS = 0) or an inductance
 The SEDZ model is equivalent to the PEDZ model. The measured in nH (X STATUS = 1).
conversion between the models is straightforward.
m1 Tx1/Tx2 PORT IMPEDANCE: SEDZ
FREQUENCY = 1.000GHz
S (1,1) = 0.205 / –126.314

1.0
IMPEDANCE = 37.272 – j12.862

2.0
0.5

m4
m2
FREQUENCY = 2.000GHz m5
S (1,1) = 0.391 / 175.770
IMPEDANCE = 21.928 + j1.492 m3

0.2 5.0
m3 m8
FREQUENCY = 3.000GHz 10
S (1,1) = 0.548 / 128.665
IMPEDANCE = 17.610 + j21.560 20
m2
0.5

1.0

2.0

5.0

10
20
m4 m1 -20
FREQUENCY = 4.000GHz
S (1,1) = 0.657 / 88.433
-10
IMPEDANCE = 20.335 + j47.066
-0.2 -5.0
S(1,1)
m5
FREQUENCY = 5.000GHz
S (1,1) = 0.719 / 52.629
IMPEDANCE = 37.502 + j88.705
5

0
-0.

-2.

m8
-1.0

FREQUENCY = 6.000GHz
14652-604

S (1,1) = 0.742 / 18.124

IMPEDANCE = 160.279 + j164.892 FREQ (0.0000Hz TO 6.000GHz)

Figure 116. Tx1 and Tx2 Series Equivalent Differential Port Impedance
Tx1/Tx2 PORT PEDZ
350 30

300 R PEDZ
L OR C PE 25
X STATUS m7
FREQUENCY = 5.000GHz
250 L OR C PE = 3.328
20
L OR C PE
X STATUS

200
R PEDZ

15
150

10
100

m7 5
50

0 0
0 1 2 3 4 5 6
FREQUENCY (GHz)
14652-204

NOTES
1. X STATUS: 0 = CAPACITANCE IN pF, 1 = INDUCTANCE IN nH.

Figure 117. Tx1 and Tx2 Parallel Equivalent Differential Port Impedance

Rev. B | Page 237 of 360

UG-992 AD9371/AD9375 System Development User Guide
m1 Rx1 PORT IMPEDANCE: SEDZ
FREQUENCY = 1.000GHz

1.0
S (1,1) = 0.582 / –16.983
IMPEDANCE = 146.615 – j75.359

2.0
0.5
m2
FREQUENCY = 2.000GHz
S (1,1) = 0.552 / –35.028
IMPEDANCE = 86.763 – j79.119 S(1,1)

0.2 5.0
m3
FREQUENCY = 3.000GHz 10
S (1,1) = 0.502 / –55.661
20
IMPEDANCE = 54.570 – j60.402

0.5

1.0

2.0

5.0

10
20
m8
m1
m4 -20
FREQUENCY = 4.000GHz
m2
-10
S (1,1) = 0.431 / –81.317 m5
IMPEDANCE = 38.567 – j40.360
-0.2 m4 m3 -5.0

m5
FREQUENCY = 5.000GHz
S (1,1) = 0.353 / –116.392
IMPEDANCE = 30.422 – j21.987

0
-0.

-2.
m8

-1.0
FREQUENCY = 6.000GHz

14652-605
S (1,1) = 0.313 / –165.302
IMPEDANCE = 26.493 – j4.660 FREQ (0.0000Hz TO 6.000GHz)

Figure 118. Rx1 Series Equivalent Differential Port Impedance

Rx1 PORT PEDZ

200 0.55

180 0.50

0.45
160
0.40
m7
140 R PEDZ
L OR C PE 0.35
L OR C PE
X STATUS
X STATUS
R PEDZ

120 0.30

100 0.25

0.20
80
m7 0.15
FREQUENCY = 5.625GHz
60 L OR C PE = 0.355
0.10
m6
40 FREQUENCY = 5.625GHz m6
0.05
R PEDZ = 32.066
20 0
0 1 2 3 4 5 6
FREQUENCY (GHz)
14652-205

NOTES
1. X STATUS: 0 = CAPACITANCE IN pF, 1 = INDUCTANCE IN nH.

Figure 119. Rx1 Parallel Equivalent Differential Port Impedance

Rev. B | Page 238 of 360

AD9371/AD9375 System Development User Guide UG-992
m1 Rx2 PORT IMPEDANCE: SEDZ
FREQUENCY = 1.000GHz
S (1,1) = 0.582 / –16.996

1.0
IMPEDANCE = 146.631 – j75.499

2.0
0.5
m2
FREQUENCY = 2.000GHz
S (1,1) = 0.553 / –35.022
IMPEDANCE = 86.750 – j79.424 S(1,1)

0.2 5.0
m3
FREQUENCY = 3.000GHz 10
S (1,1) = 0.505 / –55.681
IMPEDANCE = 54.349 – j60.798 20

0.5

1.0

2.0

5.0

10
20
m8
m1
m4 -20
FREQUENCY = 4.000GHz
S (1,1) = 0.437 / –80.857 m5 m2 -10
IMPEDANCE = 38.478 – j40.975
-0.2 m4 m3
-5.0

m5
FREQUENCY = 5.000GHz
S (1,1) = 0.361 / –114.970
IMPEDANCE = 30.298 – j20.805

0
-0.

-2.
m8

-1.0
FREQUENCY = 6.000GHz

14652-606
S (1,1) = 0.318 / –162.027
IMPEDANCE = 26.322 – j5.755 FREQ (0.0000Hz TO 6.000GHz)

Figure 120. Rx2 Series Equivalent Differential Port Impedance

Rx2 PORT PEDZ

200 0.55
m7 0.50
180
0.45
160
m6 0.40
R PEDZ
140 L OR C PE 0.35
X STATUS

L OR C PE
X STATUS
120
R PEDZ

0.30

100 0.25

0.20
80
m7 0.15
60 FREQUENCY = 2.625GHz
L OR C PE = 0.472 0.10
40 m6
FREQUENCY = 2.625GHz 0.05
R PEDZ = 137.170
20 0
0 1 2 3 4 5 6
FREQUENCY (GHz)
14652-206

NOTES
1. X STATUS: 0 = CAPACITANCE IN pF, 1 = INDUCTANCE IN nH.

Figure 121. Rx2 Parallel Equivalent Differential Port Impedance

Rev. B | Page 239 of 360

UG-992 AD9371/AD9375 System Development User Guide
m1 ORx1 PORT IMPEDANCE: SEDZ
FREQUENCY = 1.000GHz
S (1,1) = 0.556 / –23.774

1.0
IMPEDANCE = 118.509 – j76.915

2.0
0.5
m2
FREQUENCY = 2.000GHz
S (1,1) = 0.438 / –52.367
IMPEDANCE = 61.507 – j52.799 S(1,1) m5
m8
0.2 5.0
m3
FREQUENCY = 3.000GHz
S (1,1) = 0.225 / –100.662 m4 10
IMPEDANCE = 41.843 – j19.531 20

0.5

1.0

2.0

5.0

10
20
m4 m3
m1
-20
FREQUENCY = 4.000GHz
S (1,1) = 0.206 / 126.049 -10
IMPEDANCE = 37.267 + j12.959 m2
-0.2 -5.0

m5
FREQUENCY = 5.000GHz
S (1,1) = 0.478 / 69.267
IMPEDANCE = 43.349 + j50.217

0
-0.

-2.
m8

-1.0
FREQUENCY = 6.000GHz

14652-607
S (1,1) = 0.665 / 38.240
IMPEDANCE = 70.147 + j103.512 FREQ (0.0000Hz TO 6.000GHz)

Figure 122. ORx1 Series Equivalent Differential Port Impedance

ORx1 PORT PEDZ

240 110
R PEDZ
220 L OR C PE 100
X STATUS
200 90

180 80

160 70
L OR C PE
X STATUS
R PEDZ

140 60

120 50

100 40

80 m7 m6 30
FREQUENCY = 2.625GHz
L OR C PE = 0.603
60 20
m6
40 FREQUENCY = 2.625GHz 10
R PEDZ = 68.401 m7
20 0
0 1 2 3 4 5 6
FREQUENCY (GHz)
14652-207

NOTES
1. X STATUS: 0 = CAPACITANCE IN pF, 1 = INDUCTANCE IN nH.

Figure 123. ORx1 Parallel Equivalent Differential Port Impedance

Rev. B | Page 240 of 360

AD9371/AD9375 System Development User Guide UG-992
m1 ORx2 PORT IMPEDANCE: SEDZ
FREQUENCY = 1.000GHz
S (1,1) = 0.565 / –22.366

1.0
IMPEDANCE = 124.163 – j78.512

2.0
0.5
m2
FREQUENCY = 2.000GHz
S (1,1) = 0.481 / –48.396 m8
IMPEDANCE = 64.849 – j60.703 S(1,1)
5.0
0.2 m5
m3
FREQUENCY = 3.000GHz 10
S (1,1) = 0.332 / –86.090
IMPEDANCE = 41.771 – j31.109 20

0.5

1.0

2.0

5.0

10
20
m4
m4 m1 -20
FREQUENCY = 4.000GHz
S (1,1) = 0.203 / 165.980
-10
IMPEDANCE = 33.399 – j3.428 m3 m2
-0.2 -5.0

m5
FREQUENCY = 5.000GHz
S (1,1) = 0.351 / 108.738
IMPEDANCE = 32.514 + j24.639

0
-0.

-2.
m8

-1.0
FREQUENCY = 6.000GHz

14652-608
S (1,1) = 0.557 / 67.867
IMPEDANCE = 38.743 + j57.921 FREQ (0.0000Hz TO 6.000GHz)

Figure 124. ORx2 Series Equivalent Differential Port Impedance

ORx2 PORT PEDZ

200 22
R PEDZ
L OR C PE 20
180 X STATUS
18
160
16
140
14

L OR C PE
X STATUS
120
R PEDZ

12

100 10
m7 m6
FREQUENCY = 2.625GHz 8
80 L OR C PE = 0.627

m6 6
60 FREQUENCY = 2.625GHz
R PEDZ = 84.789 4
40 m7 2

20 0
0 1 2 3 4 5 6
FREQUENCY (GHz)
14652-208

NOTES
1. X STATUS: 0 = CAPACITANCE IN pF, 1 = INDUCTANCE IN nH.

Figure 125. ORx2 Parallel Equivalent Differential Port Impedance

Rev. B | Page 241 of 360

UG-992 AD9371/AD9375 System Development User Guide
m1 SnRxA PORT IMPEDANCE: SEDZ
FREQUENCY = 1.000GHz
S (1,1) = 0.780 / –27.213

1.0
IMPEDANCE = 88.599 – j161.308
m8

2.0
0.5
m2
FREQUENCY = 2.000GHz
S (1,1) = 0.759 / –61.540
IMPEDANCE = 24.861 – j78.254 S(1,1)
0.2
m5 5.0
m3
FREQUENCY = 3.000GHz 10
S (1,1) = 0.725 / –105.613
IMPEDANCE = 12.388 – j36.444 20

0.5

1.0

2.0

5.0

10
20
m4 -20
FREQUENCY = 4.000GHz
S (1,1) = 0.708 / –156.710 m4 -10
IMPEDANCE = 8.885 – j9.992 m1
-0.2 -5.0

m5
FREQUENCY = 5.000GHz m2
S (1,1) = 0.738 / 153.199 m3
IMPEDANCE = 7.963 + j11.626

0
-0.

-2.
m8

-1.0
FREQUENCY = 6.000GHz

14652-609
S (1,1) = 0.810 / 108.858
IMPEDANCE = 7.884 + j35.167 FREQ (0.0000Hz TO 6.000GHz)

Figure 126. SnRxA Series Equivalent Differential Port Impedance

SnRxA PORT PEDZ

450 2.6
R PEDZ
L OR C PE 2.4
400 X STATUS
2.2
350 2.0
1.8
300
1.6
L OR C PE
X STATUS
R PEDZ

250 m7 1.4
FREQUENCY = 2.625GHz
L OR C PE = 1.120 m7
200 1.2
1.0
150
m6 0.8

100 m6 0.6
FREQUENCY = 2.625GHz
R PEDZ = 175.185 0.4
50
0.2
0 0
0 1 2 3 4 5 6
FREQUENCY (GHz)
14652-209

NOTES
1. X STATUS: 0 = CAPACITANCE IN pF, 1 = INDUCTANCE IN nH.

Figure 127. SnRxA Parallel Equivalent Differential Port Impedance

Rev. B | Page 242 of 360

AD9371/AD9375 System Development User Guide UG-992
m1 SnRxB PORT IMPEDANCE: SEDZ
FREQUENCY = 1.000GHz
S (1,1) = 0.765 / –32.891

1.0
IMPEDANCE = 68.973 – j138.312
m5

2.0
0.5
m2 m4
FREQUENCY = 2.000GHz m8
S (1,1) = 0.694 / –80.448
IMPEDANCE = 20.740 – j54.681

0.2 5.0
m3
FREQUENCY = 3.000GHz S(1,1) 10
S (1,1) = 0.618 / –156.731
IMPEDANCE = 12.285 – j9.697 20

0.5

1.0

2.0

5.0

10
20
m4 -20
FREQUENCY = 4.000GHz m3
S (1,1) = 0.699 / –123.575
-10
IMPEDANCE = 11.300 – j25.750 m1
-0.2 -5.0

m5
FREQUENCY = 5.000GHz
S (1,1) = 0.812 / 73.164 m2
IMPEDANCE = 14.365 + j65.355

0
-0.

-2.
m8

-1.0
FREQUENCY = 6.000GHz

14652-610
S (1,1) = 0.883 / 40.428
IMPEDANCE = 25.369 + j131.501 FREQ (0.0000Hz TO 6.000GHz)

Figure 128. SnRxB Series Equivalent Differential Port Impedance

SnRxB PORT PEDZ

800 5.5
m7
FREQUENCY = 2.625GHz R PEDZ
L OR C PE = 1.860 L OR C PE 5.0
700 X STATUS
m6 4.5
FREQUENCY = 2.625GHz
600 R PEDZ = 56.797 4.0

500 3.5

L OR C PE
X STATUS
m7
R PEDZ

3.0
400
2.5
300 2.0

1.5
200
1.0
100 m6
0.5

0 0
0 1 2 3 4 5 6
FREQUENCY (GHz)
14652-210

NOTES
1. X STATUS: 0 = CAPACITANCE IN pF, 1 = INDUCTANCE IN nH.

Figure 129. SnRxB Parallel Equivalent Differential Port Impedance

Rev. B | Page 243 of 360

UG-992 AD9371/AD9375 System Development User Guide
m1 SnRxC PORT IMPEDANCE: SEDZ
FREQUENCY = 1.000GHz
S (1,1) = 0.761 / –34.020

1.0
IMPEDANCE = 66.154 – j134.156
m5
m4

2.0
0.5
m2
FREQUENCY = 2.000GHz
S (1,1) = 0.676 / –85.119 m8
IMPEDANCE = 20.217 – j50.199

0.2 5.0
m3
FREQUENCY = 3.000GHz S(1,1) 10
S (1,1) = 0.605 / –170.565
IMPEDANCE = 12.384 – j3.875 20

0.5

1.0

2.0

5.0
m3

10
20
m4 -20
FREQUENCY = 4.000GHz
S (1,1) = 0.725 / –108.201 -10
IMPEDANCE = 11.988 + j34.810
-0.2 m1 -5.0

m5
FREQUENCY = 5.000GHz
S (1,1) = 0.838 / 61.263 m2
IMPEDANCE = 16.650 + j81.954

0
-0.

-2.
m8

-1.0
FREQUENCY = 6.000GHz

14652-611
S (1,1) = 0.899 / 30.972
IMPEDANCE = 35.803 + j173.625 FREQ (0.0000Hz TO 6.000GHz)

Figure 130. SnRxC Series Equivalent Differential Port Impedance (X STATUS Transitions from 0 to 1 at 3.1 GHz)

SnRxC PORT PEDZ

900 120
m7
FREQUENCY = 2.625GHz R PEDZ
800 L OR C PE = 2.057 L OR C PE
X STATUS 100
m6
700 FREQUENCY = 2.625GHz
R PEDZ = 40.827

600 80

L OR C PE
X STATUS
500
R PEDZ

60
400

300 40
m7

200
20
100 m6

0 0
0 1 2 3 4 5 6
FREQUENCY (GHz)
14652-211

NOTES
1. X STATUS: 0 = CAPACITANCE IN pF, 1 = INDUCTANCE IN nH.

Figure 131. SnRxC Parallel Equivalent Differential Port Impedance (X STATUS Transitions from 0 to 1 at 3.1 GHz)

Rev. B | Page 244 of 360

AD9371/AD9375 System Development User Guide UG-992
TRANSMITTER BIAS AND PORT INTERFACE RF Interface Options
This section explains the dc biasing of the transmitter (Tx) Figure 134 shows the recommended RF transmitter interface. It
outputs and how to interface to each Tx port. The transmitters features a center tapped balun and offers the lowest component
operate over a wide range of frequencies. The Tx outputs are dc count of all of the options.
biased to a 1.8 V supply voltage using either RF chokes (wire
wound inductors) or a transformer center tap connection. At
full output power, each differential output side draws approximately Tx1/Tx2
100 mA of dc bias current. For a differential Tx port application, 1.8V
Tx1 OR Tx2
the total Tx current consumption is approximately 400 mA. OUTPUT STAGE
CB
Careful design of the dc bias network is required to ensure
Tx1/Tx2
optimal RF performance levels. When designing the dc bias

14652-214
network, select components with low dc resistance (RDCR) to
minimize the voltage drop across the series parasitic resistance
Figure 134. Recommended RF Transmitter Interface (Center Tapped Balun)
element with either of the suggested dc bias schemes shown in
1.8V
Figure 132 and Figure 133. The RDCR resistors indicate the parasitic
elements. As the impedance of the parasitics increase, the voltage CB
LC LC
drop (ΔV) across the parasitic element increases, causing the
transmitter RF performance (that is, PO, 1dB, PO, MAX, and so forth)
Tx1/Tx2 CC
to degrade. Select a high enough choke inductance (LC) relative
1.8V
to the load impedance to avoid degrading the output power (see Tx1 OR Tx2
OUTPUT STAGE
Figure 132).
1.8V
The recommended dc bias network is shown in Figure 133. This Tx1/Tx2 CC

14652-215
network has fewer parasitics and fewer total components.
VDC = 1.8V
Figure 135. RF Transmitter Interface (RF Chokes Bias Differential Tx Output Lines
CB with Additional Coupling Capacitors Creating a Transmission Line Balun)
LC LC
1.8V
+ +
RDCR ∆V ∆V RDCR
Tx1/Tx2 – – CB
LC LC
I BIAS =
Tx1 OR Tx2 VBIAS = 1.8 – ∆V ~100mA
OUTPUT STAGE
VBIAS = 1.8 – ∆V
Tx1/Tx2
Tx1/Tx2 IBIAS = 1.8V
͠ 100mA Tx1 OR Tx2
14652-212

OUTPUT STAGE
1.8V
Tx1/Tx2
Figure 132. RF DC Bias Configuration: Parasitic Losses Due to Wire Wound Chokes

14652-216
IBIAS = Figure 136. RF Transmitter Interface (RF Chokes Bias Differential Tx Output
Tx1/Tx2 ~100mA – ∆V + Lines and Connect to Transformer, No Additional Capacitors)
VDC = 1.8V RDCR 1.8V
Tx1 OR Tx2 V BIAS = 1.8 – ∆V
OUTPUT STAGE
V BIAS = 1.8 – ∆V CB CB
RDCR
LC LC
Tx1/Tx2 IBIAS = – ∆V +
~100mA
14652-213

Tx1/Tx2 CC
1.8V
Figure 133. RF DC Bias Configuration: Parasitic Losses Due to Center Tapped Tx1 OR Tx2 DRIVER
OUTPUT STAGE AMPLIFIER
Transformers
1.8V
Figure 134 through Figure 137 identify four basic differential Tx1/Tx2 CC
14652-217

transmitter output configurations. Impedance matching

networks (balun single-ended ports) are likely to be required to
achieve optimum device performance from the device. In Figure 137. RF Transmitter Interface (RF Chokes Bias the Differential Output
Lines That Are AC-Coupled Into the Input of a Driver Amplifier)
addition, the transmitter outputs must be ac-coupled in most
applications due to the dc bias voltage applied to the differential
output lines of the transmitter.

Rev. B | Page 245 of 360

UG-992 AD9371/AD9375 System Development User Guide
If a Tx balun is selected that requires a set of external dc bias From the empirical data, the preferred transmitter output
chokes, careful planning is required. It is necessary to find the differential load impedance is 50 Ω. Note the following:
optimum compromise between the choke physical size, choke
• The reference plane is the transmitter output evaluation
dc resistance (RDCR), and the balun low frequency insertion loss.
board ball pads.
In commercially available dc bias chokes, resistance decreases as
• The fundamental power (POUT) is inversely proportional to
size increases. However, as choke inductance increases, resistance
the real portion of the load impedance.
increases. Therefore, it is undesirable to use physically small
• The output third-order intercept point (POIP3) is inversely
chokes with high inductance because they exhibit the greatest
proportional to the real portion of the load impedance.
resistance. For example, the voltage drop of 500 nH on a 0603
• The POIP3 is higher for capacitive loads compared to
package size choke at 100 mA is roughly 50 mV.
inductive loads. Therefore, if matching errors persist
Table 168. Sample Wire Wound DC Bias Choke Resistance vs. throughout the design, it is preferable to err to the side of
Inductance (0603 and 1206 Package Sizes) capacitive rather than inductive to avoid voltage peaking
Resistance (Ω) effects.
Inductance (nH) Size 0603 Size 1206 • The optimum transmitter differential output load
100 0.10 0.08 impedance is subject to change.
200 0.15 0.10 One negative issue associated with the load-pull style matching
300 0.16 0.12 is that the transmitter port, S11, may degrade compared to the
400 0.28 0.14 small signal matching technique. However, sometimes it is not
500 0.45 0.15 possible to make a small signal style match, which is the case
600 0.52 0.20 when the transmitter output impedance of the packaged device
is capacitive. A conjugate match provides an inductive residual
Transmitter Impedance Matching Network Design reactance; this is potentially harmful to device output third-
Methodology order intercept (IP3) and harmonic distortion perspectives.
The transmitter differential output port is viewed as a medium
GENERAL RECEIVER PATH INTERFACE
signal device. Therefore, impedance matching is based on load-
pull style matching techniques as opposed to a small signal The device has three types of receivers. These include two main
design used on the receivers, which is a similar methodology to receive pathways (Rx1 and Rx2), two observation receivers
power amplifier impedance matching. The goal is to provide a (ORx1 and ORx2), and three sniffer receivers (SnRxA, SnRxB,
transmitter output differential load impedance that represents the and SnRxC). The Rx path can support up to 100 MHz bandwidth,
best compromise between the maximum output power delivered the ORx path can support up to 250 MHz bandwidth, and the
(POUT) and the highest possible third-order linearity (POIP3). SnRx path can support up to 20 MHz bandwidth. The ORx and
Rx channels are designed for differential use only. The SnRx
Load-pull is a general term that defines the power delivered into path supports both differential and single-ended usage, but
a specific load impedance. Typically, this term is applied to differential configurations are recommended.
systems where, at a given load impedance, the power delivered
is limited by either the dc power supply voltage or the maximum The receivers support a wide range of operation frequencies. In
current through the device. If enough sample points are taken, the case of the Rx and ORx channels, the differential signals
contours of delivered power (or other performance parameters interface to an integrated mixer. The mixer input pins have a dc
such as POIP3) can be plotted on the Smith chart vs. load bias of ~0.7 V and may need to be ac-coupled depending on the
impedance and frequency. common-mode voltage level of the external circuit.

Load-pull style matching is straightforward. Determine the For the SnRx channel, the input pins interface directly to an
frequency of interest and provide the load impedance that integrated low noise amplifier (LNA). The LNA input pins have
represents the desired compromise between the output power a dc bias of ~0.6 V. These inputs may need to be ac-coupled,
and linearity. The focus is on developing the preferred load depending on the common-mode voltage of the external circuit.
impedance at the Tx output ball pads. A quick contrast between To achieve best noise figure and even-order distortion (IP2)
load-pull and small signal matching is instructive and follows: performance, use the SnRx ports in differential mode.

• Load-pull: design the matching network for the preferred

load impedance at the transmitter output pads.
• Small signal: design the matching network for the
maximum power transfer based on the transducer gain.

Rev. B | Page 246 of 360

AD9371/AD9375 System Development User Guide UG-992
Important considerations for the receiver port interface are as
Rx1_INN
follows: RECEIVER
INPUT
 The device being interfaced to the transceiver. Options for Rx1_INP STAGE
(MIXER OR LNA)

14652-220
this consideration include, but are not limited to, filters,
baluns transmit/receive switches, external LNAs, and
Figure 140. Differential Receiver Interface Using a Transformer, All Receiver Inputs
external power amplifiers (PAs). It is important to
determine if the interfaced device presents a short to Rx1_INN
ground at dc. RECEIVER
 Rx and ORx maximum input power is 23 dBm (peak). The INPUT
STAGE
Rx1_INP (MIXER OR LNA)
SnRx maximum safe input power is 2 dBm (peak).

14652-221
 Rx and ORx optimum dc bias voltage is 0.7 VBIAS to ground.
The SnRx optimum dc bias voltage is 0.6 VBIAS to ground. Figure 141. Differential Receiver Interface Using a Transmission Line Balun,
All Receiver Inputs
 Board design: reference planes, transmission lines,
impedance matching, including careful attention to low Given wide RF bandwidth applications, surface-mount device
noise layout techniques, placement of transmission lines, (SMD) balun devices function well. Decent loss and differential
and accurate impedance matching are essential for optimal balance are available in relatively small (0603, 0805) packages.
performance. For receiver applications, the transmission line balun referenced
Single-Ended and Differential Receiver Input Interface in Figure 141 may be configured in multiple ways. Most
Circuits configurations are based on a Marchand planer design
Figure 138 through Figure 141 show possible single-ended and derivative like the one shown in Figure 142.
differential receiver port interface circuits. The options presented in 6
Figure 138 and Figure 139 are valid only for the SnRx channels in
1
single-ended mode. The options in Figure 140 and Figure 141
are valid for all receiver inputs operating in differential mode,
though only the Rx1 signal names are indicated. Differential 2
inputs with impedance matching may be necessary to obtain
data sheet performance levels.
Cc
SnRx1_INN
3 4 5
LNA 1: SINGLE-ENDED PORT
SnRx1_INP
2: GROUND OR BIAS
OPEN, SHORT, 3: BALANCED PORT 1
14652-218

14652-222
OTHER BAND/PATH 4: BALANCED PORT 2
5: PACKAGE GROUND
6: NO CONNECT
Figure 138. Single-Ended Input Interface Circuit, SnRx Only, Negative Side of
Differential Input Figure 142. Marchand Planer Balun Schematic

The termination applied to the balun, Pin 2 (ground or bias),

OPEN, SHORT,
SnRx1_INN may be implemented in at least two ways. For applications
OTHER BAND/PATH where a dc short to ground (through the balun) is tolerated at
LNA
Cc
SnRx1_INP
the differential ports, connecting the Balun Pin 2 pad to ground
14652-219

is the best approach. However, if the application does not allow

a short to ground, termination of Balun Pin 2 with a decoupling
Figure 139. Single-Ended Input Interface Circuit, SnRx Only, Positive Side of capacitor creates a simultaneous dc open and RF short. The
Differential Input
decoupling capacitor value may be tuned to set the RF bandwidth
low frequency corner.
If the impedance matching network component count or layout
size is a critical parameter, a good choice is to terminate Balun
Pin 2 with a decoupling capacitor.

Rev. B | Page 247 of 360

UG-992 AD9371/AD9375 System Development User Guide
General Receiver Impedance Matching Network Design For single-ended impedance matching, the PI topology is the
Methodology most flexible option. Referring to Figure 143, the S1P7, S1P8,
The device application determines the best receiver input port and S1P9 blocks form the PI shape. It is possible to reduce this
impedance matching methodology. The recommendations network to an L topology by eliminating one of the shunt
within this section are general-purpose only. components (S1P7 or S1P9).
Low Noise Matching Network Design For differential side impedance matching, the network may be
implemented as a T network (see Figure 143) or a dc block PI
If noise figure is a critical parameter in the application, low loss
network (see Figure 143). Realizing that the single-ended T
impedance matching between the receiver ports and the rest of
shape is formed by S1P2, S1P4, and S1P5, the differential T is
the system is required.
formed by inclusion of the S1P3 and S1P6 blocks. The
A low loss generic impedance matching topology is defined in differential T is horizontally symmetrical.
Figure 143. Because this topology is generic, it may be simplified by
Similarly, the components S1P1, S1P2, and S1P4 form a single-
removing unused SMD component pads to save board layout
ended PI network. The differential PI network is formed by the
area. The receiver input ports exhibit a dc bias voltage to
inclusion of the S1P3 blocks. The addition of the S1P5 and S1P6
ground. Avoid a dc short to ground on the input pins.
blocks complete the topology to form a dc block PI differential
Note that in Figure 143, the single-ended match is a Π topology. impedance matching network.
The differential side shows a differential T network in the small box
Both the T and dc block PI impedance matching topologies can
on the left and a dc block PI network in the large box on the right.
be reduced to L networks, if desired. The L network may enable
Given a three port device, such as a balun, both single-ended the widest possible impedance matching with the lowest
impedance matching and differential impedance matching number of SMD matching components.
may be required to obtain the lowest possible system power
A summary of the differential T and dc blocked differential PI
transmission loss. Implementation of an impedance matching
topology is listed in Table 169.
network on only one side rarely results in optimum small signal
power transfer. If the three port device does not exhibit a dc short from each
differential side to ground, the dc block PI topology may be
In terms of design methodology, optimum impedance matching
simplified to a standard differential PI topology (removing
network performance is not guaranteed by monitoring only
components S1P5 and S1P6). This change results in reduced
S11, the single-ended port parameter. Baluns and filters exhibit
SMD component count (four) and reduced board layout area.
dissipative loss. When the dissipative loss is severe, it prevents
the S11 single-ended side measurement from detecting Note that many devices within the system such as baluns, filters,
differential side impedance matching issues. or switches heavily influence the optimum impedance matching
topology. It is best to simulate the impedance matching options
and then implement the best overall solution.

DIFFERENTIAL MATCH

SINGLE-ENDED MATCH
S1P_EQN S1P_EQN
d S1P2
S1P_EQN S1P_EQN S1P5
BALUN S1P1 S1P4
S1P_EQN c
S1P8
S1P_EQN S1P_EQN BALUN 3PORT
CMP1
S1P9 S1P7
S1P_EQN S1P_EQN
S1P3 S1P6
14652-223

Figure 143. Generic Single-Ended to Differential Matching Topology

Table 169. Topology Advantage/Disadvantage Summary

Topology Advantage Disadvantage
Differential T Lower SMD component count (5) Impedance matching bandwidth may be up to 5%
smaller than dc blocked differential PI topology
DC Blocked Differential PI Relatively wide impedance matching bandwidth and Higher SMD component count (6)
impedance matching topology implementation flexibility

Rev. B | Page 248 of 360

AD9371/AD9375 System Development User Guide UG-992
Simplified Matching Design IMPEDANCE MATCHING NETWORK
For applications that use an external low noise amplifier (LNA) Impedance matching networks are required to achieve the
before the input receiver ports, the device noise figure may not be performance levels that are noted in the data sheet. This section
very important. An external LNA allows a simplified impedance provides example topologies and components used on the
matching topology to potentially achieve wider RF bandwidth. evaluation boards.
From an RF bandwidth viewpoint, the limiting factor becomes The S parameter models of the devices, board, balun, and SMD
the three-port device. In certain cases, RF bandwidths components are required to build an accurate system level
approaching 1.5 GHz are possible. Figure 144 illustrates the simulation. The board layout model may be obtained from an
simplified schematic. electromagnetic momentum simulator. The balun and SMD
The impedance matching network in Figure 144 adds some component models may be obtained from the balun and SMD
insertion loss to the channel. However, in applications that vendors or built from empirical data.
utilize an external LNA before the receiver input ports, the loss The impedance matching networks provided in this section
associated with this simple impedance matching network may have not been evaluated in terms of mean time to failure
not be significant to system performance. When this network is (MTTF) in high volume production. Consult with component
implemented, the noise figure of the device is expected to vendors for long-term reliability concerns. Additionally, consult
degrade somewhat with respect to an application that utilizes a with balun vendors to determine appropriate conditions for dc
low loss impedance matching methodology. However, careful biasing.
LNA selection mitigates such differences in overall system noise
figure. The impedance matching networks and the component
designators in the following diagrams are specific to the
BALUN/FILTER ADRV9371-N/PCBZ evaluation board. The board revision is
C
C1 indicated on the silkscreen under the RadioVerse™ logo.
d
L R RECEIVER
BALUN
L1 R1 The schematics show three elements in parallel; however, only
c
S1P_EQN one set of SMD component pads are placed on the board. For
S1P1 BALUN 3 PORT example, R201, L201, and C201 in Figure 145 have only one set
CMP2
14652-224

C of SMD pads for one SMD component. The schematic shows

C2
that in a generic port impedance matching network, the shunt
Figure 144. Simplified Impedance Matching Network or series elements may be a resistor, inductor, or a capacitor.
Note the following regarding the proposed topology in Figure 144: Figure 145 through Figure 149 show the schematic blocks for
the Rx1, Rx2, SnRxA, ORx1, and ORx2 channels, respectively.
 The R1 SMD component sets the real portion of the
impedance set by the balun or filter. In the transmitter (Tx) matching networks shown in Figure 150
 L1 resonates with the receiver input port capacitance, and Figure 151, the C307, L307, L308, and C308 components
for Tx1 (see Figure 150) and the C315, L315, L316, and C316
which results in the highest possible RF bandwidth.
for components for Tx2 (see Figure 151) form dc bias feeds into
 C1 and C2 are dc block capacitors. Depending on
the differential port of the transmitter. For baluns that do not
balun/filter selection, these SMD components may be
supply dc to the differential side of the balun, this is an example
replaced with 0 Ω resistors (that is, if the differential output
of an external feed topology that can be used to supply proper
lines do not exhibit a dc short to ground).
voltage to the Tx output. For the matching networks listed in
 The shunt SMD device (S1P1) on the single-ended port of
Table 175 and Table 176, these components are all DNI.
the balun/filter is intended to resonate with either the
inductance or capacitance seen at the balun/filter input
port. This component may not be necessary for particular
applications.

Rev. B | Page 249 of 360

UG-992 AD9371/AD9375 System Development User Guide
L205

R205 RX1+

C205
L201 T200
J200 3
R202 BAL_OUT1
R201 1
UNBAL_IN L204 C204 L207 C207
6 4
C201 C245 BAL_OUT2
5 2 L206

R206
L200 C200 L202 C202 C203 R203 RX1–
C206

14652-225
Figure 145. Rx1 Generic Matching Network Topology from the ADRV9371-N/PCBZ Evaluation Board
L214

R214 RX2+

C214
L209 T201
J201 3
BAL_OUT1
R209 R204
1
UNBAL_IN L213 L216 C216
6 C213
C241 4
C209 BAL_OUT2
5 2 L215

R215
L208 C208 L211 C211 C212 R212
RX2–
C215

14652-226
Figure 146. Rx2 Generic Matching Network Topology from the ADRV9371-N/PCBZ Evaluation Board
L222

R222 SNRXA+

C222
L218 T202
J202 3
BAL_OUT1
R218 R207
1
UNBAL_IN L221 L224 C224
6 C221
C242 4
C218 BAL_OUT2
5 2 L223

R223
L217 C217 L219 C219 C220 R220
SNRXA-
C223

14652-227

Figure 147. SnRxA Generic Matching Network Topology from ADRV9371-N/PCBZ Evaluation Board

Rev. B | Page 250 of 360

AD9371/AD9375 System Development User Guide UG-992
L231

R231 ORX1+

C231
L226 T203
J203 3
BAL_OUT1
R226 R208
1
UNBAL_IN L229 C229 L232 C232
6 4
C226 C243 BAL_OUT2
5 2 L230

R230
L225 C225 L227 C227 C228 R228
ORX1–
C230

14652-228
Figure 148. ORx1 Generic Matching Network Topology from the ADRV9371-N/PCBZ Evaluation Board

L239

R239 ORX2+

C239
L234 T204
J204 3
BAL_OUT1
R234 R210
1
UNBAL_IN L237 L240 C240
6 C237
C244 4
C234 BAL_OUT2
5 2 L238

R238
L233 C233 L235 C235 C236 R236
ORX2–
C238

14652-229
Figure 149. ORx2 Generic Matching Network Topology from the ADRV9371-N/PCBZ Evaluation Board

C307
VOUT4_1V8

L307
C309

TX1+ R309

L301
T305
3 J305
BAL_1 R303 R301
1
L311 L303 C303 UNBAL
C311
6 C305 C301
BAL_2
4
2 5
L305
TX1– R310
L323 C323 L324 C324
C310
L340
VOUT4_1V8
L308

C308 C320 C321 C322

VOUT4_1V8
14652-230

Figure 150. Tx1 Generic Matching Network Topology from ADRV9371-N/PCBZ Evaluation Board

Rev. B | Page 251 of 360

UG-992 AD9371/AD9375 System Development User Guide
C315
VOUT4_1V8

L315
C317

TX2+ R317

L302
T306
3 J306
BAL_1 R304 R302
1
L319 L304 C304 UNBAL
C319
6 C306 C302
BAL_2
4
2 5

R318 L305
TX2–
L328 C328 L329 C329
C318
L341
VOUT4_1V8
L316

C316 C325 C326 C327

VOUT4_1V8

14652-231
Figure 151. Tx2 Generic Matching Network Topology from ADRV9371-N/PCBZ Evaluation Board

Rev. B | Page 252 of 360

AD9371/AD9375 System Development User Guide UG-992
Selected Balun and Component Values The Suffix column in Table 170 through Table 176 indicates the
Table 170 through Table 176 show the selected balun and reference used to describe each matching network frequency
component values used in theADRV9371-N/PCBZ evaluation band. Note that circuit values for the SnRxB and SnRxC inputs
board for four matching network sets. DNI stands for do not are not included here because the ADRV9371-N/PCBZ
install (leave open). Component tolerances are also indicated. evaluation board only provides one sniffer receiver input.
Note that all tolerances are at ±5%, unless noted in parentheses.
Tolerance notations are either in percent (%) or units.

Table 170. Main Receiver Rx1

Component Location on PCB (All Tolerances at ±5% Unless Noted)
C201, C205, C206,
Frequency Suffix C200, L201, C202, C245, C203, C204, L205, L206, C207,
Band (MHz) (G) L200 R201 L202 R202 R203 L204 R205 R206 L207 T200
300 to 1000 −0.7 DNI 10 pF 27 nH 220 pF 180 pF 1.0 pF 9.1 nH 9.1 nH 0.6 pF Anaren
(±1%) (±3%) (±0.1 pF) (±3%) (±3%) (±0.1 pF) B0310J50100AHF
1800 to 2800 −2.6 10 nH 0Ω DNI 0Ω 0Ω 0.5 pF 100 pF 100 pF 3.9 nH Anaren
(±0.1 pF) BD0826J50200AHF
3300 to 3800 −3.5 DNI 0Ω 0.2 pF 0Ω 0Ω 0.3 pF 10 pF 10 pF 0.4 pF Johanson
(±0.1 pF) (±0.1 pF) (±0.1 pF) 3700BL15B050
5300 to 5900 −5.5 0.3 pF 1.2 nH DNI 0Ω 0Ω DNI 0.4 pF 0.4 pF 5.1 nH Johanson
(±0.1 pF) (±0.1 nH) (±0.1 pF) (±0.1 pF) 5400BL15B200

Table 171. Main Receiver Rx2

Component Location on PCB (All Tolerances at ±5% Unless Noted)
C209, C214, C215,
Frequency Suffix C208, L209, C211, C241, C212, C213, L214, L215, C216,
Band (MHz) (G) L208 R209 L211 R204 R212 L213 R214 R215 L216 T201
300 to 1000 −0.7 DNI 10 pF 27 nH 220 pF 180 pF 1.0 pF 9.1 nH 9.1 nH 0.6 pF Anaren
(±1%) (±3%) (±0.1 pF) (±3%) (±3%) (±0.1 pF) B0310J50100AHF
1800 to 2800 −2.6 10 nH 0Ω DNI 0Ω 0Ω 0.5 pF 100 pF 100 pF 3.9 nH Anaren
(±0.1 pF) BD0826J50200AHF
3300 to 3800 −3.5 DNI 0Ω 0.2 pF 0Ω 0Ω 0.3 pF 10 pF 10 pF 0.4 pF Johanson
(±0.1 pF) (±0.1 pF) (±0.1 pF) 3700BL15B050
5300 to 5900 −5.5 0.3 pF 1.2 nH DNI 0Ω 0Ω DNI 0.4 pF 0.4 pF 5.1 nH Johanson
(±0.1 pF) (±0.1 nH) (±0.1 pF) (±0.1 μF) 5400BL15B200

Table 172. Observation Receiver ORx1

Component Location on PCB (All Tolerances at ±5% Unless Noted)
C226, C230, C231,
Frequency Suffix C225, L226, C227, C243, C228, C229, L230, L231, C232,
Band (MHz) (G) L225 R226 L227 R208 R228 L229 R230 R231 L232 T203
300 to 1000 −0.7 DNI 15 pF 33 nH 220 pF 180 pF 1.0 pF 8.2 nH 8.2 nH 0.4 pF Anaren
(±2%) (±3%) (±0.1 pF) (±3%) (±3%) (±0.1 pF) B0310J50100AHF
1800 to 2800 −2.6 27 nH 5.6 pF DNI 0Ω 0Ω 6.2 nH 6.0 pF 6.0 pF 1.0 pF Anaren
(±0.1 pF) (±0.1 pF) (±0.1 pF) (±0.1 pF) B0322J5050AHF
3300 to 3800 −3.5 DNI 0Ω DNI 0Ω 0Ω DNI 2.0 pF 2.0 pF 7.5 nH Johanson
(±0.1 pF) (±0.1 pF) (±0.1 nH) 3700BL15B200
5300 to 5900 −5.5 10 nH 100 pF 4.7 nH 0Ω 0Ω DNI 0.6 pF 0.6 pF 1.5 nH Johanson
(±0.1 nH) (±3%) (±0.1 pF) (±0.1 pF) 5400BL15B200

Rev. B | Page 253 of 360

UG-992 AD9371/AD9375 System Development User Guide
Table 173. Observation Receiver ORx2
Component Location on PCB (All Tolerances at ±5% Unless Noted)
C234, C238, C239,
Frequency Suffix C233, L234, C235, C244, C236, C237, L238, L239, C240,
Band (MHz) (G) L233 R234 L235 R210 R236 L237 R238 R239 L240 T204
300 to 1000 −0.7 DNI 15 pF 33 nH 220 pF 180 pF 1.0 pF 8.2 nH 8.2 nH 0.4 pF Anaren
(±2%) (±3%) (±0.1 pF) (±3%) (±3%) (±0.1 pF) B0310J50100AHF
1800 to 2800 −2.6 27 nH 5.6 pF DNI 0Ω 0Ω 6.2 nH 6.0 pF 6.0 pF 1.0 pF Anaren
(±0.1 pF) (±0.1 pF) (±0.1 pF) B0322J5050AHF
3300 to 3800 −3.5 DNI 0Ω DNI 0Ω 0Ω DNI 2.0 pF 2.0 pF 7.5 nH Johanson
(±0.1 pF) (±0.1 pF) (±0.1 nH) 3700BL15B200
5300 to 5900 −5.5 DNI 100 pF 2.7 nH 0Ω 0Ω DNI 0.6 pF 0.6 pF 1.8 nH Johanson
(±0.1 nH) (±0.1 pF) (±0.1 pF) 5400BL15B200

Table 174. Sniffer Receiver SnRxA

Component Location on PCB (All Tolerances at ±5% Unless Noted)
C218, C222, C223,
Frequency Suffix C217, L218, C219, C242, C220, C221, L222, L223, C224,
Band (MHz) (G) L217 R218 L219 R207 R220 L221 R222 R223 L224 T202
300 to 1000 −0.7 75 nH 15 nH 0.7 pF 220 pF 180 pF 0.9 pF 27 nH 27 nH DNI Anaren
(±3%) (±3%) (±0.1 pF) (±0.1 pF) (±3%) (±3%) B0310J50100AHF
1800 to 2800 −2.6 0.5 pF 22 pF 3.0 nH 0Ω 100 pF DNI 5.6 nH 5.6 nH 0.6 pF Johanson
(±0.1 pF) (±0.1 pF) (±0.1 nH) (±0.05 pF) 2450BL15B200E
3300 to 3800 −3.5 100 nH 1.8 pF 100 nH 0Ω 8 pF DNI 2.5 nH 2.5 nH 4.7 nH Johanson
(±0.1 pF) (±0.1 nH) (±0.1 nH) (±0.1 nH) 3700BL15B050
5300 to 5900 −5.5 0.5 pF 1.0 nH 0.3 pF 0Ω 0Ω 3.6 nH 0.2 pF 0.2 pF 8.2 nH Johanson
(±0.05 pF) (±0.1 nH) (±0.1 pF) (±0.1 nH) (±0.1 pF) (±0.1 pF) 5400BL15B200

Table 175. Transmitter Tx1

Component Location on PCB (All Tolerances at ±5% Unless Noted)
C301,
Frequency Suffix C311, C309, C310, C303, C305, C323, L301, C324,
Band (MHz) (G) L311 R309, R310 L303 L305 R303 L323 R301 L324 L340 C322 T305
300 to 1000 −0.7 DNI 0Ω 0Ω DNI 39 nH 0 Ω 1.0 pF 5.6 nH DNI 27 nH 180 pF Anaren
(±0.1 pF) (±3%) B0322J5050AHF
1800 to 2800 −2.6 1 pF 0Ω 0Ω DNI DNI 0Ω DNI 1.5 nH 0.75 pF 27 nH 0.1 μF Mini-Circuits
(±0.1 pF) (±0.1 pF) NCS1-292+
3300 to 3800 −3.5 0.6 pF 0Ω 0Ω DNI DNI 0Ω DNI 0Ω DNI 27 nH 0.1 μF Johanson
(±0.1 pF) 3700BL15B100
5300 to 5900 −5.5 5.1 nH 1.5 nH 1.5 nH 5.1 nH DNI 0Ω DNI 0Ω DNI 0Ω 1.2 pF TDK HHM1752A2
(±3%) (±1 nH) (±1 nH) (±3%) (±0.1 pF)

Table 176. Transmitter Tx2

Component Location on PCB (All Tolerances at ±5% Unless Noted)
C302,
Frequency Suffix C319, C317, C318, C304, C306, C328, L302, C329,
Band (MHz) (G) L319 R317, R318 L304 L306 R304 L328 R302 L329 L341 C327 T306
300 to 1000 −0.7 DNI 0Ω 0Ω DNI 39 nH 0 Ω 1.0 pF 5.6 nH DNI 27 nH 180 pF Anaren
(±0.1 pF) (±3%) B0322J5050AHF
1800 to 2800 −2.6 1 pF 0Ω 0Ω DNI DNI 0Ω DNI 1.5 nH 0.75 pF 27 nH 0.1 μF Mini-Circuits
(±0.1 pF) (±0.1 pF) NCS1-292+
3300 to 3800 −3.5 0.6 pF 0Ω 0Ω DNI DNI 0Ω DNI 0Ω DNI 27 nH 0.1 μF Johanson
(±0.1 pF) 3700BL15B100
5300 to 5900 −5.5 5.1 nH 1.5 nH 1.5 nH 5.1 nH DNI 0Ω DNI 0Ω DNI 0Ω 1.2 pF TDK HHM1752A2
(±3%) (±1 nH) (±1 nH) (±3%) (±0.1 pF)

Rev. B | Page 254 of 360

AD9371/AD9375 System Development User Guide UG-992
Mykonos Tx1 and Tx2 Port Impedance
Tx1/Tx2 PORT PEDZ
The equivalent parallel equivalent differential impedances and
350 30
the corresponding S11 values for the Tx1 and Tx2 output ports
are shown in Table 177 for a series of operating frequencies 300 R PEDZ
L OR C PE 25
ranging from 1.000 GHz to 6.000 GHz. The relationship between X STATUS m7
FREQUENCY = 5.000GHz
these points is illustrated in the Smith chart in Figure 152 and 250 L OR C PE = 3.328
20
the frequency response plot in Figure 153.

L OR C PE
X STATUS
200

R PEDZ
Tx1/Tx2 PORT IMPEDANCE: SEDZ
15
1.0

150

10

2.0
0.5

m4 100
m5
m7 5
m3 50

0.2 5.0
m8 0 0
10
0 1 2 3 4 5 6
20 FREQUENCY (GHz)

14652-233
m2
0.5

1.0

2.0

5.0

NOTES
10
20

1. X STATUS: 0 = CAPACITANCE IN pF, 1 = INDUCTANCE IN nH.

m1 -20
-10
Figure 153. PEDZ vs. Frequency, Tx1 and Tx2 Ports

-0.2 -5.0 BOARD LAYOUT DESIGN RECOMMENDATIONS

S(1,1)
Circuit board layout is a critical part of the impedance matching
process. Design trade-offs are often required to balance material
5

cost, performance, and bandwidth. Refer to the RF and JESD204B

0
-0.

-2.

Transmission Line Layout section for details on how to design

-1.0

14652-232

the circuit board traces that make matching circuits more

FREQ (0.0000Hz TO 6.000GHz)
accurate.
Figure 152. SEDZ vs. Frequency, Tx1 and Tx2 Port Impedance

Table 177. PEDZ vs. Frequency

Parameter M1 M2 M3 M4 M5 M8
Frequency (GHz) 1.000 2.000 3.000 4.000 5.000 6.000
S11 +0.205/−126.314 0.391/175.770 0.548/128.665 0.657/88.433 0.719/52.629 0.742/18.124
Impedance (Ω) 37.272 – j12.862 21.298 + j1.492 17.610 + j21.560 30.335 + j47.066 37.502 + j88.705 160.279 + j164.892

Rev. B | Page 255 of 360

UG-992 AD9371/AD9375 System Development User Guide

PRINTED CIRCUIT BOARD LAYOUT GUIDELINES

Because of the integration complexity of the device and its high PCB MATERIAL AND STACK UP SELECTION
pin count, careful printed circuit board (PCB) layout is important Figure 154 shows the PCB stackup used for the evaluation
to optimize performance. This section provides a checklist of board. The board employs 14 layers to achieve proper routing
issues to look for and guidelines on how to optimize the PCB to and isolation to best demonstrate all device functionality. The
mitigate performance issues. The goal of this document is to dielectric material used on the top and the bottom layers is
help achieve the best possible performance from the device while Rogers 4003C with a thickness of 7.50 mil. The remaining
reducing board layout effort. It is assumed that the reader is an dielectric layers are FR4-370 HR. The board design uses the
experienced analog/RF engineer who understands RF PCB layout Rogers laminate for the top and the bottom layers for its low loss
and has an understanding of RF transmission lines as well as tangent at high frequencies. The ground planes under the Rogers
low noise analog design techniques. The ADRV9371-N/PCBZ laminate (Layer 2 and Layer 13) are the reference planes for the
evaluation board is used as the reference for this information, transmission lines routed on the outer surfaces. These layers are
but all guidelines are best practices that can be applied to other solid copper planes under the RF traces with no discontinuities.
reference designs. This document provides guidelines for system Layer 2 and Layer 13 are crucial to maintaining the RF signal
designers and discusses the following issues relative to layout integrity. Layer 3 and Layer 12 are used to route power supply
and power management. domains. To keep the RF area isolated from the fast transients of
• PCB material and stack up selection the digital area, the JESD204B interface lines are routed on
• Fanout and layout guidelines relative to trace widths and Layer 5 and Layer 10. Those layers have an impedance control set
spacing to 100 Ω differential for the differential JESD204B pairs. The
• Component placement and routing guidelines remaining digital signals are routed on inner Layer 7 and Layer 8.
• RF and JESD204B transmission line layout Table 178 describes details of the trace impedance controls used
• Isolation techniques used on the ADRV9371-N/PCBZ on different layers.
evaluation board RF traces on the outer layers must be a controlled impedance to
• Power management considerations—how to maximize achieve the best performance. These outer layers use 1.5 oz
performance without using linear low dropout (LDO) copper so that the RF traces are less prone to pealing. One ounce
regulators copper is used for all the inner layers in this board. All ground
• Instructions for what to do with unused pins planes on this board are full copper floods with no splits except
for vias, throughhole components, and isolation structures.
Note that it is important to route ground planes entirely to the
edge of the PCB under the SMA connectors to maintain signal
launch integrity. Power planes can be pulled back from the
board edge to decrease the risk of developing shorts with the
ground plane.

Rev. B | Page 256 of 360

AD9371/AD9375 System Development User Guide UG-992

14652-154
Figure 154. ADRV9371-N/PCBZ Evaluation Board Stackup

Table 178. ADRV9371-N/PCBZ Evaluation Board Trace Impedance Table

Impedance Tolerance (Ω) Reference Line Width (mil) Spacing (mil) Finished Finished Impedance
Require- Pos Neg Line Spacing Simulation
Layer ment (Ω) (+) (−) Type Upper Lower Designed Plotted Designed Coplaner Width (mil) (mil) (Ω)
I1comp 50 5.0 5.0 Surface I2pp 15.50 15.00 20.00 14.50 50.2
single-ended
coplaner
I1comp 100 10.0 10.0 Surface I2pp 8.00 9.00 6.00 8.50 5.50 100.1
microstrip
differential
I1comp 50 5.0 5.0 Coated I2pp 15.50 13.75 20.00 13.25 49.7
single-ended
coplaner
I1comp 100 10.0 10.0 Coated I2pp 8.00 7.50 6.00 7.00 7.00 100.6
microstrip
differential
I5mix 50 5.0 5.0 Single-ended I6pp I4pp 4.50 4.50 4.00 50.9
I5mix 100 10.0 10.0 Differential I6pp I4pp 3.60 4.25 6.40 3.75 6.25 98.9
I7mix 50 5.0 5.0 Single-ended I8pp I6pp 4.50 4.75 4.25 48.2
I7mix 100 10.0 10.0 Differential I8pp I6pp 3.60 4.00 6.40 3.50 6.50 100.6
I8mix 50 5.0 5.0 Single-ended I7pp I9pp 4.50 4.75 4.25 48.2
I8mix 100 10.0 10.0 Differential I7pp I9pp 3.60 4.00 6.40 3.50 6.50 100.6
I10mix 50 5.0 5.0 Single-ended I11pp I9pp 4.50 5.00 4.50 49.8
I10mix 100 10.0 10.0 Differential I11pp I9pp 3.60 4.50 6.40 4.00 6.00 100.8
I14sold 50 5.0 5.0 Surface I13pp 15.50 15.00 20.00 14.50 50.2
single-ended
coplaner
I14sold 100 10.0 10.0 Surface I13pp 8.00 9.00 6.00 8.50 5.50 100.1
microstrip
differential
I14sold 50 5.0 5.0 Coated I13pp 15.50 13.75 20.00 13.25 49.7
single-ended
coplaner
I14sold 100 10.0 10.0 Coated I13pp 8.00 7.50 6.00 7.00 7.00 100.6
microstrip
differential

Rev. B | Page 257 of 360

UG-992 AD9371/AD9375 System Development User Guide
FANOUT AND TRACE SPACE GUIDELINES The JESD204B interface signals must be treated differently than
The device uses a 12 mm × 12 mm, 196-ball CSP_BGA other general-purpose digital signals. These traces are routed on
package. The recommended BGA land pad size is 14 mils. The two signal layers that utilizes impedance control (Layer 5 and
pitch between the pins is 0.8 mm, which makes it impractical to Layer 10 on the ADRV9371-N/PCBZ board). The spacing between
route all signals from the balls away from the device on a single the BGA pads and each escape via is 22 mil. When the signal is
PCB layer. RF pins have been placed on the outer edges of the connected to the inner layers, a 3.6 mil trace (50 Ω) is used to
package, making it easier to route the critical signals on a single route the JESD204B signal to the FMC connector. Figure 155
PCB layer. Each digital signal is routed from the BGA pad using shows the fanout scheme of the ADRV9371-N/PCBZ evaluation
a 10 mil trace at a 45° angle to begin the route. The trace is card. Another option not used on this evaluation board is the
connected to a fanout via that is centered between four BGA via in the pad technique. Putting the fanout vias directly inside
pads to maximize separation from each signal. The the ball pads increases separation distance from other signals
recommended via size is 6 mil with a 12 mil keepout. The compared to placing the vias between four balls. This routing
signals are then routed to internal layers where they are routed approach was not used on the ADRV9371-N/PCBZ PCB
to other parts of the system. because of added cost; however, it can be used if there are no
issues with manufacturing capabilities.

4.5 mil TRACE

10 mil PIN
ESCAPE TRACE 4.5 mil TRACE

22 mil
LAND TO Ø 6 mil PAD/
VIA SPACING 12 mil KEEP OUT

Ø 14 mil BGA
LAND SIZE

14652-155

Figure 155. ADRV9371-N/PCBZ Trace Fanout Scheme

Rev. B | Page 258 of 360

AD9371/AD9375 System Development User Guide UG-992
COMPONENT PLACEMENT AND ROUTING Every effort must be made to optimize the component selection
PRIORITIES and placement to avoid performance degradation. Refer to the
RF Port Interface for more information.
The device requires few external components to function;
however, those that are needed require careful placement and RF signal path isolation is critical to achieving the level of
routing to optimize performance. The following sections isolation specified in the data sheet. More details on proper
provide a priority order and checklist for properly placing and isolation are provided in the Isolation Techniques Used on the
routing critical signals and components as well as those whose ADRV9371-N/PCBZ Evaluation section.
location and isolation are not as critical. For each RF Tx output, install a 10 μF capacitor near the balun
Signals with Highest Routing Priority power supply pin connected to the VDDA_1P8 supply. If baluns
RF lines and JESD204B interface signals are the signals that are with no dc supply connection are used, power must be supplied
most critical and must be routed with highest priority. Figure 156 to the Tx outputs using RF chokes connected between the
shows the general directions in which each of the signals must be VDDA_1P8 supply and each Tx output. In both cases, the 10 μF
routed so that they can be properly isolated from noisy signals. capacitor acts as a reservoir for Tx supply current. The Tx Balun
DC Supply Options section describes the Tx output power
RF baluns are typically used to interface single-ended signals to supply configuration in more detail.
the differential receiver and transmitter ports. These baluns and
their associated matching circuits affect overall RF performance.

1 2 3 4 5 6 7 8 9 10 11 12 13 14

VSSA ORX2+ ORX2– VSSA RX2+ RX2– VSSA VSSA RX1+ RX1– VSSA ORX1+ ORX1– VSSA
A

VDDA_RXRF VSSA VSSA VSSA VSSA VSSA RX_EXTLO– RX_EXTLO+ VSSA VSSA VSSA VSSA VSSA VDDA_3P3
B

VSNRX_ VDDA_ VDDA_ VRX_

GPIO_3P3_0 GPIO_3P3_1 VSSA VDDA_RXLO VSSA VSSA AUXADC_1 AUXADC_2 GPIO_3P3_9 RBIAS
C VCO_LDO SNRXVCO RXVCO VCO_LDO

GPIO_3P3_3 SNRXC– SNRXB– SNRXA– GPIO_3P3_5 VSSA VSSA VSSA VSSA VDDA_1P8 AUXADC_3 GPIO_3P3_7 GPIO_3P3_8 GPIO_3P3_10
D

DEV_ DEV_
GPIO_3P3_4 SNRXC+ SNRXB+ SNRXA+ VDDA_BB VSSA VSSA VSSA TX_EXTLO– TX_EXTLO+ AUXADC_0 GPIO_3P3_6
E CLK_IN+ CLK_IN–

VDDA_ VTX_
GPIO_3P3_2 VDDA_RXTX VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VDDA_TXLO GPIO_3P3_11
F TXVCO VCO_LDO

VDDA_ VDDA_ VDDA_ VDDA_ VDDA_

VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA
G CALPLL CLKSYNTH SNRXSYNTH TXSYNTH RXSYNTH

TX2– VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA GPIO_12 GPIO_11 VSSA TX1+
H

GP_
TX2+ VSSA GPIO_18 RESET TEST GPIO_2 GPIO_1 SDIO SDO GPIO_13 GPIO_10 VSSA TX1–
J INTERRUPT

VSSA VSSA SYSREF_IN+ SYSREF_IN– GPIO_5 GPIO_4 GPIO_3 GPIO_0 SCLK CSB GPIO_14 GPIO_9 VSSA VSSA
K

L VSSA VSSA SYNCINB1– SYNCINB1+ GPIO_6 GPIO_7 VSSD VDIG VDIG VSSD GPIO_15 GPIO_8 VSSA VSSA

VCLK_ RX1_ TX1_ RX2_ TX2_

VSSA SYNCINB0– SYNCINB0+ VSSA GPIO_17 GPIO_16 VDD_IF SYNCOUTB0+ SYNCOUTB0–
M VCO_LDO ENABLE ENABLE ENABLE ENABLE

VDDA_CLK VSSA SERDOUT3– SERDOUT3+ SERDOUT2– SERDOUT2+ VSSA VDDA_SER VDDA_DES SERDIN2– SERDIN2+ SERDIN3– SERDIN3+ VSSA
N

JESD_VTT_
VSSA VSSA VSSA SERDOUT1– SERDOUT1+ SERDOUT0– SERDOUT0+ VDDA_SER VSSA SERDIN0– SERDIN0+ SERDIN1– SERDIN1+
P DES
14652-156

Figure 156. RF Input/Output, DEV_CLK, and JESD204B Signal Routing Guidelines

Rev. B | Page 259 of 360

UG-992 AD9371/AD9375 System Development User Guide
Connect the external clock inputs to the DEV_CLK_IN+ (E7) It is recommended that the JESD204B interface be routed at the
and DEV_CLK_IN− (E8) balls using ac coupling capacitors. beginning of the PCB design and with the same priority as RF
Use a 100 Ω termination at the input to the device. Figure 157 signals. The JESD204B Trace Routing Recommendations
illustrates the recommended placement for these components section outlines recommendations for JESD204B interface
near the DEV_CLK_IN± balls. Traces must be shielded by routing. Ensure that appropriate isolation between these
surrounding ground with vias staggered along the edge of the differential pairs are provided. The Isolation Between JESD204B
differential trace pair. This arrangement creates a shielded Lines section provides guidelines for optimizing isolation.
channel that prevents the reference clock from any interference The RX_EXTLO− (B7), RX_EXTLO+ (B8), TX_EXTLO−
from other signals. Refer to the ADRV9371-N/PCBZ evaluation (E11), TX_EXTLO+ (E12) balls are internally dc biased. If an
card layout for exact details. external local oscillator (LO) is used, connect it via ac coupling
capacitors.

TERMINATION
RESISTOR

AC COUPLING
CAPACITORS

BGA BALLS

14652-157

Figure 157. DEV_CLK Signal Routing Recommendations

Rev. B | Page 260 of 360

AD9371/AD9375 System Development User Guide UG-992
Signals with Second Routing Priority Each power supply requires a 0.1 μF bypass capacitor near the
Power supply quality has direct impact on overall system ball at a minimum. Place the ground side of the bypass capacitor
performance. To achieve optimal performance, follow the so that ground currents flow away from other power balls and
recommendations regarding power supply routing. The their bypass capacitors.
following recommendations outline how different power For those domains shown in Figure 159 that are powered
domains can be routed and which supplies can be tied to the through a ferrite bead (FB), place the ferrite beads near the
same supply but separated by a ferrite bead or 0 Ω resistor. supply pins. It is recommended to space the ferrite beads to ensure
A general recommendation for power supply routing is to their electric fields do not influence each other. Figure 160
follow the star methodology in which each power domain is shows an example of how to place the ferrite beads, reservoir
deliver by a separate trace from the source supply. Ensure that capacitors, and decoupling capacitors. The ferrite bead must
each power trace is surrounded by ground. Figure 158 shows an supply a trace with a reservoir capacitor connected to it. It is
example of such traces routed on the evaluation card on Layer 12. recommended to shield this trace with ground and to provide
Each trace is separated from any other signal by ground plane power to the input power ball. Place a 100 nF capacitor near the
fill and vias. This approach is essential to providing necessary power supply ball with the ground side of the bypass capacitor
isolation between power domains. placed so that ground currents flow away from other power balls
and their bypass capacitors.

14652-158

Figure 158. Layout Example of Power Supply Connections Routed with Ground Shielding (Layer 12)

Rev. B | Page 261 of 360

UG-992 AD9371/AD9375 System Development User Guide
1 2 3 4 5 6 7 8 9 10 11 12 13 14

VSSA ORX2+ ORX2– VSSA RX2+ RX2– VSSA VSSA RX1+ RX1– VSSA ORX1+ ORX1– VSSA
A

VDDA_RXRF VSSA VSSA VSSA VSSA VSSA RX_EXTLO– RX_EXTLO+ VSSA VSSA VSSA VSSA VSSA VDDA_3P3
B

VSNRX_ VDDA_ VDDA_ VRX_

GPIO_3P3_0 GPIO_3P3_1 VSSA VDDA_RXLO VSSA VSSA AUXADC_1 AUXADC_2 GPIO_3P3_9 RBIAS
C VCO_LDO SNRXVCO RXVCO VCO_LDO

GPIO_3P3_3 SNRXC– SNRXB– SNRXA– GPIO_3P3_5 VSSA VSSA VSSA VSSA VDDA_1P8 AUXADC_3 GPIO_3P3_7 GPIO_3P3_8 GPIO_3P3_10
D

DEV_ DEV_
GPIO_3P3_4 SNRXC+ SNRXB+ SNRXA+ VDDA_BB VSSA VSSA VSSA TX_EXTLO– TX_EXTLO+ AUXADC_0 GPIO_3P3_6
E CLK_IN+ CLK_IN–

VDDA_ VTX_
GPIO_3P3_2 VDDA_RXTX VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VDDA_TXLO GPIO_3P3_11
F TXVCO VCO_LDO

VDDA_ VDDA_ VDDA_ VDDA_ VDDA_

VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA
G CALPLL CLKSYNTH SNRXSYNTH TXSYNTH RXSYNTH

TX2– VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA GPIO_12 GPIO_11 VSSA TX1+
H

GP_
TX2+ VSSA GPIO_18 RESET TEST GPIO_2 GPIO_1 SDIO SDO GPIO_13 GPIO_10 VSSA TX1–
J INTERRUPT

VSSA VSSA SYSREF_IN+ SYSREF_IN– GPIO_5 GPIO_4 GPIO_3 GPIO_0 SCLK CSB GPIO_14 GPIO_9 VSSA VSSA
K

VSSA VSSA SYNCINB1– SYNCINB1+ GPIO_6 GPIO_7 VSSD VDIG VDIG VSSD GPIO_15 GPIO_8 VSSA VSSA
L

VCLK_ RX1_ TX1_ RX2_ TX2_

VSSA SYNCINB0– SYNCINB0+ VSSA GPIO_17 GPIO_16 VDD_IF SYNCOUTB0+ SYNCOUTB0–
M VCO_LDO ENABLE ENABLE ENABLE ENABLE

VDDA_CLK VSSA SERDOUT3– SERDOUT3+ SERDOUT2– SERDOUT2+ VSSA VDDA_SER VDDA_DES SERDIN2– SERDIN2+ SERDIN3– SERDIN3+ VSSA
N

JESD_VTT_
VSSA VSSA VSSA SERDOUT1– SERDOUT1+ SERDOUT0– SERDOUT0+ VDDA_SER VSSA SERDIN0– SERDIN0+ SERDIN1– SERDIN1+
P DES

TRACE
WIDE TRACE HIGH CURRENT
TRACE WITH FERRITE BEAD TO ANALOG PLANE

14652-159
TRACE TO ANALOG PLANE

Figure 159. Power Supply Domains with Connection Guidelines

RESERVOIR
CAPACITOR FERRITE BEAD

VIA TO TOP DECOUPLING

LAYER CAPACITOR

SHIELDING
FROM OTHER
14652-160

SUPPLIES

Figure 160. Placement Example for Ferrite Bead, Reservoir Capacitor, and Decoupling Capacitor on the ADRV9371-N/PCBZ Evaluation Card

Rev. B | Page 262 of 360

AD9371/AD9375 System Development User Guide UG-992
Signals with Lowest Routing Priority  Connect the RESET pin (J4) to VDD_IF with a 10 kΩ
The following guidelines govern those signals that are the lowest resistor for normal operation. The device can be reset by
signal routing priority. These signals can be routed after all critical driving this pin low.
signal routes have been completed so that they do not interfere  When routing digital signals from Row H and under, it is
with the critical component placement and routing. The signals important to route them away from the analog section (Row A
shown in Figure 161 can be routed with the lowest priority. through Row G). It is recommended that digital signal routing
not pass before the dashed line highlighted in Figure 161.
 Ceramic 1 μF bypass capacitors must be placed at the
 The GPIO_3P3_N signals can be routed using inner PCB
VRX_VCO_LDO, VTX_VCO_LDO, VSNRX_VCO_LDO
layers. Those signals control analog blocks such as power
and VCLK_VCO_LDO balls. Place these capacitors as
amplifiers or low noise amplifiers. They can also be used as
close as possible to the device with the ground side of the
general-purpose analog outputs when muxed to the
bypass capacitor placed so that ground currents flow away
internal auxiliary DAC outputs. To prevent noise coupling
from other power balls and their bypass capacitors if at all
into those signals, route them away from the digital region
possible.
(before the dashed line highlighted in Figure 161).
 Connect a 14.3 kΩ resistor to RBIAS pin (C14). This
 The AUXADC_N signals can be routed using inner PCB
resistor must have a 1% tolerance or better.
layers. Those signals sense analog voltage levels such as
 The device has support for JTAG boundary scan, and the
temperature sensors. To prevent noise coupling into those
TEST ball is used to access the function. Connect the TEST
signals, route them away from the digital region (before the
ball (J6) to ground for normal operation. Refer to the data
dashed line highlighted in Figure 161).
sheet for JTAG boundary scan information.
1 2 3 4 5 6 7 8 9 10 11 12 13 14

VSSA ORX2+ ORX2– VSSA RX2+ RX2– VSSA VSSA RX1+ RX1– VSSA ORX1+ ORX1– VSSA
A

VDDA_RXRF VSSA VSSA VSSA VSSA VSSA RX_EXTLO– RX_EXTLO+ VSSA VSSA VSSA VSSA VSSA VDDA_3P3
B

VSNRX_ VDDA_ VDDA_ VRX_

C GPIO_3P3_0 GPIO_3P3_1 VCO_LDO SNRXVCO VSSA VDDA_RXLO RXVCO VCO_LDO VSSA VSSA AUXADC_1 AUXADC_2 GPIO_3P3_9 RBIAS 14.3kΩ
CAPACITOR

GPIO_3P3_3 SNRXC– SNRXB– SNRXA– GPIO_3P3_5 VSSA VSSA VSSA VSSA VDDA_1P8 AUXADC_3 GPIO_3P3_7 GPIO_3P3_8 GPIO_3P3_10
D

DEV_ DEV_
GPIO_3P3_4 SNRXC+ SNRXB+ SNRXA+ VDDA_BB VSSA VSSA VSSA TX_EXTLO– TX_EXTLO+ AUXADC_0 GPIO_3P3_6
E CLK_IN+ CLK_IN–

VDDA_ VTX_
GPIO_3P3_2 VDDA_RXTX VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VDDA_TXLO GPIO_3P3_11
F TXVCO VCO_LDO

VDDA_ VDDA_ VDDA_ VDDA_ VDDA_

VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA
G CALPLL CLKSYNTH SNRXSYNTH TXSYNTH RXSYNTH

H TX2– VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA GPIO_12 GPIO_11 VSSA TX1+

GP_
TX2+ VSSA GPIO_18 RESET TEST GPIO_2 GPIO_1 SDIO SDO GPIO_13 GPIO_10 VSSA TX1–
J INTERRUPT

VSSA VSSA SYSREF_IN+ SYSREF_IN– GPIO_5 GPIO_4 GPIO_3 GPIO_0 SCLK CSB GPIO_14 GPIO_9 VSSA VSSA
K

VSSA VSSA SYNCINB1– SYNCINB1+ GPIO_6 GPIO_7 VSSD VDIG VDIG VSSD GPIO_15 GPIO_8 VSSA VSSA
L

VCLK_ RX1_ TX1_ RX2_ TX2_

VSSA SYNCINB0– SYNCINB0+ VSSA GPIO_17 GPIO_16 VDD_IF SYNCOUTB0+ SYNCOUTB0–
M VCO_LDO ENABLE ENABLE ENABLE ENABLE

VDDA_CLK VSSA SERDOUT3– SERDOUT3+ SERDOUT2– SERDOUT2+ VSSA VDDA_SER VDDA_DES SERDIN2– SERDIN2+ SERDIN3– SERDIN3+ VSSA
N

JESD_VTT_
VSSA VSSA VSSA SERDOUT1– SERDOUT1+ SERDOUT0– SERDOUT0+ VDDA_SER VSSA SERDIN0– SERDIN0+ SERDIN1– SERDIN1+
P DES
14651-161

1µF CAPACITOR
ALL DIGITAL GPIO SIGNALS ROUTED BELOW THE DASHED LINE

Figure 161. Auxiliary ADC, SPI, Analog GPIO/Auxiliary DAC, and Digital GPIO Signal Routing Guidelines

Rev. B | Page 263 of 360

UG-992 AD9371/AD9375 System Development User Guide
RF AND JESD204B TRANSMISSION LINE LAYOUT Differential Line Design Equations
Board layout design involves compromise. The recommendations Some high level differential line design equations follow; these
within this user guide are intended for wide RF bandwidth are valid for reasonably low loss transmission lines.
applications. For narrow RF bandwidth applications, the board line Odd Impedance Mode
impedance parameters within this document may not be optimal.
Odd impedance mode is represented by the variable, ZODD.
The following list provides general suggestions for board
design: ZODD = ZDIFF ÷ 2 (33)
where ZDIFF is 100 Ω for receivers and 50 Ω for trasmitters.
• Match the evaluation board design as close as possible to
the board design files available on the product page. Even Impedance Mode
• Be attentive to power distribution and power ground Even impedance is represented by the variable, ZEVEN.
return methodology.
ZEVEN = ZCM × 2 (34)
• Do not run high speed digital lines in close proximity to dc
power distribution routes or RF line routes. where:
• Use microstrip or coplanar waveguides (CPWG) for ZCM is the common-mode impedance from each pin to ground.
transmission lines. These structures do not require via Differential Mode Characteristic Impedance
structures that cause additional impedance discontinuities
Differential mode impedance is represented by the variable, Z0.
that vary across frequency. For ports such as the Sniffer
receivers, which do not have balls on the perimeter of the Z0 = √ZODDZEVEN (35)
BGA, a via structure such as stripline may be necessary. where:
ZEVEN is a function of line coupling. As the line coupling increases,
Design the RF line systems between the device ball pad reference
both ZEVEN and Z0 increase. Given the ball pad diameter of 17.7 mil,
plane and the balun/filter reference plane for a differential
0.45 mm, and the array pitch of 31.5 mil, 0.8 mm coupled,
impedance (ZDIFF) of 100 Ω for the receivers and 50 Ω for the
microstrip differential lines are the preferred design choice.
transmitters. This design is a compromise impedance with
respect to frequency and a good starting point for design. The Single-Ended Impedance
ZDIFF can be optimized to fit a narrower frequency range. It is Single-ended impedance is represented by the variable, ZSE.
desirable to design the lines for reasonable coupling (−10 dB to
−15 dB) to promote adequate electromagnetic interface (EMI) ZSE = (ZODD + ZEVEN) ÷ 2 (36)
suppression performance. Inductance per Unit Length
In most cases, the required board artwork stackup is different Inductance per unit length is represented by the variable, Lʹ.
than the ADRV9371-N/PCBZ evaluation board stackup.
Optimization of RF transmission lines specific to the desired Z0 εr
Lʹ = (37)
board environment is essential to the design and layout process. c
The ADRV9371-N/PCBZ evaluation board uses microstrip where:
lines for Rx, ORx and Tx RF traces. The SnRx signal is routed εr is the media relative dielectric constant.
using a combination of microstrip lines on the bottom of the c is the speed of light (1.1803 × 1013 mils/sec).
PCB and stripline traces on internal layers due to board Capacitance per Unit Length
complexity. In general, it is not recommended to use vias with
Capacitance per unit length is represented by the variable, Cʹ.
RF traces unless a direct line route is not possible.
Differential lines from the balun to the Rx, ORx, SnRx and Tx εr
Cʹ = (38)
balls must be as short as possible. It is also recommended that Z 0c
the length of the single-ended transmission lines be short to Alternative Characteristic Differential Impedance
minimize the effects of parasitic coupling.
The alternative characteristic differential impedance is
System designers can optimize RF performance with the proper
represented by the variable, Z0.
selection of balun, matching components, and ac coupling
capacitors. The external local oscillator (LO) traces and the L′
Z0 = (39)
DEV_CLK_IN traces may require matching components as well C′
to ensure optimal performance. For additional information on
Line Design Examples
matching network design see the RF Port Interface section.
The following sections provide examples of transmission line
design. These design examples frequently use Equation 33
through Equation 39 and electromagnetic simulation tools to
calculate the impedance parameters.
Rev. B | Page 264 of 360
AD9371/AD9375 System Development User Guide UG-992
Example 1: Microstrip Line System, Receiver Only, Example 3: Microstrip Line System, Transmitter Traces
ZDIFF = 100 Ω Only, ZDIFF = 50 Ω
The line system described by the parameters in Table 179 is a Generally, this is a good system for transmitter systems (see
well suited line system for the receiver system. The line coupling Table 181). The line coupling is adequate, and EMI issues are
is adequate and electromagnetic interface (EMI) issues are not not expected. These lines are wide relative to the transmitter
expected. board ball pads; they must be tapered down to create minimal
This design is not acceptable for a JESD204B application. The discontinuity between the lines and pads. Some amount of line
ZDIFF requirement is met, but the ZCM requirement of 25 Ω is not width tuning may be required to obtain an adequate broadband
met. This line system is only acceptable for receiver lines. system impedance.

Table 179. Example 1 Microstrip Parametric Calculated Results Table 181. Example 3 Microstrip Parametric Calculated Results
Parameter Value Parameter Value
εr (Rogers 4003C) 3.55 εr (Rogers 4003C) 3.55
Dissipation Loss Tangent (TanD) 0.0021 Dissipation Loss Tangent (TanD) 0.0021
Height 8.0 mil Height 8.0 mil
Width 8.5 mil Width 34.0 mil
Spacing 5.0 mil Spacing 4.0 mil
ZEVEN 85.1 Ω ZEVEN 35.2 Ω
ZODD 50.2 Ω ZODD 25.2 Ω
Z0 65.4 Ω Z0 29.8 Ω
Coupling −11.8 dB Coupling −15.6 dB
Inductance per Unit Length (L/UL) 10.44 pH/mil Inductance per Unit Length (L/UL) 4.76 pH/mil
Capacitance per Unit Length (C/UL) 2.44 fF/mil Capacitance per Unit Length (C/UL) 5.36 fF/mil
ZDIFF = 2 × ZODD 100.4 Ω ZDIFF = 2 × ZODD 50.4 Ω
ZCM = ZEVEN ÷ 2 42.6 Ω ZCM = ZEVEN ÷ 2 17.6 Ω

Example 2: Microstrip Line System, Receiver and Example 4: Microstrip Line System, Receiver and
JESD204B Traces, ZDIFF = 100 Ω JESD204B Traces, Typical Production PCB, ZDIFF = 100 Ω

From a line impedance perspective, this is a good system for This line design represents a typical production circuit board
both the receiver system and JESD204B system (see Table 180). scenario (see Table 182). The low stackup height represents a
However, the lines are weakly coupled. Exercise care during the challenge to generating a ZDIFF of 100 Ω. Generally, this is an
board layout phase to reduce EMI risk. adequate line for the receiver and JESD204B systems; however,
exercise care during board layout to minimize the line to ball
Another advantage of Example 2 over Example 1 is that the line pad discontinuities and potential EMI risk.
width is closer to the board ball diameter of 17.7 mil thereby
reducing discontinuities between the line and pad structures. Table 182. Example 4 Microstrip Parametric Calculated Results
Parameter Value
Table 180. Example 2 Microstrip Parametric Calculated Results
εr (Rogers 4003C) 3.55
Parameter Value
Dissipation Loss Tangent (TanD) 0.0021
εr (Rogers 4003C) 3.55 Height 8.0 mil
Dissipation Loss Tangent (TanD) 0.0021 Width 34.0 mil
Height 8.0 mil Spacing 4.0 mil
Width 15.0 mil ZEVEN 35.2 Ω
Spacing 30.0 mil ZODD 25.2 Ω
ZEVEN 54.3 Ω Z0 29.8 Ω
ZODD 50.2 Ω Coupling −15.6 dB
Z0 52.2 Ω Inductance per Unit Length (L/UL) 4.76 pH/mil
Coupling −27.9 dB Capacitance per Unit Length (C/UL) 5.36 fF/mil
Inductance per Unit Length (L/UL) 8.33 pH/mil ZDIFF = 2 × ZODD 50.4 Ω
Capacitance per Unit Length (C/UL) 3.06 fF/mil ZCM = ZEVEN ÷ 2 17.6 Ω
ZDIFF = 2 × ZODD 100.4 Ω
ZCM = ZEVEN ÷ 2 27.2 Ω

Rev. B | Page 265 of 360

UG-992 AD9371/AD9375 System Development User Guide
Example 5: Microstrip Line System, Transmitter Traces RF Line Design Summary
Only, ZDIFF = 100 Ω As evident in Example 1 through Example 5, the RF line design
Generally, this is a good line design for the transmitter system. is a compromise between many variables. Line impedance, line
The line coupling is marginal. Exercise care during board layout to line coupling, and physical size represent the parameters
to reduce the EMI risk. Note this example assumes FR4 for the subject to compromise.
circuit board material, so the dielectric constant is substantially Smallest physical size is in direct opposition to the ZCM of the
higher than the other examples. line, which is directly opposed to the line electromagnetic
Table 183. Example 5 Microstrip Parametric Calculated interface (EMI) performance. In addition, the interface between
the RF line width and the device ball pad diameter on the PCB
Parameter Value
represents a potential discontinuity. As the RF line width
εr (Rogers 4003C) 4.6
approaches the ball pad diameter, the risk associated with
Dissipation Loss Tangent (TanD) 0.025
potential interface discontinuity reduces.
Height 3.0 mil
Width 12.0 mil The circuit shown in Figure 162 shows the layout topology for
Spacing 4.0 mil the chosen receiver matching network. Note the location and
ZEVEN 30.8 Ω orientation of each component; placement is critical to achieve
ZODD 25.2 Ω expected performance. Similarly, the circuit in Figure 163 shows
Z0 27.9 Ω the layout topology used for the transmitter matching network
Coupling −19.9 dB (see the RF Port Interface section for circuit details).
Inductance per Unit Length (L/UL) 5.07 pH/mil
Capacitance per Unit Length 6.51 fF/mil
(C/UL)
ZDIFF = 2 × ZODD 50.4 Ω
ZCM = ZEVEN ÷ 2 15.4 Ω

OPTIONAL AC DIFFERENTIAL
COUPLING PI NETWORK
CAPACITOR

BALUN

SINGLE-ENDED
PI NETWORK
14652-162

Figure 162. Receiver Matching Network on ADRV9371-N/PCBZ Evaluation Board

Rev. B | Page 266 of 360

AD9371/AD9375 System Development User Guide UG-992

SINGLE-ENDED
PI NETWORK

OPTIONAL
AC COUPLING
CAPACITOR

BALUN

DIFFERENTIAL
PI NETWORK

DC POWER
DISTRIBUTION

14652-163

Figure 163. Transmitter Matching Network on ADRV9371-N/PCBZ Evaluation Board

Rev. B | Page 267 of 360

UG-992 AD9371/AD9375 System Development User Guide
Transmitter Bias Design Considerations
This section considers the dc biasing of the device transmitter
Tx1_OUTP/
(Tx) outputs and how to interface to each Tx port. At full Tx2_OUTP IBIAS = ~100mA – ∆V +
RDCR
output power, each differential output side draws approximately VBIAS = 1.8 – ∆V VDC = 1.8V
100 mA of dc bias current. The Tx outputs are dc biased to a Tx1 OR Tx2
OUTPUT STAGE
1.8 V supply voltage using either RF chokes (wire wound VBIAS = 1.8 – ∆V
CB
RDCR
inductors) or a transformer (balun) center tap connection.
Tx1_OUTN/ – ∆V +
Tx2_OUTN IBIAS = ~100mA
Careful design of the dc bias network is required to ensure

14652-165
optimal RF performance levels. When designing the dc bias
network, select components with low dc resistance (RDCR) to
Figure 165. ADRV9371-N/PCBZ DC Bias Configuration for the Transmitter
minimize the voltage drop across the series parasitic resistance Output Using a Center Tapped Transformer
element with either of the dc bias schemes suggested in
Figure 164 and Figure 165. The resistors (RDCR) indicate the The recommended dc bias network is the one using the center
parasitic elements. As the impedance of the parasitics increase, tap balun shown in Figure 165. This network has fewer
the voltage drop (ΔV) across the parasitic element increases parasitics and fewer total components.
which causes the transmitter RF performance to degrade. The The ADRV9371-N/PCBZ evaluation board provides flexibility
choke inductance (LC) must be selected high enough relative to to configure each Tx output to either work with a center tapped
the load impedance such that it does not degrade the output transformer (balun) or a set of two closely matched wire wounded
power. If chokes are used, they must be very well matched chokes. The center tapped transformer passes the bias voltage
(including PCB traces). Uneven matching of chokes design can directly to the transmitter outputs through each differential
cause unwanted emission of spikes at the Tx output. This input. This configuration offers the lowest component count.
emission can affect components connected to the Tx output.
In some cases, the desired balun does not provide a dc
VDC = 1.8V connection to the transmitter output lines. To support this
situation, the ADRV9371-N/PCBZ evaluation board provides
the placeholders for RF chokes tied to the VDDA_1P8 (1.8 V)
CB LC LC supply. It also provides the placeholders for ac coupling capacitors
to prevent creating a dc short through the balun to ground.

RDCR + + RDCR
Impedance matching networks on the balun single-ended port
∆V ∆V are usually required to achieve optimum performance. In
Tx1_OUTP/Tx2_OUTP – –
addition, ac coupling is often required on the single-ended side
IBIAS = ~100mA if the balun contains a dc path from one of the differential
VBIAS = 1.8 – ∆V
Tx1 OR Tx2 outputs transmitter to the single-ended port.
OUTPUT STAGE
VBIAS = 1.8 – ∆V Careful planning is required for the Tx balun selection. If a Tx
Tx1_OUTN/Tx2_OUTN IBIAS = ~100mA
balun is selected that requires a set of external dc bias chokes, it
is necessary to find the optimum compromise between the
choke physical size, choke dc resistance (RDCR), and the balun
14652-164

pass-band insertion loss. Refer to the RF Port Interface section

Figure 164. ADRV9371-N/PCBZ DC Bias Configuration for the Transmitter for more information on Tx output balun and RF choke
Output Using Wire Wound Chokes selection as well as matching circuit recommendations.

Rev. B | Page 268 of 360

AD9371/AD9375 System Development User Guide UG-992
Tx Balun DC Supply Options Figure 166 shows the power supply layout configuration used
Each transmitter requires approximately 200 mA supplied on the ADRV9371-N/PCBZ board to achieve the desired Tx to
through an external connection. The PCB layout of the Tx isolation performance. This image illustrates how a trade-off
ADRV9371-N/PCBZ allows use of external chokes to provide was used when a direct star connection was not possible. To
the 1.8 V power domain to the device outputs to allow users to improve isolation, one transmitter is fed from the power plane, and
try different baluns that may not have a dc center tap pin to the plane is continued until it can be connected to the other
supply the bias voltage to the transmitter outputs. transmitter. This process keeps the impedance for the second
transmitter feed as low as possible and separates the current
To reduce switching transients when attenuation settings change,
paths enough to avoid intermingling of supply currents.
it is recommended to power the balun dc feed directly by the
1.8 V plane. Design the geometry of the 1.8 V plane so that each An example of the balun feed supply designed to achieve the
balun or each pair of chokes is isolated from those of the other channel isolation in the evaluation board is shown in Figure 167
transmitter. If careful layout and isolation of the dc supply is not and Figure 168.
followed, it can adversely affect Tx to Tx isolation.

TX1 1.8V SUPPLY

TX2 1.8V SUPPLY

1.8V SUPPLY

14652-166
Figure 166. 1.8 V Tx Power Supply Routing on the ADRV9371-N/PCBZ Evaluation Board

Rev. B | Page 269 of 360

UG-992 AD9371/AD9375 System Development User Guide
SERIES MATCHING OPTIONAL RF
COMPONENTS ISOLATION INDUCTOR

1.8V POWER PLANE

CONNECTION

1.8V
RESERVOIR
CAPACITORS

14652-167
BALUN OPTIONAL RF CHOKE DECOUPLING CAPACITOR
(NEEDED FOR BALUNS (ORIENTATION IS IMPORTANT)
WITH ONLY ONE DC FEED)

Figure 167. Transmitter Power Supply for a Balun with a Center Tap

Rev. B | Page 270 of 360

AD9371/AD9375 System Development User Guide UG-992
TX DC POWER
FEED CHOKES

DECOUPLING
CAPACITORS

1.8V TRACE
CONNECTION FROM
THE PLANE

SERIES MATCHING
COMPONENTS

BALUN

SINGLE-ENDED
SERIES BLOCKING
ELEMENT

14652-168
Figure 168. Transmitter Power Supply Using RF Chokes

DC Balun Chokes
When a Tx balun that is able to conduct dc is used, use the The ADRV9371-N/PCBZ evaluation board provides flexibility
system shown in Figure 167. Place the decoupling capacitor to use a Tx balun that is not capable of conducting dc current.
near the Tx balun as close as possible to the dc feed pin of the In such a scenario, the user must install dc chokes as well as
balun. Its orientation must be perpendicular to the device so their decoupling capacitors as highlighted in Figure 168. Care
that the return current avoids a ground loop with the ground must be taken to match both chokes to avoid potential current
pins surrounding the Tx input. The evaluation board provides spikes. Differences in parameters between both chokes can
an option to install an RF isolation inductor, which can provide cause unwanted emission at Tx outputs. Note that, if the
extra isolation between the Tx1 and Tx2 balun supply feeds. A differential input to the balun can form a dc short to ground
10 μF capacitor and a 0.1 μF capacitor are helpful on the dc feed through the balun, the series matching components must be
pin to eliminate Tx spectrum spurs and dampen the transients. capacitors. If a short can form on the single-ended side, the
Note that when this supply approach is used, the series matching single-end series blocking element must be a capacitor.
components must be dc shorts. It is recommended to use 0 Ω if an
inductor is not needed to match the balun impedance to the Tx
output impedance.

Rev. B | Page 271 of 360

UG-992 AD9371/AD9375 System Development User Guide
JESD204B Trace Routing Recommendations Stripline vs. Microstrip
Routing the JESD204B data lines requires techniques similar to When routing the PCB layout for JESD204B data lines, the
routing differential RF traces. To ensure performance of this designer must decide to route the signals using stripline or
interface, keep the differential traces as short as possible by microstrip traces. There are positives and negatives for each that
placing the device as close as possible to the baseband processor must be carefully considered.
(BBP) and route the traces as directly as possible between the
 Stripline has less loss and emits less electromagnetic
devices. Using a PCB material with a low dielectric constant
interface (EMI) than microstrip lines, but stripline traces
(<4) to minimize loss is also strongly recommended. For
require the use of vias that can add complexity to the task
distances greater than 6 inches, it is recommended to use a
of controlling the impedance by adding line inductance.
premium PCB material such as Rogers 4003C.
 Microstrip is easier to implement if the component
Routing Recommendations placement and density allow for routing on the top layer,
Route the differential pairs on a single plane using a solid simplifying the task of controlling the impedance.
ground plane as a reference on the layers above and/or below If using the top layer of the PCB is problematic or the advantages of
these traces stripline are desirable, follow these recommendations:
All JESD204B lane traces must be impedance controlled to  Minimize the number of vias.
achieve 50 Ω to ground. It is recommended that the differential  Use blind vias wherever possible to eliminate via stub
pair be coplanar and loosely coupled (a typical configuration is effects, and use microvias to minimize via inductance.
5 mil trace width, 15 mil edge to edge spacing) with the trace
 If using standard vias, use maximum via length to
width maximized.
minimize the stub size. For example, on an 8-layer board,
It is recommended that trace widths match pin/ball widths as use Layer 7 for the stripline pair.
closely as possible while maintaining impedance control. Trace  For each via pair, place a pair of ground vias in close
widths of at least 8 mils using 1 oz. copper are recommended. It is proximity to them to minimize the impedance
recommended that coupling capacitor pad size match JESD204B discontinuity.
lane trace widths as closely as possible.  For the JESD204B lines, the recommendation is to route
Pad area for all connector and passive component choices must them on the top side of the board as a differential 100 Ω
be minimized as much as possible due to a capacitive plate pair (microstrip). In the case of the ADRV9371-N/PCBZ
effect that can lead to problems with signal integrity. evaluation board, the JESD204B differential signals are
routed on inner layers of the board (Layer 5 and Layer 10)
Reference planes for impedance controlled signals must not be
as differential 100 Ω pairs (stripline). To minimize potential
segmented or broken for the entire length of a trace.
coupling, these signals are placed on an inner layer using a
The DEV_CLK_IN and SYSREF signal traces must be impedance via embedded in the component footprint pad where the
controlled for Z0 = 50 Ω. ball connects to the PCB. AC coupling capacitors (100 nF)
on these signals are placed at the connector, away from the
chip, to minimize coupling. The JESD204B interface can
operate at frequencies up to 6.4 GHz. Care must be exercised
to maintain signal integrity from the chip to the connector.

Tx Tx
DIFF A DIFF B Tx DIFF A Tx DIFF B
14652-169

TIGHTLY COUPLED LOOSELY COUPLED

DIFFERENTIAL Tx LINES DIFFERENTIAL Tx LINES

Figure 169. JESD204B Differential Pair Routing Example

Rev. B | Page 272 of 360

AD9371/AD9375 System Development User Guide UG-992
ISOLATION TECHNIQUES USED ON THE Figure 170 shows the isolation structures used on the
ADRV9371-N/PCBZ EVALUATION BOARD ADRV9371-N/PCBZ evaluation card. These structures consist
of a combination of slots and square apertures. Both structures
The device was designed to provide extremely good channel
are present on every copper layer of the PCB stack. The advantage
isolation. Significant isolation challenges must be overcome
of using square apertures is that signals can be routed between
while designing the ADRV9371-N/PCBZ evaluation board. The
the openings without disturbing the isolation benefits that the
following isolation requirements were followed to accurately
array of apertures provides.
evaluate transceiver performance:
When utilizing the proposed isolating structures, it is important
 Tx to Tx: 80 dB out to 6 GHz
to place ground vias around the slots and apertures.
 Tx to Rx: 80 dB out to 6 GHz
 Rx to Rx: 60 dB out to 6 GHz
 ORx to ORx: 60 dB out to 6 GHz
To meet those goals with significant margin, isolation structures
were introduced.

ISOLATION STRUCTURES SQUARE APERATURE

RX1 RF PATH

SLOTS
TX1 RF PATH
RX2 RF PATH

TX2 RF PATH

14652-170
Figure 170. Isolation Structures on the ADRV9371-N/PCBZ Evaluation Board

Rev. B | Page 273 of 360

UG-992 AD9371/AD9375 System Development User Guide
The methodology used on the ADRV9371-N/PCBZ evaluation For Roger 4003C material, microstrip structure (and taking in
board is shown in Figure 171. When slots are used, place ground account air as an insulator), εr = 3.55.
vias at each end of the slots and along each side. When square For FR4-370 HR material, stripline structure, εr = 4.6.
apertures are used, place at least one single ground via adjacent
to each square. It is recommended that these vias be For example, the following:
throughhole vias connecting the top to the bottom layer and all  Maximum RF signals frequency is 6 GHz.
layers in between. The function of these vias is to steer return  For Rogers 4003C material (and taking in account air as an
current to the ground planes near the apertures. insulator), using microstrip structures, and εr = 3.55, the
It is recommended to use electromagnetic simulation software to minimum wavelength is approximately 26.5 mm.
develop accurate slot spacing and square aperture layout when To fulfill the 1/10 of a wavelength rule, square aperture spacing
designing a PCB for an AD9371 family transceiver. Ensure that must be at a distance of 2.65 mm or closer.
spacing between square apertures is not more than 1/10 of the
shortest wavelength supported.
The wavelength can be calculated using Equation 40.
300
wavelength(m)  (40)
frequency(MHz)  r
where εr is the dielectric constant of the isolator material.

14652-171

Figure 171. Current Steering Vias Placed Near Isolation Slots and Apertures

Rev. B | Page 274 of 360

AD9371/AD9375 System Development User Guide UG-992
Isolation Between JESD204B Lines For accurate spacing of JESD204B fencing vias, use layout
The JESD204B interface uses eight line pairs that can operate at simulation software. Use Equation 40 with the following
speeds of up to 6.4 GHz. Care must be taken when doing PCB outlined details:
layout to ensure those lines are routed following the rules  Maximum JESD204B signal frequency is around 6.4 GHz.
described in the JESD204B Trace Routing Recommendations  For FR4-370 HR material, stripline structure, and εr = 4.6,
section. In addition, use isolation techniques to prevent crosstalk the minimum wavelength is approximately 21.9 mm.
between different JESD204B lane pairs. A technique used on
the ADRV9371-N/PCBZ evaluation board uses via fencing. To fulfill the 1/10 wavelength spacing rule, use vias spaced at a
Figure 172 illustrates this technique. Ground vias placed around distance of 2.19 mm or closer.
each JESD204B pair provide isolation and decrease crosstalk.
Spacing between vias follows the rule provided in Equation 40.
JESD204B lines are routed on Layer 5 and Layer 10 so that they
utilizes stripline structures. The dielectric material used in the
inner layers of the ADRV9371-N/PCBZ evaluation board PCB
is FR4-370 HR.

2.16mm

2.16mm

14652-172
Figure 172. Via Fencing Shield Around JESD204B Lines (Layer 10 of the ADRV9371-N/PCBZ Shown)

Rev. B | Page 275 of 360

UG-992 AD9371/AD9375 System Development User Guide
UNUSED BALLS
In some end applications, the user may decide not to use all
available inputs or outputs. In these cases, ensure that unused
pins follow the recommendations outlined in Table 184.

Table 184. Recommendations for Unused Balls

Pin No. Type Mnemonic When Pins Are Not Used
A9, A10, A5, A6 I RX1+, RX1−, RX2+, RX2− Do not connect. When active, there is a 0.7 VBIAS. When disabled, the
internal protection diodes protect the inputs.
A12, A13, A2, A3 I ORX1+, ORX1−, ORX2+, ORX2− Do not connect. When active, there is a 0.7 VBIAS. When disabled, the
internal protection diodes protect the inputs.
D4, E4, D3, E3, D2, E2 I SNRXA−, SNRXA+, SNRXB−, Connect to GND with a 1 kΩ pull-down resistor or directly to GND.
SNRXB+, SNRXC−, SNRXC+ Note that when active there is a bias voltage on those inputs.
H14, J14, H1, J1 O TX1+, TX1−, TX2−, TX2+ Do not connect.
B7, B8 I/O RX_EXTLO−, RX_EXTLO+ Do not connect.
E11, E12 I/O TX_EXTLO−, TX_EXTLO+ Do not connect.
M5, M7, M6, M8 I RX1_ENABLE, RX2_ENABLE, Connect to GND with a 1 kΩ pull-down resistor or directly to GND.
TX1_ENABLE, TX2_ENABLE
E13, C11, C12, D11 I AUXADC_0, AUXADC_1, Connect to GND with a 1 kΩ pull-down resistor or directly to GND.
AUXADC_2, AUXADC_3
H11, H12, J3, J7, J8, I/O GPIO_0 to GPIO_18 Because these pins contain an input stage, the voltage on the pin
J11, J12, K5 to K8, must be controlled. They can be tied to ground through a 1 kΩ
K11, K12, L5, L6, L11, resistor (to safeguard against misconfiguration), or they can be left
L12, M10, M11 floating, programmed as outputs, and driven low.
C1, C2, C13, D1, D5, I/O GPIO_3P3_0 to GPIO_3P3_11 Because these pins contain an input stage, the voltage on the pin
D12, D13, D14, E1, must be controlled. They can be tied to ground through a 1 kΩ
E14, F1, F14 resistor (to safeguard against misconfiguration), or they can be left
floating, programmed as outputs, and driven low.
J5 O GP_INTERRUPT Do not connect.
J6 I TEST Connect to GND.
J10 O SDO In SPI, 3-wire mode, do not connect.
M3, M4, L3, L4 I SYNCINB0−, SYNCINB0+, Connect to GND with a 1 kΩ pull-down resistor or directly to GND.
SYNCINB1−, SYNCINB1+
M13, M14 O SYNCOUTB0+, SYNCOUTB0− Do not connect.
P11, P12, P13, P14, I SERDIN0−, SERDIN0+, SERDIN1−, Do not connect. These pins have a bias on them; therefore, they
N10, N11, N12, N13 SERDIN1+, SERDIN2−, SERDIN2+, must not be tied to power or GND.
SERDIN3−, SERDIN3+
P6, P7, P4, P5, N5, O SERDOUT0−, SERDOUT0+, Do not connect. These pins have a bias on them; therefore, they
N6, N3, N4 SERDOUT1−, SERDOUT1+, must not be tied to power or GND.
SERDOUT2−, SERDOUT2+,
SERDOUT3−, SERDOUT3+

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AD9371/AD9375 System Development User Guide UG-992

POWER MANAGEMENT CONSIDERATIONS

The device has six different power supply domains: POWER SUPPLY SEQUENCE
• 1.3 V is the main analog domain that powers the major The device requires a specific power-up sequence to avoid
part of the chip, which is divided into various 1.3 V undesired power-up currents. In the optimal power-up sequence,
domains, all with a tolerance of ±2.5%. the VDIG and the VDDA supplies (all 1.3 V domains) come up
• The JESD_VTT_DES and VDDA_SER supplies are 1.3 V. first and simultaneously. If they cannot be brought up
These can be powered from the main analog core voltage, simultaneously, the VDIG supply must come up first. It is
if desired, as long as appropriate isolation is used. It is recommended to bring up the VDDA_3P3, VDDA1P8,
suggested that for best performance the JESD_VTT_DES VDD_JESD_VTT, and VDDA_SER supplies after the 1P3
and VDDA_SER supplies come from a separate regulator supplies. The VDD_IF supply can be brought up at any time.
so that they can be varied from 1.3 V to 1.2 V to adhere to Note that no device damage occurs if this sequence is not
the JESD204B specification. Both require a tolerance of ±5%. observed; however, this can result in higher than expected
• The VDIG supply is the main digital power supply. It must power-up currents. It is also recommended to toggle the RESET
be kept separate from the main 1.3 V analog supply to signal after power has stabilized prior to configuration. The
minimize digital noise coupling into analog circuits. The power-down sequence is not critical. If a power-down sequence
tolerance for this supply is ±2.5%. is followed, the VDIG supply must be removed last to avoid any
• The VDD_IF supply is a separate power domain. The back biasing of the digital control lines.
nominal input voltage on the VDD_IF can range from POWER DISTRIBUTION FOR DIFFERENT POWER
1.8 V to 2.5 V. This voltage controls the voltage levels of the SUPPLY DOMAINS
digital interface (SPI and control signals). It has a tolerance
One key aspect to ensuring good PCB performance is careful low
of ±5%.
noise power management design. Table 185 lists the pin number,
• The VDDA_3P3 supply is a 3.3 V domain. This supply
the pin name, the recommended routing technique for that pin
provides a higher voltage rail for GPIO_3P3s, receiver
from the main 1.3 V analog supply (if applicable), and a brief
mixer switches, auxiliary DACs, and the auxiliary ADC;
description of the block it powers in the chip. When routing
therefore, it is required whether the GPIO_3P3s are used
power traces to the device, follow a star configuration where a
or not. It has a tolerance of ±5%.
separate trace from a common power plane is used to power
• The VDDA_1P8 supplies the Tx output section and is
each 1.3 V power supply pins.
applied to the balun center taps. In the scenario where
baluns do not have the dc feed capability, RF chokes can be The information listed in Table 185 shows which power supply
used. They must be connected from this supply to each Tx pins must be powered by designated traces with ferrite bead and
output. This domain has a tolerance of ±5%. which pins are tied together to the power plain using 0 Ω resistors.
The VDDA_SER and JESD_VTT_DES power domains can be
connected together and driven by a separate regulator. Noise from
this supply can affect the JESD204B link performance directly.
Although the recommendation for VDDA1P3_DES is to keep it
separate from the other JESD204B supplies using a separate
trace, it is acceptable to power this input from the other 1.3 V
analog supply to simplify layout.

Table 185. Power Supply Layout Recommendations (N/A Means Not Applicable)
Maximum
Voltage Current
Pin Name Pin No. Type (V) (mA)1 Recommended Routing/Notes Description
Tx Balun or RF N/A Analog 1.8 240 1.8 V plane, separate trace to common 1.8 V supply for Tx1
Choke DC Feed supply point.
Tx Balun or RF N/A Analog 1.8 240 1.8 V plane, separate trace to common 1.8 V supply for Tx2
Choke DC Feed supply point.
VDDA_3P3 B14 Analog 3.3 200 To 3.3 V supply (routing typically not critical). GPIO 3.3 V, auxiliary
DAC, auxiliary ADC, RF
bias, supply voltage
VDD_IF M12 Analog 1.8 to 2.5 60 CMOS/LVDS interface supply (routing Interface pull-up
typically not critical). voltage (1.8 V to 2.5 V)
VDDA_1P8 D10 Analog 1.8 20 1.8 V plane, separate trace to common 1.8 V supply for Tx
supply point.
Rev. B | Page 277 of 360
UG-992 AD9371/AD9375 System Development User Guide
Maximum
Voltage Current
Pin Name Pin No. Type (V) (mA)1 Recommended Routing/Notes Description
VDIG L8, L9 Digital 1.3 1700 1.3 V separate supply domain. Use thick 1.3 V digital core high
trace to separate power domain. Use current
reservoir capacitors close to the chip.
VDDA_RXRF B1 Analog 1.3 20 Separate trace (using 0 Ω resistor) to 1.3 V Sniffer front end only
analog power plane. Use reservoir
capacitors close to the chip.
VDDA_RXTX F2 Analog 1.3 560 Separate trace (using 0 Ω resistor) to1.3 V 1.3 V supply for Tx/ORx
analog power plane. Use reservoir baseband circuits, TIA/
capacitors close to the chip. Tx GM/baseband filters
VDDA_BB E5 Analog 1.3 670 Separate trace (using 0 Ω resistor) to1.3.V Rx ADC, ORx ADC, Tx
analog power plane. Use reservoir DAC, auxiliary ADC,
capacitors close to the chip. REF_CLK
VDDA_RXLO C6 Analog 1.3 270 1.3 V separate trace (using FB) to common 1.3 V LO generator for Rx
supply point. Very sensitive to aggressors. synthesizer, external LO
VDDA_TXLO F12 Analog 1.3 400 1.3 V separate trace (using FB) to common 1.3 V LO generator for
supply point. Very sensitive to aggressors. Tx synthesizer, buffers,
external LO
VDDA_CALLPLL G4 Analog 1.3 230 1.3 V separate trace (using FB) to common 1.3 V LO generator for
supply point. Very sensitive to aggressors. calibration PLL
synthesizer
VDDA_RXSYNTH G9 Analog 1.3 12 1.3 V separate trace (using FB) to common Rx synthesizer supply
supply point. Very sensitive to aggressors.
VDDA_TXSYNTH G8 Analog 1.3 12 1.3 V separate trace (using FB) to common Tx synthesizer supply
supply point. Very sensitive to aggressors.
VDDA_SNRXSYNTH G7 Analog 1.3 12 1.3 V separate trace (using FB) to common ORx synthesizer supply
supply point. Very sensitive to aggressors.
VDDA_CLKSYNTH G6 Analog 1.3 12 1.3 V separate trace (using FB) to common Clock synthesizer
supply point. Very sensitive to aggressors. supply
VDDA_SNRXVCO C4 Analog 1.3 340 1.3 V separate trace (using FB) to common SnRx PLL LDO, LO,
supply point. Very sensitive to aggressors. buffers
VDDA_CLK N1 Analog 1.3 270 1.3 V separate trace (using FB) to common Clock LDO
supply point. Very sensitive to aggressors.
VRX_VCO_LDO C8 Analog 1.1 N/A 1 µF bypass close to chip. 1.1 V VCO supply,
decouple with 1 µF
VTX_VCO_LDO F13 Analog 1.1 N/A 1 µF bypass close to chip. 1.1 V VCO supply,
decouple with 1 µF
VSNRX_VCO_LDO C3 Analog 1.1 N/A 1 µF bypass close to chip. 1.1 V VCO supply,
decouple with 1 µF
VCLK_VCO_LDO M1 Analog 1.1 N/A 1 µF bypass close to chip. 1.1 V VCO supply,
decouple with 1 µF
VDDA_RXVCO C7 Analog 1.3 85 1.3 V separate trace (using FB) to common Rx PLL LDO
supply point. Very sensitive to aggressors.
VDDA_TXVCO F11 Analog 1.3 85 1.3 V separate trace (using FB) to common Tx PLL LDO
supply point. Very sensitive to aggressors.
VDDA_SER N8 Analog 1.2 to 1.3 120 Connect to P8, P9 and to 1.3 V. Use separate JESD204B VTT signal
trace (using FB) to common supply point. for serializer
Use reservoir capacitors close to the chip.
VDDA_SER P8 Analog 1.2 to 1.3 120 Connect to N8, P9 and to 1.3 V. Use separate JESD204B VTT signal
trace (using FB) to common supply point. for serializer
Use reservoir capacitors close to the chip.
JESD_VTT_DES P9 Analog 1.2 to 1.3 60 Connect to N8, P8 and to 1.3 V. Use separate JESD204B VTT signal
trace (using FB) to common supply point. for deserializer
Use reservoir capacitors close to the chip.
VDDA_DES N9 Analog 1.3 240 1.3 V separate trace (using FB) to common 1.3 V supply for
supply point. Use reservoir capacitors close JESD204B deserializer
to the chip.
1
Maximum current is used for sizing voltage regulators not for calculating power consumption, which is heavily dependent on operating conditions.
Rev. B | Page 278 of 360
AD9371/AD9375 System Development User Guide UG-992
ADRV9371-N/PCBZ EVALUATION BOARD POWER The power trace connections to the device shown in Figure 173
SUPPLY BLOCK DIAGRAM are made using four different devices:
The diagram in Figure 173 outlines the power supply  High current ferrite beads (FB1)
configuration used on the ADRV9371-N/PCBZ evaluation  Medium current ferrite beads with better RF rejection (FB2)
board. This configuration follows recommendations outlined in  Low current ferrite beads with high dc resistance, best RF
Table 185. The ADRV9371-N/PCBZ evaluation board supports rejection (FB3)
the recommended power-up sequence. The open drain  0 Ω resistors
input/output (I/O)[1], open drain I/O[2], and open drain
I/O[3] signals allow the user to implement external control over The use of each 0 Ω resistor accomplishes two goals:
power-up and power-down sequencing as described in the  It serves as a placeholder for a ferrite bead in cases where
Power Supply Sequence section. the user encounters noise problems and more isolation is
The ADP5054 contains four switch mode, step down regulators. required. For more details regarding ferrite bead selection,
Each of those regulators produces a different power domain refer to the RF and Clock Synthesizer Supplies section.
that supplies power to the device. Power signals to the device  It ensures that the layout engineer follows the power
are further isolates using high current ferrite beads. The device routing advice outlined in the Signals with Second Routing
uses sense line to monitor the voltage output after the ferrite Priority section. Resistor placeholders in series force the
bead. This approach ensures that the voltage drop resulting use of separate traces to deliver different power domains to
from the FB resistance is taken into account, and that the the device.
voltage level delivered is in line with expected accuracy. For more details on exact power supply implementation, refer
to the schematic of the ADRV9371-N/PCBZ evaluation board.

6.0V ~ 15V
VREG CONNECT
55kΩ ADP5054 HF BYPASS TO AD9371
OPEN-DRAIN I/O[2] ALL INPUT PINS
PWRGD 1.3V FB1
14kΩ VDDA_BB
CH1 150µF 47µF 2 × 100µF
6A BUCK VDDA_RXRF
EN SENSE VDDA_RXTX
2mm × 2mm
DUAL-FETs VDDA_DES/JESD_VTT_DES
VREG
CH2 FB1 VDDA_SER
ADP5054_EN/ 1.3V 100µF 47µF
100kΩ 6A BUCK VDDA_CALPLL
OPEN-DRAIN I/O[1]
EN SENSE
VDDA_CLK
VDDA_RXLO
3.3V
FB1 VDDA_RXVCO
CH3
2.5A BUCK 100µF 47µF VDDA_SNRXVCO
EN SENSE VDDA_TXVCO
VDDA_TXLO
1.8V
CH4 FB1 VDDA_CLKSYNTH
43.5kΩ 2.5A BUCK 47µF
OPEN-DRAIN I/O[3] VDDA_RXSYNTH
EN SENSE
VDDA_SNRXSYNTH
100kΩ
VDDA_TXSYNTH
2×
VDIG
VDDA_1P8
FMC CONNECTOR
0Ω VDD_IF
VDDA_3P3
INTERFACE VOLTAGE 2.5V
FMCA VADJ
47µF AD9528/VCXO

FB2 3P3V_CLK
WIDE TRACE/SHAPE FB2 3P3V_VCO
14652-173

TRACE
NARROW TRACE (SENSE LINES)

Figure 173. Power Supply Connection Block Diagram of ADRV9371-N/PCBZ Evaluation Card

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UG-992 AD9371/AD9375 System Development User Guide
RF AND CLOCK SYNTHESIZER SUPPLIES variation in voltage that occurs during operation is directly
The noise performance of the power domain used to power the imposed on the RF channel. Refer to Figure 173 for an example
RF blocks directly affects the phase noise. The following pins of how the power supply connections are made on the
can be powered from a single power supply using a star ADRV9371-N/PCBZ evaluation board.
configuration where each domain is separated using 0 Ω The synthesizers are more susceptible to low frequency noise
resistors: than other supplies because they have programmable loop filters.
The loop filter bandwidth defaults are 50 kHz for the Rx, Tx,
• VDDA_RXRF
and ORx synthesizers, and 350 kHz for the clock synthesizer.
• VDDA_RXTX
The loop filter bandwidth directly affects the supply noise
• VDDA_BB
rejection on the synthesizers. For example, if the loop filter
Those domains must have a minimum 100 µF capacitor placed bandwidth is 50 kHz, any noise on the supply less than 50 kHz
near the device to help mitigate effects of transients on the 1.3 V is not filtered. The roll-off of the loop filter provides a noise
analog supply. rejection of more than 50 kHz.
It is recommended that the following power domains be For each of the following power domains listed, a ferrite bead
powered using separate traces with extra isolation using a low with high isolation at the frequency of operation is recommended
DCR ferrite bead, such as the Murata BLM15AX300SN1D or a to help isolate the pin from the supply source for best performance,
similar device: which is especially important when operating in time division
• VDDA_DES duplexed (TDD) mode. Such high isolation ferrite beads tend to
• VDDA_SER also have high dc resistance. This trade-off is acceptable for the
synthesizer power inputs because their low current draws result
• VDDA_CALPLL
in relatively small voltage drops that are well within the supply
• VDDA_CLK
tolerance range.
• VDDA_RXLO
• VDDA_RXVCO It is recommended that the following power domains be
powered using a separate trace with extra isolation using a high
• VDDA_SNRXVCO
rejection ferrite bead such as the Taiyo Yuden BK1005LL470-T
• VDDA_TXVCO
or a similar device:
• VDDA_TXLO
• VDDA_CLKSYNTH
The power supply noise rejection on the synthesizer power
• VDDA_RXSYNTH
input pins is very low, meaning that any noise ripple on these
pins affects the synthesizer performance. The RF synthesizer • VDDA_SNRXSYNTH
requires more critical supply decoupling because any noise or • VDDA_TXSYNTH

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AD9371/AD9375 System Development User Guide UG-992

DEMONSTRATION SYSTEM OVERVIEW

The demonstration system enables users to evaluate the device • Using a dedicated Ethernet connection, the PC can
without having to develop custom software or hardware. The access the following ports:
system is comprised of a radio daughtercard, a Xilinx® Zynq® • 22—SSH protocol
field programmable gate array (FPGA) evaluation platform, an • 55555—access to the evaluation software on the
SanDisk® (SD) card with an operating system, a power supply, ZYNQ platform
and a C#-based evaluation software application. The evaluation • TES—available on the RadioVerse landing page
system uses an Ethernet interface to communicate with the PC. (users must have PC administrative privileges).
INITIAL SETUP Hardware Kit
The transceiver evaluation software (TES) can run with or The device demonstration system hardware kit contains the
without evaluation hardware. When TES runs without the following:
hardware connected, it can be configured for a particular
operating mode. If the evaluation hardware is connected, the • The evaluation board is a daughter card. There are two
desired operating parameters can be setup with TES and then versions: the ADRV9371-N/PCBZ for a narrow tuning
the software programs the device evaluation hardware. Once range, and the ADRV9371-N/PCBZ for tuning across the
the device is configured, use the evaluation software to transmit entire range. Both operate with no differences with the
waveforms, observe received waveforms, and initiate correction TES. The ADRV9371-N/PCBZ is used for all descriptions
algorithms. A sequence of application programming interface in this user guide.
(API) commands in the form of an IronPython script can be • Two SD cards containing the files for the Xilinx ZC706
generated and executed using the TES. motherboard. The SD card is 8 GB, Type 4.
• One SD card with the Linux operating system with
HARDWARE AND SOFTWARE REQUIREMENTS required Linux-based evaluation software (see the
The hardware and software require the following: RadioVerse landing page for further information on this).
• The Xilinx ZC706 ZYNQ evaluation platform (not • One SD card with the Linux operating system and interface
included in the demonstration kit). Both Xilinx platforms, needed to operate with the Windows-based TES.
EK-Z7-ZC706 Rev. 1.2 and AES-Z7-JESD3-G Rev. 1.2, are Hardware Setup
compatible with the device demonstration system kit.
The ZYNQ platform setup (see Figure 174) requires the following
• The device demonstration system kit.
steps:
• The operating system on the controlling PC must be
Windows® Vista SP2 (x86 or x64) or Windows 7 SP1 1. Place all jumpers in the positions shown in Figure 174.
(x86 or x64). 2. Place the SW11 toggle switches in the positions as shown
• The PC must have a free Ethernet port with the following in Figure 174 (Toggle Switch 1, Toggle Switch 2, and
constraints: Toggle Switch 5 = Position A.
• If the Ethernet port is occupied by another LAN 3. Place the SD card (included with the evaluation kit) in the
connection, use a USB to Ethernet adapter. J30 slot of the ZYNQ board.

Rev. B | Page 281 of 360

UG-992 AD9371/AD9375 System Development User Guide

J68: EXTERNAL Rx TRIGGER

J67: EXTERNAL Tx TRIGGER

SW9: SHUTDOWN

SW8: REBOOT GPIO LED L: RF Rx JESD204B SYNC

GPIO LED C: RF SnRx/Ox JESD204B SYNC
GPIO LED R: RF Tx JESD204B SYNC
GPIO LED O: FPGA PLLs LOCK

14652-301
Figure 174. Xilinx EK-Z7-ZC706 ZYNQ Motherboard with Jumper Settings and Switch Position Configured to Work with the Device Evaluation Board

Rev. B | Page 282 of 360

AD9371/AD9375 System Development User Guide UG-992
SIGNAL SYNTHESIZER

REFERENCE CLOCK SOURCE

ETHERNET 30.72MHz/+5dBm
CONNECTION

Tx2 SIGNAL GENERATOR

SNRxA

ORx2

Rx2

Rx1
PC RUNNING
EVALUATION SOFTWARE
ORx1 SIGNAL ANALYZER

Tx1

SD CARD WITH IMAGE

POWER
SWITCH

14652-302
SWITCHING 12V DC
POWER SUPPLY

Figure 175. Evaluation Board and Xilinx EK-Z7-ZC706 ZYNQ Motherboard with Connections Required for Channel 1 Transmit and Receive Testing

Do the following to set up the evaluation board for testing: 5. Connect a 12 V, 5 A power supply to the ZYNQ evaluation
1. Connect the evaluation board and the ZYNQ evaluation platform at the J22 header.
platform together, as shown in Figure 175. Use the HPC 6. Connect the ZYNQ evaluation platform to the PC with an
FMC connector (J37). Ensure proper alignment of the Ethernet cable (connect to P3). No driver installation is
connectors. required. Note the following:
2. Ensure that all jumpers on the ZYNQ motherboard, as well a. In cases where the Ethernet port is already occupied
as the SW11 position, match the settings shown in Figure 174 by another connection, use a USB to Ethernet adapter.
(1, 2, 5 = Position A). b. With an Ethernet connection dedicated to the ZYNQ
3. Insert the for use with the Windows-based transceiver platform, manually set the IPv4 address to 192.168.1.2
evaluation software (TES) SD card that came with the and set the IPv4 subnet mask to 255.255.255. See the
device evaluation kit into the ZYNQ SD card slot (J30). Instructions to Set the IPv4 Addresses section and
4. Provide a 30.72 MHz clock source (or frequency that Figure 176 to Figure 178 for instructions on setting
matches the setting selected on the AD9528 configuration the IPv4 addresses.
(Config) tab, see Figure 202), at a 5 dBm power level to the 7. Ensure that the following ports on the PC are not blocked
J401 connector on the daughter card. This signal drives the by firewall software:
reference clock into the AD9528 clock generation chip on  22: SSH protocol
the daughter card. Note that the REFA/REFA pins of  55555: access to the evaluation software on the ZYNQ
AD9528 generate the DEV_CLK signal for the device and platform
the REF_CLK signal for the field programmable gate array
(FPGA) on the ZYNQ platform. Note that the ZYNQ IP address is set by default to: 192.168.1.10.

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UG-992 AD9371/AD9375 System Development User Guide
Instructions to Set the IPv4 Addresses
To set the IPv4 addresses as instructed in the evaluation board
testing setup (Step 6b), take the following steps:
1. In the Windows Control Panel, navigate to Network
Connections > Local Area Connection > General, and
click Properties (see Figure 176).

14652-304
Figure 177. Select Internet Protocol Version 4 (TCP/IPv4)

3. Verify that the appropriate addresses (Step 6b of the

evaluation system setup) are listed for the fields, IP address
and Subnet mask, as shown in Figure 178.
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Figure 176. General Tab Properties

2. Select Networking and check Internet Protocol Version 4

(TCP/IPv4), as shown in Figure 177.

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Figure 178. Select the Proper IP Address and Subnet Mask

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AD9371/AD9375 System Development User Guide UG-992
HARDWARE SETUP FOR EXTERNAL Tx LO
LEAKAGE CALIBRATION
The device is a direct conversion transceiver. The Tx baseband SPLITTER
Tx2
dc offset and direct coupling of the local oscillator (LO) to the
ORx2
Tx output can cause an undesired continuous wave (CW)
emission at the Tx LO frequency. The purpose of the transmitter ATTENUATOR

local oscillator leakage (LOL) calibration is to minimize this

ORx1
emission. The evaluation system supports two types of Tx LOL
calibration algorithms, internal and external. Make Tx LOL ATTENUATOR

calibration algorithm selections in the calibration boxes located Tx1

SPLITTER
in the transceiver evaluation software (TES), see Figure 179 (the
full screen capture of this graphical user interface (GUI) is

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shown in Figure 184).
Figure 180. Demonstration Operation of External Tx LOL Calibration on the
Device Evaluation System

The user must connect an RF splitter at the Tx output. Connect

one of the splitter outputs to the corresponding observation
(ORx) inputs through an RF attenuator (Tx1 → ORx1, Tx2 →
ORx2). The amount of attenuation needed depends on the
attenuation introduced by the splitter. For maximum ORx gain,
do not exceed a −16 dBm signal level at the ORx input. Note
that for external Tx LOL tracking calibration, both transmitters
must loop back to both observation receivers through splitters
and attenuators.
For example, for maximum ORx gain with a maximum Tx output
signal of 7 dBm (CW), the RF splitter attenuation = 3 dB and
the RF attenuator = 20 dB (7 dBm – 3 dB – 20 dB = –16 dBm).
To use the device evaluation system with a power amplifier
14652-306

(PA), either split or couple the signal after the PA and then
connect it to the corresponding ORx channel through an
Figure 179. Tx LOL Calibration Options appropriate attenuator. Do not exceed –16 dBm maximum
When user selects Internal Tx LOL, external hardware is not signal level at the ORx input. Calculate the amount of attenuation
necessary. Note that, in this case, there is no Tx LOL tracking required based on the power level after the PA and RF coupler
calibration available. (see Figure 181).
POWER AMPLIFIER COUPLER
When the user selects External Tx LOL in the Initial Calibration
list and External Tx LOL in the Tracking Calibration list as
Tx2
shown in Figure 179, external components must be connected
ATTENUATOR
to the evaluation platform for proper operation. Figure 180 ORx2
shows the proper configuration to demonstrate performance of
the Tx LOL calibration algorithm. ATTENUATOR
ORx1

Tx1
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POWER AMPLIFIER COUPLER

Figure 181. End User Application of External Tx LOL Calibration Using the
Device Evaluation System

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UG-992 AD9371/AD9375 System Development User Guide
HARDWARE OPERATION b. To set the input level near the full scale of the ORx
Turn on the evaluation system by switching the ZYNQ board receiver, set the generator level (for a single-tone
power switch (SW1) to the on position. Two LEDs (Blue DS701 signal) to approximately −15 dBm. This level depends
and Green DS702) on the device evaluation board turn on. If on the input frequency and the gain settings through
the LEDs do not turn on, it indicates improper hardware the path.
connection. c. To set the input level near the full scale of the SnRx
receiver, set the generator level (for a single-tone
The ZYNQ evaluation system uses a Linux operating system. It signal) to approximately −16 dBm. This level depends
takes approximately 30 seconds before the system is ready for on the input frequency and the gain settings through
operation and can accept commands from PC software. Boot the path.
status can be observed on the ZYNQ GPIO LEDs (L, C, R, O) 6. For transmitter testing, connect a spectrum analyzer to
(see Figure 174 for LED locations). Take the following steps for either Tx output on the device evaluation board. Use a
proper operating sequence: shielded RG-58, 50 Ω coaxial cable (1 m or shorter) to
1. Wait approximately 15 sec after SW1 turns on and all four connect the spectrum analyzer. Terminate both Tx paths
LEDs turn on to allow the image to copy from the SD card into the spectrum analyzers or, if only one Tx is being
into the field programmable gate array (FPGA) memory. checked, terminate one Tx path into a spectrum analyzer
2. Allow another approximately 15 sec for the ZYNQ system to and terminate the other Tx into 50 Ω. Note that, initial
boot up, which is indicated by flashing LEDs. Note that the calibrations run on both channels and can take an extended
flashing sequence occurs one LED at a time. When the time to complete if a Tx channel is not correctly terminated.
LEDs cease flashing, the system is ready for normal 7. Power off must be executed using the TES or the user must
operation. power down the ZYNQ system using the SW9 push button
3. After the LEDs stop flashing, establish a connection with (see Figure 174) before the user powers down the
the PC over the Ethernet (using the transceiver evaluation evaluation system by switching SW1 off.
software (TES)).
8. When shutdown is executed using the TES, the ZYNQ
During normal operation, the LED lights indicate system operating system begins the power-down procedure. It
status as defined in Table 186. takes a few seconds to finish. All four LEDs blinking
together indicates that the user can safely power off the
Table 186. GPIO LED Status Light Indicators system using the SW1 switch on the ZYNQ platform.
GPIO LED Description
Shutdown Caution
L RF Rx JESD204B sync
C RF SnRx/ORx JESD204B sync The device evaluation system utilizes a Linux operating system.
R RF Tx JESD204B sync Linux requires time to boot up as well as time for the software
O FPGA phase-locked loops (PLLs) lock to shut down before hardware power-off. To safely shut down
the system use the power-off feature in the TES, or press the
4. Connect the reference clock signal (30.72 MHz continuous SW9 button on the ZYNQ platform before physically switching
wave (CW) tone, 5 dBm maximum) to J401. power off by using the SW1 switch. Using any other shutdown
a. After using the TES to program the system, the two procedure risks corrupting the file system on the SD card and
LEDs on the evaluation board (D401 and D402) are on. causing the evaluation system to stop operating.
b. Active LEDs indicate that the correct reference clock To shut down the system, execute one of these options
is provided and the PLLs in the AD9528 are locked.
• Close the TES application (Windows X button) and then
5. For receiver testing on the device evaluation board, use a
select Switch Zynq Off.
clean signal generator with low phase noise to provide an
input signal to the selected RF input. Use a shielded RG-58, • Select Device > Shutdown Zynq Platform in the TES.
50 Ω coaxial cable (1 m or shorter) to connect the signal After several seconds, when all four GPIO LEDs on the ZYNQ
generator to the desired RF input. To set the input level, do platform blink together, the user can safely power off the system
the following: using the SW1 switch on the ZYNQ platform.
a. To set the input level near full scale of the Rx receiver,
set the generator level (for a single-tone signal) to
approximately −15 dBm. This level depends on the
input frequency and the gain settings through the
path. Do not apply the input signal to the Rx input
when performing an initialization calibration.

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AD9371/AD9375 System Development User Guide UG-992

TRANSCEIVER EVALUATION SOFTWARE

INSTALLATION STARTING THE TRANSCEIVER EVALUATION
SOFTWARE (TES)
Download the transceiver evaluation software (TES) directly
from the design center landing page. After the initial software Click Start > All Programs > Analog Devices > AD9371
download, copy the software to the target system and unzip the Transceiver Evaluation Software > AD9371 Transceiver
files (if not already unzipped). The downloaded zip container Evaluation Software to start the software. Figure 183 shows the
contains an executable file, AD9371 Transceiver Evaluation opening page of the TES after it activates.
Software.exe. Note that the same process is followed when
using the AD9375 evaluation board (or any other compatible
variant).
PC administrator privileges are required to install TES. After
running an executable file, the standard installation process
follows. Portions of the installation build are Microsoft .NET
Framework 4.5 (which is mandatory for the software to operate)
and IronPython 2.7.4 (which is optional and recommended).

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Figure 182 shows the recommended configuration for
installation.
Figure 183. TES Interface

When the evaluation hardware is not connected, the software

can still be used in demonstration mode by following these steps:
1. Click Connect (see Figure 184) in the TES.
2. The Zynq board is disconnected message will appear, then
click OK.
After clicking OK, the software automatically enters
demonstration mode in which a subset of all the features
display.
Indication of the connection status is shown at the bottom of
the Zynq Platform software window. When Disconnected is
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the status display, the TES operates in demonstration mode.

Figure 182. Software Installation Components

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Figure 184. Transceiver Evaluation Software (TES) Project Setup Page

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AD9371/AD9375 System Development User Guide UG-992
NORMAL OPERATION Software Update
When the hardware is connected to the PC and the user wants Before continuing, determine if the latest version of software is
to use the complete evaluation system, the transceiver evaluation installed by checking for updates on the landing page of the
software (TES) will establish a connection with the ZYNQ system design center at www.analog.com/ad9371-evaluation-software.
via the Ethernet cable after the Connect button is clicked. When Typically, when performing a TES update, platform files must
proper connection is established, click DaughterCard in the also be updated. To perform a platform files update, select
device tree on the left side of the window (see Figure 185). Device > Update > Platform Files. The TES automatically
Once DaughterCard is selected, information about the revisions updates files on the ZYNQ SD card and reboots the evaluation
of the different setup blocks appear in the main window. This system.
window shows the TCP IP address set to 192.168.1.10, and the After installation of all updates, the system is ready for normal
port number set to 55555. Figure 185 shows an example of the operation.
correct connection between a PC and the ZYNQ system with a
daughter card connected to them.

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Figure 185. Setup Revision Information

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UG-992 AD9371/AD9375 System Development User Guide
CONFIGURING THE AD9371 Configuration Tab
The transceiver evaluation software (TES) contains four main The Configuration tab is the first tab within the Config tab
user configurable pages (see Figure 186 through Figure 188 and (see Figure 186). The following selections are available within
Figure 202). After the user selects the AD9371 in the device the Configuration tab:
tree, the Config tab activates. Contained within this tab are eight  Device clock frequency
subtabs that contain setup options for the device.  Number of active Rx channels
 Number of active Tx channels
 Observation/sniffer input
 Rx, Tx, ORx (Obs), and sniffer profiles
 Rx, Tx, and SnRx/ORx LO PLL

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Figure 186. Main Configuration Tab

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AD9371/AD9375 System Development User Guide UG-992
Calibration Tab Use external circuitry for External Tx LOL initialization calibration
The second user configurable tab within the Config tab is as well as Tx1 LOL and Tx2 LOL tracking calibrations. The
Calibration. Within this tab, users can enable initialization and Hardware Setup for External Tx LO Leakage Calibration section
tracking of Rx/Tx quadrature error correction (QEC) and Tx explains the external hardware configuration. The External Init
local oscillator leakage (LOL) calibrations. Figure 187 shows a Atten option, located in the Initialization Calibration section of
calibration configuration example. The user can enable or the Calibration tab (see Figure 187), allows the user to control
disable initialization calibrations as well as tracking calibrations. the level of attenuation applied internally at both Tx outputs
simultaneously.

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Figure 187. Calibration Configuration Tab

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UG-992 AD9371/AD9375 System Development User Guide
JESD204B Setup Tab desired JESD204B lane configuration, select scrambling, and
The third user configurable tab within the Config tab is the choose whether the selected framer/deframer relinks on
JESD204b Setup tab. Users can set the characteristics of the SYSREF. The user can also select either an internal (free
digital data interface within this tab. Figure 188 shows a running) or external (provided by the AD9528) SYSREF to
JESD204B setup configuration example. The user can set the synchronize the JESD204B links.

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Figure 188. JESD204b Setup Tab

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AD9371/AD9375 System Development User Guide UG-992
GPIO Configuration Tab  Check the Rx MGC Pin control box (see Figure 190 and
Figure 189), to select the GPIO pins used by Rx manual
The fourth user configurable tab within the Config tab is the
gain control (MGC) mode.
general-purpose input/output configuration (GPIO Config)
tab. Users can set the characteristics of the general-purpose
input/output (GPIO) interface. It allows the user to program

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behavior of the GPIO interface (powered from the
VDD_INTERFACE power domain). Figure 189. Rx MCG Pin control Box (Circle Highlight for Emphasis Only)
Use the GPIO Config tab, to do the following:  The user can select increment or decrement gain steps as
 Monitor the status of the GPIO pins using the GPIO well as assign particular GPIO pins to perform selected
ACTIVE controls. When modifying GPIO settings, click actions. Figure 190 shows a GPIO receive configuration
the Check GPIO button to check the new settings, and example.
click the Program GPIO to program these settings to the
transceiver (see Figure 190 and Figure 191).

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Figure 190. GPIO Tab Setup: Rx MGC, Tx TPC, and ARM GPIO Settings

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UG-992 AD9371/AD9375 System Development User Guide

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Figure 191. GPIO Tab Setup, Input/Output Manual Control and Monitor Output Mode

 Check the Tx TPC Pin control box (see Figure 190 and  The user can select attenuation step size as well as assign
Figure 192) to select the GPIO pins used by Tx transmit particular GPIO pins to perform selected actions. Figure 190
power control mode. shows a GPIO transmit configuration example.
 Check the ARM GPIO settings box (see Figure 190 and
Figure 193) to selecting the GPIO pins assigned to interface
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with the on-board ARM microcontroller.

Figure 192. Tx TPC Pin Control Checkbox (Circle Highlight for Emphasis Only)

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AD9371/AD9375 System Development User Guide UG-992
 Select the logic level (high or low) of the GPIO pins in the

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Set output Pin Level when Output Enable are set as
outputs (High or Low) section (see Figure 191). Click
Figure 193. ARM GPIO Checkbox (Circle Highlight for Emphasis Only)
either once (for high) or twice (for low) on its respective
 The user can select GPIO pin or SPI interface mode to numbered icon to set the desired logic level of each GPIO
control the on-board ARM mode operation. Figure 190 pin. To apply the logic selections, click Write Outputs (see
shows a GPIO ARM configuration example. Figure 197).
 Check the GPIO Monitor selection box (see Figure 191)
to select the GPIO pins used by the internal monitoring
block. Press the Ctrl key while clicking in the cells within

14652-324
the shown table to select the various options for selecting
the desired signals (see Figure 194). Note that only cells
from a single row can be selected at one time. The user can Figure 197. Setting Logic Level of GPIO Pins
select from a single row the entire set of monitoring output
 Read the logic level for the GPIO input only pins in the Pin
signals or a subset of them. Figure 191 shows a GPIO
Level when Output Enable are set as inputs section. Click
monitor configuration example where all signals from the
Read Inputs to populate the logic levels for the inputs,
Index 1 row are selected. The Search function helps the
high (Hi), low (Lo), or off (OFF) (see Figure 198).
user navigate in the control output signals table.

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14652-321

Figure 198. Setting GPIO Inputs to Logic High or Logic Low

Figure 194. Index 1, GPIO Monitor Selection Table Figure 191 shows a configuration example with GPIO Pin 8
to GPIO Pin 11 set to operate as outputs and GPIO Pin 12 to
 Selecting the GPIO pins used by the GPIO operating in
GPIO Pin 15 set to operate as inputs. GPIO Pin 8 and GPIO
manual input/output mode are enabled by Check the
Pin 10 are set to logic high. GPIO Pin 9 and GPIO Pin 11 are set
GPIO input/Output Pin Level box (see Figure 191 and
to logic low. GPIO Pin 12, GPIO Pin 13, and GPIO Pin 15 read
Figure 195).
back logic low, and GPIO Pin 14 reads back logic high.
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Figure 195. GPIO input/Output Pin Level Box Location (Yellow Circle for
Emphasis)

 Click the Output Enables (Outputs or Inputs) box to

select the GPIO pins to be used in manual mode (see
Figure 191). Choosing whether a GPIO pin will operate
as an output, an input, or be disabled is determined by the
number of clicks made to the selection. For example, to
select a pin (such as GPIO Pin 8 in Figure 196) to operate
as an output, place your mouse cursor over the 8 box and
click once. Each mouse click on an individual box toggles
the operational status of that pin between three options:
output (one click), input (two clicks), and disabled (three
clicks). Disabling the selected GPIO pin in manual mode
allows that GPIO pin to be used by different GPIO modes.
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Figure 196. Selecting GPIO Pin Status: Output, Input, or Disabled

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UG-992 AD9371/AD9375 System Development User Guide
3V3 GPIO Tab  Click on the numbered boxes in the Set output Pin Level
The fifth user configurable tab within the Config tab is the 3v3 when Output Enable are set as outputs (High or Low)
GPIO tab (see Figure 200). This tab sets the characteristics of section to select the logic level for the 3.3 V GPIO output only
the 3.3 V general-purpose input/output interface. It allows users pins. Click once on the box to set that 3.3 V GPIO pin to
to program the behavior of the GPIO interface (powered from a logic high and click twice on the box to set the pin to logic
3.3 V power domain). Within the 3V3 GPIO tab, the user can low. Click Write Outputs to selected the levels applied to the
select and enable operation of the 3.3 V GPIO pins in manual 3.3 V GPIO pins (see Figure 199).
input/output mode. Check the GPIO 3v3 Input/Output Pin
Level box to enable manual mode.

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Within the 3v3 GPIO tab, users can perform the following:
Figure 199. Setting Logic Levels for the 3.3 V GPIO Pins
 Click the GPIO numbered boxes in the Output Enables
(Outputs or Inputs) section (see Figure 200) to select which  Read the logic level for the 3.3 V GPIO input only pins in
3.3 V GPIO pin is used in manual mode. Click once on a the Pin Level when Output Enable are set as inputs
numbered box to set the 3.3 V GPIO pin to operate as an section. Click Read Inputs to populate the logic levels for
output, click twice to set it to operate as an input, and click the inputs, high (Hi), low (Lo), or off (OFF).
it a third time to disable manual mode for that 3.3 V GPIO
Figure 200 shows a configuration example with 3.3 V GPIO
pin. For example, in Figure 200, click once in the 0 box to set
Pin 0 to Pin 3, Pin 8, and Pin 9 set to operate as outputs, and
the 3.3 V GPIO 0 pin as an output.
3.3 V GPIO Pin 4 to Pin 7 set to operate as inputs. The 3.3 V
GPIO Pin 0, Pin 1, and Pin 8 are set to logic high, and the 3.3 V
GPIO Pin 2, Pin 3, and Pin 9 are set to logic low. The 3.3 V GPIO
Pin 4 to Pin 7 read back logic high.

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Figure 200. 3v3 GPIO Tab Setup

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AD9371/AD9375 System Development User Guide UG-992
Rx, Tx and ObsRx/Sniffer Summary Tabs using the mouse cursor as well as restoring to the full-scale plot.
The Rx Summary, Tx Summary, and ObsRx/Sniffer Summary Right-click on the graph area and select Export Data to File
tabs are primarily informative and are based on the profile within the transceiver evaluation software (TES) to export the
selection in the Configuration tab (see Figure 186). In each of data plotted on the graphs to an external file. Data can then be
these tabs, the user can check clock rates at each filter node as saved to a file for later analyses. Figure 201 shows an example of
well as filter characteristics and their pass-band flatness. Quick the Rx Summary tab with the resulting composite filter response
zooming capabilities allow zooming of the pass-band response for the chosen profile.

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Figure 201. Rx Summary Tab

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UG-992 AD9371/AD9375 System Development User Guide
Configuring the AD9528 Clock Chip On-Board VCXO Modification
The daughter card utilizes the AD9528 clock chip to provide The device evaluation board contains an on-board voltage
the reference clock, DEV_CLK, as well as a SYSREF pulse to controlled crystal oscillator (VCXO) as well as the AD9528 chip
the device and the field programmable gate array (FPGA) on responsible for the device clock and SYSREF signal generation
the ZYNQ platform via the FMC connector. Configure the and distribution. With the hardware configuration provided on
AD9528 using the Clock Setup tab (see Figure 202). Use the the evaluation board, a user can generate device clock frequencies
Ref A dropdown menu within the Clock Setup tab to select the such as 122.88 MHz, 153.6 MHz, 184.32 MHz, 245.76 MHz,
input reference frequency. Note that an external reference clock and 307.2 MHz.
must be connected to the J401 SMA connector that matches the There are limitations with the default hardware configuration in
frequency selected in the dropdown menu. The signal amplitude the scenario where user desired device frequencies are not related
must not exceed 5 dBm. to the on-board 122.88 MHz VCXO by a rational fraction.
Examples of such device clock frequencies are: 125 MHz,
133.33 MHz, 250 MHz, and 266.66 MHz. The following section
outlines these limitations and explains how to overcome them with
evaluation board hardware modifications.

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Figure 202. AD9528 Clock Setup Configuration Page

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AD9371/AD9375 System Development User Guide UG-992
PLL2 IN AD9528
OUTPUT FROM
THE PLL1 OF VCO
AD9528 TO AD9371
5-BIT DIVIDER 3450MHz... 4025MHz DEV_CLK
RF VCO 8-BIT
R1 = 0.5, 1, 2, 3, .., 31 DIVIDER
CLEAN VERSION PFD CP LPF DIVIDER
OF ON-BOARD ÷M chDIV = 1, 2, ..., 256
VCXO (M = 3, 4, OR 5)

5-BIT DIVIDER
N2 = 1, 2, 3, .., 256

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Figure 203. AD9528 PLL2 Block Diagram

AD9528 Description Example 2: This example targets a 153.6 MHz DEV_CLK.

The AD9528 contains two cascaded phase-locked loop (PLL) Using Equation 41 and Equation 42, the following results:
stages. The first PLL stage (PLL1) works with a narrow loop (122.88 MHz × 3 × 30)/3 = 3686.4 MHz (45)
filter bandwidth. PLL1 provides jitter clean up of the input 3686.4 MHz/(3 × 8) = 153.6 MHz (46)
reference signal to provide a clean clock for the input stage of Equation 45 and Equation 46 demonstrate that a DEV_CLK =
PLL2. The configuration of PLL2 is described in Figure 203. 153.6 MHz can be generated using the on-board VCXO.
PLL2 blocks are programmable and the following values can be Example 3: This example targets a DEV_CLK of 125 MHz.
selected:
Following the same process as the previous examples, the
 M = 3, 4, or 5 following results are obtained:
 N2 = 1, 2, 3, …, 256 (122.88 MHz × 3 × 30)/3 = 3686.4 MHz (47)
 R1 = 0.5, 1, 2, …, 31
3686.4 MHz/(3 × 10) = 122.88 MHz ≠ 125 MHz (48)
 chDIV = 1, 2, 3, …, 256
In the scenario presented in Equation 47 and Equation 48, the
Note that the PLL2 voltage controlled oscillator (VCO) frequency on-board VCXO cannot generate a DEV_CLK of 125 MHz.
operates from 3450 MHz to 4025 MHz. Likewise, Equation 49 and Equation 50 produce the same result
To calculate the DEV_CLK frequency, use the following equations: wherein a DEV_CLK of 125 MHz cannot be generated using
VCO Frequency = (VCXO Frequency × M × N2)/R1 (41) the on-board VCXO.

Note that the VCO can operate with a frequency range from (122.88 MHz × 3 × 31)/3 = 3809.28 MHz (49)
3450 MHz to 4025 MHz. 3809.28 MHz/(3 × 10) = 126.976 MHz ≠ 125 MHz (50)
DEVCLK Frequency = VCXO Frequency/(M × Example 4: This example uses a VCXO of 125 MHz rather than
Channel Division) (42) the 128.88 MHz used in the previous equations to achieve a
DEV_CLK of 125 MHz. By modifying the hardware to use a
AD9528 Operation Examples
VCXO of 125 MHz, a 125 MHz DEV_CLK can now be selected.
The AD9528 can only generate different DEV_CLK frequencies
(125 MHz × 3 × 30)/3 = 3750 MHz (51)
from the VCXO frequency when the ratio of the two frequencies is
a rational fraction. If the result of the DEV_CLK division and 3750 MHz/(3 × 8) = 125 MHz (52)
VCXO frequency does not create a rational fraction, the Example 5: This example returns to using a VCXO of 122.88
AD9528 cannot precisely generate the desired DEV_CLK. MHz and targets a DEV_CLK of 266.66 MHz.
The following are some examples of how DEV_CLK is calculated (122.88 MHz × 3 × 32)/3 = 3932.16 MHz (53)
based on an on-board VCXO with a frequency of 122.88 MHz.
3932.16 MHz/(3 × 5) = 262.144 MHz ≠ 266 MHz (54)
Example 1: This example targets a DEV_CLK of 245.76 MHz.
Equation 53 and Equation 54 demonstrate that a DEV_CLK of
Plugging in values to Equation 41 produces Equation 43 and,
266.66 MHz cannot be generated using the on-board VCXO.
likewise, using Equation 42 generates the results shown in
Equation 44.
(122.88 MHz × 3 × 30)/3 = 3686.4 MHz (43)
3686.4 MHz/(3 × 5) = 245.76 MHz (44)
Therefore, Equation 43 and Equation 44 demonstrate that a
DEV_CLK = 245.76 MHz can generate using the on-board VCXO.

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UG-992 AD9371/AD9375 System Development User Guide
Example 6: Like Example 5, this example attempts to generate a On-Board VCXO Hardware Replacement
266.66 MHz DEV_CLK. However, similar to achieving a The evaluation board supports two different footprints for the
125 MHz DEV_CLK through hardware modification, in this on-board voltage controlled crystal oscillator (VCXO). Figure 204
example, the 266.66 MHz DEV_CLK can be achieved by outlines two different VCXO symbols present in the evaluation
modifying the hardware to use a VCXO of 133.33 MHz rather board schematic. Both footprint details are outlined in Figure 205
than 122.88 MHz, as demonstrated in Equation 55 and and Figure 206.
Equation 56.
achieves a DEV_CLK of 266.66 MHz by modifying the
hardware with a VCXO of 133.33 MHz.
(133.33 MHz × 3 × 30)/3 = 3999.9 MHz (55)
3999.9 MHz/(3 × 5) = 266.66 MHz (56)
3P3V_VCO 3P3V_VCO

6 Y402
4 Y403
POS_VS
VCON 1 4 OUT VDD
VCNTRL OUTPUT VCON 1 3 OUT
TRI_STATE 2 CONTROL OUT
ENABLE_DISABLE
GND
GND NC
2
3 5 122.88MHz
122.88MHz

AGND
COMP_OUT

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AGND

Figure 204. Double Footprint for the On-Board VCXO

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Figure 205. VCXO Footprint: SMD, 5.0 mm × 9.0 mm

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Figure 206. VCXO Footprint: SMD, 9.0 mm × 14.0 mm

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AD9371/AD9375 System Development User Guide UG-992
VCXO Recommendations PROGRAMMING THE EVALUATION SYSTEM
The evaluation board utilizes a voltage controlled crystal After all tabs are configured, click Program to send (via the
oscillator (VCXO) manufactured by Crystek Corporation. All transceiver evaluation software (TES)) a series of application
frequency variants recommended for the evaluation board are programming interface (API) commands that are executed by a
based on the Crystek Corporation VCXO CVHD-950 series. dedicated application running on the ZYNQ platform. A
Table 187 lists the typical characteristics of the CVHD-950 progress bar is shown at the bottom of the window and, upon
series VCXO. programming completion, the system is ready to operate (see
Figure 207).
Table 187. Typical CVHD-950 Series Parameters
Parameter Value
Frequency Range 40 MHz to 130 MHz
Input Voltage 3.3 V ± 0.3 V
Input Current 15 mA typical; 25 mA maximum
Control Voltage 1.65 V ± 1.65 V
Frequency Pulling ±20 ppm APR minimum
Typical Phase Noise (100 MHz)
1 kHz −140 dBc/Hz
10 kHz −155 dBc/Hz
100 kHz −164 dBc/Hz
1 MHz −166 dBc/Hz
Phase Noise Floor −166 dBc/Hz typical,
−162 dBc/Hz maximum

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Figure 207. Program Device Window

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UG-992 AD9371/AD9375 System Development User Guide
OTHER TES FEATURES  View Log Files monitors application programming
The transceiver evaluation software (TES) provides the user with interface (API) activities. It opens a window where the
multiple options to store and load the TES and also hardware following options are available (see Figure 210):
configurations. Figure 208 outlines all dropdown menu options  Monitoring all API activates. The output is displayed in
provided by TES. an IronPython script form.
 Monitoring error log only. To observe error messages
reported by the API software layer, click Refresh Log
and content of the log window updates. Log Window
allows the user to store log messages as text files for
further analysis. Click Clear Log to clear the Log

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Window.
Figure 208. TES Device Dropdown Menu

Device Dropdown Menu

The following option selections are available in the Device
dropdown menu:
 Update > Platform Files is for updating files on the ZYNQ
SD card after installing a new version of the software. See

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the Software Update section for more details.
 Reboot Zynq Platform is for when a soft restart of the Figure 210. TES Log Window
evaluation system is needed.
 Shutdown Zynq Platform is for powering down the  Exit opens the Shutdown window (see Figure 211) where
evaluation system. The user must use this option or power the following options are available:
down the system by closing the TES application and by  Switch Zynq Off powers down the entire system and
selecting Switch Zynq Off to correctly execute the power- closes TES.
down sequence. If this process is not followed, the file  Close GUI Only closes only the TES software, and the
system on the SD card can be corrupted, and the evaluation ZYNQ system remains active
system may stop operating.  Cancel closes the Shutdown window.

File Dropdown Menu

The following selections are available in the File dropdown menu:
 Save GUI Setup stores all TES configuration settings. TES
generates an XML format file with all software settings
recorded. Click Load Setup and select the saved setup file
to load software settings.
 Load GUI Setup loads all TES configuration settings
stored in XML format using the Save GUI Setup option.
 Load Custom Profile allows the user to load a custom
version of the TES profile using the Filter Wizard software
14652-338

available at the RadioVerse landing page.

 Clear Custom Profile restores the TES software to the
Figure 211. Shutdown Window
state before a custom profile was loaded.
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Figure 209. TES File Dropdown Menu

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AD9371/AD9375 System Development User Guide UG-992
Tools Dropdown Menu Table 188. TES Files
Figure 212 shows the Tools dropdown menu. File Description
headless.c Provides an example file that
calls into the API to initialize
the device.
headless.h Header file for headless.c.

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user_name.c Contains all initialization values
for the structures members
Figure 212. Transceiver Evaluation Software (TES) Tools Dropdown Menu
used by APIs.
This menu allows selection of the following options: user_name.h Header file for user_name.c.
 Options allows the user to configure a path to the user_name_ad9528init.c Contains all initialization values
for the structures used by the
Iron Python library folder (see Figure 213). This setting
AD9528 (clock IC) APIs
is automatically populated with the path set during the
Memory Dump Provides users with the ability
installation process. to store register values from
the internal ARM processor, the
register map, and the ZYNQ
field programmable gate array
(FPGA) register map. When the
user clicks Memory Dump, the
user must enter a file name for
the file and select a location
where those files are to be
stored. The TES then reads
internal register values and
stores them in three separate
files: user_name.bin,
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user_name_MykonosReg.txt,
and user_name_FpgaReg.txt
Figure 213. TES Options Window user_name_bin For internal ARM processor
dump.
 Create Script allows the storing of the initialization script.
user_name_ For register dump.
The TES allows the creation of a script in the following MykonosReg.txt
forms: user_name_FpgaReg.txt For ZYNQ FPGA register dump.
 Python. When this function executes, the user is
asked for the script file name and place where it can be
stored. TES generates the new_name.py file with all
API initialization calls in the form of IronPython
functions. This file can then execute using the Iron
Python Script tab shown in Figure 226.
 C Script. This action opens the Save as window,
requires the user to name the file and specify its
location for storage. Based on configuration settings
outlined in the Configuring the AD9371 section, the
TES sets up structure members values that are then
used by application programming interface (API)
commands. The TES allows the user to create a *.c file
that contains all initial values. This file can be imported
into the system of the user that utilizes APIs. The TES
generates five separate files the include headless.c,
headless.h, user_name.c, user_name.h, and
user_name_ad9528init.c (see Table 188).

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Help Dropdown Menu System Status Bar
The Help dropdown menu (see Figure 217) includes the The TES provides the user with visual information about the
following: current state of the evaluation system (see Figure 215).

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 API Help File opens the Mykonos Device API file in
Windows help format (*.chm). Refer to the software detail
Figure 215. TES Status Bar
maual that comes with the software when looking for
detailed information about the API commands. The status bar information can be interpreted as follows:
 DLL Help File opens ADI ZC706 TCPIP Client DLL file  Zynq Platform: connected or disconnected.
in Windows help format (*.chm). Refer to this document  Connected. PC established connection with the
when looking for detailed information about functions to ZYNQ evaluation system,
control the device that use the Xilinx ZC706 FPGA  Disconnected. No connection between PC and the
platform. ZYNQ evaluation system.
 About opens an information window about the transceiver  Radio: on or off.
evaluation software (TES) and delay-locked loop (DLL)
 On. The device is enabled and ready to transmit/receive.
versions installed on the PC as well as for the software and
 Off. The device must be initialized and moved into
firmware versions installed on the ZYNQ SD card. It also
the radio on state before data can be transmitted or
displays information about the internal ARM firmware
received.
version of the device (see Figure 214).
 Tracking: TxQEC, TxLOL, or RxQEC.
 TxQEC, TxLOL, RxQEC. Those controls display the status
of the tracking calibrations used by the device.
 Green control indicates calibration is enabled and
active.
 Red control indicates calibration is enabled but not
active.
 Grey control indicates calibration is disabled (using
the calibration tab described in the Calibration Tab
section of this user guide).
 Programmed Successfully indicates the progress when
programming the evaluation system (see Figure 216).
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Figure 214. TES Help About Window

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Figure 216. Program Status Bar

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Figure 217. TES Help Dropdown Menu

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AD9371/AD9375 System Development User Guide UG-992
RECEIVER SETUP received data in both frequency and time domains. An example
Rx Signal Chain of a captured waveform is shown in Figure 218.
After configuring the TES using the Config tab and programming The upper plot displays the fast Fourier transform (FFT) result.
the system by executing the Program function, the system is Check the corresponding boxes to select if both Rx1 and Rx2 data
ready for normal operation. Select Receive Data to open the are displayed in this window, or only one of type of data is
RxDataPlot function, as shown in Figure 218. From the Receive displayed.
Data tab, the user can enter the radio frequency (RF) Rx center The lower plot shows the time domain waveform.
frequency in megahertz, and set the Rx gain by entering the
Check the corresponding boxes to select if both Rx1 and Rx2 data
desired gain index for each Rx channel. The gain index refers to
are displayed in this window, or only one of type of data is
the value in the programmable gain index table. Refer to the
displayed. The user can also select if only I or only Q data is
Gain Control section for details on implementing the gain
displayed in the same manner.
index table. The user can also enable or disable Rx1/Rx2
quadrature error correction (QEC) tracing calibrations as well The time domain waveform display supports zoom function by
as rerun Rx initialization calibrations from this window. selecting the region of the time plot to zoom in to. Right-click
on the Time Domain window and select Undo All Zoom/Pan
Click the play symbol in the Receiver Data tab, to move the
to return the time domain plot to its original scale. Check the
device to the receive state and to generate graphs for the
AutoScale box to enable automatic scale in the time domain plot.

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Figure 218. Rx Receiver Data Tab

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UG-992 AD9371/AD9375 System Development User Guide
If the fast Fourier transform (FFT) analysis is selected • Rx1 QEC Tracking and Rx2 QEC Tracking: enable or
(multicolored pie chart symbol), basic analysis information from disable Rx1/Rx2 QEC tracking calibrations. Check Rx1
the FFT is displayed on the left side of the screen. The FFT QEC Tracking to enable tracking calibration for the Rx1
results are displayed separately for each Rx channel. path and check Rx2 QEC Tracking to enable tracking
Select among the following in the RxTrigger dropdown box: calibration for the Rx2 path. Tracking calibrations operate
when an Rx signal path receives data.
• IMMEDIATE starts the capture as soon as the SPI
• ObsRx Sniffer Data: opens the ObsDataPlot page (see
command is received to initiate capture.
Figure 219). When this tab is open, the user can enter the
• EXT_SMA starts the capture when a high level is present observation receive (ObsRx) radio frequency (RF) center
at Connector J68 on the ZYNQ platform. frequency in megahertz, and set the ObsRx gain by
• TDD_SM_PULSE hands over control of the Rx datapaths entering the desired gain index. The gain index refers to
to the state machine that is implemented in the ZYNQ on- the value in the programmable gain index table. See the
board field programmable gate array (FPGA). Use this Gain Control section for details on implementing the gain
option when the device operates in the time division index table.
duplexed (TDD) mode. • ObsChannel: This dropdown menu (see Figure 219) offers
The floppy disk icon saves the receive data to a file. Selecting the following input choices:
this option opens a window allowing selection of the format for • Internal path allows the ObsRx path to be used by
the exported data. The file type can be specified as one of the internal calibrations. See the Gain Control section for
following: details on calibration requirements.
• SNIFFER A—Sniffer A input is the only sniffer input
• Agilent Data. The TES adds a header to the saved file that
accessible on the device evaluation system.
Agilent VSA software can read and use to demodulate the
data. The header is followed by data stored in I <TAB> Q • SNIFFER B—It is not used and it is not available.
[new_line] format. • SNIFFER C—It is not used and it is not available.
• No Header (Tab delimited). The TES saves data as a text • ORx1 with TxLO—Used to select the ORx1 channel
file where I data is separated by <TAB> from Q data. Each and the Tx LO PLL.
data record is finished with a [new_line] character. There is • ORx2 with TXLO— Used to select the ORx2 channel
no header information stored in this file format. and the Tx LO PLL.
• No Header (Comma delimited). The TES saves data as a • ORx1 with SNIFFERLO— Used to select the ORx1
text file where I data is separated by a comma [,] from Q channel and the SNIFFERLO PLL.
data. Each data line is finished with a [new_line] character. • ORx2 with SNIFFERLO— Used to select the ORx2
There is no header information stored in this file format. channel and the Tx LO PLL.

Additional settings in the Receive Data tab include the following: When clicking the play symbol in the ObsRx Sniffer Data tab,
the device moves to the receive state and graphs the output data.
• # Samples: the number of points saved to the file is
An example of a captured waveform is shown in Figure 219.
determined by the number of samples selected in this box
(see Figure 218).
• Rx Init Cals: click Rx Init Cals to rerun initial Rx calibrations.
When calibrations execute, the button changes its appearance
to running. Do not apply an input signal to the Rx input
when performing an initialization calibration.

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AD9371/AD9375 System Development User Guide UG-992

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Figure 219. Observation Rx Receive Tab

The upper plot displays the fast Fourier transform (FFT) result When a file type chosen, the following happens within the file
and the lower plot shows the time domain waveform. The user chosen:
can select if only I or only Q data is displayed. The time domain
 Agilent Data. The TES adds a header to the saved file that
waveform display supports a zoom function by selecting the
Agilent VSA software can read and use to demodulate the
region of the time plot to zoom in to. Right-click the Time
data. The header is followed by data stored in I <TAB> Q
Domain window and selectUndo All Zoom/Pan to return the
[new_line] format.
time domain plot to its original scale.
 No Header (Tab delimited). Saves data as a text file where
If the FFT analysis is selected (multicolored pie chart symbol), I data is separated by <TAB> from Q data. Each data
basic analysis information from the FFT displays on the left side record is finished with [new_line] character. There is no
of the screen. header information in stored this file format.
Click the floppy disk icon to save the data received by the  No Header (Comma delimited). Saves data as a text file
observation receive (ObsRx) channel. By selecting this window, where I data is separated by comma [,] from Q data. Each
users can select the format for the exported data. data line is finished with [new_line] character. There is no
header information stored in this file format.
 # Samples. The number of points saved to the file is
determined by the number of samples selected in the
# Samples box.

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TRANSMITTER SETUP The time domain waveform display supports zoom function by
Selecting the Transmit Data tab opens the page shown in selecting the region of the time plot to zoom in to. To return the
Figure 220. plot to its original scale, right-click Time Domain window and
select Undo All Zoom/Pan. To enable automatic scaling in the
The upper plot displays the fast Fourier transform (FFT) result. time domain plot, check the AutoScale box.
Check the corresponding box(es) to select if both Tx1 and Tx2
data are displayed in this window, or if only one type of data is From the Transmit Data tab, the user can enter the radio
displayed. frequency (RF) Tx center frequency in megahertz, change
the attenuation level independently for each Tx output,
The lower plot shows the time domain waveform. Check the enable/disable various calibrations, control data scaling, and
corresponding box(es) to select if both Tx1 and Tx2 data are transmit continuous wave (CW) tones or a desired Tx data file.
displayed in this window, or if only one type of data is displayed.
The user can also select if only I or only Q data is displayed.

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Figure 220. Transmit Data Tab

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AD9371/AD9375 System Development User Guide UG-992
Transmitter Data Options  Press Play to enable device data transmitted on the Tx1/Tx2
The transceiver evaluation software (TES) provides the outputs. It starts a process where the generated continuous
following options for inputting transmitter data: wave (CW) data or the I/Q data in the Tx1 and Tx2 files
are sent to the device. The data is stored on the ZYNQ
 A single tone or two tones can be generated by the evaluation
motherboard RAM, and the RAM pointer loops through
system using the Tone Parameters menu (see Figure 221).
the data continuously until Stop is clicked.
 The Tx1 Attenuation (dB) input controls analog attenuation
in the Tx1 channel. It provides 0.05 dB of attenuation control
accuracy. Tx2 Attenuation (dB) performs the same
operation on the Tx2 channel.
 Tx1 Scaling (dBFS) input controls digital scaling of data
sent over the Tx1 channel. It can be varied in 1 dB steps. It
is only available for Tx data loaded using the Load Tx1/
Load Tx2 buttons. Tx2 Scaling (dBFS) performs the same
operation on the data sent over the Tx2 channel.
 Check the Tx1 LOL Tracking box to enable Tx local

14652-348
oscillator leakage (LOL) tracking calibration. Calibration
Figure 221. Tx ToneParameters Setup Menu
improves the LOL performance on the Tx1 channel. Check
the Tx2 LOL Tracking box to perform the same operation
Within Tone Parameters, the user can select the number on the Tx2 channel. To perform Tx LOL tracking calibrations,
of tones (1 or 2) for transmission on the selected Tx output. external circuitry is required to route the Tx signals back
The user has control over the tone frequency offset with through an ORx receiver input. For more details, see the
respect to the local oscillator (LO) frequency as well as Hardware Setup for External Tx LO Leakage Calibration
tone amplitude in dBFS. Select Save Tx Raw Data into a section. Note that for external Tx LOL tracking calibration,
File to store those signals in the form of text files. Before both transmitters must loop back to both observation
data can populate into those files, Play must be clicked. receivers through splitters and attenuators.
 To select user generated data files, use the Load Tx1 and  Check the Tx1 QEC Tracking box to enable a Tx quadrature
Load Tx2 buttons as follows: error correction (QEC) tracking calibration on the Tx1
 Format these files as: I sample <tab> Q sample channel. Calibration improves the QEC performance.
<new_line> per line. Each I or Q sample must be in a Check the Tx2 QEC Tracking box to perform the same
range between +32768 and −32767. operation on the Tx2 channel.
 If values of I and Q samples are smaller, check the Note that Tx1/Tx2 LOL and QEC tracking calibrations
Scaling Required box in the Load file menu to scale can only operate when the observational receive path is
the values up to numbers in the correct range. configured for use by internal calibrations. When the user
 File size is limited to 4 megasamples for each channel enables Tx outputs, the TES automatically reconfigures the
(I data = 4 megasamples maximum, and Q data = observational receive path to the internal calibration mode.
4 megasamples maximum). The ZYNQ platform, The user can change the observational receive path at any
allocates 134,217,728 MB for each buffer. Rx1, Rx2, time using the ObsRx Sniffer Data tab.
ORx, Tx1, and Tx2 have separate buffers. Each datapath  Click Tx Init Cals to run Tx initialization QEC and LO
uses four bytes (16-bit for I sample and 16-bit for Q leakage calibrations. Run these calculations first before
sample); each datapath has 33,554,432, 16-bit I/Q pairs transmitting real data. Terminate both Tx paths into
dedicated for sample collection. At a 122.88 MSPS I/Q spectrum analyzers unless only one Tx is monitored; in
data rate, this translates to 273 ms of capture time for that case, terminate the unused Tx into a 50 Ω termination
each channel. to avoid extended initial calibration times. Longer initial
calibration times occur when they are running on both
channels, and when a Tx channel is improperly terminated.

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TDD MODE  D denotes a subframe reserved for downlink transmissions
The transceiver evaluation hardware together with the  U denotes a subframe reserved for uplink transmissions
transceiver evaluation software (TES) provide capabilities  S denotes a special subframe with the three fields: DwPTS
to demonstrate time division duplex (TDD) operation. The (downlink pilot time slot), GP (guard period), and UpPTS
following sections explain the setup and operation in the TES (uplink pilot time slot)
to observe TDD operation and characterize performance. The TES provides a preset configuration for all uplink and
LTE TDD Frame Structure downlink configurations with both a 5 ms and 10 ms downlink
Preset configurations provided in the TES follow 3GPP™ to uplink switch point periodicity. All preset configurations are
specifications (TS 36.211 version 10.0.0 Release 10), in which shown in Figure 222. In the case of the 5 ms downlink to uplink
Frame Structure Type 2 is utilized for TDD operation. In this switch point periodicity, the special subframe exists in both half
configuration, each 10 ms radio frame consists of two, 5 ms half frames. In case of 10 ms downlink to uplink switch point
frames. Each half frame consists of five 1 ms subframes. The periodicity, the special subframe only exists in the first half
supported uplink and downlink configurations are listed in frame.
Table 189 where the following parameters are described for each
subframe in a radio frame:

Table 189. Uplink and Downlink Configurations (Source: Table 4.2-2; 3GPP TS 36.211, Version 10.0.0, Release 10)
Subframe Number
Uplink and Downlink Configuration Downlink to Uplink Switchpoint Timing (ms) 0 1 2 3 4 5 6 7 8 9
0 5 D S U U U D S U U U
1 5 D S U U D D S U U D
2 5 D S U D D D S U D D
3 10 D S U U U D D D D D
4 10 D S U U D D D D D D
5 10 D S U D D D D D D D
6 5 D S U U U D S U U D

DL = DOWNLINK SUBFRAME
UL = UPLINK SUBFRAME
1 FRAME = 10ms SS = SPECIAL SWITCHING SUBFRAME
1 SUBFRAME = 1ms

0 DL SS UL UL UL DL SS UL UL UL

1 DL SS UL UL DL DL SS UL UL DL

2 DL SS UL DL DL DL SS UL DL DL

3 DL SS UL UL UL DL DL DL DL DL

4 DL SS UL UL DL DL DL DL DL DL

5 DL SS UL DL DL DL DL DL DL DL
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6 DL SS UL UL UL DL SS UL UL DL

Figure 222. Graphical Representation of Uplink and Downlink Configurations in the TDD Frame

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AD9371/AD9375 System Development User Guide UG-992
Evaluation Hardware in TDD Mode The ARM processor inside the device uses the Rx enable, Tx
For time division duplex (TDD) operation, the initialization enable, and GPIO signals controlled by the ZYNQ FPGA to
calibrations are run just as they are for frequency division determine when the device is in the Rx state, Tx state, ORx
duplex (FDD) mode. After the initialization calibrations are state, and so forth. Figure 223 is a timing diagram of the Tx
complete, the TDD command is used to configure the device enable and Rx enable signals during the LTE Configuration 0
into TDD mode. type frame. The device responds based on the signal levels of
TX_ENABLE and RX_ENABLE. Note that, for proper calibration
The field programmable gate array (FPGA) on the ZYNQ
operation, the minimum required duration for the Rx enable or
platform contains a configurable TDD state machine to control
Tx enable signal is 800 μs.
the Tx enable, Rx enable, and GPIO hardware signals provided
GP 1ms
to the device. The TDD/FDD Switching tab in transceiver
evaluation software (TES) allows enabling and disabling of the
LTE UL-DL
TDD state machine and configuring of the Tx/Rx regions in the CONFIG 0 D S U U U D S U U U

TDD frame pulse to either a preset LTE™ TDD configuration or

a user defined configuration.
TX_ENABLE

OVERLAP

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RX_ENABLE

Figure 223. Timing Diagram Showing Example RX_ENABLE/TX_ENABLE

Signaling for LTE Uplink and Downlink Configuration 0

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UG-992 AD9371/AD9375 System Development User Guide
TES Interface for TDD Mode  The TES also provides a special mode, custom
Figure 224 shows the transceiver evaluation software (TES) LTETDD0 mode that configures the hardware and
time division duplex (TDD) interface tab. The parameters software with LTE TDD 0 frame timing, optimized
available within are as follows: specifically to suit the evaluation system. The TES also
provides Tx data files with timing optimized for this
 Preset allows the selection of one of eight LTE TDD Type 2
particular mode. The Resources subfolder inside the TES
frame structures (described in the LTE TDD Frame
installation folder is where the TDD0_245.76_
Structure section) as well as provides options for user
Downlink_20MHz_TM3p1.txt file is located.
specific TDD frame timing, such as custom mode or
custom LTETDD0 mode.  The Total Frame Time[μs] field determines the total
 In custom mode, all parameters described in this section length of a single TDD frame in microseconds.
can configure the desired radio frequency (RF) paths
with user specific timing.

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Figure 224. The TES TDD Interface Tab

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AD9371/AD9375 System Development User Guide UG-992
The Transmit Path section of the time division duplex (TDD) The number of parameters available in the Obs Channels section
parameters allows the control the following fields: determines operation details for the internal ORx/sniffer path.
Note that there is only one internal observation/sniffer path;
 The First Tx1 Time[μs] field determines the beginning and
therefore, only one function mentioned as follows can be active at
end of the first Tx1 subframes (or group of subframes).
any given time (see Figure 224):
 The Start Time [μs] field determines the beginning of a
subframe (or group of subframes) in a single frame.  The First ORx1 TxLO Time[μs] field determines the beginning
 The Stop Time [μs] field determines the end of a subframe and end of the first ORx1 subframes (or group of subframes).
(or group of subframes) in a single frame.  The First ORx2 TxLO Time[μs] field determines the
beginning and end of the first ORx2 subframes (or group of
The transceiver evaluation software (TES) TDD interface
subframes).
follows the convention where a subframe (or group of
 If more than one ORx1 subframe (or group of subframes) is
subframes) is enabled at the end and loops back to the
used, the Second ORx1 TxLO Time[μs] field determines the
beginning of a frame border. The subframe (or group of
beginning and end of the second ORx1 subframes (or group
subframes) beginning is marked at the end of a single frame.
of subframes).
Figure 225 shows the naming conventions used in the TES.
 If more than one ORx1 subframe (or group of subframes) is
used, the Second ORx2 TxLO Time[μs] field determines the
FIRST SECOND
STOP TIME STOP TIME beginning and end of the second ORx2 subframes (or group
FIRST SECOND
START TIME START TIME of subframes).
 The Sniffer SnfLO time[μs] field determines the beginning
and end of the sniffer subframes (or group of subframes).
 The First Internal Calibration Timing[μs] field determines
FIRST SECOND the beginning and end of the first internal calibration window.
STOP TIME
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STOP TIME
SECOND FIRST
Use the minimum duration of 800 μs for the internal calibration
START TIME START TIME
window.
Figure 225. Naming Convention Used for TDD Start/Stop Description in the TES
 The Second Internal Calibration Timing[μs] field determines
 The First Tx2 Time[μs] field determines the beginning and the beginning and end of the second internal calibration
end of the first Tx2 subframes (or group of subframes). window. Use the minimum duration of 800 μs for the
 If more than one Tx1 subframe (or group of subframes) is internal calibration window.
used, the Second Tx1 Time[μs] field determines the
The Misc section of the TDD parameters allows control of the
beginning and end of the second Tx1 subframes (or group of
following fields (see Figure 224):
subframes).
 If more than one Tx2 subframe (or group of subframes) is  The Tx path delay (+/-μs) field allows the user to delay data
used, the Second Tx2 Time[μs] field determines the beginning sent to the Tx path over the JESD204B interface in reference
and end of the second Tx2 subframes (or group of subframes). to the TX_ENABLE signal.
 The Rx path delay (+/-μs) field allows the user to delay data
The Receive Path section of the TDD parameters allows control received from the Rx path over the JESD204B interface in
of the following fields: reference to the RX_ENABLE signal.
 The First Rx1 Time[μs] field determines the beginning and  The Obs Rx Path Delay (+/-μs) field allows delaying of data
end of the first Rx1 subframes (or group of subframes). It received from the ORx path over the JESD204B interface in
follows the same convention as described in Figure 225. reference to the ORx_ENABLE signal.
 The First Rx2 Time[μs] field determines the beginning and  In TDD mode, the device evaluation hardware generates a
end of the first Rx2 subframes (or group of subframes). pulse on SMA Connector J67, located on the ZYNQ platform.
 If more than one Rx1 subframe (or group of subframes) is The External Trigger J67(μs) parameter controls the
used, the Second Rx1 Time[μs] field determines the beginning position and the width of that pulse in reference to the start
and end of the second Rx1 subframes (or group of subframes). of the TDD frame.
 If more than one Rx2 subframe (or group of subframes) is  The Loop N Times option allows control of the number of
used, the Second Rx2 Time[μs] field determines the beginning loop repetitions. The allowable range is from 1 to 15, or the
and end of the second Rx2 subframes (or group of subframes). repetitions loop until stopped by the user.
The bottom part of the TDD/FDD Switching tab in the TES
provides a diagram of the timing parameters entered in the table
shown in Figure 224. This feature allows the user to visually check
activities on the Rx, Tx, and ORx datapaths.

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UG-992 AD9371/AD9375 System Development User Guide
The time division duplex (TDD) page (see Figure 224) also The device evaluation system provides a synchronization pulse on
contains four buttons to interact with the user. A description of the ZYNQ motherboard SMA Connector J67. Use this pulse to
the functionalities provided by these buttons follows: synchronize external measurement equipment. Fine tuning of this
signal can be applied using the TES interface described in the TES
• Press SetUp TDD Timing to cause the current TDD
Interface for TDD Mode section. After all hardware is connected
configuration stop/start parameters from the table to be
properly, the user can start configuring the software.
written into the field programmable gate array (FPGA) and
sets up the state machine for operation. This button also TES Configuration
zeroes the Tx datapath, resets the Tx RAM pointer to the A number of steps must be performed before enabling TDD
start address of the data, and then reconnects the Tx RAM in mode using the TES. The following list provides guidelines for
the ZYNQ FPGA to the Tx datapath. Finally, it enables the completing these steps:
TDD state machine and starts the data. After the evaluation
system is in the TDD state, this button changes its name to 1. Using the TES interface described in the Configuring the
Disable TDD. Press Disable TDD to stop the TDD state AD9371Configuring the section, perform the following
machine. steps:
a. Select profiles for the Rx channels, Tx channels, and
• After the user sets up TDD mode and presses the SetUp
ORx or SnRx channels (if used).
TDD Timing button, the device evaluation system enables
b. Set the same frequency for the Tx PLL and the Rx PLL.
the TDD state machine, and the TDD mode becomes
In TDD mode, both the Rx and Tx operate at the same
operational. There is no data present at the Tx output until
frequency; therefore, select the same carrier frequency
the user presses the Enable Tx Data Transmit button. This
for both the Rx and Tx radio frequency (RF) phase-
button enables the data transfer in the FPGA. The Tx
locked loops (PLLs).
datapath is zeroed until the Enable Tx Data Transmit
2. Use the calibration page described in the Configuring the
button is pressed (data does not start until the Enable Tx
AD9371 section, to enable the desired calibrations.
Data Transmit button is pressed). After being placed in
3. After all configurations are complete, click Program to
TDD mode, the Tx data is sent continuously to the device
program the device evaluation system (see Figure 207).
through the JESD204B link, which is not gated by the
4. After the device evaluation system is programmed, move to
TX_ENABLE signal. Therefore, the content of the TDD Tx
the Receiver Data tab shown in Figure 218. In this tab,
data files must be properly time aligned to the TDD state
perform the following actions:
machine signals.
a. Set RxTrigger to TDD_SM_PULSE value.
• The Save TDD Frame Timing button saves TDD timing to
b. Set the number of samples in # Samples to at least
the file in a text readable format.
1 frame length (10 ms for standard LTE TDD Type 2
• The Load TDD Frame Timing button loads TDD timing
frame structures described in the LTE TDD Frame
from the previously saved TDD timing file using the save
Structure section).
TDD frame timing option.
c. Click Play.
Setting Up TDD Functionality 5. Click the Transmit Data tab shown in Figure 220. In this
Perform the following steps to operate the device evaluation tab, perform the following actions:
system and the transceiver evaluation software (TES) in a. Load the data files that are time aligned with the desired
TDD mode. LTE TDD Type 2 frame structure. The TES provides an
example data file that can be used with LTE TDD 0 Type 2
Hardware Configuration frame structure. See the TES Interface for TDD Mode
Follow the hardware configuration described instructions found section for more information.
in the Hardware Setup section. If external local oscillator (LO) b. Click the Play button.
calibrations are used, setup must contain external hardware 6. Select the desired TDD timing profile using the TES TDD/
connections between the Tx outputs and ORx inputs, as FDD Switching tab shown in Figure 224. A detailed description
described in the Hardware Setup for External Tx LO Leakage of this tab is provided in the TES Interface for TDD Mode
Calibration section. section. After all timing settings are configured, perform the
following actions:
a. Click SetUp TDD Timings.
b. Click Enable Tx Data Transmit.
If the user does not follow this sequence, the TES software
provides real-time pop-up warning messages. These messages
inform the user about possible misconfigured settings.

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AD9371/AD9375 System Development User Guide UG-992
SCRIPTING Scripts generated using the Tools > Create Script > Python function
After the user configures the device to the desired profile, a script can load, modify if needed, and run in the IronPython Script
can generate with all application programming interface (API) tab. Figure 226 shows the Iron Python Script tab after executing
initialization calls in the form of IronPython functions. The Tools the File > New function in the Iron Python Script tab. The top
> Create Script > Python function can accomplish this task. portion of the window contains IronPython script commands, and
Refer to the Tools Dropdown Menu section for more details. the bottom part of the window displays the script output.

The Iron Python Script tab allows the user to use IronPython to
write a unique sequence of events and then execute them using
the device evaluation system.

14652-353

Figure 226. Iron Python Script Window

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The Iron Python Script tab offers a number of options to manipulate The Build dropdown menu in the Iron Python Script tab, shown
the editing and execution of the Iron Python scripts. The File drop- in Figure 228, offers the user following options:
down menu in the Iron Python Script tab, shown in Figure 227,
 Run. This function executes the Iron Python script open in
offers the user following options:
the active script tab using the device evaluation hardware.
 New. This function creates a new Iron Python script that Script output is displayed in bottom side of the Iron Python
connects to the device evaluation system and checks the API script tab.
version operating on the ZYNQ hardware.  Clear Script. This function clears the Iron Python script
 Load. This function allows the user to load previously stored editing window.
Iron Python scripts.  Clear Output. This function clears the Iron Python script
 Save and Save As. These functions allow the user to store output window.
Iron Python scripts.
 Close. This function closes the currently active Iron Python
script tab.

14652-354
Figure 227. File Menu in the Iron Python Script Window

14652-355
Figure 228. Build Menu in the Iron Python Script Window

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AD9371/AD9375 System Development User Guide UG-992
IronPython Script Example
The following example, which is generated after executing the File > New function in the IronPython Script tab, connects to the device
evaluation system and then checks and displays the application programming interface (API) version operating on the ZYNQ hardware.
########################
#ADI Demo Python Script
########################

#Import Reference to the DLL

import clr
clr.AddReferenceToFileAndPath("C:\\Program Files (x86)\\Analog Devices\\AD9371
Transceiver Evaluation Software\\AdiCmdServerClient.dll")
from AdiCmdServerClient import AdiCommandServerClient
from AdiCmdServerClient import Mykonos

#Create an Instance of the Class

Link = AdiCommandServerClient.Instance

#Connect to the Zynq Platform

if(Link.hw.Connected == 1):
Connect = 0
else:
Connect = 1
Link.hw.Connect("192.168.1.10", 55555)

#Read the Version

print Link.version()

#Disconnect from the Zynq Platform

if(Connect == 1):
Link.hw.Disconnect()

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UG-992 AD9371/AD9375 System Development User Guide
When using the Iron Python window, the user can execute any 2. If the LED sequence is not as described, check the jumper
application programming interface (API) command. settings and the SW11 positions on the ZYNQ platform. If
The list of all API commands is provided by the transceiver these are correct, check if the SD card is correct and properly
evaluation software (TES). Review this list by executing Help > inserted in the J30 socket. Use the SD card provided with the
DLL Help File. When called in the IronPython window, rename evaluation system.
all API functions to reflect the Iron Python mnemonic: If there is still a problem, and the user is certain that the ZYNQ
MYKONOS_ → Mykonos. platform is operational, contact an Analog Devices representative
Add a header with a new class instance for a new connection. For at www.analog.com/en/landing-pages/001/sdr-radioverse-
example, after calling pavilion/support.html.

#Create an Instance of the Class LED Active, TES Reports That Hardware Not Connected
Link = AdiCommandServerClient.Instance At startup, if the LEDs are active but the TES reports that
The new class instance for device evaluation hardware is hardware is not connected, perform the following actions:
Link. 1. Check if the Ethernet cable is properly connected between
the PC used to run the TES and the ZYNQ platform. The
An example of an API function called using Iron Python is as
LEDs on the ZYNQ platform next to the Ethernet socket
follows. If checking the gain index for Rx1 signal chain use the
flash when the connection is active.
following API function:
2. If the cable is properly connected, check if Windows is able
MYKONOS_getRx1Gain() to communicate over the Ethernet port with the ZYNQ
The user calls the following Iron Python function (assuming that platform. Check if the IP number and open ports for the
the platform was initialized using example code described Ethernet connection used to communicate with the ZYNQ
previously): platform follow what is described in the Hardware Setup
print Link.Mykonos.getRx1Gain() section.
3. Run cmd.exe on the Window operating system and then
Troubleshooting
type ping 192.168.1.10. The user then sees a reply from the
This section provides a quick help guide if the system is not ZYNQ platform. If no reply is received, connection with the
operational. This guide assumes that the user followed all ZYNQ platform must be reexamined.
instructions and that the hardware configuration matches that 4. If connection with the ZYNQ platform is established but the
described in this user guide. TES still reports that hardware is not available, ensure that
Startup Port 22 (SSH) and Port 55555 (evaluation software) are not
No LED Activity blocked by firewall software on the Ethernet connection used
to communicate with the ZYNQ platform. Both ports must
If there is no LED activity at startup, perform the following actions: be open for normal operation. Refer to the Hardware Setup
1. Check if the board is powered properly (12 V must be section for more details.
present at the J22 input). After powering on the ZYNQ
Error Handling
platform (SW1 is turned on), the following is true:
a. The fan on the ZYNQ platform is activated. The TES provides the user with a number of error messages in
b. A number of green LEDs on the ZYNQ platform near case there are problems with hardware or software configuration.
SW1 are on with no red LEDs active on the ZYNQ The error messages the TES displays provide a description of the
platform. problem encountered by the software. If an error description
c. The ZYNQ GPIO LEDs follow the sequence described refers to the delayed-locked loop (DLL) command, refer to the
in the Hardware Operation section. API and DLL help files supplied with the TES.

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AD9371/AD9375 System Development User Guide UG-992

DPD, CLGC, AND VSWR MEASUREMENT (AD9375 ONLY)

The AD9375 device variant provides digital signal processing based on a pruned implementation of generalized memory
capabilities in the embedded ARM processor using closed-loop polynomials (GMP) that are a generalized subset of the well
feedback signals from the observation receiver channels. These known Volterra series. The simplified polynomial used in the
functions improve transmitter performance, measure system AD9375 models a large number of PA characteristics such as
output, and reduce system power consumption. The list of weak nonlinearities, temperature variation, and memory effects.
functions includes the following: digital predistortion (DPD), Integration of the DPD into the transceiver chip results in
closed-loop gain control (CLGC), and voltage standing wave significant system level cost, space, and power savings when
ratio (VSWR) measurement. compared to conventional external implementations. The DPD
This section describes the hardware setup and application implementation on the AD9375 is especially well suited for use
programming interface (API) commands used to control these in a small cell application (typically 0.1 W to 10 W at the
transmitter features. While the API descriptions are intended antenna), where significant cost savings can be achieved at
for customer software developers, the paragraphs describing the conventional performance levels.
DPD graphical user interface (GUI) can guide the evaluation of The DPD algorithm runs on the ARM processor of the AD9375
the DPD algorithm performance by the systems designers of the and calculates the coefficients and terms of the inverse PA model.
customer. The combination of this information can develop This model predistorts the digital baseband signal before digital-
system designs using these algorithms and to develop the code to-analog conversion and transmission of samples to the Tx
to integrate control into the baseband processor (BBP). upconverter (this output becomes the radio frequency (RF)
input to the PA). This computation is performed along with
DPD OVERVIEW
other transceiver operations as specified by the priorities of the
The DPD is a feature available on the AD9375 that enables ARM scheduler. The PA output is sampled using an external
users to achieve higher power amplifier (PA) efficiency while loopback to an observation receiver (ORx) port on the AD9375.
still meeting adjacent channel leakage ratio (ACLR) A simplified representation of the implementation of DPD in
requirements in the Tx signal chain for compliance with 3GPP AD9375 is shown in Figure 229.
and European Telecommunications Standards Institute (ETSI)
standards for LTE and other technologies. The DPD works on
the principle of predistorting the Tx data to cancel distortion
caused by PA compression. The DPD engine in the AD9375 is

DPD FEEDBACK
COUPLER
1, 2, 4 PA–1 Tx1 PA1 FILTER/DUPLEXER
MODEL
JESD204B

DPD FEEDBACK
COUPLER
1, 2, 4 PA–1 Tx2 PA2 FILTER/DUPLEXER
MODEL

ORx1
14652-704

AD9375 ARM ORx

ORx2

Figure 229. Representation of the Integrated DPD Implementation in AD9375

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UG-992 AD9371/AD9375 System Development User Guide
Figure 229 illustrates that the Tx1 and Tx2 digital datastreams application programming interface (API) command to tune
are first upsampled by a factor of 1, 2, or 4 depending on the modeling performance (see additionalDelayOffset in Table 193).
active Tx profile. The digital datastreams are sent via JESD204B Alignment accuracy and tuning is most important when
interfaces. Upsampling allows the baseband processor (BBP) to performing DPD on wider bandwidth signals.
transmit a lower rate on the JESD204B link than is needed for For a given x(n) and a set of three time aligned y(n) samples, a
the full digital predistortion (DPD) bandwidth, saving valuable correlation computation involving 22 generalized memory
JESD204B resources, which directly translates to power savings polynomials (GMP) nonlinear functions of the y samples is
and lower data rates in the digital front end (DFE). This performed. Sampling is random and on the fly; it can be
upsampling is done to achieve a wide enough bandwidth interrupted and resumed at any time. Samples are spread out
expansion for the DPD algorithm to obtain optimal results. and tend to be less correlated so that the features are more
DPD algorithms in general require a bandwidth 3× to 5× larger independent and their correlation converges faster than with
than the signal bandwidth to correct for power amplifier (PA) blocks of consecutive samples. In practice, less than 2048 sparse
nonlinearities that cause higher adjacent channel leakage ration captures are required for a full adaptation update. Using only 22
(ACLR) levels. The ORx input is sparsely time sampled and fed features reduces the number of required samples because the
to the ARM for DPD processing. The DPD engine then correlates number of features limits the degrees of freedom that need to be
the ORx and transceiver (Tx) samples to calculate the latest learned in the PA model.
coefficients. The DPD engine performs a brief check on model
error before updating the lookup tables (LUTs) that feed the DPD Actuator Model Configurations
correction coefficients into the DPD actuator hardware. Due to A few configurable adjustments of the DPD actuator datapath
the relatively simple implementation of this algorithm, the are also supported. These are Model 0 through Model 3 and
overall time taken to react to sudden changes in Tx waveforms is involve multiplexing various LUT outputs differently (see
relatively short and is typically less than 1 second (actual time Figure 230 to Figure 233). As shown in accompanying figures,
depends on the configurable parameters of the DPD and ARM the magnitude squared data is put through a compander that
scheduling). Certain protection criteria are designed into the has been optimized for LTE signals. The companded input is
algorithm to prevent damage to the PA due to large model errors. then used to address each of the four LUTs which contains the
DPD coefficients. The output of the LUTs is then multiplexed
Sample Capture
depending on the model configuration being used (see
Samples used to learn the latest model are captured by the ARM modelVersion in Model 2 (see Figure 232 and Table 193) is
processor using a sparse sampling technique. Whenever the recommended as a starting point for most power amplifiers
processor is available, it captures a time aligned sample set of (PAs), especially for gallium arsenide (GaAs) PAs, and gives
seven Tx samples x(n), x(n − 1) … x(n − 6) and seven good wideband performance, as does Model 3. Model 0 and
consecutive ORx samples y(n), y(n − 1) … , y(n − 6). Model 1 may achieve superior narrow-band performance in
Time alignment is performed during the device initialization by some cases. The absence of deeper delay terms in Model 0
generating a pseudonoise (PN) sequence and maximizing Tx to prevents the DPD from overfitting on narrow-band signals.
ORx correlation to within 1/16 of a sample period. Delay for Model 1 has also been shown to give marginally better
alignment is implemented with a first in, first out (FIFO) and a performance for some lateral diffused metal-oxide
1/16 sample fractional delay filter. Additional fractional sample semiconductors (LDMOS) PAs.
offsets from the initialized delay can be introduced with an
{X = 1, 2, 4}
JESDD Tx

Xt X Z–1

LUT 1
I2 + Q2
+
LUT 2
Z–1
COMPAND Yt
LUT + SATURATE
0
+
LUT 3
14652-705

Yt = f1(|Xt|) Xt + f2(|Xt – 1|) Xt + f3(|Xt|) Xt – 1

Figure 230. Model 0

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AD9371/AD9375 System Development User Guide UG-992
{X = 1, 2, 4}

JESDD Tx
Xt X Z–1

LUT 1
I2 + Q2

LUT 2 +
Z–1
COMPAND Yt
LUT + SATURATE
LUT 4
Z–1

+
LUT 3

14652-706
Yt = f1(|Xt|) Xt + f2(|Xt – 1|) Xt + f3(|Xt|) Xt – 1 + f4(|Xt – 1|) (Xt + Xt – 1)

Figure 231. Model 1

{X = 1, 2, 4}
JESDD Tx

Xt X Z–1

LUT 1
I2 + Q2

LUT 2 +
Z–1
COMPAND Yt
LUT + SATURATE
LUT 4
Z–2

+
LUT 3

14652-707
Yt = f1(|Xt|) Xt + f2 (|Xt – 1|) Xt + f3(|Xt|) Xt – 1 + f4(|Xt – 2|) Xt

Figure 232. Model 2

{X = 1, 2, 4}
JESDD Tx

Xt X Z–1

LUT 1
I2 + Q2

LUT 2 +
Z–1
COMPAND Yt
LUT + SATURATE
LUT 4
Z–2

+
LUT 3
14652-708

Yt = f1(|Xt|) Xt + f2(|Xt –1|) Xt + f3(|Xt|) Xt –1 + f4(|Xt –2|) (Xt + Xt –1 )

Figure 233. Model 3

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UG-992 AD9371/AD9375 System Development User Guide
High Amplitude Model Priors When the prior model is Gaussian distributed (for example,
One of the challenges in a digital predistortion (DPD) system is some guess vector α 0 values and the associated precision
how to handle large swings in input signal power. Immediately matrix (P) are an inverse covariance matrix), the combined
after a transition event (low to high or high to low power), the estimate of prior and new data follows Equation 57. The matrix
power amplifier (PA) amplifies in a different region of its (F) denotes the correlation feature matrix used by the DPD.
operating curve than where the training samples for the current
model were taken. At this moment, the model may be inaccurate
1

α  F H F  P  F H y  P α0  (57)
and adjacent channel leakage ratio (ACLR) performance may where:
degrade. Another model update may not occur for a few
α values are the DPD model coefficient vector.
milliseconds, and the emissions are higher during this time.
FHF is the autocorrelation of the feature matrix
P is the precision matrix.
POOR EXTRAPOLATION
WHEN HIGH AMPLITUDE
POINTS NOT INCLUDED
y is ORx sample vector.
α 0 is the prior model vector.

In the AD9375 DPD, α 0 prior coefficients can be programmed

OUTPUT

at startup or during operation (if it is known that the operating

condition of the PA is about to change) with the save and restore
DPD model application programming interface (API). The
prior model precision matrix P is scaled by a modelPriorWeight
API parameter that scales the strength in the final solution (see
modelPriorWeight in Table 193). Setting the weight higher
causes the prior model precision matrix (P) to have more
14652-709

INPUT influence than the current data when determining the final
Figure 234. Model Accuracy Deviation with High Amplitude Swings coefficients used for the lookup tables (LUTs).
Typically, the challenging situations are low to high power Optionally, the prior model coefficients can update automatically
transitions, where the model is first fit to small signal during high power data (by default, within 1 dB of the highest
measurements, then the PA operates on high power data. At Tx rms power observed by the DPD) by setting this option in
high amplitudes, the model is an extrapolation of polynomial the API or GUI default: enabled. When automatically updated,
fits at lower amplitudes. P is the diagonal portion of the correlation matrix [CYY = FHF]
If operating at low power for a long duration, leaky correlation and α 0 is the solution vector from the previous iteration of
averaging eventually diminishes high amplitude PA model DPD that included high power rms data.
information. One mitigating approach is to keep some high
power measurement data in the correlation matrix at all times,
even if the data is outdated. Stored high amplitude samples can be
stratified across fixed amplitude bins. In every model regression,
these samples can be included so that the polynomials fit these
high power sample points as well. This technique is adequate to
keep performance stable before a full update with fresh high
amplitude training samples. However, this technique generally
requires a large number of samples to work well, and it is hard
to store enough samples.
Instead, the AD9375 DPD incorporates a probabilistic prior

model on  values (DPD actuator terms) when solving for
new model coefficients, which provides information about what
the higher order coefficients should be if they are not well
defined based on the current low amplitude data.

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AD9371/AD9375 System Development User Guide UG-992
CLGC OVERVIEW VOLTAGE STANDING WAVE RATIO
The closed-loop gain control (CLGC) feature in the AD9375 MEASUREMENT OVERVIEW
enables a constant gain level to be maintained at the ORx input The voltage standing wave ratio (VSWR) on a transmission line
(total gain from Tx output to ORx input) which translates to a is defined as the ratio of the voltage maxima to the voltage minima
constant output power (POUT) at the power amplifier (PA) for a along the line. The VSWR measurement feature in the AD9375
given digital input level. The gain level is controlled by modifying facilitates the computation of this quantity by means of using
the Tx attenuation and by specifying a desired loop gain value the ORx path that is time multiplexed to measure both the
(here, gain means the net loop gain and attenuation combined, forward and reflected voltages. An example block diagram is
including all transceiver gain and attenuation blocks on-chip). shown in Figure 235.
Note that the CLGC must be enabled to establish the total Formally,
desired loop gain in the system. The CLGC feature in the AD9375
reacts to changes in the overall system loopback, which includes 1 Γ
VSWR  (58)
PA and channel gain as well as ORx gain variations. ORx gain 1 Γ
variations over time, temperature, and bandwidth are typically
where:
minimal; however, the user must refer to the AD9375 data sheet
VSWR is the voltage standing wave ratio.
to verify the tolerance over these factors in the user-specific use
R/Tx
case. Therefore, the CLGC primarily compensates for any PA Γ
gain drift over time and temperature by periodically monitoring F/Tx
and modifying the Tx attenuation to achieve a constant target where:
gain. Note that the CLGC does not track when power at the R is the reflected power.
ORx input results in a digital signal less than −39 dBFS to avoid F is the forward power measured at the ORx.
damage to the PA by either increasing the Tx power too much, Tx is the transmit power measured within the device.
or by causing CLGC instability issues due to the low ORx power Note that R and F must be calculated at different time intervals;
available (see the Other Considerations section for more therefore, the accuracy of the VSWR measurement can be
information). This compensation protects the PA if the ORx impacted by signal statistics (VSWR performance with fast
gets disconnected, or if some other component in the loopback changing and dynamic signals may vary).
fails. A minimum Tx attenuation can also be configured to
protect the PA during CLGC tracking (see
tx1AttenLimit/tx2AttenLimit parameter in Table 195).

ISOLATOR
DIRECTIONAL
AD9375 IN COUPLER OUT F
SPLITTER

Tx PATH
DPD PA SIMULATE ANTENNA
Tx CPL IN CPL OUT MISMATCH
R
TERMINATOR OPEN
TERMINATOR REFLECTION
ADJUSTABLE
VSWR MONITOR GPIO Af ATTENUATOR ATTENUATOR
ON ARM 0/1 AT 3.3V

TTL Ar ATTENUATOR
RF1
SWITCH f
ORx ORX
RF_COM r
ORx PATH RF2
14652-710

Figure 235. VSWR Measurement Setup Example

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UG-992 AD9371/AD9375 System Development User Guide

DPD GUI
The digital predistortion (DPD) graphical user interface (GUI) These features are described in subsequent sections of this user
is the primary evaluation tool for the DPD, closed-loop gain guide. In addition, the DPD, application programming interface
control (CLGC), and voltage standing wave ratio (VSWR) (API), and delay-locked loop (DLL) may be used to interact and
features. Figure 236 shows the initial DPD GUI, and Figure 237 control the DPD via Python or C#. The transceiver evaluation
shows the GUI when it is connected to the command server. All software (TES) GUI supports an IronPython tab that may be
DPD functionality can be controlled from this DPD GUI. It also used for scripting purposes.
incorporates waveform generation, CLGC, and VSWR control.

14652-711
Figure 236. Initial DPD GUI Interface—Not Connected to Command Server

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AD9371/AD9375 System Development User Guide UG-992

14652-712
Figure 237. Initial DPD GUI Interface—After Connecting to Command Server

WAVEFORM SETUP
The baseband waveform characteristics can be manipulated using the Tx Baseband Waveform section of the GUI (see Figure 238).

CARRIER SETUP

CRF SETUP 14652-713

Figure 238. Waveform Characteristics

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UG-992 AD9371/AD9375 System Development User Guide
Carrier Setup CFR Setup
The modulation is based on the wireless standard chosen from A CFR algorithm is provided along with the GUI for evaluation
the dropdown list box (LTE or Custom). The suggested modes purposes. When a target peak to average power ratio (PAPR) is
for adjacent channel leakage ratio (ACLR) conformance testing specified, the CFR algorithm clips and shapes the baseband
according to 3GPP Technical Specification (TS) 36.141 are waveform to prevent high PAPR on the Tx output. CFR is a
E-UTRA test model (E-TM) 1.1 (maximum power) and E-TM 1.2 typical prerequisite in most DPD setups to prevent the PA from
(boosting). However, more dynamic waveforms such as E-TM 2.0 going into deep saturation and to achieve higher power added
can also be selected (although not intended for ACLR compliance efficiency (PAE). To validate the CFR, view the complementary
tests). The maximum fully occupied bandwidth that can be cumulative distribution function (CCDF) of the Tx signal on a
selected is 20 MHz. However, a number of smaller waveforms spectrum analyzer. When setting the PA bias voltages (in the
may be spliced together, resulting in an aggregated configuration. reference setup, the SKY66297-11 is biased at 5.1 V), account
For example, a 4 × 5 MHz LTE waveform can be generated and for the crest factor of the test waveform. A peak to average ratio
transmitted in a 1011 configuration to give 15 MHz of signal (PAR) of 7.5 dB to 8.5 dB is typical for a 20 MHz LTE FDD
bandwidth in 20 MHz of spectrum. A baseband frequency offset waveform post CFR. Note that the CFR operations on the test
may also be specified to position the waveforms at a non-zero waveforms are precomputed in the GUI software. A CFR block
(non dc) offset from the RF local oscillator (LO). Digital back is not integrated into the AD9375 transceiver. Tweaking the
off is applied by means of the digital scale input. The digital PAR value while evaluating the AD9375 DPD for error vector
predistortion (DPD) requires digital expansion headroom to magnitude (EVM) tests is recommended because the optimal
operate; therefore, it is recommended to apply at least −3 dBFS point between choosing a high enough PAR (to achieve better
digital back off to the signal. Note that the DPD algorithm can EVM performance) while maintaining desired levels of ACLR
handle up to 40 MHz of fully occupied bandwidth while still margin and power output at the PA is user and use case
exceeding the ACLR specification for some power amplifiers dependent. Also note that, a 10 ms waveform must be used for
(PAs). However, this result is contingent upon the bandwidth full frame LTE EVM tests. While gated EVM measurements
performance of the PA because memory effects increase with may be possible and are valid, these measurements may not give
increasing signal bandwidth. The user must verify PA performance the user the same insight into PA and DPD behavior as a full
against the report published by the PA vendor. For wider frame test. Synchronization between the REF_CLK source and
bandwidths, choose an appropriate Tx DPD profile and a PA the spectrum analyzer is recommended to minimize phase
that can support video bandwidths exceeding what is required inaccuracies that affect EVM. Refer to the EVM Tests section
for the signal. PA gain flatness may also play a role in the for additional details.
achievable ACLR performance.
Custom Waveforms
Click within the dropdown menu that currently displays LTE in
Figure 238 for access to this option. Only LTE frequency
division duplex (FDD) downlink (DL) waveforms are included
in the DPD GUI library. For other technologies and special
configurations, use the Custom option and load the waveform
using a complex I/Q tabbed text file (no headers). Enter the
sample rate and ensure that the waveform time length is as
expected. Choose the scaling and the crest factor reduction
(CFR) as desired, and load the waveform while leaving all other
carrier setup controls as don’t care. If the user does not want the
DPD GUI to replicate the baseband waveform, set the Number
of Carriers to 1× mode. Choosing any other value creates copies
of the waveform around dc (LO).

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AD9371/AD9375 System Development User Guide UG-992
DPD SETUP ORx Noise Floor Correction
When a waveform is loaded, power on the power amplifier (PA) The ORx noise floor correction is a one time GUI calibration
and enable the digital predistortion (DPD). When the PA is where the noise floor on the ORx path is measured and then
powered on, the long-term evolution (LTE) waveform received correction is applied to reduce the effects of the ORx noise floor
on the ORx input is visible on the graph as a red trace. on the received signal (see Figure 239). Note that this correction
runs in the GUI and should not be confused with device
To enable the DPD, take the following steps:
calibration. Enabling this correction decreases the noise floor of
1. Click Initialize PA Cals to reset the DPD actuator and run the displayed ORx signal and generally improves the accuracy
the DPD initialization calibration. Initialization is required of the adjacent channel leakage ratio (ACLR) displayed by the
for proper time alignment of DPD samples (external delay GUI. This setting has no effect on the actual Tx output (observed
measurement). To reiterate, DPD does not function unless on, say, a spectrum analyzer) apart from a momentary loss of
this initialization step is completed. When run, the transmission while the actual calibration measurement is
AD9375 Embedded DPD Interface, PA Calibrations performed.
section, changes as shown in Figure 240.
PA1/PA2 On/Off Control
2. Check the Activate DPD box for the DPD to begin the
adaptation process (see Figure 236). Refer to the two GPIO, GPIO (PA 1) and GPIO (PA 2), buttons
shown at the top of Figure 237. These buttons control the GPIO
The pink trace in Figure 239 shows the power spectral density pins, which in turn can control PA 1 and PA 2, respectively. Use
(PSD) of the transmitter output with no DPD adaptation. The the dropdown menus attached to the GPIO (PA 1) and GPIO
yellow trace is the PA ouput PSD that is received by the ORx (PA 2) buttons to assign the GPIO_3P3 pins. Red indicates that the
channel. There should be a noticeable improvement in the PA pin is currently disabled (0), and green indicates that the pin is
output adjacent channel level rejection (ACLR) from the no toggled on (1). The text within the dropdown menu displays the
DPD case (pink trace) and the DPD on case (yellow trace). If status that the pin toggles to when clicked. Note that this is an
this not the case, or an error shows in the DPD Status section, optional feature, and the exact voltage reference or PA enabled
proceed to the Error Messages and Debug Information section. signal must be derived from the 3.3 V GPIO pin.
Tx Channel Control
The Tx Channel dropdown menu controls the channel currently
displayed within the ACLR graph and also controls the individual
settings (see Figure 236). Enabling or disabling the DPD and/or
the closed-loop gain control (CLGC) can be done separately for
both channels. Due to the multiplexed nature of the ORx, the
ORx Gain Index is also common for both channels.
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Figure 239. DPD GUI FFT Plot

Click Reset PA Cal to reset the DPD at any time. This operation
performs a full reset of the DPD actuator and reinitializes the
DPD, ensuring proper time alignment for the DPD samples.
Once the DPD resets, check DPD Adaptation to reenabled it.
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Figure 240. DPD Setup Tab

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Tx/ORx Control Tx Attenuation
The Tx / ORx Control section controls some of the parameters The Tx Attenuation box within the Tx / ORx Control section
for the Tx channel that were selected using the Tx Channel controls the attenuation for the current channel.
dropdown menu (see Figure 236).
Tx PLL Frequency
ORx Gain Index
The Tx PLL Freq: box within the Tx / ORx Control section
The ORx Gain Index box within the Tx / ORx Control section controls the frequency of operation of the current Tx channel.
can vary from 238 to 255. This value controls the ORx gain (for Modifying this value while radio calibrations are running can
both TX channels) and starting at a low value during initialization lead to poor performance with other tracking calibrations.
is recommended. Increase the gain index to a value where the Reprogramming the device (or at least rerunning initialization
AM-AM plot does not have too many outliers (AM-AM appears calibrations at the new frequency of operation) is recommended
thin and the samples are tight around the linear plot), which in such cases. For reprogramming the device or rerunning the
implies less noise on the ORx. A good gain index achieves a initialization calibrations, disconnect the digital predistortion
−12 dBFS value for a single 20 MHz LTE carrier with 7.5 dB (DPD) GUI and use the TES software or other methods (for
peak to average ratio (PAR), which allows a margin of 4.5 dB for example, Python scripts) to perform the necessary operations.
the occurrence of statistically rare samples exceeding the 7.5 dB Note that the DPD performance degrades with large frequency
peak value while not saturating the ORx, resulting in linear steps. For such cases, rerun the DPD initialization calibrations
operation. A clean, linear ORx is key to a successful DPD within the PA Calibrations section and then check off the
operation. With the default ORx gain table, the ORx gain Activate DPD box (see Figure 236).
changes n dB for an n value change in index; for example,
3 dB for a change from 238 to 241.

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Figure 241. Tx/ORx Control Section

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AD9371/AD9375 System Development User Guide UG-992
DPD Configuration
PA CALIBRATION CONFIGURATION
The DPD Configuration section of the AD9375 PA
Calibration configuration is controlled using the window shown
Calibrations Configuration window allows the user to
in Figure 242. The subsequent sections explain each setting. See
manipulate certain key parameters of the DPD engine (see
the Systems Design Considerations section for details on digital
Figure 242). For more detailed instructions on tuning DPD
predistortion (DPD) tuning procedure using some of these
using these configuration parameters, see the Systems Design
settings.
Considerations section.
General The DPD memory model dropdown menu allows the selection
Adjust the Delay Offset controls in decrements or increments of between four different polynomial models to model the PA
of 1/16 of a sample, where the fractional part is the x/16 (see the with, based on various implementations of generalized memory
dropdown menu), and the integer delay values can be adjusted polynomials (see Figure 242). See the DPD Actuator Model
using the integer dropdown menu (see Figure 242). For example, Configurations section for more details. Refer to the
chose −, 1, and 1/16 in the respective dropdown menus for a modelVersion parameter in Table 193 for a detailed description.
−1 value with a 1/16 sample delay. Changes in the delay offset
The Samples per update text box controls the number of input
values requires rerunning the DPD initialization calibration.
samples required to complete a DPD adaptation (see Figure 242).
Refer to the additionalDelayOffset parameter in Table 193 for
Refer to the samples parameter in Table 193 for a detailed
a detailed description.
description.
The linear feedback shift register (LFSR) level and iterations
The Automatically reject outlier samples box is deprecated
control the power level of the wideband signal that is sent
and its use is not supported (see Figure 242). Refer to the
during the DPD initialization calibration. PN-Seq Level is a
robustModeling parameter in Table 193 for more details.
fixed value for information only (see Figure 242). Refer to the
pathDelayPnSeqLevel parameter in Table 193 for a detailed
description.

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Figure 242. AD9375 PA Calibrations Configuration Window

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UG-992 AD9371/AD9375 System Development User Guide
Enable the Update saved model at high Tx RMS box to allow The DPD algorithm works by minimizing the Tx to ORx sample
the DPD to update a separate high power power amplifier (PA) error. However, due to PA or external loop spectral asymmetries,
model that remembers high amplitude PA characteristics and the adjacent channel leakage ratio (ACLR) performance may be
improves adjacent channel leakage ratio (ACLR) in dynamic power worse on certain sides of the desired signal. The AD9375 DPD
conditions (see Figure 242). Refer to the highPowerModelUpdate includes a 4-tap finite impulse response (FIR) filter that can
parameter in Table 193 for a detailed description. help shape the error such that the DPD focuses more on the
The Saved model weight text box controls how much weight or error on the poorer performing side of the spectrum. This
influence the high power startup power amplifier (PA) model is frequency-weighting is achieved by adding zeros and creating
given when computing the final applied predistortion function an FIR filter that is overlaid on the ACLR spectrum of the DPD
(see Figure 242). Refer to the modelPriorWeight parameter in GUI as a red curve. By default, one zero is placed at (64 + 0j) on
Table 193 for a detailed description. the complex Z plane to help minimize the Δ-Σ shaped noise at
the ORx band edges. Additional zeros can be placed to create
The update saved model at high Tx RMS parameter allows different filter shapes depending on how the user wants to
enabling or disabling of the DPD prior model update. direct the attention of the DPD. Deeper notches instruct the
The Model averaging factor text box controls how much weight DPD that it must focus less on the errors in the notched out
the previous DPD correlations can exert on the current adaptation. part of the spectrum, while the response shapes outside of the
Refer to the damping parameter in Table 193 for a detailed desired signal bands make the DPD focus more on those parts
description. of the spectrum.
Increase the value in the Model error threshold text box if For example, see Figure 242 and note the multicarrier 3 × 5 MHz
additional model errors must be allowed in a DPD adaptation 101 configuration. The locations of the zeros indicate that the DPD
before error code 0x09 occurs. This value is not configurable via must focus more on the ACLR side of the spectrum rather than the
the application programming interface (API). error in the carriers themselves. The improvement for tougher
Adjust the value in the AM-AM Outlier threshold text box to cases can be as good as 2 dB to 3 dB in ACLR performance.
control the occurrence of the AM_AM_OUTLIERS error (0x0A). Note, however, that some error vector magnitude (EVM)
Generally, this threshold is only violated when the PA is deep into degradation may occur due to the lack of focus of the DPD
compression and heavily saturated. Refer to the outlierThreshold on the carrier themselves. As always, tuning the DPD is a
parameter in Table 193 for a detailed description. systems choice and must be done with due consideration to
the permissible limits of performance tolerance for all systems
metrics, 3GPP mandated or otherwise. Refer to the numWeights
and weights[3] parameters in Table 193 for a detailed description.

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AD9371/AD9375 System Development User Guide UG-992
ERROR MESSAGES AND DEBUG INFORMATION calibration calibration, even if DPD is disabled (that is, the
The DPD GUI has the capability to display the operating status tracking calibration mask does not contain a DPD calibration).
of the DPD adaptation. If an error occurs during an adaptation, Current model error (see Figure 243) is a measure of how close
the error status is displayed in the DPD Status window. Click the current PA model is to the actual PA. This error is calculated
the error status to open the debug message. The DPD Status before the DPD applies the newly learned coefficients to predict
window displays the total number of DPD adaptations that have the PA output from the current input samples for a short instance
occurred along with the current model error. of time to calculate this error. A threshold for this model error
Total Adaptations (see Figure 243) shows the number of can be set in the DPD Configuration window. If the error
successful DPD adaptations that have occurred since the last exceeds this threshold, DPD adaptation does not occur, and the
DPD initialization calibration (Reset PA Cal). If an error occurs DPD returns an ERROR 9 (MODEL_ERROR_TOO_HIGH).
during a DPD iteration, the total number of adaptations does not For more information on the DPD, closed-loop gain control
count up. For an erroneous adaptation, an error status appears (CLGC), and voltage standing wave ratio (VSWR) status codes,
and the DPD adaptation is not applied to the actuator. respectively, and troubleshooting options, see Table 194, Table 196,
It is important to note that the last known good model is always and Table 198.
stored in the DPD actuator and applied to the Tx samples until
the DPD hardware is reset using a DPD initialization

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Figure 243. DPD Status Window and Status Codes

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DPD API
This section describes all the application programming It is important to note the following:
interface (API) data structures and functions that are associated
• Running the external initialization calibrations (external
with the digital predistortion (DPD) feature.
LO leakage (LOL), DPD, CLGC, and VSWR initialization
ARM SETUP COMMANDS calibrations) in a single execution of the MYKONOS_
A few ARM setup commands are introduced in the following runInitCals(…) results in running the initialization
subsection that are ancillary to DPD, closed-loop gain control calibrations in the following order: VSWR, LOL, DPD, and
(CLGC), and voltage standing wave ratio (VSWR) operation. CLGC.
• It is recommended that the user always perform DPD,
The following API functions enable the use of the DPD, CLGC,
CLGC, and VSWR initialization calibrations at the Tx
and VSWR calibrations. These functions must be called in
attenuation value that corresponds to the final rated power
order to successfully execute these calibrations.
amplifier (PA) operating power conditions. Following this
MYKONOS_runInitCals (…) recommendation improves the path delay estimation of the
mykonosErr_t calibrations in general and reduces variability from run to
MYKONOS_runInitCals(mykonosDevice_t run because the signal noise ratio (SNR) at ORx is better
*device, uint32_t calMask) when there is more of the pseudonoise (PN) sequence to
Description correlate with. A small deviation in the estimated path delay
can cause a DPD performance degradation of up to 3 dB.
This function performs the ARM initialization calibrations (init
• When using an older ARM version or when running
cals) that are prerequisites for the calibrations present in the
initialization calibrations differently than is suggested in
enableMask enabled by MYKONOS_enableTrackingCals(…).
the first bullet, it is important to remember that VSWR
This command must be called when the device is in the
initialization calibration sets up the path observed by the
radioOff state.
ORx switch (forward or reflected), and therefore, must be
Parameter executed before the other external initialization
• *device: This is a structure pointer for the device data calibrations, such as the LOL, DPD, and CLGC
structure. calibrations, which are calibrations that require knowledge
• calMask: Initialization calibration mask for initializing the of the external loopback path delay. For example, if each of
different calibrations. the external initialization calibrations are run separately,
the following sequence is recommended: VSWR, LOL,
Table 190. Initial Calibrations Bit Mask DPD, and CLGC initialization calibrations. It is important
calMask Bit description to not override the VSWR switch control by writing to the
0 Tx baseband filter GPIO pin that is used by the VSWR calibration.
1 ADC runner
2 transimpedance amplifier (TIA) 3 dB corner
3 DC offset
4 Tx attenuation delay
5 Rx gain delay
6 Flash calibration
7 Path delay
8 Tx local oscillator (LO) leakage internal
9 Tx LO leakage external
10 Tx quadrature error correction (QEC) initialization
11 Loopback Rx LO delay
12 Loopback Rx QEC initialization
13 Rx LO delay
14 Rx QEC initialization
15 DPD initialization
16 CLGC initialization
17 VSWR initialization

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AD9371/AD9375 System Development User Guide UG-992
MYKONOS_enableTrackingCals(…) The host must set the ORx path source to OBS_INTERNALCALS
mykonosErr_t by calling MYKONOS_setObsRxPathSource(…). Setting the
MYKONOS_enableTrackingCals(mykonosDevice_t ORx path source to OBS_INTERNALCALS enables scheduling
*device, uint32_t enableMask) of regular tracking radio calibrations, such as Tx QEC and
Description Tx local oscillator leakage (LOL) tracking along with DPD
tracking in either frequency division duplex (FDD) or time
This function sets which ARM tracking calibrations are enabled division duplex (TDD), ARM command or pin mode. See the
during the radioOn state. The command must be called during Observation Receiver (ORx) section for ORx channel setup
the radioOff state. Any of the closed-loop gain control (CLGC), details. Performing the previously mentioned steps enables the
and voltage standing wave ratio (VSWR), and digital predistortion ARM to access ORx data and initiates the DPD, CLGC, and
(DPD) tracking calibrations may be enabled using this function VSWR tracking and measurement processes.
by selecting the appropriate value for the tracking calibration mask.
MYKONOS_setAllTrackCalState(…)
Parameters
mykonosErr_t
• *device: This is a structure pointer for the device data MYKONOS_setAllTrackCalState(mykonosDevice_
structure. t *device, uint32_t trackCals)
• enableMask: This is the tracking calibration mask for Description
enabling the different tracking calibrations. Options are
This function sets which ARM tracking calibrations are allowed
shown in Table 191.
to track during the radioOn state (also known as the suspend/
Table 191. Tracking Calibration Bit Mask resume or pause/resume feature). The command can be called in
enableMask Bit Description either the radioOff or radioOn state, with the primary intent
0 TRACK_RX1_QEC being that this function be used by the user in the radioOn state
1 TRACK_RX2_QEC to quickly suspend or resume calibrations. Note that the state of
2 TRACK_ORX1_QEC the calibration (paused: no updates scheduled by ARM, or
3 TRACK_ORX2_QEC resumed: normal expected behavior) is sticky between the
4 TRACK_TX1_LOL radioOff and the radioOn states when in a tracking state (and
5 TRACK_TX2_LOL even if the respective initialization calibrations are performed).
6 TRACK_TX1_QEC It is the responsibility of the host to control the state of the
7 TRACK_TX2_QEC calibrations. By controlling the trackCals bit mask, calibrations
8 TRACK_TX1_DPD can be suspended (bit value of 0) or active/resumed (bit value of 1).
9 TRACK_TX2_DPD Parameters
10 TRACK_TX1_CLGC
• *device: This is a structure pointer for the device data
11 TRACK_TX2_CLGC
structure whose calibrations are to be suspended or
12 TRACK_TX1_VSWR
resumed.
13 TRACK_TX2_VSWR
• trackCals: The value specified by this argument is some
subset of the currently enabled tracking calibration mask
• To ensure that the tracking calibrations runs correctly,
bits that controls which calibrations are to suspended or
enforce the following sequence:
resumed. An error code is returned if the user attempts to
1. Run initial calibrations with the xxx_INIT calibration bits resume a calibration that is not part of the active tracking
enabled in the calmask during the initialization process. calibration bit mask defined by enableMask in MYKONOS_
The application programming interface (API) is enableTrackingCals(…). For the allowed bit mask values,
MYKONOS_runInitCals(…). refer to Table 191.
2. Set tracking calibration mask to include the TRACK_
TX1_DPD, TRACK_TX2_DPD, TRACK_TX1_CLGC,
TRACK_TX2_CLGC, TRACK_TX1_VSWR, and/or
TRACK_TX2_VSWR mask bits, depending on the desired
calibrations for each channel.
3. Note that the TRACK_ORX1_QEC and the TRACK_
ORX2_QEC mask bits must be set in order to have
successful DPD, CLGC, and VSWR tracking.
4. The API is MYKONOS_enableTrackingCals(…).

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MYKONOS_getAllTrackCalState(…) DPD API DATA STRUCTURES
mykonosErr_t The data structures associated with the digital predistortion (DPD)
MYKONOS_getAllTrackCalState(mykonosDevice_ functionality follow.
t *device, uint32_t *trackCals)
int8_cpx
Description
The int8_cpx structure is used within the mykonosDpdConfig_t
This function reads back the ARM tracking calibrations that are structure to hold an int8_t complex number that is used in the
allowed to track during the radioOn state (also known as the weights member described in Table 193.
suspend/resume or pause/resume feature). The command can
be called in either the radioOff or the radioOn state, with the
primary intent being that this function be used by the user in
the radioOn state. Note that the state of the calibration (paused:
no updates scheduled by ARM, or active/resumed: normal
expected behavior) is sticky between the radioOff and the
radioOn states when in a tracking state (and even if the
respective initialization calibrations are performed). It is the

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responsibility of the host to control the state of the calibrations.
Parameters Figure 244. int8_cpx Structure

 *device: This is a structure pointer for the device data typedef struct
structure whose calibrations are to suspended or resumed. {
 *trackCals: The value returned in this pointer shows int8_t real;
currently enabled tracking calibration mask bits that int8_t imag;
represent which calibrations have been suspended (bit
} int8_cpx;
value of 0) or active/resumed (bit value of 1). The active
tracking calibration bit mask defined by enableMask in
Table 192. int8_cpx Structure Member Description
MYKONOS_enableTrackingCals(…) can be used to
Structure
determine which bit mask values shown in Table 191 are Member Valid Values Description
available.
real −128…+127 The real part of the
complex number used in
the weights member of the
mykonosDpdConfig_t
structure.
imag −128…+127 The imaginary part of the
complex number used in
the weights member of the
mykonosDpdConfig_t
structure.

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AD9371/AD9375 System Development User Guide UG-992
mykonosDpdConfig_t typedef struct
mykonosDpdConfig_t is the main data structure that stores all {
of the parameters relevant to the DPD configuration. This uint8_t damping;
information is loaded into the ARM memory using the uint8_t numWeights;
MYKONOS_configDpd() function before running the DPD
uint8_t modelVersion;
initialization or tracking calibrations. The unified modeling
language (UML) representation of the structure is shown in uint8_t highPowerModelUpdate;
Figure 245. uint8_t modelPriorWeight;
uint8_t robustModeling;
uint16_t samples;
uint16_t outlierThreshold;
int16_t additionalDelayOffset;
uint16_t pathDelayPnSeqLevel;
int8_cpx weights[3];
} mykonosDpdConfig_t;
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Figure 245. mykonosDpdConfig_t UML Representation

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UG-992 AD9371/AD9375 System Development User Guide
Table 193. AD9375 Digital Predistortion (DPD) Configuration Structure Member Description
Structure Member Valid Values Description
damping 0…15 1/(2DAMPING + 8) is a weighting factor multiplied to past DPD correlations when
computing a new DPD correlation matrix for every DPD iteration. The default
value of this factor is 5, resulting in a 1/8192 value. This parameter may be viewed
as a leakage factor to avoid overtraining the model on a new set of samples while
retaining some memory or history of the previous correlations (this is because the
past correlations are accumulated in a leaky fashion). A 0 value results in infinite
damping (that is, past correlation values are accumulated forever with no leakage). It is
recommended that this parameter be adjusted in conjunction with the samples
parameter. Note that DPD performance can vary quite a bit for dynamic signals
when adjusting this parameter.
numWeights 0…3 Number of weights to use in the weights[3] member of this structure for frequency
weighting of the DPD error.
modelVersion 0…3 DPD model version: one of four different polynomial models. The choice of the
optimum model usually depends on the power amplifier (PA) and operating
bandwidth.
highPowerModelUpdate 0, 1 A 1 value for this member results in the update of a separate high power or prior
PA model that is used to remember the high amplitude PA characteristics and to
improve the adjacent channel leakage ratio (ACLR) in dynamic power conditions.
Updates to the high power model are made when the Tx rms power is within 1 dB
of the historical peak Tx rms. During periods of lower Tx power, the DPD algorithm
includes the stored higher power model for computing the PA predistorter model
if the DPD has ever tracked successfully while this parameter was high. During low
to high power transitions, DPD already has adaptation coefficients for the Tx higher
powered samples improving dynamic performance. Setting this parameter to 0
disables updates to the prior model and uses the initial loaded model instead (if
one was provided at startup). Default: 1.
modelPriorWeight 0…32 weight = 2modelPriorWeight + 10. This parameter controls how much weight or influence
the high power/startup PA model is given when computing the final applied
predistortion function. A larger value causes adaptation to move less from the
high power/startup PA model, limiting low power ACLR improvement but
improving high power ACLR during fast low to high power transitions. Default: 20.
robustModeling 0, 1 Note that this feature has been marked for deprecation and use of this feature is
discouraged.
samples 64…32768 Number of Tx and ORx I/Q samples to capture. Default is 512. The DPD algorithm
computes the model coefficients by sparsely sampling the Tx and ORx data, and
this parameter controls the number of capture blocks required per update.
Reducing the number of samples per update results in faster processing at the risk
of possible reduced performance (depending on input waveform and PA
conditions).
outlierThreshold 1…8192 This is the threshold for samples to be discarded if they are outside of the 1:1 line
on the AM-AM plot. Default: 4096 (50% of 8192). Adjust this input to control the
occurrence of the AM_AM_OUTLIERS (0x0A) DPD status message/error from the
ARM. Generally, this threshold is exceeded only when the PA is deep into compression
and heavily saturated. Too many outliers (higher than percentage of samples set
using this parameter) cause the current model adaptation to be discarded.
Increase the threshold to force the DPD to adapt to a more nonlinear PA state
(performance varies according to PA).
additionalDelayOffset −64…+64 This parameter adds or reduces delay to the external sample delay assessed
during the sample time alignment process. Resolution of additional delay is 1/16
of an ORx sample. Delay Offset = additionalDelayOffset/16. Using 16 for this
parameter implies a 1-sample delay. Default: 0. By default, the DPD algorithm in
the AD9375 begins the PA model from the peak in the cross correlation between
the PA input and output samples (using the sample time alignment delay
determined during the DPD initialization calibration). However, for modeling
some PAs, it may be beneficial to offset the model slightly from the correlation
peak by a fixed amount (usually a fraction of a sample). In many PAs, the peak in
the impulse response is not the lead (zero lag) coefficient. Time alignment offset
allows the learning model impulse terms before this peak and can improve
modeling accuracy and DPD performance. Changes in the delay offset values
require rerunning the DPD initialization calibration.

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AD9371/AD9375 System Development User Guide UG-992
Structure Member Valid Values Description
pathDelayPnSeqLevel 1…8192 Amplitude level of broadband pseudonoise (PN) sequence sent out during DPD
initialization calibration. Default: 255 (−30 dBFS = 20 log10(value/8192)). Analog
Devices recommends using the default value for this parameter unless the PA is
highly sensitive to broadband radio frequency (RF) input tones. Note that the user
must always perform the DPD, CLGC, and VSWR initialization calibrations at the Tx
attenuation value that corresponds to the final rated PA operating power conditions,
which improves the estimation of the path delay and reduces variability from run
to run.
weights[3] −128…+127 DPD model error frequency weighting. The DPD algorithm works by minimizing
the Tx to ORx sample error. The AD9375 R1 DPD includes a 4-tap FIR filter that can
help shape the error such that DPD focuses more on the error at certain
frequencies. Each element of the weights member holds a Z-plane zero location
that will shape the filter response of the FIR to influence the frequencies at which
DPD is most focused. By default, one zero is placed at (64 + 0j) on the complex-Z
plane to help minimize the Δ-Σ shaped noise at the ORx band edges. Refer to the
PA Calibration Configuration section for more information on this parameter.

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mykonosDpdStatus_t
The mykonosDpdStatus_t structure contains four members that typedef struct
provide information on the status of the digital predistortion {
(DPD) calibration. This structure can be used as an error
uint32_t dpdErrorStatus;
checker and debug tool for the DPD.
uint32_t dpdTrackCount;
uint32_t dpdModelErrorPercent;
uint32_t dpdExtPathDelay;
} mykonosDpdStatus_t;

14652-721

Figure 246. mykonosDpdStatus_t Structure

Table 194. AD9375 DPD Status Structure Member Description

Structure Member Value Description
dpdErrorStatus 0 No error: DPD operation is normal.
1 ORx disabled: The observation receiver (ORx) for this channel is currently disabled.
2 Tx disabled: The transmitter for this channel is currently disabled.
3 Path delay not setup: indicates that the process for sample alignment arrived at
an invalid answer. This error is most commonly caused by a Tx or ORx that is not
physically connected or a PA that is switched off. Ensure that everything is properly
connected, and that the PA is turned on, and then rerun the DPD initialization.
4 DPD initialization not run: must run DPD initialization calibration for the DPD to
start adaptations.
5 ORx signal too low: The ORx signal is lower than −28 dBFS. Ensure that the PA is
on and all SMA cables are connected properly. Consider increasing the ORx gain
index or removing the physical attenuation between the PA and ORx input.
6 ORx signal saturated: The ORx measured too many samples above the configured
saturation threshold. Consider reducing the ORx gain index or adding attenuation
between the PA and the ORx input. The saturation threshold level is not configurable
by application programming interface (API) and is defaulted to 87% of 0 dBFS.
When this error occurs, the DPD zeroes out the correlators and starts over to
prevent corrupting future adaptations.
7 Tx signal too low: The Tx signal is off or has too little power for DPD adaptation to
proceed. Consider increasing the digital Tx signal power. Threshold is −28 dBFS.
8 Tx signal saturated: The post DPD Tx signal amplitude exceeds the configured
saturation threshold. Decrease the Tx waveform digital peak value (scaling) to
allow for sufficient amplitude expansion during predistortion (for example,
−3 dBFS). When this error occurs, the DPD zeroes out the correlators, zeroes the
prior model used, and starts over to prevent corruption of future adaptations.
9 Model error high: The DPD model error is higher than 10%, and the calculated
model was not applied to the DPD actuator. This condition can occur if the PA is
highly nonlinear, or the signal chain is adjusted while DPD adaptation is still being
performed. When this error occurs, the DPD zeroes out the correlators and starts
over to prevent corruption of future adaptations.
10 AM-AM outliers: Too many PA input to output samples were out of the configured
linearity boundaries. Consider backing off the PA or adjusting the dpdOutlierThreshold
in mykonosDpdConfig_t (see Table 192). When this error occurs, the DPD zeroes
out the correlators and starts over to prevent corruption of future adaptations.

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AD9371/AD9375 System Development User Guide UG-992
Structure Member Value Description
11 Invalid Tx profile.
12 ORx quadrature error correction (QEC) disabled: Set the calmask bits to enable ORx
QEC1/QEC2 tracking calibrations because the DPD relies on the assumption that
the ORx is a clean representation of the power amplifier (PA) output.
dpdTrackCount 0..0xFFFFFFFF Number of times the DPD has successfully run since DPD initialization calibration.
dpdModelErrorPercent 0..1000 Percent error of PA model ×10 to include 1 decimal place.
dpdExtPathDelay 0..0xFFFFFFFF External path delay from Tx output to ORx input, at 1/16 sample resolution of the
ORx sample rate. Calculate true value by dividing this member.

DPD FUNCTIONALITY API FUNCTIONS Parameters

The application programming interface (API) functions • *device: This is the device data structure pointer from
associated with the digital predistortion (DPD) functionality which the DPD status is read back.
follow. Refer to the Tracking Calibrations section for more • txChannel: Input argument to set which Tx channel the
information on setting up the calibration from an ARM system function reads back the DPD status for. Valid enumeration
standpoint. values are Tx1 and Tx2 only.
MYKONOS_configDpd (…) • *dpdStatus: This is a pointer to the structure that contains
mykonosErr_t the returned DPD status information.
MYKONOS_configDpd(mykonosDevice_t *device) MYKONOS_saveDpdModel(…)
Description mykonosErr_t
This function call configures the device with the parameters in MYKONOS_saveDpdModel(mykonosDevice_t
*device, mykonosTxChannels_t txChannel,
the DPD data structure, mykonosDpdConfig_t. This function
uint8_t *modelDataBuffer, uint32_t
also performs some sanity checks to the data parameters (range
modelNumberBytes)
and ARM state checks) in the mykonosDpdConfig_t data
structure. This function can be called when the device is in Description
either the radioOn or radioOff state. However, not all parameters This function reads a copy of the DPD prior model (or high Tx
in the mykonosDpdConfig_t structure can be changed in power model) from the ARM memory and saves it to the user
radioOn state. This function must be called in the radioOff state memory specified by the modelDataBuffer pointer. The device
when attempting to change the additionalDelayOffset and must be in the radioOff state to call this function.
pathDelayPnSeqLevel parameters. Changes to the latter
Parameters
parameters do not take effect unless modified in a radioOff
state, and are ignored by the API and ARM. • *device: This is the device data structure pointer from
which the DPD model is saved.
MYKONOS_getDpdConfig(…)
• txChannel: specifies the Tx channels for which the DPD
mykonosErr_t models are saved. Valid values are TX1, TX2, and
MYKONOS_getDpdConfig(mykonosDevice_t
TX1_TX2.
*device)
• The user must provide the correct buffer size with the
Description modelNumberBytes argument. 172 bytes per channel are
This function reads the DPD config structure from the ARM expected.
memory and updates the device → tx → dpdConfig data structure.
There are no radio state dependencies for this function.
MYKONOS_getDPDStatus(…)
mykonosErr_t
MYKONOS_getDPDStatus(mykonosDevice_t
*device, mykonosTxChannels_t txChannel,
mykonosDpdStatus_t *dpdStatus)
Description
This function reads back the DPD calibration status from the
ARM processor and returns the result to the mykonosDpdStatus_t
structure.

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UG-992 AD9371/AD9375 System Development User Guide
MYKONOS_restoreDpdModel (…) Parameters
mykonosErr_t • *device: This is the device data structure pointer whose
MYKONOS_restoreDpdModel(mykonosDevice_t DPD actuator is being bypassed.
*device, mykonosTxChannels_t txChannel,
uint8_t *modelDataBuffer, uint32_t • txChannel: specifies the Tx channels for which the DPD
modelNumberBytes) actuators must be controlled. Valid values are TX1, TX2,
and TX1_TX2.
Description
• By setting the argument actState to 0, the DPD actuator for
This function writes a copy of the user specific digital the specified txChannel is bypassed. A 1 for actState reenables
predistortion (DPD) model to the ARM memory, pointed to by the use of the DPD actuator for the desired channel.
the modelDataBuffer pointer, and instructs the ARM to install
that DPD model into the ARM memory as a prior model. The MYKONOS_resetDpd (…)
device must be in the radioOff state to call this function. Note mykonosErr_t
that resetting or reinitializing the device overwrites the restored MYKONOS_resetDpd(mykonosDevice_t *device,
DPD model data. mykonosTxChannels_t txChannel, uint8_t
reset)
Parameters
Description
• *device: This is the device data structure pointer on to
This function enables the user to reset the DPD actuator for a
which the DPD model is restored or loaded.
given Tx channel. The user can call this function in the radioOn
• txChannel: specifies the Tx channels for which the DPD state. However, it is recommended that the user suspend (pause)
models are loaded. Valid values are TX1, TX2, and the DPD calibration before using this function to synchronize
TX1_TX2. all internal ARM scheduler tasks. The DPD calibration can be
• The user must provide the correct buffer size with the resumed when this function successfully executes.
modelNumberBytes argument. 172 bytes per channel are
expected. The model data pointed to by the modelDataBuffer Parameters
pointer must contain modelNumberBytes, resulting in an • *device: This is the device data structure pointer whose
error otherwise. DPD actuator is being bypassed.
MYKONOS_setDpdActState (…) • txChannel: specifies the Tx channels for which the DPD
actuators must be controlled. Valid values are TX1, TX2,
mykonosErr_t
and TX1_TX2.
MYKONOS_setDpdActState(mykonosDevice_t
*device, mykonosTxChannels_t txChannel, • reset: A 1 resets the DPD actuator and the prior model.
uint8_t actState) Calling this function with a reset value of 1 is equivalent to
performing a DPD initialization calibration but without
Description
performing the external path delay measurement in
This function enables the user to bypass the DPD actuator on a radioOff mode that is typical of the DPD initialization
given Tx channel. This function can be called in the radioOn calibration (no PN sequence is transmitted). A 0 is not a
state. However, it is recommended that the user suspend valid choice.
(pause) the DPD calibration before using this function to
synchronize all internal ARM scheduler tasks. The DPD Note that a 2 for this argument is reserved for future use.
calibration can be resumed when this function has been
successfully executed.

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AD9371/AD9375 System Development User Guide UG-992

CLGC TRACKING CALIBRATION

To enable the closed-loop gain control (CLGC), click The Tx RMS and ORx RMS are a measure of the rms value of
Initialize/Reset PA Cals. Next, check off the CLGC box to the digital power measured by the CLGC at the Tx or ORx
allow the CLGC to start measuring the gain of the Tx to ORx measurement points. Refer to the txRms and orxRms
path and to update statuses. Note that tracking (applying parameters in Table 196 for a detailed description.
control) does not begin until the selection of the Track box A description of the Status codes can be found in Table 196.
shown in Figure 248.
CLGC CONFIGURATION
The value in the Desired Gain box is the desired loopback gain
that is usually negative when the total loop attenuation is higher See Figure 242 to see the following CLGC digital predistortion
than the total loop gain. Refer to the tx1DesiredGain/ (DPD) GUI settings.
tx2DesiredGain parameters in Table 195 for a detailed The Tx Atten Min Limit is the absolute minimum attenuation
description. allowed during CLGC tracking. This box allows some level of
The value displayed in the Current Gain box is the current PA protection from the CLGC gain going too high. Refer to the
loopback gain. Refer to the currentGain parameter in Table 196 tx1AttenLimit and tx2AttenLimit parameters in Table 195 for a
for a detailed description. detailed description.

The Track check box allows the CLGC to control the loop gain The Control Ratio field controls the rate at which the CLGC
by changing the Tx attenuation. When first enabling the CLGC tracks the gain changes. Refer to the tx1ControlRatio and
using the DPD GUI (and not via the application programming tx2ControlRatio parameters in Table 195 for a detailed
interface (API)-/delay locked loop (DLL)-based scripts), the description.
current gain is set as the desired gain (that is, the previously The Tx Rel Threshold feature lets the CLGC flag rapid changes
configured desired gain value is overwritten). Refer to the from the target desired gain. Check the box next to this feature
allowTx1AttenUpdates and allowTx2AttenUpdates parameters to enable the relative threshold. Refer to the tx1RelThreshold
in Table 195 for a detailed description. and tx2RelThreshold parameters in Table 195 for a detailed
description.

14652-722

Figure 247. Closed-Loop Gain Control (CLGC) Tracking

14652-723

Figure 248. CLGC Control and Status Display

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UG-992 AD9371/AD9375 System Development User Guide

CLGC API
This section describes all of the application programming typedef struct
interface (API) data structures and functions that are associated {
with the closed-loop gain control (CLGC) feature.
int16_t tx1DesiredGain;
CLGC API DATA STRUCTURES int16_t tx2DesiredGain;
The data structures associated with the CLGC functionality are uint16_t tx1AttenLimit;
listed in the following subsections. uint16_t tx2AttenLimit;
mykonosClgcConfig_t uint16_t tx1ControlRatio;
The mykonosClgcConfig_t structure is the main data structure uint16_t tx2ControlRatio;
that stores all parameters for the CLGC configuration. The uint8_t allowTx1AttenUpdates;
information in this structure is loaded into the ARM using the
uint8_t allowTx2AttenUpdates;
MYKONOS_configClgc() function. The unified modeling
language (UML) representation of the structure is shown in int16_t additionalDelayOffset;
Figure 249. uint16_t pathDelayPnSeqLevel;
uint16_t tx1RelThreshold;
uint16_t tx2RelThreshold;
uint8_t tx1RelThresholdEn;
uint8_t tx2RelThresholdEn;
} mykonosClgcConfig_t;
14652-724

Figure 249. mykonosClgcConfig_t UML Structure

Table 195. AD9375 CLGC Config Structure Member Description

Structure Member Valid Values Description
tx1DesiredGain/tx2DesiredGain −10000…+10000 Value given by 100 × (Desired Gain in dB). Represents total
gain and attenuation from AD9375 Tx1/Tx2 output to
ORx1/Orx2 input in (dB × 100). Default: 0.
tx1AttenLimit/tx2AttenLimit 0…40 No typical value suggested; user must define value and can be
set in increments of 1 dB from 0 dB to 40 dB. Parameter depends
on power amplifier (PA) and external loopback attenuation.
Value is set to protect PA by making sure that Tx1/Tx2
attenuation is not reduced less than the limit during CLGC
tracking. Default value is 0.

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AD9371/AD9375 System Development User Guide UG-992
Structure Member Valid Values Description
tx1ControlRatio/tx2ControlRatio 1…100 This parameter controls the control logic for the CLGC tracking
on Tx1/Tx2. Higher values indicate a more aggressive change
in the direction of the gain change. This parameter can be seen
as a fraction of the gain change that is proportional to the
difference between current and desired gains. Default value: 75
which corresponds to a control ratio of 75%.
allowTx1AttenUpdates/allowTx2AttenUpdates 0, 1 A 0 implies that the CLGC calibration runs but that the Tx1/Tx2
attenuation values do not get updated. User can still read back
power measurements. A 1 implies that the CLGC calibration
runs, and Tx1/Tx2 attenuation values automatically update.
additionalDelayOffset −64…+64 This parameter adds or reduces delay to the external sample
delay assessed during the sample time alignment process
performed with the CLGC initialization calibration. Resolution
of additional delay is 1/16 of a sample. Delay offset =
additionalDelayOffset/16. Using 16 for this parameter implies a
1-sample delay. Default: 0. Changes in the delay offset values
requires rerunning the CLGC initialization calibration. Because
the effect of tuning this value on calibration performance may
not be immediately apparent, it is recommended that a value
similar to that in the mykonosDpdConfig_t structure be used
here as well.
pathDelayPnSeqLevel 0…8192 Amplitude level of broadband pseudonoise (PN) sequence
sent out during CLGC initialization calibration. Default: 255 (−30
dBFS = 20log10(Value/8192). Analog Devices recommends
using the default value for this parameter unless the PA is
highly sensitive to broadband RF input tones. The user must
always perform DPD, CLGC, and VSWR initialization calibrations
at the Tx attenuation value that corresponds to the final rated
power amplifier (PA) operating power conditions, which improves
the estimation of the path delay and reduces variability from
run to run.
tx1RelThreshold/tx2RelThreshold 0…10000 Value given by 100 × (Relative Gain Threshold in dB). Enforce this
threshold by setting tx1RelThresholdEn/tx2RelThresholdEn to 1 in
mykonosClgcConfig_t. When the CLGC is tracking at a given
gain level in steady state, this threshold represents the maximum
dB change allowed in currentGain from one CLGC iteration to
the next. ERR_16 is thrown if the relative threshold is violated.
Note that the steady state condition implies that the currentGain
and desiredGain values are fairly close because the relative
threshold test condition checks the currentGain against a bound
of desiredGain ± tx1RelThreshold/tx2RelThreshold limit.
Default value is 600 (6 dB).
tx1RelThresholdEn/tx2RelThresholdEn 0, 1 A 1 enforces the use of tx1RelThreshold/Tx2RelThreshold limit
check set in mykonosClgcConfig_t. A 0 bypasses this check.
Default value is 0.

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UG-992 AD9371/AD9375 System Development User Guide
mykonosClgcStatus_t
This structure contains six members that provide information typedef struct
on the closed-loop gain control (CLGC) calibration status. This {
structure can be used as an error checker and debug tool for the
uint32_t errorStatus;
CLGC.
uint32_t trackCount;
int32_t desiredGain;
int32_t currentGain;
uint32_t txGain;
int32_t txRms;
int32_t orxRms;
14652-725
} mykonosClgcStatus_t;

Figure 250. mykonosClgcStatus_t Structure

Table 196. AD9375 CLGC Status Structure Member Description
Structure Member Value Description
errorStatus 0 No error.
1 Tx is disabled.
2 ORx is disabled.
3 Loopback switch is closed.
4 Data measurement aborted during capture: calibration interrupted by a higher
priority task or calibration. This error is a warning message to note that something
interrupted sample collection.
5 No initialization calibration was run.
6 Path delay not setup.
7 CLGC is running but does not apply control. Not enough samples were collected for
control signal generation. This error can also occur when the ORx signal is less than
the −39 dBFS threshold. Recovering from this error requires manual intervention.
8 Control value is out of range.
9 CLGC feature is disabled. This error is displayed when allowTx1AttenUpdates/
allowTx2AttenUpdates are disabled.
10 Tx attenuation is capped. CLGC control reaches cap limit (Tx1AttenLimit/
Tx2AttenLimit in mykonosClgcConfig_t, see Table 195.).
11 Gain measurement error during tracking.
12 No GPIO configured in single ORx configuration.
13 Tx is not observable with any of the ORx channels.
14 ORx tracking must be enabled; ORx_QEC tracking calibration must be enabled
before running CLGC.
15 Power amplifier (PA) protection activated: PA Protection hardware feature will
preempt any CLGC control. Check GP_INT status.
16 Relative threshold violated; currentGain of the CLGC increased more than the
relative threshold set by tx1RelThreshold/tx2RelThreshold in mykonosClgcConfig_t.
trackCount 0..0xFFFFFFFF Number of times CLGC has successfully run since CLGC initialization calibration.
desiredGain −10000..+10000 Desired loop gain (can be negative if total attenuation is greater than amplification)
from Tx output to ORx input. Desired GaindB = desiredGain/100
currentGain −10000..+10000 Current measured gain in 1/100ths dB scale. Current GaindB = currentGain/100

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AD9371/AD9375 System Development User Guide UG-992
Structure Member Value Description
txGain 0..4000 Current Tx attenuation setting for a given channel in 0.05 dB resolution, as determined
by the CLGC algorithm. However, this value is written to by the CLGC algorithm and
may differ slightly from Tx attenuation returned by
MYKONOS_getTx1/2Attenuation() due to these actions not being synchronous.
Tx AttenuationdB = txGain/200
txRms −2147483648..+2147483647 RMS Tx digital sample power measured at the output of the DPD actuator.
Measurement resolution is 0.01 dB. Prms dBFS = txRms/100.
orxRms −2147483648..+2147483647 RMS ORx digital sample power measured within the DPD block on the ORx side.
Measuremen resolution is 0.01 dB. Prms dBFS = orxRms/100.

CLGC FUNCTIONALITY API FUNCTIONS MYKONOS_getClgcStatus(…)

The application programming interface (API) functions associated mykonosErr_t
with the closed-loop gain control (CLGC) functionality follow. MYKONOS_getClgcStatus(mykonosDevice_t
*device, mykonosTxChannels_t txChannel,
MYKONOS_configClgc(…) mykonosClgcStatus_t *clgcStatus)
mykonosErr_t Description
MYKONOS_configClgc(mykonosDevice_t
*device) This function reads back the CLGC calibration status from the
ARM processor and returns the result to the mykonosClgcStatus_t
Description
structure.
This function call configures the device with the parameters in
Parameters
the CLGC data structure, mykonosDpdConfig_t. This function
also performs some sanity checks to the data parameters (range  *device: This is the device data structure pointer from
and ARM state checks) in the mykonosClgcConfig_t data which the CLGC status is read back.
structure. This function can be called when the device is in  txChannel: input argument to set which Tx channel the
either the radioOn or the radioOff state. However, not all function reads back the CLGC status for. Valid enumeration
parameters in the mykonosClgcConfig_t structure can be values are TX1 or TX2 only.
changed in the radioOn state. Call this function in the radioOff  *clgcStatus: This is a pointer to the structure that contains
state when attempting to change the additionalDelayOffset and the returned CLGC status information.
pathDelayPnSeqLevel parameters. Changes to the latter
parameters do not take effect unless modified in a radioOff MYKONOS_setClgcGain(…)
state and are ignored by the API and ARM. mykonosErr_t
MYKONOS_setClgcGain(mykonosDevice_t
MYKONOS_getClgcConfig(…) *device, mykonosTxChannels_t txChannel,
mykonosErr_t int16_t gain)
MYKONOS_getClgcConfig(mykonosDevice_t Description
*device)
This function configures the tx1DesiredGain/tx2DesiredGain
Description
parameters in the CLGC data structure, mykonosClgcConfig_t,
This function reads the CLGC configuration structure from the in the radioOn state.
ARM memory and updates the device → tx → clgcConfig data
Parameters
structure. There are no radio state dependencies for this
function.  *device: This is the device data structure pointer for which
this function takes effect.
 txChannel: input argument to set which Tx channel is to be
modified. Valid enumeration values are TX1, TX2, and
TX1_TX2.
 gain: This is the new value written into tx1DesiredGain/
tx2DesiredGain.
Note that because the update of most mykonosClgcConfig_t
parameters is allowed in the radioOn state, use this function if
only the tx1DesiredGain/tx2DesiredGain needs updating.
Issuing this command (instead of configClgc() in the radioOn
state) can also be slightly faster due to the reduced number of
API to ARM interactions.

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VSWR TRACKING CALIBRATION

To enable the voltage standing wave ratio (VSWR) measurement, Note that to change the GPIO pin or GPIO polarity for the
click Initialize/Reset PA Cals. Next, check off the VSWR box switch, the VSWR measurement must be disabled by unchecking
to enable the VSWR tracking calibration. The VSWR monitoring the VSWR check box.
begins, and the VSWR Monitoring window shown in Figure 253 The ORx Switch GPIO Setting section includes the following:
starts displaying new values. To calculate the VSWR number,
use the rms/complex gains by computing the ratio of the reflected  Ch1 GPIO: Use this box to select the 3.3 V GPIO pin used
gain to the forward gain to obtain Γ, as shown in Equation 58 found to control the VSWR switch on Tx1.
in the Voltage Standing Wave Ratio Measurement Overview  Ch1 Polarity: Use this box to select the polarity of the
section. 3.3 V GPIO pin for the forward path on Tx1 (1 = high
level, and 0 = low level). The opposite polarity is used for
VSWR MONITORING the reflection path.
Gain  Ch2 GPIO: Use this box to select the 3.3 V GPIO pin used
The VSWR monitoring Forward Gain section includes the to control the VSWR switch on Tx2.
following:  Ch2 Polarity: Use this box to select the polarity of the
 RMS: forward rms gain measured from Tx to ORx path. 3.3 V GPIO pin for the forward path on Tx2 (1 = high
level, and 0 = low level). The opposite polarity is used for
 REAL: real part of the forward path complex gain.
the reflection path.
 IMAGINARY: imaginary part of the forward path
complex gain. VSWR State
The VSWR monitoring Reverse Gain section includes the The VSWR monitoring VSWR State section includes the
following: following:

 RMS: reflected rms gain measured from antenna to ORx.  Channel: The Tx channel for which the VSWR status is
 REAL: real part of the reflected path complex gain. being displayed.
 IMAGINARY: imaginary part of the reflected path  Enabled: displays whether the VSWR calibration is
complex gain. currently enabled or disabled.
 Status: displays the VSWR error code.
ORx Switch GPIO Setting  VSWR Counter: displays the number of times the VSWR
The ORx Switch GPIO Setting section controls the switch that has been successfully scheduled since VSWR initialization
selects between the forward path and the reflected path. These calibration.
two paths (forward and reflected) are time multiplexed into the
ORx and controlled by the VSWR calibration via a designated
GPIO_3.3 V pin.
14652-726

Figure 251. VSWR Monitoring Window

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VSWR API
This section describes all of the application programming typedef struct
interface (API) data structures and functions that are associated {
with the voltage standing wave ratio (VSWR) feature.
int16_t additionalDelayOffset;
VSWR API DATA STRUCTURES uint16_t pathDelayPnSeqLevel;
The data structures associated with the VSWR functionality are
listed in the following subsections. uint8_t tx1VswrSwitchGpio3p3Pin;
mykonosVswrConfig_t uint8_t tx2VswrSwitchGpio3p3Pin;
The mykonosVswrConfig_t structure is the main data structure uint8_t tx1VswrSwitchPolarity;
that stores all parameters for the VSWR measurement uint8_t tx2VswrSwitchPolarity;
configuration. The information in this structure is loaded into
uint8_t tx1VswrSwitchDelay_us;
the ARM using the MYKONOS_configVswr() function. The
UML representation of the structure is shown in Figure 252. uint8_t tx2VswrSwitchDelay_us;
} mykonosVswrConfig_t;
14652-727

Figure 252. mykonosVswrConfig_t UML Structure

Table 197. AD9375 VSWR Configuration Structure Member Description

Structure Member Valid Values Description
additionalDelayOffset −64…+64 This parameter adds or reduces delay to the external
sample delay assessed during the sample time alignment
process. Resolution of additional delay is 1/16 of an
ORx sample. Delay offset = additionalDelayOffset/16.
Using 16 for this parameter implies a 1-sample delay.
Default: 0. Changes in the delay offset values requires
rerunning the VSWR initialization calibration. Because
the effect of tuning, this value on calibration
performance may not be immediately apparent, it is
recommended that a value similar to that in the
mykonosDpdConfig_t structure is used here, as well.
pathDelayPnSeqLevel 0…8192 Amplitude level of broadband pseudonoise (PN)
sequence sent out during VSWR initialization calibration.
Default: 255 (−30 dBFS = 20 log10(Value/8192). Analog
Devices recommends using the default value for this
parameter unless the power amplifier (PA) is highly
sensitive to broadband RF input tones. The user must
always perform the DPD, CLGC, and VSWR initialization
calibrations at the Tx attenuation value that corresponds
to the final rated PA operating power conditions, which
improves the estimation of the path delay and reduces
variability from run to run.

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UG-992 AD9371/AD9375 System Development User Guide
Structure Member Valid Values Description
tx1VswrSwitchGpio3p3Pin/tx2VswrSwitchGpio3p3Pin 0…11 The GPIO_3P3_x pin used to control the VSWR switch
for Tx1/Tx2 (output from AD9375).
tx1VswrSwitchPolarity/tx2VswrSwitchPolarity 0, 1 The GPIO_3P3_x pin polarity for the forward path of
Tx1/Tx2, opposite used for reflection path (1 = high
level, and 0 = low level).
tx1VswrSwitchDelay_ms/tx2VswrSwitchDelay_us 0…255 Delay for Tx1/Tx2 VSWR calibration to expect reflection
data at ORx (until data capture starts) after flipping the
VSWR switch. These have microsecond resolution.

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AD9371/AD9375 System Development User Guide UG-992
mykonosVswrStatus_t typedef struct
The mykonosVswrStatus_t structure contains members that {
provide information on the status of the voltage standing wave uint32_t errorStatus;
ratio (VSWR) measurement. This structure can be used as a uint32_t trackCount;
status/error checker and debug tool for the VSWR.
int32_t forwardGainRms_dB;
int32_t forwardGainReal;
int32_t forwardGainImag;
int32_t reflectedGainRms_dB;
int32_t reflectedGainReal;
int32_t reflectedGainImag;
int32_t vswr_forward_tx_rms;
int32_t vswr_forward_orx_rms;
int32_t vswr_reflection_tx_rms;
int32_t vswr_reflection_orx_rms;
} mykonosVswrStatus_t;
14652-728

Figure 253. mykonosVswrStatus_t Structure

Table 198. AD9375 VSWR Status Structure Member Description

Structure Member Value Description
errorStatus 0 No error: normal VSWR operation.
1 Tx datapath not enabled: the transmitter for this channel is currently disabled.
2 ORx datapath is not enabled.
3 Loopback switch is closed.
4 VSWR initialization calibration not run: rerun VSWR initialization calibration.
5 Path delay error: check external path and rerun VSWR initialization calibration.
6 Data measurement was aborted: warning message to show that
something interrupted data collection.
7 VSWR disabled: check tracking calibration mask.
8 Entered calibration but VSWR measurement could not be completed.
9 No GPIO pin configured for single ORx configuration. Used in shared ORx
mode.
10 Tx is not observable with any of the ORx channels. Used in shared ORx mode.
trackCount 0..0xFFFFFFFF Number of times VSWR has successfully run since VSWR initialization
calibration.
forwardGainRms_dB 0..1000 Forward rms gain measured from Tx to ORx path (1 = 0.01 dB gain).
forwardGainReal 0..1000 Real part of the forward path complex gain (1 = 0.01 linear gain).
forwardGainImag 0..1000 Imaginary part of the forward path complex gain (1 = 0.01 linear gain).
reflectedGainRms_dB 0..1000 Measured reflected path gain in rms (1 = 0.01 dB gain).
reflectedGainReal 0..1000 Real part of the reflected path complex gain (1 = 0.01 linear gain).
reflectedGainImag 0..1000 Imaginary part of the reflected path complex gain (1 = 0.01 linear gain).

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UG-992 AD9371/AD9375 System Development User Guide
Structure Member Value Description
vswr_forward_tx_rms −2147483648..+2147483647 RMS Tx digital sample power measured at the output of the DPD actuator
in the forward measurement mode. Measurement resolution is 0.01 dB.
Expect a 21 dB offset from the JESD204B dBFS value as well as from the
txRms data reported by the CLGC. Prms dBFS = txRms/100 +21 dB.
vswr_forward_orx_rms −2147483648..+2147483647 RMS ORx digital sample power measured at the DPD block for t.he ORx
data in the forward measurement mode. Measurement resolution is
0.01 dB. Expect a 21 dB offset from the JESD204B dBFS value as well as
from the txRms data reported by the CLGC. Prms dBFS = orxRms/100 +21 dB.
vswr_reflection_tx_rms −2147483648..+2147483647 RMS Tx digital sample power measured at the output of the DPD actuator
for the reverse measurement. Measurement resolution is 0.01 dB. Expect a
21 dB offset from the JESD204B dBFS value as well as from the txRms data
reported by the CLGC. Prms dBFS = txRms/100 +21 dB.
vswr_reflection_orx_rms −2147483648..+2147483647 RMS ORx digital sample power measured at the DPD block for the ORx
data in the reverse measurement mode. Measurement resolution is
0.01 dB. Expect a 21 dB offset from the JESD204B dBFS value as well as
from the orxRms data reported by the CLGC. Prms dBFS = orxRms/100 +21 dB.

VSWR FUNCTIONALITY API FUNCTIONS MYKONOS_getVswrStatus(…)

The application programming interface (API) functions associated mykonosErr_t
with the voltage standing wave ratio (VSWR) functionality are MYKONOS_getVswrStatus(mykonosDevice_t
listed in the following subsections. *device, mykonosTxChannels_t txChannel,
mykonosVswrStatus_t *vswrStatus)
MYKONOS_configVswr(…)
Description
mykonosErr_t
MYKONOS_configVswr(mykonosDevice_t This function reads back the VSWR calibration status from the
*device) ARM processor and returns the result to the
mykonosVswrStatus_t structure.
Description
Parameters
This function call configures the device with the parameters in
the VSWR data structure, mykonosVswrConfig_t. This function • *device: This is the device data structure pointer from
also performs some sanity checks to the data parameters (range which the VSWR status is read back.
and ARM state checks) in the mykonosVswrConfig_t data • txChannel: Input argument to set which Tx channel the
structure. The device must be in the radioOff state before this function reads back the VSWR status for. Valid
function can be called. enumeration values are TX1 or TX2 only.
MYKONOS_getVswrConfig(…) • *vswrStatus: This is a pointer to the structure that contains
the returned VSWR status information.
mykonosErr_t
MYKONOS_getVswrConfig(mykonosDevice_t
*device)
Description
This function reads the VSWR config structure from the ARM
memory and updates the device → tx → vswrConfig data structure.
There are no radio state dependencies for this function.

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AD9371/AD9375 System Development User Guide UG-992

SYSTEMS DESIGN CONSIDERATIONS

DPD TUNING PROCEDURE 8. Adjust the modelPriorWeight such that the right level of DPD
The following tuning procedure is suggested to iteratively find adaptation agility or inertia is achieved at different attenuation
the digital predistortion (DPD) configuration parameters that and/or baseband power levels. Refer to Table 193 and the
DPD Model Save/Restore Functionality section for more
optimize performance for any given power amplifier (PA). As
guidance.
the DPD affects and is affected by many system considerations,
a balance must be found between the different performance Refer to the debug notes in the Troubleshooting Issues by
metrics such that all metrics are within the limits of tolerance of Making Changes to the DPD Configuration Structure section.
the application or use case. Refer to the mykonosDpdConfig_t
section for more details regarding the parameters being
DPD MODEL SAVE/RESTORE FUNCTIONALITY
adjusted here. The save and restore functionality included in the AD9375 is
designed to speed up or enhance the DPD adaptation in the
1. Starting with the default setup and a given test waveform
field. This function can save the DPD model data during the
(for example, 1 × 20 MHz E-TM 1.1), apply the DPD and
factory calibration phase of base station equipment deployment,
note the adjacent channel leakage ratio (ACLR) and other
such that the saved model(s) can be reused when the operating
systems metrics.
conditions in the field are similar to the factory test conditions.
2. Choose an appropriate DPD modelVersion for the given
Therefore, by training the DPD on a known set of parameters
PA: the model that minimizes asymmetry and performs
and test conditions considered difficult, and by choosing a
close to, if not better than, the values noted in Step 1 is
higher value of the model prior weight (see Table 193) when
probably the best suited for the given PA.
restoring the saved model, DPD gets a head start on tackling
3. Increase or decrease the damping or model averaging
similar conditions in the field.
factor such that any fluctuations in the spectrum are down
to an acceptable minimum. An alternate application for this functionality is when frequency
4. Increase or decrease the samples per update parameter, hopping within certain bands is desired, where the latest DPD
such that any fluctuations in the spectrum (time varying model can be saved before switching frequencies, and a host
ACLR) are down to an acceptable minimum. Note that baseband processor (BBP) can restore this saved model when
increasing the value of this parameter implies longer DPD returning to the older frequency of operation. The user is
adaptation cycles and vice versa. For some PAs, increasing encouraged to devise a scheme that suits the application (for
this value may improve the spectral performance example, with the help of the parameters detailed in Table 194)
(regrowth) further away from the local oscillator (LO) to determine whether the current DPD model is a good model
frequency (dc). Because Step 3 and Step 4 are both or not. An example is using the dpdModelErrorPercent as
complementary and similar in some respects, tuning guidance for checking a predefined acceptable threshold before
iteratively between these steps before proceeding is saving the DPD model.
recommended. Note that it is the responsibility of the user to record metadata,
5. Note the external sample delay in the DPD Status section such as the frequency of operation, DPD configuration
leading up to this step (see Figure 243). Adjust the structure, and the Tx channel and PA used, while saving the
additionalDelayOffset value in decrements or increments DPD model data. Restoring a DPD model to a different Tx path
of 1/16 of a sample starting from the default value of 0. or configuration than from when the model was saved does not
Iteratively, find the best value of delay offset that improves yield the desired performance. Ideally, with all else being equal,
the ACLR value (up to 2 dB to 3 dB can be expected in restoring a saved model replicates the exact same DPD
some cases). For some fractional sample delays, the AM- performance as when the DPD model was saved. Note that the
AM plot starts misbehaving. It is recommended that the device needs to be in radioOff mode before saving or restoring.
user not exceed these arbitrary boundary values.
Note that because this DPD relies on having a good prior model
6. Once some acceptable level of performance is achieved,
when adapting to PA behavior under different operating
adjust the frequency weights to shape the DPD error
conditions, users are highly encouraged to leverage the save and
spectrum more evenly and correct asymmetries in the
restore feature for preloading a prior model.
ACLR.
7. Enable the closed-loop gain control (CLGC) if desired
(refer to the CLGC Tracking Cal section for controlling the
CLGC). Iterate Step 1 through Step 6 as needed with each gain
level. Note that the compensation of PA gain flatness vs.
frequency or temperature is not an objective of the AD9375
DPD/CLGC and must be handled by the system of the
customer (baseband processor (BBP) or other control).
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UG-992 AD9371/AD9375 System Development User Guide
Practical System Considerations to When Using Save GUIDELINES FOR DEVELOPING AND
and Restore TROUBLESHOOTING A DPD SYSTEM
As mentioned in the DPD Model Save/Restore Functionality In the course of developing a system that uses any DPD solution,
section, the save and restore feature is a useful technique to there are a number of tests that must be run to pass conformance
jumpstart the digital predistortion (DPD) with a known good testing limits set by regulatory bodies such as 3GPP, the FCC,
model. However, the following important practical system and ETSI. Therefore, while it is important to verify that the
considerations and trade-offs must be considered while basic DPD requirements of the user are met with the integrated
evaluating and implementing this feature: DPD solution of the AD9375 (such as adjacent channel leakage
• The quality of the saved DPD model is completely dependent ratio (ACLR) correction with desired occupied bandwidth), the
on the power amplifier (PA) type and conditions under user is also encouraged to study various other system design
which the DPD model was saved. This dependence implies metrics, such as time division duplexed (TDD) configuration
that if the operating conditions between when the factory timing and its impact on the ARM calibrations scheduler, RF
calibration was performed and when the basestation trace and antenna coupling in a MIMO application, impact on
equipment first boots up in the field are drastically factory calibration and test times when using the save/restore
different, the saved DPD model may lead to poor DPD functionality for loading a good prior model, studying the
adapatations. For example, if the prior model was saved impact of 3GPP LTE E-TM2 or broadcast channel only
when the system was operational for fifteen minutes in the waveforms on spectrum emission mask (SEM) and ACLR
factory, and it had sufficient time to self heat and reach requirements, and so on. Most of these topics are covered under
thermal equilibrium with the environment while the boot-up separate headings in the following sections, with this section
conditions are drastically different and may be either hotter dedicated to troubleshooting DPD specific problems for a
or cooler than the factory conditions. system that uses the AD9375. These subsections are especially
• Temperature range considerations. Because the behavior of useful when the customer has migrated from the evaluation
a PA can change with operating temperature, it may be phase to bringing up a system prototype.
necessary to save the prior models in different temperature Dissecting the DPD, CLGC, and VSWR Status Logs
regions. For example, consider saving three models for One of the best possible resources that a user has access to when
room, hot, and cold temperature ranges. identifying system issues is to make extensive use of the DPD,
• Massive multiple input, multiple output (MIMO) system closed-loop gain control (CLGC), voltage standing wave ratio
design. When designing massive MIMO systems, it can (VSWR), and other calibration status structures. It is highly
become impractical to save models for each path of a recommended that the user build diagnostics into the RF
64T64R system, for instance, during the factory calibration software suite that allow the baseband processor (BBP) to
due to time, memory, and/or practical limitations. collect time stamped status logs. This strategy helps the user
In addition, note that, due to the limitations in the use cases identify issues in the system by observing the response of
previously described, it is recommended to also explore calibrations to various stimuli (waveforms, operating conditions,
alternative options, such as booting the system with no prior and so on) during system bring-up as well as during normal
model (for example, right after the DPD initialization calibration) field operation. Because the DPD family of calibrations are
and monitoring the DPD status for indications on when a given dependent on, or seek to control components that reside
model of a channel is suitable for saving to memory. Controlling outside of the AD9375, the calibrations are sensitive to any
when the highPowerModelUpdate member in the Mykonos- system level disturbances. Therefore, it is important to have
DpdConfig_t is enabled allows the system to be setup to operate access to contextual diagnostic status readbacks that allow the
with a prior model. If the output spectrum cannot be retrieved in analysis of the calibration statuses of the system.
the system of the user (that is, no ORx is routed), the DPD
model error and error status in mykonosDpdStatus_t can give a
fair indication of whether a given channel has adapted successfully.
Some experimentation is required to determine what works best
for the overall system of the user, and trade offs between
software complexity and system requirements may be needed.

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AD9371/AD9375 System Development User Guide UG-992
EVM Tests To understand this further, it is important to remember that the
More often than not, the preliminary digital predistorition ARM schedules all of the calibrations based on a priority table.
(DPD) evaluation of the user centers around adjacent channel Each calibration attempts to run and capture the requisite
leakage ratio (ACLR) tests for various signal conditions. number of sample points as soon as the update interval expires,
However, because the closed loop of the DPD extends well with higher priority calibrations having the ability to interrupt
beyond the AD9375 and encompasses the power amplifier (PA) the lower priority calibrations at specific points within a the
and any other loopback components, any variation that affects execution of a calibration. Therefore, it is shown that certain
the output spectrum is expected to be corrected by the DPD low priority calibrations fail to update in certain TDD
algorithm This correction necessitates the study of both out of configurations. See Table 199 for the update rate for the
band (ACLR and SEM) and in-band (error vector magnitude AD9375 calibrations.
(EVM)) metrics. Because the EVM captures any latent phase Table 199. Default Priority and Update Intervals for the
issues in the PA and other loopback components, it is important
AD9375 Calibrations
to study the residual EVM of the entire signal chain with and
Priority Calibration Update Interval (ms)
without DPD with various signals and in different operating
1 Tx local oscillator leakage 2000
conditions. For example, short duration pulses trigger most PA (LOL) external
gain and phase drifts. The E-TM2 waveform has sparsely 2 DPD 250
occupied data resource blocks (RBs) and contains a distinct 3 Closed-loop gain control 250
time domain pulsed signature when compared to the E-TM3.1 (CLGC)
waveform, which looks more or less uniform (due to the fully 4 Voltage standing wave ratio 1000
occupied nature of the waveform). Therefore, performing EVM (VSWR)
tests along with ACLR tests results in a better system check. 5 Tx quadrature error 30000
correction (QEC)
Troubleshooting Issues by Making Changes to the DPD
6 ORx QEC 1000
Configuration Structure
7 Rx QEC 5
When initially tuning for ACLR and SEM specifications with a
static signal, it is recommended to set the damping or model Because the DPD configuration structure allows the capturing
averaging factor to 1 and the modelPriorWeight to 0. The of a variable number of samples, it is important to tune the ACLR
significance of these parameters becomes more apparent when performance not just in frequency division duplex (FDD) but
dealing with dynamic signal cases where the baseband processor also in TDD, such that a good trade-off exists between acceptable
(BBP) may switch between different types of signals and/or be ACLR performance and other metrics, while also allowing
accompanied by ramping power up and down digitally for entire sufficient time for the lower priority calibrations to run. In the
waveforms, or by controlling certain RBs. By making these event that the lower priority calibrations do not run, performance
changes, the objective is to identify if the damped correlations deviates from that stated in the AD9375 data sheet. When the
or the prior model has degraded the performance. These tests samples parameter fails to provide the necessary margin for
are especially useful when performing long-term stability tests. calibrations to run, consider changing the update rate of the
DPD and CLGC calibrations (because these are the calibrations
DESIGNING A SYSTEM FOR A TDD APPLICATION that take the longest times for their respective data captures). To
Long term evolution (LTE) supports the use of a time division inquire about instructions for changing the update rate, go to the
duplexed (TDD) frame, and the AD9375 DPD can be used following: www.analog.com/en/applications/technology/sdr-
when the device is set up in TDD mode. Refer to the TDD radioverse-pavilion-home/rf-transceiver-support.html.
Configuration and Setup section for more details. TDD
configurations vary from a downlink (DL) to uplink (UL) ratio
of 20% (TDD Configuration 0) to 80% (TDD Configuration 5).
Because DPD runs as an ARM calibration only when the ORx is
configured in INTERNAL_CALS mode, the amount of DL data
observable by DPD depends greatly on the TDD configuration
used and the time allowed by the user for the AD9375 to perform
all of its calibrations. Therefore, when some low DL duty-cycle
configurations are used, the possibility exists that certain
calibrations do not get sufficient time to execute.

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EXTERNAL LOOPBACK FLATNESS REQUIREMENTS Outside of the ±10 MHz frequency range, the ACLR improvement
The adjacent channel leakage ratio (ACLR) improvement that is smaller, 22 dBc at ±20 MHz. Then, Figure 254 shows that the
the AD9375 digital predistortion (DPD) can provide degrades required loopback flatness out to this frequency is only < 0.25 dB.
at frequencies where the loopback channel is not flat. The At ±30 MHz, the ACLR improvement is only 12 dBc. According
loopback flatness requirement at a given frequency depends on to Figure 254, loopback flatness is then relaxed and must only be
the ideal DPD ACLR improvement at the given frequency. The <0.8 dB. Beyond about ±50 MHz, the ideal ACLR improvement is
ideal ACLR improvement is defined as the ACLR improvement only 5 dBc. In this case, the loopback channel can have up to
observed for the PA with the DPD using a near perfect loopback 1.6 dB greater gain or as low as −1.9 dB less gain and not affect
channel (over 5 × bandwidth). performance. Note that if no ACLR improvement occurs at a
given frequency, the flatness at that frequency can be as poor as
The theoretical formula for how much the loopback channel ±3 dB and not cause noticeable distortion.
gain can vary without degrading the ACLR from this ideal case 1.6
by more than 1 dBc follows: 1.4
1.2
 ACLR  9
  1.0
20log10 1  10 20   GAIN  0.8
 
  0.6
0.4
 ACLR  9
  0.2

GAIN (dB)
20log10 1  10 20  0 ALLOWED LOOPBACK
  –0.2 GAIN VARIATION
  –0.4
–0.6
where: –0.8
ACLR is the ideal ACLR improvement at the frequency of interest. –1.0
–1.2
GAIN is an allowed gain at that frequency. Note that GAIN is given
–1.4
in dB relative to the loopback gain at the LTE carrier frequency. –1.6
–1.8
For example, in Figure 255, a single 20 MHz LTE carrier is

14652-729
–30 –28 –26 –24 –22 –20 –18 –16 –14 –12 –10 –8 –6
transmitted and centered on the local oscillator (LO) through a ACLR IMPROVEMENT WITH DPD (dBc)
gallium nitride (GaN) power amplifier (PA) and with a near Figure 254. Range Over Which Loopback Gain Can Vary Without Affecting
ideal loopback channel. The ACLR improvement with DPD is DPD ACLR Improvement by More Than 1 dBc of Degradation
observed as 28 dBc at ±10 MHz. Therefore, the DPD loopback flatness requirements are a
Looking at Figure 254, gain flatness at ±10 MHz must be <0.1 dB function of the desired ACLR improvement. To not degrade
to not degrade digital predistortion (DPD) performance (at optimal predistortion results by more than 1 dB, obey the
±10 MHz) by more than 1 dBc from the ideal loopback case. flatness requirements shown in Figure 254.

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Figure 255. Power Spectral Density of PA Output Showing Before (Magenta) and After DPD (Yellow)

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UG-992 AD9371/AD9375 System Development User Guide
CLGC CONVERGENCE TIME with the important nonlinear characteristics of the PA before
The closed-loop gain control (CLGC) convergence time is switching to an E-TM2 or similar broadcast signal. Note that the
typically < 5 seconds for full stable convergence. Figure 256 shows PA must be operating at its rated power for the model to be a
a power vs. time graph of the convergence time required for a meaningful prior model.
20 dB change in the CLGC tx1DesiredGain/tx2DesiredGain Analog Devices highly recommends the use of a CFR algorithm,
parameter (see Table 195). Note that the CLGC is continuously however rudimentary, to improve the stability of the DPD
tracking when these changes are applied, and that the AD9375 algorithm. Even though the user may devise a scheme involving
is in radioOff mode when the config parameter is updated. the DPD Model Save/Restore Functionality, the need for a CFR
30 is not entirely obviated, and the CFR must only be used after
8dBm TO 28dBm TRANSITION
consulting with an Analog Devices representative at
www.analog.com/en/landing-pages/001/sdr-radioverse-
25
pavilion/support.html.
Maximum Occupied Signal Bandwidth
POWER (dBm)

20
The maximum occupied linearizable signal bandwidth for most
PAs is 40 MHz with this DPD. Some PAs may be linearizable at
15
wider RF bandwidths (contiguous or noncontiguous carrier
aggregation); however, typical levels of ACLR correction with
10 DPD cannot be guaranteed nor justified in these cases. For PA
recommendations that suit specific applications, consult with an
5
Analog Devices representative at www.analog.com/en/landing-
14652-731

14.0 14.2 14.4 14.6 14.8 15.0 pages/001/sdr-radioverse-pavilion/support.html.

TIME (Seconds)

Figure 256. Power vs. Time Showing CLGC Tracking a 20 dB Change in the
Using DPD with GaN PAs
Desired Gain Parameter Even though the AD9375 DPD models the RF behavior at
DPD LIMITATIONS baseband of a given PA and doesn’t really care about the PA
process type nor design architecture, certain types of PAs such
The following subsections outline AD9375 digital predistortion
as gallium nitride (GaN) PAs can pose significant linearization
(DPD) limitations and guidelines to observe during system challenges. Note that some GaN PAs may be linearizable after
design that allow workarounds of these limitations.
following the standard tuning procedure; however, there exists a
Need for Crest Factor Reduction very clear motivation to look at specific system level tests to qualify
The AD9375 DPD seeks to predistort the true radio frequency a PA with DPD. For example, even though the ACLR performance
(RF) behavior of a power amplifier (PA) using a simple behavioral may be within the system design specifications, it is important
model with a limited number of polynomial terms. Therefore, to also measure error vector magnitude (EVM) for standard
with the reduced complexity of the DPD solution, it is difficult signals such as E-TM3.1 and E-TM2. For PA recommendations
to model large behavioral variations in the PA at widely varying that suit user specific applications, consult with an Analog
power levels. One of the easiest ways to improve the reliability Devices representative at www.analog.com/en/landing-
and stability of DPD is to employ a crest factor reduction (CFR) pages/001/sdr-radioverse-pavilion/support.html.
algorithm in the baseband processor (BBP) to reduce the peak OTHER CONSIDERATIONS
to average ratio (PAR) of the baseband signal seen by the DPD
The following are other considerations to keep in mind:
block. The CFR algorithm helps to prevent cases where the
DPD observes a sparse sample set of the nonlinear behavior of  It is recommended to keep Tx to ORx isolation greater
the PA (as is the case with high PAR signals) and makes poor than −55 dBc to avoid any negative effects on DPD
guesses or extrapolations of the unobserved behavior. These performance, which is a useful consideration to keep in
erroneous estimates can often manifest as spurious signals mind during printed circuit board (PCB) layout.
adjacent to the desired signal on a spectrum analyzer. For  The minimum ORx rms power threshold required by the
example, if a user starts DPD tracking with an E-TM2 signal CLGC is set to −39 dBFS by default; however, this number
(PAR = ~12 dB) and no prior information, the DPD sees a very can be modified, if required, at the expense of accepting
poor excitation of the nonlinear PA behavior and makes poor some degradation in tracking tolerance at ORx power
assumptions. The situation is made even worse when the prior levels below −39 dBFS. To inquire about setup instructions,
model of the DPD is corrupted with this poor data set. The go to www.analog.com/en/landing-pages/001/sdr-
solution is to train the DPD on a fully occupied E-TM3.1-like radioverse-pavilion/support.html.
signal with an 8 dB PAR or lower to update the prior model

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AD9371/AD9375 System Development User Guide UG-992

TYPICAL TEST SETUP AND DPD PERFORMANCE

The SKY66297-11 power amplifier (PA) is optimized for signals Figure 257 shows a typical setup for testing the DPD with the
of no more than 20 MHz bandwidth. A waveform setup with a SKY66297-11 PA while keeping the PA within its optimized
total bandwidth greater than 20 MHz pushes the PA out of its bandwidth. Note that these are the initial conditions and some
optimized range, and performance measures, such as the adjacent configurations inputs can be changed to achieve better
channel leakage ratio (ACLR) and error vector magnitude performance. Prior to enabling the DPD, the AM-AM plot must
(EVM), may start to degrade. This degradation is due to show compression (weak nonlinearity). If not, reduce the Tx
limitations of the PA and cannot necessarily be attributed to the attenuation until the PA AM-AM output starts to roll over and
digital predistortion (DPD) algorithm. To see the full benefit compress. Figure 258 shows the DPD performance with the
that the AD9375 DPD solution can deliver, the PA must be closed-loop gain control (CLGC) enabled. The ORx Gain Index
tested using signals that conform to the limitations of each can be increased up to a point where most of the points on the
individual PA. As a first order test to confirm the DPD AM-AM plot are close to the linear curve as possible. The
performance, recreate similar settings as shown in Figure 257 ACLR achieved using this setup after enabling DPD is typically
and Figure 258. −50 dBc (or better) at a 28 dBm output power (POUT).

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Figure 257. Typical Test Setup

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Figure 258. DPD Performance with CLGC Enabled

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AD9371/AD9375 System Development User Guide UG-992

TDD SETUP INSTRUCTIONS

Apart from the normal user actions necessary for digital time to maximize DPD performance. Alternatively, the
predistortion (DPD) operation, take the following steps to perform user can enable tracking calibrations throughout the frame
the DPD with time division duplexed (TDD) waveforms. so that Rx calibrations can also be scheduled during Rx or
1. Program the device to operate in TDD mode using the TES uplink (UL) bursts. Note that, by default, the DPD, the
or scripts. closed-loop gain control (CLGC), and the voltage standing
2. Disconnect from the TES and launch the DPD GUI. wave ratio (VSWR) do not track in ORx1 or ORx2 path
Because the DPD GUI only has frequency division duplex source modes.
(FDD) waveforms in its library, use the Custom waveform 5. Click SetUp TDD Timings → Enable Tx Data Transmit to
dropdown menu to load the desired TDD waveform. Refer start the TDD bursts. After disconnecting from the TES,
to the Waveform Setup section for more information. running the DPD initialization calibration, and enabling
3. Close the DPD GUI and connect using the TES. Navigate the DPD adaptation, observe the DPD status. Note that a
to the TDD/FDD Switching tab and set up the Tx and Rx spectrum analyzer must be used for observing the spectrum
frame timing according to the baseband signal loaded in because the ORx data display (ACLR and AM-AM plots)
Step 2. Refer to Figure 259 for a Configuration 1 setup. used in the GUI cannot display TDD bursts.
4. Choose the tracking calibration timing to observe different Alternatively, the TES Transmit Data tab can load a TDD
Tx or downlink (DL) bursts in the TDD waveform (ORx 1 waveform (in this case, skip Step 2). However, the DPD must be
and ORx2 cannot be active at the same time) to enable the separately enabled. If there is some misalignment observed in
DPD to adapt to both the Tx1 and the Tx2 outputs. Allow gated measurements, repeat Step 5 until the frame bursts are
for some guard period (variable) around the Tx switching properly aligned.

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Figure 259. TES TDD Configuration 1 Waveform Switching Configuration with Tx Tracking Calibrations

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Figure 260. TDD Configuration 1 Waveform with Digital Predistortion (DPD), Gated PXA Measurement

ESD Caution
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection
circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.

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